1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/IR/DebugInfoMetadata.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetOptions.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "x86-instr-info"
47 
48 #define GET_INSTRINFO_CTOR_DTOR
49 #include "X86GenInstrInfo.inc"
50 
51 static cl::opt<bool>
52     NoFusing("disable-spill-fusing",
53              cl::desc("Disable fusing of spill code into instructions"),
54              cl::Hidden);
55 static cl::opt<bool>
56 PrintFailedFusing("print-failed-fuse-candidates",
57                   cl::desc("Print instructions that the allocator wants to"
58                            " fuse, but the X86 backend currently can't"),
59                   cl::Hidden);
60 static cl::opt<bool>
61 ReMatPICStubLoad("remat-pic-stub-load",
62                  cl::desc("Re-materialize load from stub in PIC mode"),
63                  cl::init(false), cl::Hidden);
64 static cl::opt<unsigned>
65 PartialRegUpdateClearance("partial-reg-update-clearance",
66                           cl::desc("Clearance between two register writes "
67                                    "for inserting XOR to avoid partial "
68                                    "register update"),
69                           cl::init(64), cl::Hidden);
70 static cl::opt<unsigned>
71 UndefRegClearance("undef-reg-clearance",
72                   cl::desc("How many idle instructions we would like before "
73                            "certain undef register reads"),
74                   cl::init(128), cl::Hidden);
75 
76 
77 // Pin the vtable to this file.
78 void X86InstrInfo::anchor() {}
79 
80 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
81     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
82                                                : X86::ADJCALLSTACKDOWN32),
83                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
84                                                : X86::ADJCALLSTACKUP32),
85                       X86::CATCHRET,
86                       (STI.is64Bit() ? X86::RET64 : X86::RET32)),
87       Subtarget(STI), RI(STI.getTargetTriple()) {
88 }
89 
90 bool
91 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
92                                     Register &SrcReg, Register &DstReg,
93                                     unsigned &SubIdx) const {
94   switch (MI.getOpcode()) {
95   default: break;
96   case X86::MOVSX16rr8:
97   case X86::MOVZX16rr8:
98   case X86::MOVSX32rr8:
99   case X86::MOVZX32rr8:
100   case X86::MOVSX64rr8:
101     if (!Subtarget.is64Bit())
102       // It's not always legal to reference the low 8-bit of the larger
103       // register in 32-bit mode.
104       return false;
105     LLVM_FALLTHROUGH;
106   case X86::MOVSX32rr16:
107   case X86::MOVZX32rr16:
108   case X86::MOVSX64rr16:
109   case X86::MOVSX64rr32: {
110     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
111       // Be conservative.
112       return false;
113     SrcReg = MI.getOperand(1).getReg();
114     DstReg = MI.getOperand(0).getReg();
115     switch (MI.getOpcode()) {
116     default: llvm_unreachable("Unreachable!");
117     case X86::MOVSX16rr8:
118     case X86::MOVZX16rr8:
119     case X86::MOVSX32rr8:
120     case X86::MOVZX32rr8:
121     case X86::MOVSX64rr8:
122       SubIdx = X86::sub_8bit;
123       break;
124     case X86::MOVSX32rr16:
125     case X86::MOVZX32rr16:
126     case X86::MOVSX64rr16:
127       SubIdx = X86::sub_16bit;
128       break;
129     case X86::MOVSX64rr32:
130       SubIdx = X86::sub_32bit;
131       break;
132     }
133     return true;
134   }
135   }
136   return false;
137 }
138 
139 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
140   if (MI.mayLoad() || MI.mayStore())
141     return false;
142 
143   // Some target-independent operations that trivially lower to data-invariant
144   // instructions.
145   if (MI.isCopyLike() || MI.isInsertSubreg())
146     return true;
147 
148   unsigned Opcode = MI.getOpcode();
149   using namespace X86;
150   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
151   // However, they set flags and are perhaps the most surprisingly constant
152   // time operations so we call them out here separately.
153   if (isIMUL(Opcode))
154     return true;
155   // Bit scanning and counting instructions that are somewhat surprisingly
156   // constant time as they scan across bits and do other fairly complex
157   // operations like popcnt, but are believed to be constant time on x86.
158   // However, these set flags.
159   if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
160       isTZCNT(Opcode))
161     return true;
162   // Bit manipulation instructions are effectively combinations of basic
163   // arithmetic ops, and should still execute in constant time. These also
164   // set flags.
165   if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
166       isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
167       isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
168       isTZMSK(Opcode))
169     return true;
170   // Bit extracting and clearing instructions should execute in constant time,
171   // and set flags.
172   if (isBEXTR(Opcode) || isBZHI(Opcode))
173     return true;
174   // Shift and rotate.
175   if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
176       isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
177     return true;
178   // Basic arithmetic is constant time on the input but does set flags.
179   if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
180       isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
181     return true;
182   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
183   if (isADCX(Opcode) || isADOX(Opcode) || isANDN(Opcode))
184     return true;
185   // Unary arithmetic operations.
186   if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
187     return true;
188   // Unlike other arithmetic, NOT doesn't set EFLAGS.
189   if (isNOT(Opcode))
190     return true;
191   // Various move instructions used to zero or sign extend things. Note that we
192   // intentionally don't support the _NOREX variants as we can't handle that
193   // register constraint anyways.
194   if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
195     return true;
196   // Arithmetic instructions that are both constant time and don't set flags.
197   if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
198     return true;
199   // LEA doesn't actually access memory, and its arithmetic is constant time.
200   if (isLEA(Opcode))
201     return true;
202   // By default, assume that the instruction is not data invariant.
203   return false;
204 }
205 
206 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
207   switch (MI.getOpcode()) {
208   default:
209     // By default, assume that the load will immediately leak.
210     return false;
211 
212   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
213   // However, they set flags and are perhaps the most surprisingly constant
214   // time operations so we call them out here separately.
215   case X86::IMUL16rm:
216   case X86::IMUL16rmi8:
217   case X86::IMUL16rmi:
218   case X86::IMUL32rm:
219   case X86::IMUL32rmi8:
220   case X86::IMUL32rmi:
221   case X86::IMUL64rm:
222   case X86::IMUL64rmi32:
223   case X86::IMUL64rmi8:
224 
225   // Bit scanning and counting instructions that are somewhat surprisingly
226   // constant time as they scan across bits and do other fairly complex
227   // operations like popcnt, but are believed to be constant time on x86.
228   // However, these set flags.
229   case X86::BSF16rm:
230   case X86::BSF32rm:
231   case X86::BSF64rm:
232   case X86::BSR16rm:
233   case X86::BSR32rm:
234   case X86::BSR64rm:
235   case X86::LZCNT16rm:
236   case X86::LZCNT32rm:
237   case X86::LZCNT64rm:
238   case X86::POPCNT16rm:
239   case X86::POPCNT32rm:
240   case X86::POPCNT64rm:
241   case X86::TZCNT16rm:
242   case X86::TZCNT32rm:
243   case X86::TZCNT64rm:
244 
245   // Bit manipulation instructions are effectively combinations of basic
246   // arithmetic ops, and should still execute in constant time. These also
247   // set flags.
248   case X86::BLCFILL32rm:
249   case X86::BLCFILL64rm:
250   case X86::BLCI32rm:
251   case X86::BLCI64rm:
252   case X86::BLCIC32rm:
253   case X86::BLCIC64rm:
254   case X86::BLCMSK32rm:
255   case X86::BLCMSK64rm:
256   case X86::BLCS32rm:
257   case X86::BLCS64rm:
258   case X86::BLSFILL32rm:
259   case X86::BLSFILL64rm:
260   case X86::BLSI32rm:
261   case X86::BLSI64rm:
262   case X86::BLSIC32rm:
263   case X86::BLSIC64rm:
264   case X86::BLSMSK32rm:
265   case X86::BLSMSK64rm:
266   case X86::BLSR32rm:
267   case X86::BLSR64rm:
268   case X86::TZMSK32rm:
269   case X86::TZMSK64rm:
270 
271   // Bit extracting and clearing instructions should execute in constant time,
272   // and set flags.
273   case X86::BEXTR32rm:
274   case X86::BEXTR64rm:
275   case X86::BEXTRI32mi:
276   case X86::BEXTRI64mi:
277   case X86::BZHI32rm:
278   case X86::BZHI64rm:
279 
280   // Basic arithmetic is constant time on the input but does set flags.
281   case X86::ADC8rm:
282   case X86::ADC16rm:
283   case X86::ADC32rm:
284   case X86::ADC64rm:
285   case X86::ADCX32rm:
286   case X86::ADCX64rm:
287   case X86::ADD8rm:
288   case X86::ADD16rm:
289   case X86::ADD32rm:
290   case X86::ADD64rm:
291   case X86::ADOX32rm:
292   case X86::ADOX64rm:
293   case X86::AND8rm:
294   case X86::AND16rm:
295   case X86::AND32rm:
296   case X86::AND64rm:
297   case X86::ANDN32rm:
298   case X86::ANDN64rm:
299   case X86::OR8rm:
300   case X86::OR16rm:
301   case X86::OR32rm:
302   case X86::OR64rm:
303   case X86::SBB8rm:
304   case X86::SBB16rm:
305   case X86::SBB32rm:
306   case X86::SBB64rm:
307   case X86::SUB8rm:
308   case X86::SUB16rm:
309   case X86::SUB32rm:
310   case X86::SUB64rm:
311   case X86::XOR8rm:
312   case X86::XOR16rm:
313   case X86::XOR32rm:
314   case X86::XOR64rm:
315 
316   // Integer multiply w/o affecting flags is still believed to be constant
317   // time on x86. Called out separately as this is among the most surprising
318   // instructions to exhibit that behavior.
319   case X86::MULX32rm:
320   case X86::MULX64rm:
321 
322   // Arithmetic instructions that are both constant time and don't set flags.
323   case X86::RORX32mi:
324   case X86::RORX64mi:
325   case X86::SARX32rm:
326   case X86::SARX64rm:
327   case X86::SHLX32rm:
328   case X86::SHLX64rm:
329   case X86::SHRX32rm:
330   case X86::SHRX64rm:
331 
332   // Conversions are believed to be constant time and don't set flags.
333   case X86::CVTTSD2SI64rm:
334   case X86::VCVTTSD2SI64rm:
335   case X86::VCVTTSD2SI64Zrm:
336   case X86::CVTTSD2SIrm:
337   case X86::VCVTTSD2SIrm:
338   case X86::VCVTTSD2SIZrm:
339   case X86::CVTTSS2SI64rm:
340   case X86::VCVTTSS2SI64rm:
341   case X86::VCVTTSS2SI64Zrm:
342   case X86::CVTTSS2SIrm:
343   case X86::VCVTTSS2SIrm:
344   case X86::VCVTTSS2SIZrm:
345   case X86::CVTSI2SDrm:
346   case X86::VCVTSI2SDrm:
347   case X86::VCVTSI2SDZrm:
348   case X86::CVTSI2SSrm:
349   case X86::VCVTSI2SSrm:
350   case X86::VCVTSI2SSZrm:
351   case X86::CVTSI642SDrm:
352   case X86::VCVTSI642SDrm:
353   case X86::VCVTSI642SDZrm:
354   case X86::CVTSI642SSrm:
355   case X86::VCVTSI642SSrm:
356   case X86::VCVTSI642SSZrm:
357   case X86::CVTSS2SDrm:
358   case X86::VCVTSS2SDrm:
359   case X86::VCVTSS2SDZrm:
360   case X86::CVTSD2SSrm:
361   case X86::VCVTSD2SSrm:
362   case X86::VCVTSD2SSZrm:
363   // AVX512 added unsigned integer conversions.
364   case X86::VCVTTSD2USI64Zrm:
365   case X86::VCVTTSD2USIZrm:
366   case X86::VCVTTSS2USI64Zrm:
367   case X86::VCVTTSS2USIZrm:
368   case X86::VCVTUSI2SDZrm:
369   case X86::VCVTUSI642SDZrm:
370   case X86::VCVTUSI2SSZrm:
371   case X86::VCVTUSI642SSZrm:
372 
373   // Loads to register don't set flags.
374   case X86::MOV8rm:
375   case X86::MOV8rm_NOREX:
376   case X86::MOV16rm:
377   case X86::MOV32rm:
378   case X86::MOV64rm:
379   case X86::MOVSX16rm8:
380   case X86::MOVSX32rm16:
381   case X86::MOVSX32rm8:
382   case X86::MOVSX32rm8_NOREX:
383   case X86::MOVSX64rm16:
384   case X86::MOVSX64rm32:
385   case X86::MOVSX64rm8:
386   case X86::MOVZX16rm8:
387   case X86::MOVZX32rm16:
388   case X86::MOVZX32rm8:
389   case X86::MOVZX32rm8_NOREX:
390   case X86::MOVZX64rm16:
391   case X86::MOVZX64rm8:
392     return true;
393   }
394 }
395 
396 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
397   const MachineFunction *MF = MI.getParent()->getParent();
398   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
399 
400   if (isFrameInstr(MI)) {
401     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
402     SPAdj -= getFrameAdjustment(MI);
403     if (!isFrameSetup(MI))
404       SPAdj = -SPAdj;
405     return SPAdj;
406   }
407 
408   // To know whether a call adjusts the stack, we need information
409   // that is bound to the following ADJCALLSTACKUP pseudo.
410   // Look for the next ADJCALLSTACKUP that follows the call.
411   if (MI.isCall()) {
412     const MachineBasicBlock *MBB = MI.getParent();
413     auto I = ++MachineBasicBlock::const_iterator(MI);
414     for (auto E = MBB->end(); I != E; ++I) {
415       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
416           I->isCall())
417         break;
418     }
419 
420     // If we could not find a frame destroy opcode, then it has already
421     // been simplified, so we don't care.
422     if (I->getOpcode() != getCallFrameDestroyOpcode())
423       return 0;
424 
425     return -(I->getOperand(1).getImm());
426   }
427 
428   // Currently handle only PUSHes we can reasonably expect to see
429   // in call sequences
430   switch (MI.getOpcode()) {
431   default:
432     return 0;
433   case X86::PUSH32i8:
434   case X86::PUSH32r:
435   case X86::PUSH32rmm:
436   case X86::PUSH32rmr:
437   case X86::PUSHi32:
438     return 4;
439   case X86::PUSH64i8:
440   case X86::PUSH64r:
441   case X86::PUSH64rmm:
442   case X86::PUSH64rmr:
443   case X86::PUSH64i32:
444     return 8;
445   }
446 }
447 
448 /// Return true and the FrameIndex if the specified
449 /// operand and follow operands form a reference to the stack frame.
450 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
451                                   int &FrameIndex) const {
452   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
453       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
454       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
455       MI.getOperand(Op + X86::AddrDisp).isImm() &&
456       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
457       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
458       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
459     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
460     return true;
461   }
462   return false;
463 }
464 
465 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
466   switch (Opcode) {
467   default:
468     return false;
469   case X86::MOV8rm:
470   case X86::KMOVBkm:
471     MemBytes = 1;
472     return true;
473   case X86::MOV16rm:
474   case X86::KMOVWkm:
475   case X86::VMOVSHZrm:
476   case X86::VMOVSHZrm_alt:
477     MemBytes = 2;
478     return true;
479   case X86::MOV32rm:
480   case X86::MOVSSrm:
481   case X86::MOVSSrm_alt:
482   case X86::VMOVSSrm:
483   case X86::VMOVSSrm_alt:
484   case X86::VMOVSSZrm:
485   case X86::VMOVSSZrm_alt:
486   case X86::KMOVDkm:
487     MemBytes = 4;
488     return true;
489   case X86::MOV64rm:
490   case X86::LD_Fp64m:
491   case X86::MOVSDrm:
492   case X86::MOVSDrm_alt:
493   case X86::VMOVSDrm:
494   case X86::VMOVSDrm_alt:
495   case X86::VMOVSDZrm:
496   case X86::VMOVSDZrm_alt:
497   case X86::MMX_MOVD64rm:
498   case X86::MMX_MOVQ64rm:
499   case X86::KMOVQkm:
500     MemBytes = 8;
501     return true;
502   case X86::MOVAPSrm:
503   case X86::MOVUPSrm:
504   case X86::MOVAPDrm:
505   case X86::MOVUPDrm:
506   case X86::MOVDQArm:
507   case X86::MOVDQUrm:
508   case X86::VMOVAPSrm:
509   case X86::VMOVUPSrm:
510   case X86::VMOVAPDrm:
511   case X86::VMOVUPDrm:
512   case X86::VMOVDQArm:
513   case X86::VMOVDQUrm:
514   case X86::VMOVAPSZ128rm:
515   case X86::VMOVUPSZ128rm:
516   case X86::VMOVAPSZ128rm_NOVLX:
517   case X86::VMOVUPSZ128rm_NOVLX:
518   case X86::VMOVAPDZ128rm:
519   case X86::VMOVUPDZ128rm:
520   case X86::VMOVDQU8Z128rm:
521   case X86::VMOVDQU16Z128rm:
522   case X86::VMOVDQA32Z128rm:
523   case X86::VMOVDQU32Z128rm:
524   case X86::VMOVDQA64Z128rm:
525   case X86::VMOVDQU64Z128rm:
526     MemBytes = 16;
527     return true;
528   case X86::VMOVAPSYrm:
529   case X86::VMOVUPSYrm:
530   case X86::VMOVAPDYrm:
531   case X86::VMOVUPDYrm:
532   case X86::VMOVDQAYrm:
533   case X86::VMOVDQUYrm:
534   case X86::VMOVAPSZ256rm:
535   case X86::VMOVUPSZ256rm:
536   case X86::VMOVAPSZ256rm_NOVLX:
537   case X86::VMOVUPSZ256rm_NOVLX:
538   case X86::VMOVAPDZ256rm:
539   case X86::VMOVUPDZ256rm:
540   case X86::VMOVDQU8Z256rm:
541   case X86::VMOVDQU16Z256rm:
542   case X86::VMOVDQA32Z256rm:
543   case X86::VMOVDQU32Z256rm:
544   case X86::VMOVDQA64Z256rm:
545   case X86::VMOVDQU64Z256rm:
546     MemBytes = 32;
547     return true;
548   case X86::VMOVAPSZrm:
549   case X86::VMOVUPSZrm:
550   case X86::VMOVAPDZrm:
551   case X86::VMOVUPDZrm:
552   case X86::VMOVDQU8Zrm:
553   case X86::VMOVDQU16Zrm:
554   case X86::VMOVDQA32Zrm:
555   case X86::VMOVDQU32Zrm:
556   case X86::VMOVDQA64Zrm:
557   case X86::VMOVDQU64Zrm:
558     MemBytes = 64;
559     return true;
560   }
561 }
562 
563 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
564   switch (Opcode) {
565   default:
566     return false;
567   case X86::MOV8mr:
568   case X86::KMOVBmk:
569     MemBytes = 1;
570     return true;
571   case X86::MOV16mr:
572   case X86::KMOVWmk:
573   case X86::VMOVSHZmr:
574     MemBytes = 2;
575     return true;
576   case X86::MOV32mr:
577   case X86::MOVSSmr:
578   case X86::VMOVSSmr:
579   case X86::VMOVSSZmr:
580   case X86::KMOVDmk:
581     MemBytes = 4;
582     return true;
583   case X86::MOV64mr:
584   case X86::ST_FpP64m:
585   case X86::MOVSDmr:
586   case X86::VMOVSDmr:
587   case X86::VMOVSDZmr:
588   case X86::MMX_MOVD64mr:
589   case X86::MMX_MOVQ64mr:
590   case X86::MMX_MOVNTQmr:
591   case X86::KMOVQmk:
592     MemBytes = 8;
593     return true;
594   case X86::MOVAPSmr:
595   case X86::MOVUPSmr:
596   case X86::MOVAPDmr:
597   case X86::MOVUPDmr:
598   case X86::MOVDQAmr:
599   case X86::MOVDQUmr:
600   case X86::VMOVAPSmr:
601   case X86::VMOVUPSmr:
602   case X86::VMOVAPDmr:
603   case X86::VMOVUPDmr:
604   case X86::VMOVDQAmr:
605   case X86::VMOVDQUmr:
606   case X86::VMOVUPSZ128mr:
607   case X86::VMOVAPSZ128mr:
608   case X86::VMOVUPSZ128mr_NOVLX:
609   case X86::VMOVAPSZ128mr_NOVLX:
610   case X86::VMOVUPDZ128mr:
611   case X86::VMOVAPDZ128mr:
612   case X86::VMOVDQA32Z128mr:
613   case X86::VMOVDQU32Z128mr:
614   case X86::VMOVDQA64Z128mr:
615   case X86::VMOVDQU64Z128mr:
616   case X86::VMOVDQU8Z128mr:
617   case X86::VMOVDQU16Z128mr:
618     MemBytes = 16;
619     return true;
620   case X86::VMOVUPSYmr:
621   case X86::VMOVAPSYmr:
622   case X86::VMOVUPDYmr:
623   case X86::VMOVAPDYmr:
624   case X86::VMOVDQUYmr:
625   case X86::VMOVDQAYmr:
626   case X86::VMOVUPSZ256mr:
627   case X86::VMOVAPSZ256mr:
628   case X86::VMOVUPSZ256mr_NOVLX:
629   case X86::VMOVAPSZ256mr_NOVLX:
630   case X86::VMOVUPDZ256mr:
631   case X86::VMOVAPDZ256mr:
632   case X86::VMOVDQU8Z256mr:
633   case X86::VMOVDQU16Z256mr:
634   case X86::VMOVDQA32Z256mr:
635   case X86::VMOVDQU32Z256mr:
636   case X86::VMOVDQA64Z256mr:
637   case X86::VMOVDQU64Z256mr:
638     MemBytes = 32;
639     return true;
640   case X86::VMOVUPSZmr:
641   case X86::VMOVAPSZmr:
642   case X86::VMOVUPDZmr:
643   case X86::VMOVAPDZmr:
644   case X86::VMOVDQU8Zmr:
645   case X86::VMOVDQU16Zmr:
646   case X86::VMOVDQA32Zmr:
647   case X86::VMOVDQU32Zmr:
648   case X86::VMOVDQA64Zmr:
649   case X86::VMOVDQU64Zmr:
650     MemBytes = 64;
651     return true;
652   }
653   return false;
654 }
655 
656 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
657                                            int &FrameIndex) const {
658   unsigned Dummy;
659   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
660 }
661 
662 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
663                                            int &FrameIndex,
664                                            unsigned &MemBytes) const {
665   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
666     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
667       return MI.getOperand(0).getReg();
668   return 0;
669 }
670 
671 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
672                                                  int &FrameIndex) const {
673   unsigned Dummy;
674   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
675     unsigned Reg;
676     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
677       return Reg;
678     // Check for post-frame index elimination operations
679     SmallVector<const MachineMemOperand *, 1> Accesses;
680     if (hasLoadFromStackSlot(MI, Accesses)) {
681       FrameIndex =
682           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
683               ->getFrameIndex();
684       return MI.getOperand(0).getReg();
685     }
686   }
687   return 0;
688 }
689 
690 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
691                                           int &FrameIndex) const {
692   unsigned Dummy;
693   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
694 }
695 
696 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
697                                           int &FrameIndex,
698                                           unsigned &MemBytes) const {
699   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
700     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
701         isFrameOperand(MI, 0, FrameIndex))
702       return MI.getOperand(X86::AddrNumOperands).getReg();
703   return 0;
704 }
705 
706 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
707                                                 int &FrameIndex) const {
708   unsigned Dummy;
709   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
710     unsigned Reg;
711     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
712       return Reg;
713     // Check for post-frame index elimination operations
714     SmallVector<const MachineMemOperand *, 1> Accesses;
715     if (hasStoreToStackSlot(MI, Accesses)) {
716       FrameIndex =
717           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
718               ->getFrameIndex();
719       return MI.getOperand(X86::AddrNumOperands).getReg();
720     }
721   }
722   return 0;
723 }
724 
725 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
726 static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
727   // Don't waste compile time scanning use-def chains of physregs.
728   if (!BaseReg.isVirtual())
729     return false;
730   bool isPICBase = false;
731   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
732          E = MRI.def_instr_end(); I != E; ++I) {
733     MachineInstr *DefMI = &*I;
734     if (DefMI->getOpcode() != X86::MOVPC32r)
735       return false;
736     assert(!isPICBase && "More than one PIC base?");
737     isPICBase = true;
738   }
739   return isPICBase;
740 }
741 
742 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
743                                                      AAResults *AA) const {
744   switch (MI.getOpcode()) {
745   default:
746     // This function should only be called for opcodes with the ReMaterializable
747     // flag set.
748     llvm_unreachable("Unknown rematerializable operation!");
749     break;
750 
751   case X86::LOAD_STACK_GUARD:
752   case X86::AVX1_SETALLONES:
753   case X86::AVX2_SETALLONES:
754   case X86::AVX512_128_SET0:
755   case X86::AVX512_256_SET0:
756   case X86::AVX512_512_SET0:
757   case X86::AVX512_512_SETALLONES:
758   case X86::AVX512_FsFLD0SD:
759   case X86::AVX512_FsFLD0SH:
760   case X86::AVX512_FsFLD0SS:
761   case X86::AVX512_FsFLD0F128:
762   case X86::AVX_SET0:
763   case X86::FsFLD0SD:
764   case X86::FsFLD0SS:
765   case X86::FsFLD0F128:
766   case X86::KSET0D:
767   case X86::KSET0Q:
768   case X86::KSET0W:
769   case X86::KSET1D:
770   case X86::KSET1Q:
771   case X86::KSET1W:
772   case X86::MMX_SET0:
773   case X86::MOV32ImmSExti8:
774   case X86::MOV32r0:
775   case X86::MOV32r1:
776   case X86::MOV32r_1:
777   case X86::MOV32ri64:
778   case X86::MOV64ImmSExti8:
779   case X86::V_SET0:
780   case X86::V_SETALLONES:
781   case X86::MOV16ri:
782   case X86::MOV32ri:
783   case X86::MOV64ri:
784   case X86::MOV64ri32:
785   case X86::MOV8ri:
786   case X86::PTILEZEROV:
787     return true;
788 
789   case X86::MOV8rm:
790   case X86::MOV8rm_NOREX:
791   case X86::MOV16rm:
792   case X86::MOV32rm:
793   case X86::MOV64rm:
794   case X86::MOVSSrm:
795   case X86::MOVSSrm_alt:
796   case X86::MOVSDrm:
797   case X86::MOVSDrm_alt:
798   case X86::MOVAPSrm:
799   case X86::MOVUPSrm:
800   case X86::MOVAPDrm:
801   case X86::MOVUPDrm:
802   case X86::MOVDQArm:
803   case X86::MOVDQUrm:
804   case X86::VMOVSSrm:
805   case X86::VMOVSSrm_alt:
806   case X86::VMOVSDrm:
807   case X86::VMOVSDrm_alt:
808   case X86::VMOVAPSrm:
809   case X86::VMOVUPSrm:
810   case X86::VMOVAPDrm:
811   case X86::VMOVUPDrm:
812   case X86::VMOVDQArm:
813   case X86::VMOVDQUrm:
814   case X86::VMOVAPSYrm:
815   case X86::VMOVUPSYrm:
816   case X86::VMOVAPDYrm:
817   case X86::VMOVUPDYrm:
818   case X86::VMOVDQAYrm:
819   case X86::VMOVDQUYrm:
820   case X86::MMX_MOVD64rm:
821   case X86::MMX_MOVQ64rm:
822   // AVX-512
823   case X86::VMOVSSZrm:
824   case X86::VMOVSSZrm_alt:
825   case X86::VMOVSDZrm:
826   case X86::VMOVSDZrm_alt:
827   case X86::VMOVSHZrm:
828   case X86::VMOVSHZrm_alt:
829   case X86::VMOVAPDZ128rm:
830   case X86::VMOVAPDZ256rm:
831   case X86::VMOVAPDZrm:
832   case X86::VMOVAPSZ128rm:
833   case X86::VMOVAPSZ256rm:
834   case X86::VMOVAPSZ128rm_NOVLX:
835   case X86::VMOVAPSZ256rm_NOVLX:
836   case X86::VMOVAPSZrm:
837   case X86::VMOVDQA32Z128rm:
838   case X86::VMOVDQA32Z256rm:
839   case X86::VMOVDQA32Zrm:
840   case X86::VMOVDQA64Z128rm:
841   case X86::VMOVDQA64Z256rm:
842   case X86::VMOVDQA64Zrm:
843   case X86::VMOVDQU16Z128rm:
844   case X86::VMOVDQU16Z256rm:
845   case X86::VMOVDQU16Zrm:
846   case X86::VMOVDQU32Z128rm:
847   case X86::VMOVDQU32Z256rm:
848   case X86::VMOVDQU32Zrm:
849   case X86::VMOVDQU64Z128rm:
850   case X86::VMOVDQU64Z256rm:
851   case X86::VMOVDQU64Zrm:
852   case X86::VMOVDQU8Z128rm:
853   case X86::VMOVDQU8Z256rm:
854   case X86::VMOVDQU8Zrm:
855   case X86::VMOVUPDZ128rm:
856   case X86::VMOVUPDZ256rm:
857   case X86::VMOVUPDZrm:
858   case X86::VMOVUPSZ128rm:
859   case X86::VMOVUPSZ256rm:
860   case X86::VMOVUPSZ128rm_NOVLX:
861   case X86::VMOVUPSZ256rm_NOVLX:
862   case X86::VMOVUPSZrm: {
863     // Loads from constant pools are trivially rematerializable.
864     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
865         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
866         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
867         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
868         MI.isDereferenceableInvariantLoad(AA)) {
869       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
870       if (BaseReg == 0 || BaseReg == X86::RIP)
871         return true;
872       // Allow re-materialization of PIC load.
873       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
874         return false;
875       const MachineFunction &MF = *MI.getParent()->getParent();
876       const MachineRegisterInfo &MRI = MF.getRegInfo();
877       return regIsPICBase(BaseReg, MRI);
878     }
879     return false;
880   }
881 
882   case X86::LEA32r:
883   case X86::LEA64r: {
884     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
885         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
886         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
887         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
888       // lea fi#, lea GV, etc. are all rematerializable.
889       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
890         return true;
891       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
892       if (BaseReg == 0)
893         return true;
894       // Allow re-materialization of lea PICBase + x.
895       const MachineFunction &MF = *MI.getParent()->getParent();
896       const MachineRegisterInfo &MRI = MF.getRegInfo();
897       return regIsPICBase(BaseReg, MRI);
898     }
899     return false;
900   }
901   }
902 }
903 
904 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
905                                  MachineBasicBlock::iterator I,
906                                  Register DestReg, unsigned SubIdx,
907                                  const MachineInstr &Orig,
908                                  const TargetRegisterInfo &TRI) const {
909   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
910   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
911                             MachineBasicBlock::LQR_Dead) {
912     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
913     // effects.
914     int Value;
915     switch (Orig.getOpcode()) {
916     case X86::MOV32r0:  Value = 0; break;
917     case X86::MOV32r1:  Value = 1; break;
918     case X86::MOV32r_1: Value = -1; break;
919     default:
920       llvm_unreachable("Unexpected instruction!");
921     }
922 
923     const DebugLoc &DL = Orig.getDebugLoc();
924     BuildMI(MBB, I, DL, get(X86::MOV32ri))
925         .add(Orig.getOperand(0))
926         .addImm(Value);
927   } else {
928     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
929     MBB.insert(I, MI);
930   }
931 
932   MachineInstr &NewMI = *std::prev(I);
933   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
934 }
935 
936 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
937 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
938   for (const MachineOperand &MO : MI.operands()) {
939     if (MO.isReg() && MO.isDef() &&
940         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
941       return true;
942     }
943   }
944   return false;
945 }
946 
947 /// Check whether the shift count for a machine operand is non-zero.
948 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
949                                               unsigned ShiftAmtOperandIdx) {
950   // The shift count is six bits with the REX.W prefix and five bits without.
951   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
952   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
953   return Imm & ShiftCountMask;
954 }
955 
956 /// Check whether the given shift count is appropriate
957 /// can be represented by a LEA instruction.
958 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
959   // Left shift instructions can be transformed into load-effective-address
960   // instructions if we can encode them appropriately.
961   // A LEA instruction utilizes a SIB byte to encode its scale factor.
962   // The SIB.scale field is two bits wide which means that we can encode any
963   // shift amount less than 4.
964   return ShAmt < 4 && ShAmt > 0;
965 }
966 
967 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
968                                   unsigned Opc, bool AllowSP, Register &NewSrc,
969                                   bool &isKill, MachineOperand &ImplicitOp,
970                                   LiveVariables *LV, LiveIntervals *LIS) const {
971   MachineFunction &MF = *MI.getParent()->getParent();
972   const TargetRegisterClass *RC;
973   if (AllowSP) {
974     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
975   } else {
976     RC = Opc != X86::LEA32r ?
977       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
978   }
979   Register SrcReg = Src.getReg();
980   isKill = MI.killsRegister(SrcReg);
981 
982   // For both LEA64 and LEA32 the register already has essentially the right
983   // type (32-bit or 64-bit) we may just need to forbid SP.
984   if (Opc != X86::LEA64_32r) {
985     NewSrc = SrcReg;
986     assert(!Src.isUndef() && "Undef op doesn't need optimization");
987 
988     if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
989       return false;
990 
991     return true;
992   }
993 
994   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
995   // another we need to add 64-bit registers to the final MI.
996   if (SrcReg.isPhysical()) {
997     ImplicitOp = Src;
998     ImplicitOp.setImplicit();
999 
1000     NewSrc = getX86SubSuperRegister(SrcReg, 64);
1001     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1002   } else {
1003     // Virtual register of the wrong class, we have to create a temporary 64-bit
1004     // vreg to feed into the LEA.
1005     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1006     MachineInstr *Copy =
1007         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1008             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1009             .addReg(SrcReg, getKillRegState(isKill));
1010 
1011     // Which is obviously going to be dead after we're done with it.
1012     isKill = true;
1013 
1014     if (LV)
1015       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1016 
1017     if (LIS) {
1018       SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy);
1019       SlotIndex Idx = LIS->getInstructionIndex(MI);
1020       LiveInterval &LI = LIS->getInterval(SrcReg);
1021       LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1022       if (S->end.getBaseIndex() == Idx)
1023         S->end = CopyIdx.getRegSlot();
1024     }
1025   }
1026 
1027   // We've set all the parameters without issue.
1028   return true;
1029 }
1030 
1031 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1032                                                          MachineInstr &MI,
1033                                                          LiveVariables *LV,
1034                                                          LiveIntervals *LIS,
1035                                                          bool Is8BitOp) const {
1036   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1037   MachineBasicBlock &MBB = *MI.getParent();
1038   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1039   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1040               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1041          "Unexpected type for LEA transform");
1042 
1043   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1044   // something like this:
1045   //   Opcode = X86::LEA32r;
1046   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1047   //   OutRegLEA =
1048   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1049   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1050   if (!Subtarget.is64Bit())
1051     return nullptr;
1052 
1053   unsigned Opcode = X86::LEA64_32r;
1054   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1055   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1056   Register InRegLEA2;
1057 
1058   // Build and insert into an implicit UNDEF value. This is OK because
1059   // we will be shifting and then extracting the lower 8/16-bits.
1060   // This has the potential to cause partial register stall. e.g.
1061   //   movw    (%rbp,%rcx,2), %dx
1062   //   leal    -65(%rdx), %esi
1063   // But testing has shown this *does* help performance in 64-bit mode (at
1064   // least on modern x86 machines).
1065   MachineBasicBlock::iterator MBBI = MI.getIterator();
1066   Register Dest = MI.getOperand(0).getReg();
1067   Register Src = MI.getOperand(1).getReg();
1068   Register Src2;
1069   bool IsDead = MI.getOperand(0).isDead();
1070   bool IsKill = MI.getOperand(1).isKill();
1071   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1072   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1073   MachineInstr *ImpDef =
1074       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1075   MachineInstr *InsMI =
1076       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1077           .addReg(InRegLEA, RegState::Define, SubReg)
1078           .addReg(Src, getKillRegState(IsKill));
1079   MachineInstr *ImpDef2 = nullptr;
1080   MachineInstr *InsMI2 = nullptr;
1081 
1082   MachineInstrBuilder MIB =
1083       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1084   switch (MIOpc) {
1085   default: llvm_unreachable("Unreachable!");
1086   case X86::SHL8ri:
1087   case X86::SHL16ri: {
1088     unsigned ShAmt = MI.getOperand(2).getImm();
1089     MIB.addReg(0).addImm(1ULL << ShAmt)
1090        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1091     break;
1092   }
1093   case X86::INC8r:
1094   case X86::INC16r:
1095     addRegOffset(MIB, InRegLEA, true, 1);
1096     break;
1097   case X86::DEC8r:
1098   case X86::DEC16r:
1099     addRegOffset(MIB, InRegLEA, true, -1);
1100     break;
1101   case X86::ADD8ri:
1102   case X86::ADD8ri_DB:
1103   case X86::ADD16ri:
1104   case X86::ADD16ri8:
1105   case X86::ADD16ri_DB:
1106   case X86::ADD16ri8_DB:
1107     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1108     break;
1109   case X86::ADD8rr:
1110   case X86::ADD8rr_DB:
1111   case X86::ADD16rr:
1112   case X86::ADD16rr_DB: {
1113     Src2 = MI.getOperand(2).getReg();
1114     bool IsKill2 = MI.getOperand(2).isKill();
1115     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1116     if (Src == Src2) {
1117       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1118       // just a single insert_subreg.
1119       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1120     } else {
1121       if (Subtarget.is64Bit())
1122         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1123       else
1124         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1125       // Build and insert into an implicit UNDEF value. This is OK because
1126       // we will be shifting and then extracting the lower 8/16-bits.
1127       ImpDef2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF),
1128                         InRegLEA2);
1129       InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1130                    .addReg(InRegLEA2, RegState::Define, SubReg)
1131                    .addReg(Src2, getKillRegState(IsKill2));
1132       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1133     }
1134     if (LV && IsKill2 && InsMI2)
1135       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1136     break;
1137   }
1138   }
1139 
1140   MachineInstr *NewMI = MIB;
1141   MachineInstr *ExtMI =
1142       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1143           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1144           .addReg(OutRegLEA, RegState::Kill, SubReg);
1145 
1146   if (LV) {
1147     // Update live variables.
1148     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1149     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1150     if (IsKill)
1151       LV->replaceKillInstruction(Src, MI, *InsMI);
1152     if (IsDead)
1153       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1154   }
1155 
1156   if (LIS) {
1157     LIS->InsertMachineInstrInMaps(*ImpDef);
1158     SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI);
1159     if (ImpDef2)
1160       LIS->InsertMachineInstrInMaps(*ImpDef2);
1161     SlotIndex Ins2Idx;
1162     if (InsMI2)
1163       Ins2Idx = LIS->InsertMachineInstrInMaps(*InsMI2);
1164     SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1165     SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(*ExtMI);
1166     LIS->getInterval(InRegLEA);
1167     LIS->getInterval(OutRegLEA);
1168     if (InRegLEA2)
1169       LIS->getInterval(InRegLEA2);
1170 
1171     // Move the use of Src up to InsMI.
1172     LiveInterval &SrcLI = LIS->getInterval(Src);
1173     LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(NewIdx);
1174     if (SrcSeg->end == NewIdx.getRegSlot())
1175       SrcSeg->end = InsIdx.getRegSlot();
1176 
1177     if (InsMI2) {
1178       // Move the use of Src2 up to InsMI2.
1179       LiveInterval &Src2LI = LIS->getInterval(Src2);
1180       LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(NewIdx);
1181       if (Src2Seg->end == NewIdx.getRegSlot())
1182         Src2Seg->end = Ins2Idx.getRegSlot();
1183     }
1184 
1185     // Move the definition of Dest down to ExtMI.
1186     LiveInterval &DestLI = LIS->getInterval(Dest);
1187     LiveRange::Segment *DestSeg =
1188         DestLI.getSegmentContaining(NewIdx.getRegSlot());
1189     assert(DestSeg->start == NewIdx.getRegSlot() &&
1190            DestSeg->valno->def == NewIdx.getRegSlot());
1191     DestSeg->start = ExtIdx.getRegSlot();
1192     DestSeg->valno->def = ExtIdx.getRegSlot();
1193   }
1194 
1195   return ExtMI;
1196 }
1197 
1198 /// This method must be implemented by targets that
1199 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1200 /// may be able to convert a two-address instruction into a true
1201 /// three-address instruction on demand.  This allows the X86 target (for
1202 /// example) to convert ADD and SHL instructions into LEA instructions if they
1203 /// would require register copies due to two-addressness.
1204 ///
1205 /// This method returns a null pointer if the transformation cannot be
1206 /// performed, otherwise it returns the new instruction.
1207 ///
1208 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1209                                                   LiveVariables *LV,
1210                                                   LiveIntervals *LIS) const {
1211   // The following opcodes also sets the condition code register(s). Only
1212   // convert them to equivalent lea if the condition code register def's
1213   // are dead!
1214   if (hasLiveCondCodeDef(MI))
1215     return nullptr;
1216 
1217   MachineFunction &MF = *MI.getParent()->getParent();
1218   // All instructions input are two-addr instructions.  Get the known operands.
1219   const MachineOperand &Dest = MI.getOperand(0);
1220   const MachineOperand &Src = MI.getOperand(1);
1221 
1222   // Ideally, operations with undef should be folded before we get here, but we
1223   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1224   // Without this, we have to forward undef state to new register operands to
1225   // avoid machine verifier errors.
1226   if (Src.isUndef())
1227     return nullptr;
1228   if (MI.getNumOperands() > 2)
1229     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1230       return nullptr;
1231 
1232   MachineInstr *NewMI = nullptr;
1233   Register SrcReg, SrcReg2;
1234   bool Is64Bit = Subtarget.is64Bit();
1235 
1236   bool Is8BitOp = false;
1237   unsigned MIOpc = MI.getOpcode();
1238   switch (MIOpc) {
1239   default: llvm_unreachable("Unreachable!");
1240   case X86::SHL64ri: {
1241     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1242     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1243     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1244 
1245     // LEA can't handle RSP.
1246     if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1247                                         Src.getReg(), &X86::GR64_NOSPRegClass))
1248       return nullptr;
1249 
1250     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1251                 .add(Dest)
1252                 .addReg(0)
1253                 .addImm(1ULL << ShAmt)
1254                 .add(Src)
1255                 .addImm(0)
1256                 .addReg(0);
1257     break;
1258   }
1259   case X86::SHL32ri: {
1260     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1261     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1262     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1263 
1264     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1265 
1266     // LEA can't handle ESP.
1267     bool isKill;
1268     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1269     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1270                         ImplicitOp, LV, LIS))
1271       return nullptr;
1272 
1273     MachineInstrBuilder MIB =
1274         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1275             .add(Dest)
1276             .addReg(0)
1277             .addImm(1ULL << ShAmt)
1278             .addReg(SrcReg, getKillRegState(isKill))
1279             .addImm(0)
1280             .addReg(0);
1281     if (ImplicitOp.getReg() != 0)
1282       MIB.add(ImplicitOp);
1283     NewMI = MIB;
1284 
1285     break;
1286   }
1287   case X86::SHL8ri:
1288     Is8BitOp = true;
1289     LLVM_FALLTHROUGH;
1290   case X86::SHL16ri: {
1291     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1292     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1293     if (!isTruncatedShiftCountForLEA(ShAmt))
1294       return nullptr;
1295     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1296   }
1297   case X86::INC64r:
1298   case X86::INC32r: {
1299     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1300     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1301         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1302     bool isKill;
1303     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1304     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1305                         ImplicitOp, LV, LIS))
1306       return nullptr;
1307 
1308     MachineInstrBuilder MIB =
1309         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1310             .add(Dest)
1311             .addReg(SrcReg, getKillRegState(isKill));
1312     if (ImplicitOp.getReg() != 0)
1313       MIB.add(ImplicitOp);
1314 
1315     NewMI = addOffset(MIB, 1);
1316     break;
1317   }
1318   case X86::DEC64r:
1319   case X86::DEC32r: {
1320     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1321     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1322         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1323 
1324     bool isKill;
1325     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1326     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1327                         ImplicitOp, LV, LIS))
1328       return nullptr;
1329 
1330     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1331                                   .add(Dest)
1332                                   .addReg(SrcReg, getKillRegState(isKill));
1333     if (ImplicitOp.getReg() != 0)
1334       MIB.add(ImplicitOp);
1335 
1336     NewMI = addOffset(MIB, -1);
1337 
1338     break;
1339   }
1340   case X86::DEC8r:
1341   case X86::INC8r:
1342     Is8BitOp = true;
1343     LLVM_FALLTHROUGH;
1344   case X86::DEC16r:
1345   case X86::INC16r:
1346     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1347   case X86::ADD64rr:
1348   case X86::ADD64rr_DB:
1349   case X86::ADD32rr:
1350   case X86::ADD32rr_DB: {
1351     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1352     unsigned Opc;
1353     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1354       Opc = X86::LEA64r;
1355     else
1356       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1357 
1358     const MachineOperand &Src2 = MI.getOperand(2);
1359     bool isKill2;
1360     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1361     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, isKill2,
1362                         ImplicitOp2, LV, LIS))
1363       return nullptr;
1364 
1365     bool isKill;
1366     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1367     if (Src.getReg() == Src2.getReg()) {
1368       // Don't call classify LEAReg a second time on the same register, in case
1369       // the first call inserted a COPY from Src2 and marked it as killed.
1370       isKill = isKill2;
1371       SrcReg = SrcReg2;
1372     } else {
1373       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1374                           ImplicitOp, LV, LIS))
1375         return nullptr;
1376     }
1377 
1378     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1379     if (ImplicitOp.getReg() != 0)
1380       MIB.add(ImplicitOp);
1381     if (ImplicitOp2.getReg() != 0)
1382       MIB.add(ImplicitOp2);
1383 
1384     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1385     if (LV && Src2.isKill())
1386       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1387     break;
1388   }
1389   case X86::ADD8rr:
1390   case X86::ADD8rr_DB:
1391     Is8BitOp = true;
1392     LLVM_FALLTHROUGH;
1393   case X86::ADD16rr:
1394   case X86::ADD16rr_DB:
1395     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1396   case X86::ADD64ri32:
1397   case X86::ADD64ri8:
1398   case X86::ADD64ri32_DB:
1399   case X86::ADD64ri8_DB:
1400     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1401     NewMI = addOffset(
1402         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1403         MI.getOperand(2));
1404     break;
1405   case X86::ADD32ri:
1406   case X86::ADD32ri8:
1407   case X86::ADD32ri_DB:
1408   case X86::ADD32ri8_DB: {
1409     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1410     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1411 
1412     bool isKill;
1413     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1414     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1415                         ImplicitOp, LV, LIS))
1416       return nullptr;
1417 
1418     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1419                                   .add(Dest)
1420                                   .addReg(SrcReg, getKillRegState(isKill));
1421     if (ImplicitOp.getReg() != 0)
1422       MIB.add(ImplicitOp);
1423 
1424     NewMI = addOffset(MIB, MI.getOperand(2));
1425     break;
1426   }
1427   case X86::ADD8ri:
1428   case X86::ADD8ri_DB:
1429     Is8BitOp = true;
1430     LLVM_FALLTHROUGH;
1431   case X86::ADD16ri:
1432   case X86::ADD16ri8:
1433   case X86::ADD16ri_DB:
1434   case X86::ADD16ri8_DB:
1435     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1436   case X86::SUB8ri:
1437   case X86::SUB16ri8:
1438   case X86::SUB16ri:
1439     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1440     return nullptr;
1441   case X86::SUB32ri8:
1442   case X86::SUB32ri: {
1443     if (!MI.getOperand(2).isImm())
1444       return nullptr;
1445     int64_t Imm = MI.getOperand(2).getImm();
1446     if (!isInt<32>(-Imm))
1447       return nullptr;
1448 
1449     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1450     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1451 
1452     bool isKill;
1453     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1454     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1455                         ImplicitOp, LV, LIS))
1456       return nullptr;
1457 
1458     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1459                                   .add(Dest)
1460                                   .addReg(SrcReg, getKillRegState(isKill));
1461     if (ImplicitOp.getReg() != 0)
1462       MIB.add(ImplicitOp);
1463 
1464     NewMI = addOffset(MIB, -Imm);
1465     break;
1466   }
1467 
1468   case X86::SUB64ri8:
1469   case X86::SUB64ri32: {
1470     if (!MI.getOperand(2).isImm())
1471       return nullptr;
1472     int64_t Imm = MI.getOperand(2).getImm();
1473     if (!isInt<32>(-Imm))
1474       return nullptr;
1475 
1476     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1477 
1478     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1479                                       get(X86::LEA64r)).add(Dest).add(Src);
1480     NewMI = addOffset(MIB, -Imm);
1481     break;
1482   }
1483 
1484   case X86::VMOVDQU8Z128rmk:
1485   case X86::VMOVDQU8Z256rmk:
1486   case X86::VMOVDQU8Zrmk:
1487   case X86::VMOVDQU16Z128rmk:
1488   case X86::VMOVDQU16Z256rmk:
1489   case X86::VMOVDQU16Zrmk:
1490   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1491   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1492   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1493   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1494   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1495   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1496   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1497   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1498   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1499   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1500   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1501   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1502   case X86::VBROADCASTSDZ256rmk:
1503   case X86::VBROADCASTSDZrmk:
1504   case X86::VBROADCASTSSZ128rmk:
1505   case X86::VBROADCASTSSZ256rmk:
1506   case X86::VBROADCASTSSZrmk:
1507   case X86::VPBROADCASTDZ128rmk:
1508   case X86::VPBROADCASTDZ256rmk:
1509   case X86::VPBROADCASTDZrmk:
1510   case X86::VPBROADCASTQZ128rmk:
1511   case X86::VPBROADCASTQZ256rmk:
1512   case X86::VPBROADCASTQZrmk: {
1513     unsigned Opc;
1514     switch (MIOpc) {
1515     default: llvm_unreachable("Unreachable!");
1516     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1517     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1518     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1519     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1520     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1521     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1522     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1523     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1524     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1525     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1526     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1527     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1528     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1529     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1530     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1531     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1532     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1533     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1534     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1535     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1536     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1537     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1538     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1539     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1540     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1541     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1542     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1543     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1544     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1545     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1546     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1547     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1548     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1549     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1550     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1551     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1552     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1553     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1554     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1555     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1556     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1557     }
1558 
1559     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1560               .add(Dest)
1561               .add(MI.getOperand(2))
1562               .add(Src)
1563               .add(MI.getOperand(3))
1564               .add(MI.getOperand(4))
1565               .add(MI.getOperand(5))
1566               .add(MI.getOperand(6))
1567               .add(MI.getOperand(7));
1568     break;
1569   }
1570 
1571   case X86::VMOVDQU8Z128rrk:
1572   case X86::VMOVDQU8Z256rrk:
1573   case X86::VMOVDQU8Zrrk:
1574   case X86::VMOVDQU16Z128rrk:
1575   case X86::VMOVDQU16Z256rrk:
1576   case X86::VMOVDQU16Zrrk:
1577   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1578   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1579   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1580   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1581   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1582   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1583   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1584   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1585   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1586   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1587   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1588   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1589     unsigned Opc;
1590     switch (MIOpc) {
1591     default: llvm_unreachable("Unreachable!");
1592     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1593     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1594     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1595     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1596     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1597     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1598     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1599     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1600     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1601     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1602     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1603     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1604     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1605     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1606     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1607     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1608     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1609     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1610     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1611     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1612     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1613     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1614     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1615     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1616     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1617     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1618     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1619     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1620     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1621     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1622     }
1623 
1624     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1625               .add(Dest)
1626               .add(MI.getOperand(2))
1627               .add(Src)
1628               .add(MI.getOperand(3));
1629     break;
1630   }
1631   }
1632 
1633   if (!NewMI) return nullptr;
1634 
1635   if (LV) {  // Update live variables
1636     if (Src.isKill())
1637       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1638     if (Dest.isDead())
1639       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1640   }
1641 
1642   MachineBasicBlock &MBB = *MI.getParent();
1643   MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
1644 
1645   if (LIS) {
1646     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1647     if (SrcReg)
1648       LIS->getInterval(SrcReg);
1649     if (SrcReg2)
1650       LIS->getInterval(SrcReg2);
1651   }
1652 
1653   return NewMI;
1654 }
1655 
1656 /// This determines which of three possible cases of a three source commute
1657 /// the source indexes correspond to taking into account any mask operands.
1658 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1659 /// possible.
1660 /// Case 0 - Possible to commute the first and second operands.
1661 /// Case 1 - Possible to commute the first and third operands.
1662 /// Case 2 - Possible to commute the second and third operands.
1663 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1664                                        unsigned SrcOpIdx2) {
1665   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1666   if (SrcOpIdx1 > SrcOpIdx2)
1667     std::swap(SrcOpIdx1, SrcOpIdx2);
1668 
1669   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1670   if (X86II::isKMasked(TSFlags)) {
1671     Op2++;
1672     Op3++;
1673   }
1674 
1675   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1676     return 0;
1677   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1678     return 1;
1679   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1680     return 2;
1681   llvm_unreachable("Unknown three src commute case.");
1682 }
1683 
1684 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1685     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1686     const X86InstrFMA3Group &FMA3Group) const {
1687 
1688   unsigned Opc = MI.getOpcode();
1689 
1690   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1691   // analysis. The commute optimization is legal only if all users of FMA*_Int
1692   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1693   // not implemented yet. So, just return 0 in that case.
1694   // When such analysis are available this place will be the right place for
1695   // calling it.
1696   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1697          "Intrinsic instructions can't commute operand 1");
1698 
1699   // Determine which case this commute is or if it can't be done.
1700   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1701                                          SrcOpIdx2);
1702   assert(Case < 3 && "Unexpected case number!");
1703 
1704   // Define the FMA forms mapping array that helps to map input FMA form
1705   // to output FMA form to preserve the operation semantics after
1706   // commuting the operands.
1707   const unsigned Form132Index = 0;
1708   const unsigned Form213Index = 1;
1709   const unsigned Form231Index = 2;
1710   static const unsigned FormMapping[][3] = {
1711     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1712     // FMA132 A, C, b; ==> FMA231 C, A, b;
1713     // FMA213 B, A, c; ==> FMA213 A, B, c;
1714     // FMA231 C, A, b; ==> FMA132 A, C, b;
1715     { Form231Index, Form213Index, Form132Index },
1716     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1717     // FMA132 A, c, B; ==> FMA132 B, c, A;
1718     // FMA213 B, a, C; ==> FMA231 C, a, B;
1719     // FMA231 C, a, B; ==> FMA213 B, a, C;
1720     { Form132Index, Form231Index, Form213Index },
1721     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1722     // FMA132 a, C, B; ==> FMA213 a, B, C;
1723     // FMA213 b, A, C; ==> FMA132 b, C, A;
1724     // FMA231 c, A, B; ==> FMA231 c, B, A;
1725     { Form213Index, Form132Index, Form231Index }
1726   };
1727 
1728   unsigned FMAForms[3];
1729   FMAForms[0] = FMA3Group.get132Opcode();
1730   FMAForms[1] = FMA3Group.get213Opcode();
1731   FMAForms[2] = FMA3Group.get231Opcode();
1732 
1733   // Everything is ready, just adjust the FMA opcode and return it.
1734   for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
1735     if (Opc == FMAForms[FormIndex])
1736       return FMAForms[FormMapping[Case][FormIndex]];
1737 
1738   llvm_unreachable("Illegal FMA3 format");
1739 }
1740 
1741 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1742                              unsigned SrcOpIdx2) {
1743   // Determine which case this commute is or if it can't be done.
1744   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1745                                          SrcOpIdx2);
1746   assert(Case < 3 && "Unexpected case value!");
1747 
1748   // For each case we need to swap two pairs of bits in the final immediate.
1749   static const uint8_t SwapMasks[3][4] = {
1750     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1751     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1752     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1753   };
1754 
1755   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1756   // Clear out the bits we are swapping.
1757   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1758                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1759   // If the immediate had a bit of the pair set, then set the opposite bit.
1760   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1761   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1762   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1763   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1764   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1765 }
1766 
1767 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1768 // commuted.
1769 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1770 #define VPERM_CASES(Suffix) \
1771   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1772   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1773   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1774   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1775   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1776   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1777   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1778   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1779   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1780   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1781   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1782   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1783 
1784 #define VPERM_CASES_BROADCAST(Suffix) \
1785   VPERM_CASES(Suffix) \
1786   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1787   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1788   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1789   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1790   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1791   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1792 
1793   switch (Opcode) {
1794   default: return false;
1795   VPERM_CASES(B)
1796   VPERM_CASES_BROADCAST(D)
1797   VPERM_CASES_BROADCAST(PD)
1798   VPERM_CASES_BROADCAST(PS)
1799   VPERM_CASES_BROADCAST(Q)
1800   VPERM_CASES(W)
1801     return true;
1802   }
1803 #undef VPERM_CASES_BROADCAST
1804 #undef VPERM_CASES
1805 }
1806 
1807 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1808 // from the I opcode to the T opcode and vice versa.
1809 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1810 #define VPERM_CASES(Orig, New) \
1811   case X86::Orig##128rr:    return X86::New##128rr;   \
1812   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1813   case X86::Orig##128rm:    return X86::New##128rm;   \
1814   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1815   case X86::Orig##256rr:    return X86::New##256rr;   \
1816   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1817   case X86::Orig##256rm:    return X86::New##256rm;   \
1818   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1819   case X86::Orig##rr:       return X86::New##rr;      \
1820   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1821   case X86::Orig##rm:       return X86::New##rm;      \
1822   case X86::Orig##rmkz:     return X86::New##rmkz;
1823 
1824 #define VPERM_CASES_BROADCAST(Orig, New) \
1825   VPERM_CASES(Orig, New) \
1826   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1827   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1828   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1829   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1830   case X86::Orig##rmb:      return X86::New##rmb;      \
1831   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1832 
1833   switch (Opcode) {
1834   VPERM_CASES(VPERMI2B, VPERMT2B)
1835   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1836   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1837   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1838   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1839   VPERM_CASES(VPERMI2W, VPERMT2W)
1840   VPERM_CASES(VPERMT2B, VPERMI2B)
1841   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
1842   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1843   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1844   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
1845   VPERM_CASES(VPERMT2W, VPERMI2W)
1846   }
1847 
1848   llvm_unreachable("Unreachable!");
1849 #undef VPERM_CASES_BROADCAST
1850 #undef VPERM_CASES
1851 }
1852 
1853 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1854                                                    unsigned OpIdx1,
1855                                                    unsigned OpIdx2) const {
1856   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1857     if (NewMI)
1858       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1859     return MI;
1860   };
1861 
1862   switch (MI.getOpcode()) {
1863   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1864   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1865   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1866   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1867   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1868   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1869     unsigned Opc;
1870     unsigned Size;
1871     switch (MI.getOpcode()) {
1872     default: llvm_unreachable("Unreachable!");
1873     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1874     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1875     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1876     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1877     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1878     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1879     }
1880     unsigned Amt = MI.getOperand(3).getImm();
1881     auto &WorkingMI = cloneIfNew(MI);
1882     WorkingMI.setDesc(get(Opc));
1883     WorkingMI.getOperand(3).setImm(Size - Amt);
1884     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1885                                                    OpIdx1, OpIdx2);
1886   }
1887   case X86::PFSUBrr:
1888   case X86::PFSUBRrr: {
1889     // PFSUB  x, y: x = x - y
1890     // PFSUBR x, y: x = y - x
1891     unsigned Opc =
1892         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1893     auto &WorkingMI = cloneIfNew(MI);
1894     WorkingMI.setDesc(get(Opc));
1895     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1896                                                    OpIdx1, OpIdx2);
1897   }
1898   case X86::BLENDPDrri:
1899   case X86::BLENDPSrri:
1900   case X86::VBLENDPDrri:
1901   case X86::VBLENDPSrri:
1902     // If we're optimizing for size, try to use MOVSD/MOVSS.
1903     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1904       unsigned Mask, Opc;
1905       switch (MI.getOpcode()) {
1906       default: llvm_unreachable("Unreachable!");
1907       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
1908       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
1909       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1910       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1911       }
1912       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1913         auto &WorkingMI = cloneIfNew(MI);
1914         WorkingMI.setDesc(get(Opc));
1915         WorkingMI.removeOperand(3);
1916         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1917                                                        /*NewMI=*/false,
1918                                                        OpIdx1, OpIdx2);
1919       }
1920     }
1921     LLVM_FALLTHROUGH;
1922   case X86::PBLENDWrri:
1923   case X86::VBLENDPDYrri:
1924   case X86::VBLENDPSYrri:
1925   case X86::VPBLENDDrri:
1926   case X86::VPBLENDWrri:
1927   case X86::VPBLENDDYrri:
1928   case X86::VPBLENDWYrri:{
1929     int8_t Mask;
1930     switch (MI.getOpcode()) {
1931     default: llvm_unreachable("Unreachable!");
1932     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
1933     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
1934     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
1935     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
1936     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
1937     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
1938     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
1939     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
1940     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
1941     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
1942     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
1943     }
1944     // Only the least significant bits of Imm are used.
1945     // Using int8_t to ensure it will be sign extended to the int64_t that
1946     // setImm takes in order to match isel behavior.
1947     int8_t Imm = MI.getOperand(3).getImm() & Mask;
1948     auto &WorkingMI = cloneIfNew(MI);
1949     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1950     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1951                                                    OpIdx1, OpIdx2);
1952   }
1953   case X86::INSERTPSrr:
1954   case X86::VINSERTPSrr:
1955   case X86::VINSERTPSZrr: {
1956     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1957     unsigned ZMask = Imm & 15;
1958     unsigned DstIdx = (Imm >> 4) & 3;
1959     unsigned SrcIdx = (Imm >> 6) & 3;
1960 
1961     // We can commute insertps if we zero 2 of the elements, the insertion is
1962     // "inline" and we don't override the insertion with a zero.
1963     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1964         countPopulation(ZMask) == 2) {
1965       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1966       assert(AltIdx < 4 && "Illegal insertion index");
1967       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1968       auto &WorkingMI = cloneIfNew(MI);
1969       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1970       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1971                                                      OpIdx1, OpIdx2);
1972     }
1973     return nullptr;
1974   }
1975   case X86::MOVSDrr:
1976   case X86::MOVSSrr:
1977   case X86::VMOVSDrr:
1978   case X86::VMOVSSrr:{
1979     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1980     if (Subtarget.hasSSE41()) {
1981       unsigned Mask, Opc;
1982       switch (MI.getOpcode()) {
1983       default: llvm_unreachable("Unreachable!");
1984       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
1985       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
1986       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1987       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1988       }
1989 
1990       auto &WorkingMI = cloneIfNew(MI);
1991       WorkingMI.setDesc(get(Opc));
1992       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1993       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1994                                                      OpIdx1, OpIdx2);
1995     }
1996 
1997     // Convert to SHUFPD.
1998     assert(MI.getOpcode() == X86::MOVSDrr &&
1999            "Can only commute MOVSDrr without SSE4.1");
2000 
2001     auto &WorkingMI = cloneIfNew(MI);
2002     WorkingMI.setDesc(get(X86::SHUFPDrri));
2003     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2004     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2005                                                    OpIdx1, OpIdx2);
2006   }
2007   case X86::SHUFPDrri: {
2008     // Commute to MOVSD.
2009     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2010     auto &WorkingMI = cloneIfNew(MI);
2011     WorkingMI.setDesc(get(X86::MOVSDrr));
2012     WorkingMI.removeOperand(3);
2013     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2014                                                    OpIdx1, OpIdx2);
2015   }
2016   case X86::PCLMULQDQrr:
2017   case X86::VPCLMULQDQrr:
2018   case X86::VPCLMULQDQYrr:
2019   case X86::VPCLMULQDQZrr:
2020   case X86::VPCLMULQDQZ128rr:
2021   case X86::VPCLMULQDQZ256rr: {
2022     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2023     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2024     unsigned Imm = MI.getOperand(3).getImm();
2025     unsigned Src1Hi = Imm & 0x01;
2026     unsigned Src2Hi = Imm & 0x10;
2027     auto &WorkingMI = cloneIfNew(MI);
2028     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2029     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2030                                                    OpIdx1, OpIdx2);
2031   }
2032   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2033   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2034   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2035   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2036   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2037   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2038   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2039   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2040   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2041   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2042   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2043   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2044   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2045   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2046   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2047   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2048   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2049   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2050   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2051   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2052   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2053   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2054   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2055   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2056     // Flip comparison mode immediate (if necessary).
2057     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2058     Imm = X86::getSwappedVPCMPImm(Imm);
2059     auto &WorkingMI = cloneIfNew(MI);
2060     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2061     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2062                                                    OpIdx1, OpIdx2);
2063   }
2064   case X86::VPCOMBri: case X86::VPCOMUBri:
2065   case X86::VPCOMDri: case X86::VPCOMUDri:
2066   case X86::VPCOMQri: case X86::VPCOMUQri:
2067   case X86::VPCOMWri: case X86::VPCOMUWri: {
2068     // Flip comparison mode immediate (if necessary).
2069     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2070     Imm = X86::getSwappedVPCOMImm(Imm);
2071     auto &WorkingMI = cloneIfNew(MI);
2072     WorkingMI.getOperand(3).setImm(Imm);
2073     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2074                                                    OpIdx1, OpIdx2);
2075   }
2076   case X86::VCMPSDZrr:
2077   case X86::VCMPSSZrr:
2078   case X86::VCMPPDZrri:
2079   case X86::VCMPPSZrri:
2080   case X86::VCMPSHZrr:
2081   case X86::VCMPPHZrri:
2082   case X86::VCMPPHZ128rri:
2083   case X86::VCMPPHZ256rri:
2084   case X86::VCMPPDZ128rri:
2085   case X86::VCMPPSZ128rri:
2086   case X86::VCMPPDZ256rri:
2087   case X86::VCMPPSZ256rri:
2088   case X86::VCMPPDZrrik:
2089   case X86::VCMPPSZrrik:
2090   case X86::VCMPPDZ128rrik:
2091   case X86::VCMPPSZ128rrik:
2092   case X86::VCMPPDZ256rrik:
2093   case X86::VCMPPSZ256rrik: {
2094     unsigned Imm =
2095                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2096     Imm = X86::getSwappedVCMPImm(Imm);
2097     auto &WorkingMI = cloneIfNew(MI);
2098     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2099     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2100                                                    OpIdx1, OpIdx2);
2101   }
2102   case X86::VPERM2F128rr:
2103   case X86::VPERM2I128rr: {
2104     // Flip permute source immediate.
2105     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2106     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2107     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2108     auto &WorkingMI = cloneIfNew(MI);
2109     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2110     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2111                                                    OpIdx1, OpIdx2);
2112   }
2113   case X86::MOVHLPSrr:
2114   case X86::UNPCKHPDrr:
2115   case X86::VMOVHLPSrr:
2116   case X86::VUNPCKHPDrr:
2117   case X86::VMOVHLPSZrr:
2118   case X86::VUNPCKHPDZ128rr: {
2119     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2120 
2121     unsigned Opc = MI.getOpcode();
2122     switch (Opc) {
2123     default: llvm_unreachable("Unreachable!");
2124     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2125     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2126     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2127     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2128     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2129     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2130     }
2131     auto &WorkingMI = cloneIfNew(MI);
2132     WorkingMI.setDesc(get(Opc));
2133     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2134                                                    OpIdx1, OpIdx2);
2135   }
2136   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2137     auto &WorkingMI = cloneIfNew(MI);
2138     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2139     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2140     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2141     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2142                                                    OpIdx1, OpIdx2);
2143   }
2144   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2145   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2146   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2147   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2148   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2149   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2150   case X86::VPTERNLOGDZrrik:
2151   case X86::VPTERNLOGDZ128rrik:
2152   case X86::VPTERNLOGDZ256rrik:
2153   case X86::VPTERNLOGQZrrik:
2154   case X86::VPTERNLOGQZ128rrik:
2155   case X86::VPTERNLOGQZ256rrik:
2156   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2157   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2158   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2159   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2160   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2161   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2162   case X86::VPTERNLOGDZ128rmbi:
2163   case X86::VPTERNLOGDZ256rmbi:
2164   case X86::VPTERNLOGDZrmbi:
2165   case X86::VPTERNLOGQZ128rmbi:
2166   case X86::VPTERNLOGQZ256rmbi:
2167   case X86::VPTERNLOGQZrmbi:
2168   case X86::VPTERNLOGDZ128rmbikz:
2169   case X86::VPTERNLOGDZ256rmbikz:
2170   case X86::VPTERNLOGDZrmbikz:
2171   case X86::VPTERNLOGQZ128rmbikz:
2172   case X86::VPTERNLOGQZ256rmbikz:
2173   case X86::VPTERNLOGQZrmbikz: {
2174     auto &WorkingMI = cloneIfNew(MI);
2175     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2176     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2177                                                    OpIdx1, OpIdx2);
2178   }
2179   default: {
2180     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2181       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2182       auto &WorkingMI = cloneIfNew(MI);
2183       WorkingMI.setDesc(get(Opc));
2184       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2185                                                      OpIdx1, OpIdx2);
2186     }
2187 
2188     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2189                                                       MI.getDesc().TSFlags);
2190     if (FMA3Group) {
2191       unsigned Opc =
2192         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2193       auto &WorkingMI = cloneIfNew(MI);
2194       WorkingMI.setDesc(get(Opc));
2195       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2196                                                      OpIdx1, OpIdx2);
2197     }
2198 
2199     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2200   }
2201   }
2202 }
2203 
2204 bool
2205 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2206                                             unsigned &SrcOpIdx1,
2207                                             unsigned &SrcOpIdx2,
2208                                             bool IsIntrinsic) const {
2209   uint64_t TSFlags = MI.getDesc().TSFlags;
2210 
2211   unsigned FirstCommutableVecOp = 1;
2212   unsigned LastCommutableVecOp = 3;
2213   unsigned KMaskOp = -1U;
2214   if (X86II::isKMasked(TSFlags)) {
2215     // For k-zero-masked operations it is Ok to commute the first vector
2216     // operand. Unless this is an intrinsic instruction.
2217     // For regular k-masked operations a conservative choice is done as the
2218     // elements of the first vector operand, for which the corresponding bit
2219     // in the k-mask operand is set to 0, are copied to the result of the
2220     // instruction.
2221     // TODO/FIXME: The commute still may be legal if it is known that the
2222     // k-mask operand is set to either all ones or all zeroes.
2223     // It is also Ok to commute the 1st operand if all users of MI use only
2224     // the elements enabled by the k-mask operand. For example,
2225     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2226     //                                                     : v1[i];
2227     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2228     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2229 
2230     // The k-mask operand has index = 2 for masked and zero-masked operations.
2231     KMaskOp = 2;
2232 
2233     // The operand with index = 1 is used as a source for those elements for
2234     // which the corresponding bit in the k-mask is set to 0.
2235     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2236       FirstCommutableVecOp = 3;
2237 
2238     LastCommutableVecOp++;
2239   } else if (IsIntrinsic) {
2240     // Commuting the first operand of an intrinsic instruction isn't possible
2241     // unless we can prove that only the lowest element of the result is used.
2242     FirstCommutableVecOp = 2;
2243   }
2244 
2245   if (isMem(MI, LastCommutableVecOp))
2246     LastCommutableVecOp--;
2247 
2248   // Only the first RegOpsNum operands are commutable.
2249   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2250   // that the operand is not specified/fixed.
2251   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2252       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2253        SrcOpIdx1 == KMaskOp))
2254     return false;
2255   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2256       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2257        SrcOpIdx2 == KMaskOp))
2258     return false;
2259 
2260   // Look for two different register operands assumed to be commutable
2261   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2262   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2263       SrcOpIdx2 == CommuteAnyOperandIndex) {
2264     unsigned CommutableOpIdx2 = SrcOpIdx2;
2265 
2266     // At least one of operands to be commuted is not specified and
2267     // this method is free to choose appropriate commutable operands.
2268     if (SrcOpIdx1 == SrcOpIdx2)
2269       // Both of operands are not fixed. By default set one of commutable
2270       // operands to the last register operand of the instruction.
2271       CommutableOpIdx2 = LastCommutableVecOp;
2272     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2273       // Only one of operands is not fixed.
2274       CommutableOpIdx2 = SrcOpIdx1;
2275 
2276     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2277     // operand and assign its index to CommutableOpIdx1.
2278     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2279 
2280     unsigned CommutableOpIdx1;
2281     for (CommutableOpIdx1 = LastCommutableVecOp;
2282          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2283       // Just ignore and skip the k-mask operand.
2284       if (CommutableOpIdx1 == KMaskOp)
2285         continue;
2286 
2287       // The commuted operands must have different registers.
2288       // Otherwise, the commute transformation does not change anything and
2289       // is useless then.
2290       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2291         break;
2292     }
2293 
2294     // No appropriate commutable operands were found.
2295     if (CommutableOpIdx1 < FirstCommutableVecOp)
2296       return false;
2297 
2298     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2299     // to return those values.
2300     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2301                               CommutableOpIdx1, CommutableOpIdx2))
2302       return false;
2303   }
2304 
2305   return true;
2306 }
2307 
2308 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2309                                          unsigned &SrcOpIdx1,
2310                                          unsigned &SrcOpIdx2) const {
2311   const MCInstrDesc &Desc = MI.getDesc();
2312   if (!Desc.isCommutable())
2313     return false;
2314 
2315   switch (MI.getOpcode()) {
2316   case X86::CMPSDrr:
2317   case X86::CMPSSrr:
2318   case X86::CMPPDrri:
2319   case X86::CMPPSrri:
2320   case X86::VCMPSDrr:
2321   case X86::VCMPSSrr:
2322   case X86::VCMPPDrri:
2323   case X86::VCMPPSrri:
2324   case X86::VCMPPDYrri:
2325   case X86::VCMPPSYrri:
2326   case X86::VCMPSDZrr:
2327   case X86::VCMPSSZrr:
2328   case X86::VCMPPDZrri:
2329   case X86::VCMPPSZrri:
2330   case X86::VCMPSHZrr:
2331   case X86::VCMPPHZrri:
2332   case X86::VCMPPHZ128rri:
2333   case X86::VCMPPHZ256rri:
2334   case X86::VCMPPDZ128rri:
2335   case X86::VCMPPSZ128rri:
2336   case X86::VCMPPDZ256rri:
2337   case X86::VCMPPSZ256rri:
2338   case X86::VCMPPDZrrik:
2339   case X86::VCMPPSZrrik:
2340   case X86::VCMPPDZ128rrik:
2341   case X86::VCMPPSZ128rrik:
2342   case X86::VCMPPDZ256rrik:
2343   case X86::VCMPPSZ256rrik: {
2344     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2345 
2346     // Float comparison can be safely commuted for
2347     // Ordered/Unordered/Equal/NotEqual tests
2348     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2349     switch (Imm) {
2350     default:
2351       // EVEX versions can be commuted.
2352       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2353         break;
2354       return false;
2355     case 0x00: // EQUAL
2356     case 0x03: // UNORDERED
2357     case 0x04: // NOT EQUAL
2358     case 0x07: // ORDERED
2359       break;
2360     }
2361 
2362     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2363     // when masked).
2364     // Assign them to the returned operand indices here.
2365     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2366                                 2 + OpOffset);
2367   }
2368   case X86::MOVSSrr:
2369     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2370     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2371     // AVX implies sse4.1.
2372     if (Subtarget.hasSSE41())
2373       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2374     return false;
2375   case X86::SHUFPDrri:
2376     // We can commute this to MOVSD.
2377     if (MI.getOperand(3).getImm() == 0x02)
2378       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2379     return false;
2380   case X86::MOVHLPSrr:
2381   case X86::UNPCKHPDrr:
2382   case X86::VMOVHLPSrr:
2383   case X86::VUNPCKHPDrr:
2384   case X86::VMOVHLPSZrr:
2385   case X86::VUNPCKHPDZ128rr:
2386     if (Subtarget.hasSSE2())
2387       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2388     return false;
2389   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2390   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2391   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2392   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2393   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2394   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2395   case X86::VPTERNLOGDZrrik:
2396   case X86::VPTERNLOGDZ128rrik:
2397   case X86::VPTERNLOGDZ256rrik:
2398   case X86::VPTERNLOGQZrrik:
2399   case X86::VPTERNLOGQZ128rrik:
2400   case X86::VPTERNLOGQZ256rrik:
2401   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2402   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2403   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2404   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2405   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2406   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2407   case X86::VPTERNLOGDZ128rmbi:
2408   case X86::VPTERNLOGDZ256rmbi:
2409   case X86::VPTERNLOGDZrmbi:
2410   case X86::VPTERNLOGQZ128rmbi:
2411   case X86::VPTERNLOGQZ256rmbi:
2412   case X86::VPTERNLOGQZrmbi:
2413   case X86::VPTERNLOGDZ128rmbikz:
2414   case X86::VPTERNLOGDZ256rmbikz:
2415   case X86::VPTERNLOGDZrmbikz:
2416   case X86::VPTERNLOGQZ128rmbikz:
2417   case X86::VPTERNLOGQZ256rmbikz:
2418   case X86::VPTERNLOGQZrmbikz:
2419     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2420   case X86::VPDPWSSDYrr:
2421   case X86::VPDPWSSDrr:
2422   case X86::VPDPWSSDSYrr:
2423   case X86::VPDPWSSDSrr:
2424   case X86::VPDPWSSDZ128r:
2425   case X86::VPDPWSSDZ128rk:
2426   case X86::VPDPWSSDZ128rkz:
2427   case X86::VPDPWSSDZ256r:
2428   case X86::VPDPWSSDZ256rk:
2429   case X86::VPDPWSSDZ256rkz:
2430   case X86::VPDPWSSDZr:
2431   case X86::VPDPWSSDZrk:
2432   case X86::VPDPWSSDZrkz:
2433   case X86::VPDPWSSDSZ128r:
2434   case X86::VPDPWSSDSZ128rk:
2435   case X86::VPDPWSSDSZ128rkz:
2436   case X86::VPDPWSSDSZ256r:
2437   case X86::VPDPWSSDSZ256rk:
2438   case X86::VPDPWSSDSZ256rkz:
2439   case X86::VPDPWSSDSZr:
2440   case X86::VPDPWSSDSZrk:
2441   case X86::VPDPWSSDSZrkz:
2442   case X86::VPMADD52HUQZ128r:
2443   case X86::VPMADD52HUQZ128rk:
2444   case X86::VPMADD52HUQZ128rkz:
2445   case X86::VPMADD52HUQZ256r:
2446   case X86::VPMADD52HUQZ256rk:
2447   case X86::VPMADD52HUQZ256rkz:
2448   case X86::VPMADD52HUQZr:
2449   case X86::VPMADD52HUQZrk:
2450   case X86::VPMADD52HUQZrkz:
2451   case X86::VPMADD52LUQZ128r:
2452   case X86::VPMADD52LUQZ128rk:
2453   case X86::VPMADD52LUQZ128rkz:
2454   case X86::VPMADD52LUQZ256r:
2455   case X86::VPMADD52LUQZ256rk:
2456   case X86::VPMADD52LUQZ256rkz:
2457   case X86::VPMADD52LUQZr:
2458   case X86::VPMADD52LUQZrk:
2459   case X86::VPMADD52LUQZrkz:
2460   case X86::VFMADDCPHZr:
2461   case X86::VFMADDCPHZrk:
2462   case X86::VFMADDCPHZrkz:
2463   case X86::VFMADDCPHZ128r:
2464   case X86::VFMADDCPHZ128rk:
2465   case X86::VFMADDCPHZ128rkz:
2466   case X86::VFMADDCPHZ256r:
2467   case X86::VFMADDCPHZ256rk:
2468   case X86::VFMADDCPHZ256rkz:
2469   case X86::VFMADDCSHZr:
2470   case X86::VFMADDCSHZrk:
2471   case X86::VFMADDCSHZrkz: {
2472     unsigned CommutableOpIdx1 = 2;
2473     unsigned CommutableOpIdx2 = 3;
2474     if (X86II::isKMasked(Desc.TSFlags)) {
2475       // Skip the mask register.
2476       ++CommutableOpIdx1;
2477       ++CommutableOpIdx2;
2478     }
2479     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2480                               CommutableOpIdx1, CommutableOpIdx2))
2481       return false;
2482     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2483         !MI.getOperand(SrcOpIdx2).isReg())
2484       // No idea.
2485       return false;
2486     return true;
2487   }
2488 
2489   default:
2490     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2491                                                       MI.getDesc().TSFlags);
2492     if (FMA3Group)
2493       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2494                                            FMA3Group->isIntrinsic());
2495 
2496     // Handled masked instructions since we need to skip over the mask input
2497     // and the preserved input.
2498     if (X86II::isKMasked(Desc.TSFlags)) {
2499       // First assume that the first input is the mask operand and skip past it.
2500       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2501       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2502       // Check if the first input is tied. If there isn't one then we only
2503       // need to skip the mask operand which we did above.
2504       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2505                                              MCOI::TIED_TO) != -1)) {
2506         // If this is zero masking instruction with a tied operand, we need to
2507         // move the first index back to the first input since this must
2508         // be a 3 input instruction and we want the first two non-mask inputs.
2509         // Otherwise this is a 2 input instruction with a preserved input and
2510         // mask, so we need to move the indices to skip one more input.
2511         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2512           ++CommutableOpIdx1;
2513           ++CommutableOpIdx2;
2514         } else {
2515           --CommutableOpIdx1;
2516         }
2517       }
2518 
2519       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2520                                 CommutableOpIdx1, CommutableOpIdx2))
2521         return false;
2522 
2523       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2524           !MI.getOperand(SrcOpIdx2).isReg())
2525         // No idea.
2526         return false;
2527       return true;
2528     }
2529 
2530     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2531   }
2532   return false;
2533 }
2534 
2535 static bool isConvertibleLEA(MachineInstr *MI) {
2536   unsigned Opcode = MI->getOpcode();
2537   if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2538       Opcode != X86::LEA64_32r)
2539     return false;
2540 
2541   const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2542   const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2543   const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2544 
2545   if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2546       Scale.getImm() > 1)
2547     return false;
2548 
2549   return true;
2550 }
2551 
2552 bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2553   // Currently we're interested in following sequence only.
2554   //   r3 = lea r1, r2
2555   //   r5 = add r3, r4
2556   // Both r3 and r4 are killed in add, we hope the add instruction has the
2557   // operand order
2558   //   r5 = add r4, r3
2559   // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2560   unsigned Opcode = MI.getOpcode();
2561   if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2562     return false;
2563 
2564   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2565   Register Reg1 = MI.getOperand(1).getReg();
2566   Register Reg2 = MI.getOperand(2).getReg();
2567 
2568   // Check if Reg1 comes from LEA in the same MBB.
2569   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2570     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2571       Commute = true;
2572       return true;
2573     }
2574   }
2575 
2576   // Check if Reg2 comes from LEA in the same MBB.
2577   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2578     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2579       Commute = false;
2580       return true;
2581     }
2582   }
2583 
2584   return false;
2585 }
2586 
2587 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2588   switch (MI.getOpcode()) {
2589   default: return X86::COND_INVALID;
2590   case X86::JCC_1:
2591     return static_cast<X86::CondCode>(
2592         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2593   }
2594 }
2595 
2596 /// Return condition code of a SETCC opcode.
2597 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2598   switch (MI.getOpcode()) {
2599   default: return X86::COND_INVALID;
2600   case X86::SETCCr: case X86::SETCCm:
2601     return static_cast<X86::CondCode>(
2602         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2603   }
2604 }
2605 
2606 /// Return condition code of a CMov opcode.
2607 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2608   switch (MI.getOpcode()) {
2609   default: return X86::COND_INVALID;
2610   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2611   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2612     return static_cast<X86::CondCode>(
2613         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2614   }
2615 }
2616 
2617 /// Return the inverse of the specified condition,
2618 /// e.g. turning COND_E to COND_NE.
2619 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2620   switch (CC) {
2621   default: llvm_unreachable("Illegal condition code!");
2622   case X86::COND_E:  return X86::COND_NE;
2623   case X86::COND_NE: return X86::COND_E;
2624   case X86::COND_L:  return X86::COND_GE;
2625   case X86::COND_LE: return X86::COND_G;
2626   case X86::COND_G:  return X86::COND_LE;
2627   case X86::COND_GE: return X86::COND_L;
2628   case X86::COND_B:  return X86::COND_AE;
2629   case X86::COND_BE: return X86::COND_A;
2630   case X86::COND_A:  return X86::COND_BE;
2631   case X86::COND_AE: return X86::COND_B;
2632   case X86::COND_S:  return X86::COND_NS;
2633   case X86::COND_NS: return X86::COND_S;
2634   case X86::COND_P:  return X86::COND_NP;
2635   case X86::COND_NP: return X86::COND_P;
2636   case X86::COND_O:  return X86::COND_NO;
2637   case X86::COND_NO: return X86::COND_O;
2638   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2639   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2640   }
2641 }
2642 
2643 /// Assuming the flags are set by MI(a,b), return the condition code if we
2644 /// modify the instructions such that flags are set by MI(b,a).
2645 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2646   switch (CC) {
2647   default: return X86::COND_INVALID;
2648   case X86::COND_E:  return X86::COND_E;
2649   case X86::COND_NE: return X86::COND_NE;
2650   case X86::COND_L:  return X86::COND_G;
2651   case X86::COND_LE: return X86::COND_GE;
2652   case X86::COND_G:  return X86::COND_L;
2653   case X86::COND_GE: return X86::COND_LE;
2654   case X86::COND_B:  return X86::COND_A;
2655   case X86::COND_BE: return X86::COND_AE;
2656   case X86::COND_A:  return X86::COND_B;
2657   case X86::COND_AE: return X86::COND_BE;
2658   }
2659 }
2660 
2661 std::pair<X86::CondCode, bool>
2662 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2663   X86::CondCode CC = X86::COND_INVALID;
2664   bool NeedSwap = false;
2665   switch (Predicate) {
2666   default: break;
2667   // Floating-point Predicates
2668   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2669   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2670   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2671   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2672   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2673   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2674   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2675   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2676   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2677   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2678   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2679   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2680   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2681   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2682 
2683   // Integer Predicates
2684   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2685   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2686   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2687   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2688   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2689   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2690   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2691   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2692   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2693   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2694   }
2695 
2696   return std::make_pair(CC, NeedSwap);
2697 }
2698 
2699 /// Return a cmov opcode for the given register size in bytes, and operand type.
2700 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2701   switch(RegBytes) {
2702   default: llvm_unreachable("Illegal register size!");
2703   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2704   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2705   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2706   }
2707 }
2708 
2709 /// Get the VPCMP immediate for the given condition.
2710 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2711   switch (CC) {
2712   default: llvm_unreachable("Unexpected SETCC condition");
2713   case ISD::SETNE:  return 4;
2714   case ISD::SETEQ:  return 0;
2715   case ISD::SETULT:
2716   case ISD::SETLT: return 1;
2717   case ISD::SETUGT:
2718   case ISD::SETGT: return 6;
2719   case ISD::SETUGE:
2720   case ISD::SETGE: return 5;
2721   case ISD::SETULE:
2722   case ISD::SETLE: return 2;
2723   }
2724 }
2725 
2726 /// Get the VPCMP immediate if the operands are swapped.
2727 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2728   switch (Imm) {
2729   default: llvm_unreachable("Unreachable!");
2730   case 0x01: Imm = 0x06; break; // LT  -> NLE
2731   case 0x02: Imm = 0x05; break; // LE  -> NLT
2732   case 0x05: Imm = 0x02; break; // NLT -> LE
2733   case 0x06: Imm = 0x01; break; // NLE -> LT
2734   case 0x00: // EQ
2735   case 0x03: // FALSE
2736   case 0x04: // NE
2737   case 0x07: // TRUE
2738     break;
2739   }
2740 
2741   return Imm;
2742 }
2743 
2744 /// Get the VPCOM immediate if the operands are swapped.
2745 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2746   switch (Imm) {
2747   default: llvm_unreachable("Unreachable!");
2748   case 0x00: Imm = 0x02; break; // LT -> GT
2749   case 0x01: Imm = 0x03; break; // LE -> GE
2750   case 0x02: Imm = 0x00; break; // GT -> LT
2751   case 0x03: Imm = 0x01; break; // GE -> LE
2752   case 0x04: // EQ
2753   case 0x05: // NE
2754   case 0x06: // FALSE
2755   case 0x07: // TRUE
2756     break;
2757   }
2758 
2759   return Imm;
2760 }
2761 
2762 /// Get the VCMP immediate if the operands are swapped.
2763 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2764   // Only need the lower 2 bits to distinquish.
2765   switch (Imm & 0x3) {
2766   default: llvm_unreachable("Unreachable!");
2767   case 0x00: case 0x03:
2768     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2769     break;
2770   case 0x01: case 0x02:
2771     // Need to toggle bits 3:0. Bit 4 stays the same.
2772     Imm ^= 0xf;
2773     break;
2774   }
2775 
2776   return Imm;
2777 }
2778 
2779 /// Return true if the Reg is X87 register.
2780 static bool isX87Reg(unsigned Reg) {
2781   return (Reg == X86::FPCW || Reg == X86::FPSW ||
2782           (Reg >= X86::ST0 && Reg <= X86::ST7));
2783 }
2784 
2785 /// check if the instruction is X87 instruction
2786 bool X86::isX87Instruction(MachineInstr &MI) {
2787   for (const MachineOperand &MO : MI.operands()) {
2788     if (!MO.isReg())
2789       continue;
2790     if (isX87Reg(MO.getReg()))
2791       return true;
2792   }
2793   return false;
2794 }
2795 
2796 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2797   switch (MI.getOpcode()) {
2798   case X86::TCRETURNdi:
2799   case X86::TCRETURNri:
2800   case X86::TCRETURNmi:
2801   case X86::TCRETURNdi64:
2802   case X86::TCRETURNri64:
2803   case X86::TCRETURNmi64:
2804     return true;
2805   default:
2806     return false;
2807   }
2808 }
2809 
2810 bool X86InstrInfo::canMakeTailCallConditional(
2811     SmallVectorImpl<MachineOperand> &BranchCond,
2812     const MachineInstr &TailCall) const {
2813   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2814       TailCall.getOpcode() != X86::TCRETURNdi64) {
2815     // Only direct calls can be done with a conditional branch.
2816     return false;
2817   }
2818 
2819   const MachineFunction *MF = TailCall.getParent()->getParent();
2820   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2821     // Conditional tail calls confuse the Win64 unwinder.
2822     return false;
2823   }
2824 
2825   assert(BranchCond.size() == 1);
2826   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2827     // Can't make a conditional tail call with this condition.
2828     return false;
2829   }
2830 
2831   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2832   if (X86FI->getTCReturnAddrDelta() != 0 ||
2833       TailCall.getOperand(1).getImm() != 0) {
2834     // A conditional tail call cannot do any stack adjustment.
2835     return false;
2836   }
2837 
2838   return true;
2839 }
2840 
2841 void X86InstrInfo::replaceBranchWithTailCall(
2842     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2843     const MachineInstr &TailCall) const {
2844   assert(canMakeTailCallConditional(BranchCond, TailCall));
2845 
2846   MachineBasicBlock::iterator I = MBB.end();
2847   while (I != MBB.begin()) {
2848     --I;
2849     if (I->isDebugInstr())
2850       continue;
2851     if (!I->isBranch())
2852       assert(0 && "Can't find the branch to replace!");
2853 
2854     X86::CondCode CC = X86::getCondFromBranch(*I);
2855     assert(BranchCond.size() == 1);
2856     if (CC != BranchCond[0].getImm())
2857       continue;
2858 
2859     break;
2860   }
2861 
2862   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2863                                                          : X86::TCRETURNdi64cc;
2864 
2865   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2866   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2867   MIB.addImm(0); // Stack offset (not used).
2868   MIB->addOperand(BranchCond[0]); // Condition.
2869   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2870 
2871   // Add implicit uses and defs of all live regs potentially clobbered by the
2872   // call. This way they still appear live across the call.
2873   LivePhysRegs LiveRegs(getRegisterInfo());
2874   LiveRegs.addLiveOuts(MBB);
2875   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2876   LiveRegs.stepForward(*MIB, Clobbers);
2877   for (const auto &C : Clobbers) {
2878     MIB.addReg(C.first, RegState::Implicit);
2879     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2880   }
2881 
2882   I->eraseFromParent();
2883 }
2884 
2885 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2886 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2887 // fallthrough MBB cannot be identified.
2888 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2889                                             MachineBasicBlock *TBB) {
2890   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2891   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2892   // and fallthrough MBB. If we find more than one, we cannot identify the
2893   // fallthrough MBB and should return nullptr.
2894   MachineBasicBlock *FallthroughBB = nullptr;
2895   for (MachineBasicBlock *Succ : MBB->successors()) {
2896     if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
2897       continue;
2898     // Return a nullptr if we found more than one fallthrough successor.
2899     if (FallthroughBB && FallthroughBB != TBB)
2900       return nullptr;
2901     FallthroughBB = Succ;
2902   }
2903   return FallthroughBB;
2904 }
2905 
2906 bool X86InstrInfo::AnalyzeBranchImpl(
2907     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2908     SmallVectorImpl<MachineOperand> &Cond,
2909     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2910 
2911   // Start from the bottom of the block and work up, examining the
2912   // terminator instructions.
2913   MachineBasicBlock::iterator I = MBB.end();
2914   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2915   while (I != MBB.begin()) {
2916     --I;
2917     if (I->isDebugInstr())
2918       continue;
2919 
2920     // Working from the bottom, when we see a non-terminator instruction, we're
2921     // done.
2922     if (!isUnpredicatedTerminator(*I))
2923       break;
2924 
2925     // A terminator that isn't a branch can't easily be handled by this
2926     // analysis.
2927     if (!I->isBranch())
2928       return true;
2929 
2930     // Handle unconditional branches.
2931     if (I->getOpcode() == X86::JMP_1) {
2932       UnCondBrIter = I;
2933 
2934       if (!AllowModify) {
2935         TBB = I->getOperand(0).getMBB();
2936         continue;
2937       }
2938 
2939       // If the block has any instructions after a JMP, delete them.
2940       while (std::next(I) != MBB.end())
2941         std::next(I)->eraseFromParent();
2942 
2943       Cond.clear();
2944       FBB = nullptr;
2945 
2946       // Delete the JMP if it's equivalent to a fall-through.
2947       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2948         TBB = nullptr;
2949         I->eraseFromParent();
2950         I = MBB.end();
2951         UnCondBrIter = MBB.end();
2952         continue;
2953       }
2954 
2955       // TBB is used to indicate the unconditional destination.
2956       TBB = I->getOperand(0).getMBB();
2957       continue;
2958     }
2959 
2960     // Handle conditional branches.
2961     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2962     if (BranchCode == X86::COND_INVALID)
2963       return true;  // Can't handle indirect branch.
2964 
2965     // In practice we should never have an undef eflags operand, if we do
2966     // abort here as we are not prepared to preserve the flag.
2967     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2968       return true;
2969 
2970     // Working from the bottom, handle the first conditional branch.
2971     if (Cond.empty()) {
2972       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2973       if (AllowModify && UnCondBrIter != MBB.end() &&
2974           MBB.isLayoutSuccessor(TargetBB)) {
2975         // If we can modify the code and it ends in something like:
2976         //
2977         //     jCC L1
2978         //     jmp L2
2979         //   L1:
2980         //     ...
2981         //   L2:
2982         //
2983         // Then we can change this to:
2984         //
2985         //     jnCC L2
2986         //   L1:
2987         //     ...
2988         //   L2:
2989         //
2990         // Which is a bit more efficient.
2991         // We conditionally jump to the fall-through block.
2992         BranchCode = GetOppositeBranchCondition(BranchCode);
2993         MachineBasicBlock::iterator OldInst = I;
2994 
2995         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2996           .addMBB(UnCondBrIter->getOperand(0).getMBB())
2997           .addImm(BranchCode);
2998         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2999           .addMBB(TargetBB);
3000 
3001         OldInst->eraseFromParent();
3002         UnCondBrIter->eraseFromParent();
3003 
3004         // Restart the analysis.
3005         UnCondBrIter = MBB.end();
3006         I = MBB.end();
3007         continue;
3008       }
3009 
3010       FBB = TBB;
3011       TBB = I->getOperand(0).getMBB();
3012       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3013       CondBranches.push_back(&*I);
3014       continue;
3015     }
3016 
3017     // Handle subsequent conditional branches. Only handle the case where all
3018     // conditional branches branch to the same destination and their condition
3019     // opcodes fit one of the special multi-branch idioms.
3020     assert(Cond.size() == 1);
3021     assert(TBB);
3022 
3023     // If the conditions are the same, we can leave them alone.
3024     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3025     auto NewTBB = I->getOperand(0).getMBB();
3026     if (OldBranchCode == BranchCode && TBB == NewTBB)
3027       continue;
3028 
3029     // If they differ, see if they fit one of the known patterns. Theoretically,
3030     // we could handle more patterns here, but we shouldn't expect to see them
3031     // if instruction selection has done a reasonable job.
3032     if (TBB == NewTBB &&
3033                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3034                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3035       BranchCode = X86::COND_NE_OR_P;
3036     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3037                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3038       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3039         return true;
3040 
3041       // X86::COND_E_AND_NP usually has two different branch destinations.
3042       //
3043       // JP B1
3044       // JE B2
3045       // JMP B1
3046       // B1:
3047       // B2:
3048       //
3049       // Here this condition branches to B2 only if NP && E. It has another
3050       // equivalent form:
3051       //
3052       // JNE B1
3053       // JNP B2
3054       // JMP B1
3055       // B1:
3056       // B2:
3057       //
3058       // Similarly it branches to B2 only if E && NP. That is why this condition
3059       // is named with COND_E_AND_NP.
3060       BranchCode = X86::COND_E_AND_NP;
3061     } else
3062       return true;
3063 
3064     // Update the MachineOperand.
3065     Cond[0].setImm(BranchCode);
3066     CondBranches.push_back(&*I);
3067   }
3068 
3069   return false;
3070 }
3071 
3072 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3073                                  MachineBasicBlock *&TBB,
3074                                  MachineBasicBlock *&FBB,
3075                                  SmallVectorImpl<MachineOperand> &Cond,
3076                                  bool AllowModify) const {
3077   SmallVector<MachineInstr *, 4> CondBranches;
3078   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3079 }
3080 
3081 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3082                                           MachineBranchPredicate &MBP,
3083                                           bool AllowModify) const {
3084   using namespace std::placeholders;
3085 
3086   SmallVector<MachineOperand, 4> Cond;
3087   SmallVector<MachineInstr *, 4> CondBranches;
3088   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3089                         AllowModify))
3090     return true;
3091 
3092   if (Cond.size() != 1)
3093     return true;
3094 
3095   assert(MBP.TrueDest && "expected!");
3096 
3097   if (!MBP.FalseDest)
3098     MBP.FalseDest = MBB.getNextNode();
3099 
3100   const TargetRegisterInfo *TRI = &getRegisterInfo();
3101 
3102   MachineInstr *ConditionDef = nullptr;
3103   bool SingleUseCondition = true;
3104 
3105   for (MachineInstr &MI : llvm::drop_begin(llvm::reverse(MBB))) {
3106     if (MI.modifiesRegister(X86::EFLAGS, TRI)) {
3107       ConditionDef = &MI;
3108       break;
3109     }
3110 
3111     if (MI.readsRegister(X86::EFLAGS, TRI))
3112       SingleUseCondition = false;
3113   }
3114 
3115   if (!ConditionDef)
3116     return true;
3117 
3118   if (SingleUseCondition) {
3119     for (auto *Succ : MBB.successors())
3120       if (Succ->isLiveIn(X86::EFLAGS))
3121         SingleUseCondition = false;
3122   }
3123 
3124   MBP.ConditionDef = ConditionDef;
3125   MBP.SingleUseCondition = SingleUseCondition;
3126 
3127   // Currently we only recognize the simple pattern:
3128   //
3129   //   test %reg, %reg
3130   //   je %label
3131   //
3132   const unsigned TestOpcode =
3133       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3134 
3135   if (ConditionDef->getOpcode() == TestOpcode &&
3136       ConditionDef->getNumOperands() == 3 &&
3137       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3138       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3139     MBP.LHS = ConditionDef->getOperand(0);
3140     MBP.RHS = MachineOperand::CreateImm(0);
3141     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3142                         ? MachineBranchPredicate::PRED_NE
3143                         : MachineBranchPredicate::PRED_EQ;
3144     return false;
3145   }
3146 
3147   return true;
3148 }
3149 
3150 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3151                                     int *BytesRemoved) const {
3152   assert(!BytesRemoved && "code size not handled");
3153 
3154   MachineBasicBlock::iterator I = MBB.end();
3155   unsigned Count = 0;
3156 
3157   while (I != MBB.begin()) {
3158     --I;
3159     if (I->isDebugInstr())
3160       continue;
3161     if (I->getOpcode() != X86::JMP_1 &&
3162         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3163       break;
3164     // Remove the branch.
3165     I->eraseFromParent();
3166     I = MBB.end();
3167     ++Count;
3168   }
3169 
3170   return Count;
3171 }
3172 
3173 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3174                                     MachineBasicBlock *TBB,
3175                                     MachineBasicBlock *FBB,
3176                                     ArrayRef<MachineOperand> Cond,
3177                                     const DebugLoc &DL,
3178                                     int *BytesAdded) const {
3179   // Shouldn't be a fall through.
3180   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3181   assert((Cond.size() == 1 || Cond.size() == 0) &&
3182          "X86 branch conditions have one component!");
3183   assert(!BytesAdded && "code size not handled");
3184 
3185   if (Cond.empty()) {
3186     // Unconditional branch?
3187     assert(!FBB && "Unconditional branch with multiple successors!");
3188     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3189     return 1;
3190   }
3191 
3192   // If FBB is null, it is implied to be a fall-through block.
3193   bool FallThru = FBB == nullptr;
3194 
3195   // Conditional branch.
3196   unsigned Count = 0;
3197   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3198   switch (CC) {
3199   case X86::COND_NE_OR_P:
3200     // Synthesize NE_OR_P with two branches.
3201     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3202     ++Count;
3203     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3204     ++Count;
3205     break;
3206   case X86::COND_E_AND_NP:
3207     // Use the next block of MBB as FBB if it is null.
3208     if (FBB == nullptr) {
3209       FBB = getFallThroughMBB(&MBB, TBB);
3210       assert(FBB && "MBB cannot be the last block in function when the false "
3211                     "body is a fall-through.");
3212     }
3213     // Synthesize COND_E_AND_NP with two branches.
3214     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3215     ++Count;
3216     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3217     ++Count;
3218     break;
3219   default: {
3220     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3221     ++Count;
3222   }
3223   }
3224   if (!FallThru) {
3225     // Two-way Conditional branch. Insert the second branch.
3226     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3227     ++Count;
3228   }
3229   return Count;
3230 }
3231 
3232 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3233                                    ArrayRef<MachineOperand> Cond,
3234                                    Register DstReg, Register TrueReg,
3235                                    Register FalseReg, int &CondCycles,
3236                                    int &TrueCycles, int &FalseCycles) const {
3237   // Not all subtargets have cmov instructions.
3238   if (!Subtarget.canUseCMOV())
3239     return false;
3240   if (Cond.size() != 1)
3241     return false;
3242   // We cannot do the composite conditions, at least not in SSA form.
3243   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3244     return false;
3245 
3246   // Check register classes.
3247   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3248   const TargetRegisterClass *RC =
3249     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3250   if (!RC)
3251     return false;
3252 
3253   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3254   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3255       X86::GR32RegClass.hasSubClassEq(RC) ||
3256       X86::GR64RegClass.hasSubClassEq(RC)) {
3257     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3258     // Bridge. Probably Ivy Bridge as well.
3259     CondCycles = 2;
3260     TrueCycles = 2;
3261     FalseCycles = 2;
3262     return true;
3263   }
3264 
3265   // Can't do vectors.
3266   return false;
3267 }
3268 
3269 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3270                                 MachineBasicBlock::iterator I,
3271                                 const DebugLoc &DL, Register DstReg,
3272                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3273                                 Register FalseReg) const {
3274   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3275   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3276   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3277   assert(Cond.size() == 1 && "Invalid Cond array");
3278   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3279                                     false /*HasMemoryOperand*/);
3280   BuildMI(MBB, I, DL, get(Opc), DstReg)
3281       .addReg(FalseReg)
3282       .addReg(TrueReg)
3283       .addImm(Cond[0].getImm());
3284 }
3285 
3286 /// Test if the given register is a physical h register.
3287 static bool isHReg(unsigned Reg) {
3288   return X86::GR8_ABCD_HRegClass.contains(Reg);
3289 }
3290 
3291 // Try and copy between VR128/VR64 and GR64 registers.
3292 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3293                                         const X86Subtarget &Subtarget) {
3294   bool HasAVX = Subtarget.hasAVX();
3295   bool HasAVX512 = Subtarget.hasAVX512();
3296 
3297   // SrcReg(MaskReg) -> DestReg(GR64)
3298   // SrcReg(MaskReg) -> DestReg(GR32)
3299 
3300   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3301   if (X86::VK16RegClass.contains(SrcReg)) {
3302     if (X86::GR64RegClass.contains(DestReg)) {
3303       assert(Subtarget.hasBWI());
3304       return X86::KMOVQrk;
3305     }
3306     if (X86::GR32RegClass.contains(DestReg))
3307       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3308   }
3309 
3310   // SrcReg(GR64) -> DestReg(MaskReg)
3311   // SrcReg(GR32) -> DestReg(MaskReg)
3312 
3313   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3314   if (X86::VK16RegClass.contains(DestReg)) {
3315     if (X86::GR64RegClass.contains(SrcReg)) {
3316       assert(Subtarget.hasBWI());
3317       return X86::KMOVQkr;
3318     }
3319     if (X86::GR32RegClass.contains(SrcReg))
3320       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3321   }
3322 
3323 
3324   // SrcReg(VR128) -> DestReg(GR64)
3325   // SrcReg(VR64)  -> DestReg(GR64)
3326   // SrcReg(GR64)  -> DestReg(VR128)
3327   // SrcReg(GR64)  -> DestReg(VR64)
3328 
3329   if (X86::GR64RegClass.contains(DestReg)) {
3330     if (X86::VR128XRegClass.contains(SrcReg))
3331       // Copy from a VR128 register to a GR64 register.
3332       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3333              HasAVX    ? X86::VMOVPQIto64rr  :
3334                          X86::MOVPQIto64rr;
3335     if (X86::VR64RegClass.contains(SrcReg))
3336       // Copy from a VR64 register to a GR64 register.
3337       return X86::MMX_MOVD64from64rr;
3338   } else if (X86::GR64RegClass.contains(SrcReg)) {
3339     // Copy from a GR64 register to a VR128 register.
3340     if (X86::VR128XRegClass.contains(DestReg))
3341       return HasAVX512 ? X86::VMOV64toPQIZrr :
3342              HasAVX    ? X86::VMOV64toPQIrr  :
3343                          X86::MOV64toPQIrr;
3344     // Copy from a GR64 register to a VR64 register.
3345     if (X86::VR64RegClass.contains(DestReg))
3346       return X86::MMX_MOVD64to64rr;
3347   }
3348 
3349   // SrcReg(VR128) -> DestReg(GR32)
3350   // SrcReg(GR32)  -> DestReg(VR128)
3351 
3352   if (X86::GR32RegClass.contains(DestReg) &&
3353       X86::VR128XRegClass.contains(SrcReg))
3354     // Copy from a VR128 register to a GR32 register.
3355     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3356            HasAVX    ? X86::VMOVPDI2DIrr  :
3357                        X86::MOVPDI2DIrr;
3358 
3359   if (X86::VR128XRegClass.contains(DestReg) &&
3360       X86::GR32RegClass.contains(SrcReg))
3361     // Copy from a VR128 register to a VR128 register.
3362     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3363            HasAVX    ? X86::VMOVDI2PDIrr  :
3364                        X86::MOVDI2PDIrr;
3365   return 0;
3366 }
3367 
3368 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3369                                MachineBasicBlock::iterator MI,
3370                                const DebugLoc &DL, MCRegister DestReg,
3371                                MCRegister SrcReg, bool KillSrc) const {
3372   // First deal with the normal symmetric copies.
3373   bool HasAVX = Subtarget.hasAVX();
3374   bool HasVLX = Subtarget.hasVLX();
3375   unsigned Opc = 0;
3376   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3377     Opc = X86::MOV64rr;
3378   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3379     Opc = X86::MOV32rr;
3380   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3381     Opc = X86::MOV16rr;
3382   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3383     // Copying to or from a physical H register on x86-64 requires a NOREX
3384     // move.  Otherwise use a normal move.
3385     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3386         Subtarget.is64Bit()) {
3387       Opc = X86::MOV8rr_NOREX;
3388       // Both operands must be encodable without an REX prefix.
3389       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3390              "8-bit H register can not be copied outside GR8_NOREX");
3391     } else
3392       Opc = X86::MOV8rr;
3393   }
3394   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3395     Opc = X86::MMX_MOVQ64rr;
3396   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3397     if (HasVLX)
3398       Opc = X86::VMOVAPSZ128rr;
3399     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3400       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3401     else {
3402       // If this an extended register and we don't have VLX we need to use a
3403       // 512-bit move.
3404       Opc = X86::VMOVAPSZrr;
3405       const TargetRegisterInfo *TRI = &getRegisterInfo();
3406       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3407                                          &X86::VR512RegClass);
3408       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3409                                         &X86::VR512RegClass);
3410     }
3411   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3412     if (HasVLX)
3413       Opc = X86::VMOVAPSZ256rr;
3414     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3415       Opc = X86::VMOVAPSYrr;
3416     else {
3417       // If this an extended register and we don't have VLX we need to use a
3418       // 512-bit move.
3419       Opc = X86::VMOVAPSZrr;
3420       const TargetRegisterInfo *TRI = &getRegisterInfo();
3421       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3422                                          &X86::VR512RegClass);
3423       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3424                                         &X86::VR512RegClass);
3425     }
3426   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3427     Opc = X86::VMOVAPSZrr;
3428   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3429   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3430     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3431   if (!Opc)
3432     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3433 
3434   if (Opc) {
3435     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3436       .addReg(SrcReg, getKillRegState(KillSrc));
3437     return;
3438   }
3439 
3440   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3441     // FIXME: We use a fatal error here because historically LLVM has tried
3442     // lower some of these physreg copies and we want to ensure we get
3443     // reasonable bug reports if someone encounters a case no other testing
3444     // found. This path should be removed after the LLVM 7 release.
3445     report_fatal_error("Unable to copy EFLAGS physical register!");
3446   }
3447 
3448   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3449                     << RI.getName(DestReg) << '\n');
3450   report_fatal_error("Cannot emit physreg copy instruction");
3451 }
3452 
3453 Optional<DestSourcePair>
3454 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3455   if (MI.isMoveReg())
3456     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3457   return None;
3458 }
3459 
3460 static unsigned getLoadStoreRegOpcode(Register Reg,
3461                                       const TargetRegisterClass *RC,
3462                                       bool IsStackAligned,
3463                                       const X86Subtarget &STI, bool load) {
3464   bool HasAVX = STI.hasAVX();
3465   bool HasAVX512 = STI.hasAVX512();
3466   bool HasVLX = STI.hasVLX();
3467 
3468   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3469   default:
3470     llvm_unreachable("Unknown spill size");
3471   case 1:
3472     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3473     if (STI.is64Bit())
3474       // Copying to or from a physical H register on x86-64 requires a NOREX
3475       // move.  Otherwise use a normal move.
3476       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3477         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3478     return load ? X86::MOV8rm : X86::MOV8mr;
3479   case 2:
3480     if (X86::VK16RegClass.hasSubClassEq(RC))
3481       return load ? X86::KMOVWkm : X86::KMOVWmk;
3482     if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3483       assert(STI.hasFP16());
3484       return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3485     }
3486     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3487     return load ? X86::MOV16rm : X86::MOV16mr;
3488   case 4:
3489     if (X86::GR32RegClass.hasSubClassEq(RC))
3490       return load ? X86::MOV32rm : X86::MOV32mr;
3491     if (X86::FR32XRegClass.hasSubClassEq(RC))
3492       return load ?
3493         (HasAVX512 ? X86::VMOVSSZrm_alt :
3494          HasAVX    ? X86::VMOVSSrm_alt :
3495                      X86::MOVSSrm_alt) :
3496         (HasAVX512 ? X86::VMOVSSZmr :
3497          HasAVX    ? X86::VMOVSSmr :
3498                      X86::MOVSSmr);
3499     if (X86::RFP32RegClass.hasSubClassEq(RC))
3500       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3501     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3502       assert(STI.hasBWI() && "KMOVD requires BWI");
3503       return load ? X86::KMOVDkm : X86::KMOVDmk;
3504     }
3505     // All of these mask pair classes have the same spill size, the same kind
3506     // of kmov instructions can be used with all of them.
3507     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3508         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3509         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3510         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3511         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3512       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3513     llvm_unreachable("Unknown 4-byte regclass");
3514   case 8:
3515     if (X86::GR64RegClass.hasSubClassEq(RC))
3516       return load ? X86::MOV64rm : X86::MOV64mr;
3517     if (X86::FR64XRegClass.hasSubClassEq(RC))
3518       return load ?
3519         (HasAVX512 ? X86::VMOVSDZrm_alt :
3520          HasAVX    ? X86::VMOVSDrm_alt :
3521                      X86::MOVSDrm_alt) :
3522         (HasAVX512 ? X86::VMOVSDZmr :
3523          HasAVX    ? X86::VMOVSDmr :
3524                      X86::MOVSDmr);
3525     if (X86::VR64RegClass.hasSubClassEq(RC))
3526       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3527     if (X86::RFP64RegClass.hasSubClassEq(RC))
3528       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3529     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3530       assert(STI.hasBWI() && "KMOVQ requires BWI");
3531       return load ? X86::KMOVQkm : X86::KMOVQmk;
3532     }
3533     llvm_unreachable("Unknown 8-byte regclass");
3534   case 10:
3535     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3536     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3537   case 16: {
3538     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3539       // If stack is realigned we can use aligned stores.
3540       if (IsStackAligned)
3541         return load ?
3542           (HasVLX    ? X86::VMOVAPSZ128rm :
3543            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3544            HasAVX    ? X86::VMOVAPSrm :
3545                        X86::MOVAPSrm):
3546           (HasVLX    ? X86::VMOVAPSZ128mr :
3547            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3548            HasAVX    ? X86::VMOVAPSmr :
3549                        X86::MOVAPSmr);
3550       else
3551         return load ?
3552           (HasVLX    ? X86::VMOVUPSZ128rm :
3553            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3554            HasAVX    ? X86::VMOVUPSrm :
3555                        X86::MOVUPSrm):
3556           (HasVLX    ? X86::VMOVUPSZ128mr :
3557            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3558            HasAVX    ? X86::VMOVUPSmr :
3559                        X86::MOVUPSmr);
3560     }
3561     llvm_unreachable("Unknown 16-byte regclass");
3562   }
3563   case 32:
3564     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3565     // If stack is realigned we can use aligned stores.
3566     if (IsStackAligned)
3567       return load ?
3568         (HasVLX    ? X86::VMOVAPSZ256rm :
3569          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3570                      X86::VMOVAPSYrm) :
3571         (HasVLX    ? X86::VMOVAPSZ256mr :
3572          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3573                      X86::VMOVAPSYmr);
3574     else
3575       return load ?
3576         (HasVLX    ? X86::VMOVUPSZ256rm :
3577          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3578                      X86::VMOVUPSYrm) :
3579         (HasVLX    ? X86::VMOVUPSZ256mr :
3580          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3581                      X86::VMOVUPSYmr);
3582   case 64:
3583     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3584     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3585     if (IsStackAligned)
3586       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3587     else
3588       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3589   }
3590 }
3591 
3592 Optional<ExtAddrMode>
3593 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3594                                       const TargetRegisterInfo *TRI) const {
3595   const MCInstrDesc &Desc = MemI.getDesc();
3596   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3597   if (MemRefBegin < 0)
3598     return None;
3599 
3600   MemRefBegin += X86II::getOperandBias(Desc);
3601 
3602   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3603   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3604     return None;
3605 
3606   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3607   // Displacement can be symbolic
3608   if (!DispMO.isImm())
3609     return None;
3610 
3611   ExtAddrMode AM;
3612   AM.BaseReg = BaseOp.getReg();
3613   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3614   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3615   AM.Displacement = DispMO.getImm();
3616   return AM;
3617 }
3618 
3619 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3620                                            const Register Reg,
3621                                            int64_t &ImmVal) const {
3622   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3623     return false;
3624   // Mov Src can be a global address.
3625   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3626     return false;
3627   ImmVal = MI.getOperand(1).getImm();
3628   return true;
3629 }
3630 
3631 bool X86InstrInfo::preservesZeroValueInReg(
3632     const MachineInstr *MI, const Register NullValueReg,
3633     const TargetRegisterInfo *TRI) const {
3634   if (!MI->modifiesRegister(NullValueReg, TRI))
3635     return true;
3636   switch (MI->getOpcode()) {
3637   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3638   // X.
3639   case X86::SHR64ri:
3640   case X86::SHR32ri:
3641   case X86::SHL64ri:
3642   case X86::SHL32ri:
3643     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3644            "expected for shift opcode!");
3645     return MI->getOperand(0).getReg() == NullValueReg &&
3646            MI->getOperand(1).getReg() == NullValueReg;
3647   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3648   // null value.
3649   case X86::MOV32rr:
3650     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3651       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3652     });
3653   default:
3654     return false;
3655   }
3656   llvm_unreachable("Should be handled above!");
3657 }
3658 
3659 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3660     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3661     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3662     const TargetRegisterInfo *TRI) const {
3663   const MCInstrDesc &Desc = MemOp.getDesc();
3664   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3665   if (MemRefBegin < 0)
3666     return false;
3667 
3668   MemRefBegin += X86II::getOperandBias(Desc);
3669 
3670   const MachineOperand *BaseOp =
3671       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3672   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3673     return false;
3674 
3675   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3676     return false;
3677 
3678   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3679       X86::NoRegister)
3680     return false;
3681 
3682   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3683 
3684   // Displacement can be symbolic
3685   if (!DispMO.isImm())
3686     return false;
3687 
3688   Offset = DispMO.getImm();
3689 
3690   if (!BaseOp->isReg())
3691     return false;
3692 
3693   OffsetIsScalable = false;
3694   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3695   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3696   // there is no use of `Width` for X86 back-end at the moment.
3697   Width =
3698       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3699   BaseOps.push_back(BaseOp);
3700   return true;
3701 }
3702 
3703 static unsigned getStoreRegOpcode(Register SrcReg,
3704                                   const TargetRegisterClass *RC,
3705                                   bool IsStackAligned,
3706                                   const X86Subtarget &STI) {
3707   return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3708 }
3709 
3710 static unsigned getLoadRegOpcode(Register DestReg,
3711                                  const TargetRegisterClass *RC,
3712                                  bool IsStackAligned, const X86Subtarget &STI) {
3713   return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3714 }
3715 
3716 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3717                                        MachineBasicBlock::iterator MI,
3718                                        Register SrcReg, bool isKill, int FrameIdx,
3719                                        const TargetRegisterClass *RC,
3720                                        const TargetRegisterInfo *TRI) const {
3721   const MachineFunction &MF = *MBB.getParent();
3722   const MachineFrameInfo &MFI = MF.getFrameInfo();
3723   assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3724          "Stack slot too small for store");
3725   if (RC->getID() == X86::TILERegClassID) {
3726     unsigned Opc = X86::TILESTORED;
3727     // tilestored %tmm, (%sp, %idx)
3728     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3729     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3730     BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3731     MachineInstr *NewMI =
3732         addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3733             .addReg(SrcReg, getKillRegState(isKill));
3734     MachineOperand &MO = NewMI->getOperand(2);
3735     MO.setReg(VirtReg);
3736     MO.setIsKill(true);
3737   } else {
3738     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3739     bool isAligned =
3740         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3741         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3742     unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3743     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3744         .addReg(SrcReg, getKillRegState(isKill));
3745   }
3746 }
3747 
3748 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3749                                         MachineBasicBlock::iterator MI,
3750                                         Register DestReg, int FrameIdx,
3751                                         const TargetRegisterClass *RC,
3752                                         const TargetRegisterInfo *TRI) const {
3753   if (RC->getID() == X86::TILERegClassID) {
3754     unsigned Opc = X86::TILELOADD;
3755     // tileloadd (%sp, %idx), %tmm
3756     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3757     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3758     MachineInstr *NewMI =
3759         BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3760     NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3761                               FrameIdx);
3762     MachineOperand &MO = NewMI->getOperand(3);
3763     MO.setReg(VirtReg);
3764     MO.setIsKill(true);
3765   } else {
3766     const MachineFunction &MF = *MBB.getParent();
3767     const MachineFrameInfo &MFI = MF.getFrameInfo();
3768     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3769     bool isAligned =
3770         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3771         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3772     unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3773     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3774                       FrameIdx);
3775   }
3776 }
3777 
3778 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3779                                   Register &SrcReg2, int64_t &CmpMask,
3780                                   int64_t &CmpValue) const {
3781   switch (MI.getOpcode()) {
3782   default: break;
3783   case X86::CMP64ri32:
3784   case X86::CMP64ri8:
3785   case X86::CMP32ri:
3786   case X86::CMP32ri8:
3787   case X86::CMP16ri:
3788   case X86::CMP16ri8:
3789   case X86::CMP8ri:
3790     SrcReg = MI.getOperand(0).getReg();
3791     SrcReg2 = 0;
3792     if (MI.getOperand(1).isImm()) {
3793       CmpMask = ~0;
3794       CmpValue = MI.getOperand(1).getImm();
3795     } else {
3796       CmpMask = CmpValue = 0;
3797     }
3798     return true;
3799   // A SUB can be used to perform comparison.
3800   case X86::SUB64rm:
3801   case X86::SUB32rm:
3802   case X86::SUB16rm:
3803   case X86::SUB8rm:
3804     SrcReg = MI.getOperand(1).getReg();
3805     SrcReg2 = 0;
3806     CmpMask = 0;
3807     CmpValue = 0;
3808     return true;
3809   case X86::SUB64rr:
3810   case X86::SUB32rr:
3811   case X86::SUB16rr:
3812   case X86::SUB8rr:
3813     SrcReg = MI.getOperand(1).getReg();
3814     SrcReg2 = MI.getOperand(2).getReg();
3815     CmpMask = 0;
3816     CmpValue = 0;
3817     return true;
3818   case X86::SUB64ri32:
3819   case X86::SUB64ri8:
3820   case X86::SUB32ri:
3821   case X86::SUB32ri8:
3822   case X86::SUB16ri:
3823   case X86::SUB16ri8:
3824   case X86::SUB8ri:
3825     SrcReg = MI.getOperand(1).getReg();
3826     SrcReg2 = 0;
3827     if (MI.getOperand(2).isImm()) {
3828       CmpMask = ~0;
3829       CmpValue = MI.getOperand(2).getImm();
3830     } else {
3831       CmpMask = CmpValue = 0;
3832     }
3833     return true;
3834   case X86::CMP64rr:
3835   case X86::CMP32rr:
3836   case X86::CMP16rr:
3837   case X86::CMP8rr:
3838     SrcReg = MI.getOperand(0).getReg();
3839     SrcReg2 = MI.getOperand(1).getReg();
3840     CmpMask = 0;
3841     CmpValue = 0;
3842     return true;
3843   case X86::TEST8rr:
3844   case X86::TEST16rr:
3845   case X86::TEST32rr:
3846   case X86::TEST64rr:
3847     SrcReg = MI.getOperand(0).getReg();
3848     if (MI.getOperand(1).getReg() != SrcReg)
3849       return false;
3850     // Compare against zero.
3851     SrcReg2 = 0;
3852     CmpMask = ~0;
3853     CmpValue = 0;
3854     return true;
3855   }
3856   return false;
3857 }
3858 
3859 bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
3860                                         Register SrcReg, Register SrcReg2,
3861                                         int64_t ImmMask, int64_t ImmValue,
3862                                         const MachineInstr &OI, bool *IsSwapped,
3863                                         int64_t *ImmDelta) const {
3864   switch (OI.getOpcode()) {
3865   case X86::CMP64rr:
3866   case X86::CMP32rr:
3867   case X86::CMP16rr:
3868   case X86::CMP8rr:
3869   case X86::SUB64rr:
3870   case X86::SUB32rr:
3871   case X86::SUB16rr:
3872   case X86::SUB8rr: {
3873     Register OISrcReg;
3874     Register OISrcReg2;
3875     int64_t OIMask;
3876     int64_t OIValue;
3877     if (!analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) ||
3878         OIMask != ImmMask || OIValue != ImmValue)
3879       return false;
3880     if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
3881       *IsSwapped = false;
3882       return true;
3883     }
3884     if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
3885       *IsSwapped = true;
3886       return true;
3887     }
3888     return false;
3889   }
3890   case X86::CMP64ri32:
3891   case X86::CMP64ri8:
3892   case X86::CMP32ri:
3893   case X86::CMP32ri8:
3894   case X86::CMP16ri:
3895   case X86::CMP16ri8:
3896   case X86::CMP8ri:
3897   case X86::SUB64ri32:
3898   case X86::SUB64ri8:
3899   case X86::SUB32ri:
3900   case X86::SUB32ri8:
3901   case X86::SUB16ri:
3902   case X86::SUB16ri8:
3903   case X86::SUB8ri:
3904   case X86::TEST64rr:
3905   case X86::TEST32rr:
3906   case X86::TEST16rr:
3907   case X86::TEST8rr: {
3908     if (ImmMask != 0) {
3909       Register OISrcReg;
3910       Register OISrcReg2;
3911       int64_t OIMask;
3912       int64_t OIValue;
3913       if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
3914           SrcReg == OISrcReg && ImmMask == OIMask) {
3915         if (OIValue == ImmValue) {
3916           *ImmDelta = 0;
3917           return true;
3918         } else if (static_cast<uint64_t>(ImmValue) ==
3919                    static_cast<uint64_t>(OIValue) - 1) {
3920           *ImmDelta = -1;
3921           return true;
3922         } else if (static_cast<uint64_t>(ImmValue) ==
3923                    static_cast<uint64_t>(OIValue) + 1) {
3924           *ImmDelta = 1;
3925           return true;
3926         } else {
3927           return false;
3928         }
3929       }
3930     }
3931     return FlagI.isIdenticalTo(OI);
3932   }
3933   default:
3934     return false;
3935   }
3936 }
3937 
3938 /// Check whether the definition can be converted
3939 /// to remove a comparison against zero.
3940 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
3941                                     bool &ClearsOverflowFlag) {
3942   NoSignFlag = false;
3943   ClearsOverflowFlag = false;
3944 
3945   switch (MI.getOpcode()) {
3946   default: return false;
3947 
3948   // The shift instructions only modify ZF if their shift count is non-zero.
3949   // N.B.: The processor truncates the shift count depending on the encoding.
3950   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3951   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3952      return getTruncatedShiftCount(MI, 2) != 0;
3953 
3954   // Some left shift instructions can be turned into LEA instructions but only
3955   // if their flags aren't used. Avoid transforming such instructions.
3956   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3957     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3958     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3959     return ShAmt != 0;
3960   }
3961 
3962   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3963   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3964      return getTruncatedShiftCount(MI, 3) != 0;
3965 
3966   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3967   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3968   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3969   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3970   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3971   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3972   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3973   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3974   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3975   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3976   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3977   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3978   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3979   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3980   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3981   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3982   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
3983   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3984   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
3985   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
3986   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
3987   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
3988   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3989   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3990   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3991   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3992   case X86::LZCNT16rr: case X86::LZCNT16rm:
3993   case X86::LZCNT32rr: case X86::LZCNT32rm:
3994   case X86::LZCNT64rr: case X86::LZCNT64rm:
3995   case X86::POPCNT16rr:case X86::POPCNT16rm:
3996   case X86::POPCNT32rr:case X86::POPCNT32rm:
3997   case X86::POPCNT64rr:case X86::POPCNT64rm:
3998   case X86::TZCNT16rr: case X86::TZCNT16rm:
3999   case X86::TZCNT32rr: case X86::TZCNT32rm:
4000   case X86::TZCNT64rr: case X86::TZCNT64rm:
4001     return true;
4002   case X86::AND64ri32:   case X86::AND64ri8:  case X86::AND32ri:
4003   case X86::AND32ri8:    case X86::AND16ri:   case X86::AND16ri8:
4004   case X86::AND8ri:      case X86::AND64rr:   case X86::AND32rr:
4005   case X86::AND16rr:     case X86::AND8rr:    case X86::AND64rm:
4006   case X86::AND32rm:     case X86::AND16rm:   case X86::AND8rm:
4007   case X86::XOR64ri32:   case X86::XOR64ri8:  case X86::XOR32ri:
4008   case X86::XOR32ri8:    case X86::XOR16ri:   case X86::XOR16ri8:
4009   case X86::XOR8ri:      case X86::XOR64rr:   case X86::XOR32rr:
4010   case X86::XOR16rr:     case X86::XOR8rr:    case X86::XOR64rm:
4011   case X86::XOR32rm:     case X86::XOR16rm:   case X86::XOR8rm:
4012   case X86::OR64ri32:    case X86::OR64ri8:   case X86::OR32ri:
4013   case X86::OR32ri8:     case X86::OR16ri:    case X86::OR16ri8:
4014   case X86::OR8ri:       case X86::OR64rr:    case X86::OR32rr:
4015   case X86::OR16rr:      case X86::OR8rr:     case X86::OR64rm:
4016   case X86::OR32rm:      case X86::OR16rm:    case X86::OR8rm:
4017   case X86::ANDN32rr:    case X86::ANDN32rm:
4018   case X86::ANDN64rr:    case X86::ANDN64rm:
4019   case X86::BLSI32rr:    case X86::BLSI32rm:
4020   case X86::BLSI64rr:    case X86::BLSI64rm:
4021   case X86::BLSMSK32rr:  case X86::BLSMSK32rm:
4022   case X86::BLSMSK64rr:  case X86::BLSMSK64rm:
4023   case X86::BLSR32rr:    case X86::BLSR32rm:
4024   case X86::BLSR64rr:    case X86::BLSR64rm:
4025   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4026   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4027   case X86::BLCI32rr:    case X86::BLCI32rm:
4028   case X86::BLCI64rr:    case X86::BLCI64rm:
4029   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4030   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4031   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4032   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4033   case X86::BLCS32rr:    case X86::BLCS32rm:
4034   case X86::BLCS64rr:    case X86::BLCS64rm:
4035   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4036   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4037   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4038   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4039   case X86::BZHI32rr:    case X86::BZHI32rm:
4040   case X86::BZHI64rr:    case X86::BZHI64rm:
4041   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4042   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4043   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4044   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4045     // These instructions clear the overflow flag just like TEST.
4046     // FIXME: These are not the only instructions in this switch that clear the
4047     // overflow flag.
4048     ClearsOverflowFlag = true;
4049     return true;
4050   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4051   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4052   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4053   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4054     // BEXTR doesn't update the sign flag so we can't use it. It does clear
4055     // the overflow flag, but that's not useful without the sign flag.
4056     NoSignFlag = true;
4057     return true;
4058   }
4059 }
4060 
4061 /// Check whether the use can be converted to remove a comparison against zero.
4062 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4063   switch (MI.getOpcode()) {
4064   default: return X86::COND_INVALID;
4065   case X86::NEG8r:
4066   case X86::NEG16r:
4067   case X86::NEG32r:
4068   case X86::NEG64r:
4069     return X86::COND_AE;
4070   case X86::LZCNT16rr:
4071   case X86::LZCNT32rr:
4072   case X86::LZCNT64rr:
4073     return X86::COND_B;
4074   case X86::POPCNT16rr:
4075   case X86::POPCNT32rr:
4076   case X86::POPCNT64rr:
4077     return X86::COND_E;
4078   case X86::TZCNT16rr:
4079   case X86::TZCNT32rr:
4080   case X86::TZCNT64rr:
4081     return X86::COND_B;
4082   case X86::BSF16rr:
4083   case X86::BSF32rr:
4084   case X86::BSF64rr:
4085   case X86::BSR16rr:
4086   case X86::BSR32rr:
4087   case X86::BSR64rr:
4088     return X86::COND_E;
4089   case X86::BLSI32rr:
4090   case X86::BLSI64rr:
4091     return X86::COND_AE;
4092   case X86::BLSR32rr:
4093   case X86::BLSR64rr:
4094   case X86::BLSMSK32rr:
4095   case X86::BLSMSK64rr:
4096     return X86::COND_B;
4097   // TODO: TBM instructions.
4098   }
4099 }
4100 
4101 /// Check if there exists an earlier instruction that
4102 /// operates on the same source operands and sets flags in the same way as
4103 /// Compare; remove Compare if possible.
4104 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4105                                         Register SrcReg2, int64_t CmpMask,
4106                                         int64_t CmpValue,
4107                                         const MachineRegisterInfo *MRI) const {
4108   // Check whether we can replace SUB with CMP.
4109   switch (CmpInstr.getOpcode()) {
4110   default: break;
4111   case X86::SUB64ri32:
4112   case X86::SUB64ri8:
4113   case X86::SUB32ri:
4114   case X86::SUB32ri8:
4115   case X86::SUB16ri:
4116   case X86::SUB16ri8:
4117   case X86::SUB8ri:
4118   case X86::SUB64rm:
4119   case X86::SUB32rm:
4120   case X86::SUB16rm:
4121   case X86::SUB8rm:
4122   case X86::SUB64rr:
4123   case X86::SUB32rr:
4124   case X86::SUB16rr:
4125   case X86::SUB8rr: {
4126     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4127       return false;
4128     // There is no use of the destination register, we can replace SUB with CMP.
4129     unsigned NewOpcode = 0;
4130     switch (CmpInstr.getOpcode()) {
4131     default: llvm_unreachable("Unreachable!");
4132     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4133     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4134     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4135     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4136     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4137     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4138     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4139     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4140     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4141     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4142     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4143     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4144     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4145     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4146     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4147     }
4148     CmpInstr.setDesc(get(NewOpcode));
4149     CmpInstr.removeOperand(0);
4150     // Mutating this instruction invalidates any debug data associated with it.
4151     CmpInstr.dropDebugNumber();
4152     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4153     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4154         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4155       return false;
4156   }
4157   }
4158 
4159   // The following code tries to remove the comparison by re-using EFLAGS
4160   // from earlier instructions.
4161 
4162   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4163 
4164   // Transformation currently requires SSA values.
4165   if (SrcReg2.isPhysical())
4166     return false;
4167   MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
4168   assert(SrcRegDef && "Must have a definition (SSA)");
4169 
4170   MachineInstr *MI = nullptr;
4171   MachineInstr *Sub = nullptr;
4172   MachineInstr *Movr0Inst = nullptr;
4173   bool NoSignFlag = false;
4174   bool ClearsOverflowFlag = false;
4175   bool ShouldUpdateCC = false;
4176   bool IsSwapped = false;
4177   X86::CondCode NewCC = X86::COND_INVALID;
4178   int64_t ImmDelta = 0;
4179 
4180   // Search backward from CmpInstr for the next instruction defining EFLAGS.
4181   const TargetRegisterInfo *TRI = &getRegisterInfo();
4182   MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
4183   MachineBasicBlock::reverse_iterator From =
4184       std::next(MachineBasicBlock::reverse_iterator(CmpInstr));
4185   for (MachineBasicBlock *MBB = &CmpMBB;;) {
4186     for (MachineInstr &Inst : make_range(From, MBB->rend())) {
4187       // Try to use EFLAGS from the instruction defining %SrcReg. Example:
4188       //     %eax = addl ...
4189       //     ...                // EFLAGS not changed
4190       //     testl %eax, %eax   // <-- can be removed
4191       if (&Inst == SrcRegDef) {
4192         if (IsCmpZero &&
4193             isDefConvertible(Inst, NoSignFlag, ClearsOverflowFlag)) {
4194           MI = &Inst;
4195           break;
4196         }
4197         // Cannot find other candidates before definition of SrcReg.
4198         return false;
4199       }
4200 
4201       if (Inst.modifiesRegister(X86::EFLAGS, TRI)) {
4202         // Try to use EFLAGS produced by an instruction reading %SrcReg.
4203         // Example:
4204         //      %eax = ...
4205         //      ...
4206         //      popcntl %eax
4207         //      ...                 // EFLAGS not changed
4208         //      testl %eax, %eax    // <-- can be removed
4209         if (IsCmpZero) {
4210           NewCC = isUseDefConvertible(Inst);
4211           if (NewCC != X86::COND_INVALID && Inst.getOperand(1).isReg() &&
4212               Inst.getOperand(1).getReg() == SrcReg) {
4213             ShouldUpdateCC = true;
4214             MI = &Inst;
4215             break;
4216           }
4217         }
4218 
4219         // Try to use EFLAGS from an instruction with similar flag results.
4220         // Example:
4221         //     sub x, y  or  cmp x, y
4222         //     ...           // EFLAGS not changed
4223         //     cmp x, y      // <-- can be removed
4224         if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
4225                                  Inst, &IsSwapped, &ImmDelta)) {
4226           Sub = &Inst;
4227           break;
4228         }
4229 
4230         // MOV32r0 is implemented with xor which clobbers condition code. It is
4231         // safe to move up, if the definition to EFLAGS is dead and earlier
4232         // instructions do not read or write EFLAGS.
4233         if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
4234             Inst.registerDefIsDead(X86::EFLAGS, TRI)) {
4235           Movr0Inst = &Inst;
4236           continue;
4237         }
4238 
4239         // Cannot do anything for any other EFLAG changes.
4240         return false;
4241       }
4242     }
4243 
4244     if (MI || Sub)
4245       break;
4246 
4247     // Reached begin of basic block. Continue in predecessor if there is
4248     // exactly one.
4249     if (MBB->pred_size() != 1)
4250       return false;
4251     MBB = *MBB->pred_begin();
4252     From = MBB->rbegin();
4253   }
4254 
4255   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4256   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4257   // If we are done with the basic block, we need to check whether EFLAGS is
4258   // live-out.
4259   bool FlagsMayLiveOut = true;
4260   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4261   MachineBasicBlock::iterator AfterCmpInstr =
4262       std::next(MachineBasicBlock::iterator(CmpInstr));
4263   for (MachineInstr &Instr : make_range(AfterCmpInstr, CmpMBB.end())) {
4264     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4265     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4266     // We should check the usage if this instruction uses and updates EFLAGS.
4267     if (!UseEFLAGS && ModifyEFLAGS) {
4268       // It is safe to remove CmpInstr if EFLAGS is updated again.
4269       FlagsMayLiveOut = false;
4270       break;
4271     }
4272     if (!UseEFLAGS && !ModifyEFLAGS)
4273       continue;
4274 
4275     // EFLAGS is used by this instruction.
4276     X86::CondCode OldCC = X86::COND_INVALID;
4277     if (MI || IsSwapped || ImmDelta != 0) {
4278       // We decode the condition code from opcode.
4279       if (Instr.isBranch())
4280         OldCC = X86::getCondFromBranch(Instr);
4281       else {
4282         OldCC = X86::getCondFromSETCC(Instr);
4283         if (OldCC == X86::COND_INVALID)
4284           OldCC = X86::getCondFromCMov(Instr);
4285       }
4286       if (OldCC == X86::COND_INVALID) return false;
4287     }
4288     X86::CondCode ReplacementCC = X86::COND_INVALID;
4289     if (MI) {
4290       switch (OldCC) {
4291       default: break;
4292       case X86::COND_A: case X86::COND_AE:
4293       case X86::COND_B: case X86::COND_BE:
4294         // CF is used, we can't perform this optimization.
4295         return false;
4296       case X86::COND_G: case X86::COND_GE:
4297       case X86::COND_L: case X86::COND_LE:
4298       case X86::COND_O: case X86::COND_NO:
4299         // If OF is used, the instruction needs to clear it like CmpZero does.
4300         if (!ClearsOverflowFlag)
4301           return false;
4302         break;
4303       case X86::COND_S: case X86::COND_NS:
4304         // If SF is used, but the instruction doesn't update the SF, then we
4305         // can't do the optimization.
4306         if (NoSignFlag)
4307           return false;
4308         break;
4309       }
4310 
4311       // If we're updating the condition code check if we have to reverse the
4312       // condition.
4313       if (ShouldUpdateCC)
4314         switch (OldCC) {
4315         default:
4316           return false;
4317         case X86::COND_E:
4318           ReplacementCC = NewCC;
4319           break;
4320         case X86::COND_NE:
4321           ReplacementCC = GetOppositeBranchCondition(NewCC);
4322           break;
4323         }
4324     } else if (IsSwapped) {
4325       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4326       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4327       // We swap the condition code and synthesize the new opcode.
4328       ReplacementCC = getSwappedCondition(OldCC);
4329       if (ReplacementCC == X86::COND_INVALID)
4330         return false;
4331       ShouldUpdateCC = true;
4332     } else if (ImmDelta != 0) {
4333       unsigned BitWidth = TRI->getRegSizeInBits(*MRI->getRegClass(SrcReg));
4334       // Shift amount for min/max constants to adjust for 8/16/32 instruction
4335       // sizes.
4336       switch (OldCC) {
4337       case X86::COND_L: // x <s (C + 1)  -->  x <=s C
4338         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4339           return false;
4340         ReplacementCC = X86::COND_LE;
4341         break;
4342       case X86::COND_B: // x <u (C + 1)  -->  x <=u C
4343         if (ImmDelta != 1 || CmpValue == 0)
4344           return false;
4345         ReplacementCC = X86::COND_BE;
4346         break;
4347       case X86::COND_GE: // x >=s (C + 1)  -->  x >s C
4348         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4349           return false;
4350         ReplacementCC = X86::COND_G;
4351         break;
4352       case X86::COND_AE: // x >=u (C + 1)  -->  x >u C
4353         if (ImmDelta != 1 || CmpValue == 0)
4354           return false;
4355         ReplacementCC = X86::COND_A;
4356         break;
4357       case X86::COND_G: // x >s (C - 1)  -->  x >=s C
4358         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4359           return false;
4360         ReplacementCC = X86::COND_GE;
4361         break;
4362       case X86::COND_A: // x >u (C - 1)  -->  x >=u C
4363         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4364           return false;
4365         ReplacementCC = X86::COND_AE;
4366         break;
4367       case X86::COND_LE: // x <=s (C - 1)  -->  x <s C
4368         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4369           return false;
4370         ReplacementCC = X86::COND_L;
4371         break;
4372       case X86::COND_BE: // x <=u (C - 1)  -->  x <u C
4373         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4374           return false;
4375         ReplacementCC = X86::COND_B;
4376         break;
4377       default:
4378         return false;
4379       }
4380       ShouldUpdateCC = true;
4381     }
4382 
4383     if (ShouldUpdateCC && ReplacementCC != OldCC) {
4384       // Push the MachineInstr to OpsToUpdate.
4385       // If it is safe to remove CmpInstr, the condition code of these
4386       // instructions will be modified.
4387       OpsToUpdate.push_back(std::make_pair(&Instr, ReplacementCC));
4388     }
4389     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4390       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4391       FlagsMayLiveOut = false;
4392       break;
4393     }
4394   }
4395 
4396   // If we have to update users but EFLAGS is live-out abort, since we cannot
4397   // easily find all of the users.
4398   if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
4399     for (MachineBasicBlock *Successor : CmpMBB.successors())
4400       if (Successor->isLiveIn(X86::EFLAGS))
4401         return false;
4402   }
4403 
4404   // The instruction to be updated is either Sub or MI.
4405   assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
4406   Sub = MI != nullptr ? MI : Sub;
4407   MachineBasicBlock *SubBB = Sub->getParent();
4408   // Move Movr0Inst to the appropriate place before Sub.
4409   if (Movr0Inst) {
4410     // Only move within the same block so we don't accidentally move to a
4411     // block with higher execution frequency.
4412     if (&CmpMBB != SubBB)
4413       return false;
4414     // Look backwards until we find a def that doesn't use the current EFLAGS.
4415     MachineBasicBlock::reverse_iterator InsertI = Sub,
4416                                         InsertE = Sub->getParent()->rend();
4417     for (; InsertI != InsertE; ++InsertI) {
4418       MachineInstr *Instr = &*InsertI;
4419       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4420           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4421         Movr0Inst->getParent()->remove(Movr0Inst);
4422         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4423                                    Movr0Inst);
4424         break;
4425       }
4426     }
4427     if (InsertI == InsertE)
4428       return false;
4429   }
4430 
4431   // Make sure Sub instruction defines EFLAGS and mark the def live.
4432   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4433   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4434   FlagDef->setIsDead(false);
4435 
4436   CmpInstr.eraseFromParent();
4437 
4438   // Modify the condition code of instructions in OpsToUpdate.
4439   for (auto &Op : OpsToUpdate) {
4440     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4441         .setImm(Op.second);
4442   }
4443   // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
4444   for (MachineBasicBlock *MBB = &CmpMBB; MBB != SubBB;
4445        MBB = *MBB->pred_begin()) {
4446     assert(MBB->pred_size() == 1 && "Expected exactly one predecessor");
4447     if (!MBB->isLiveIn(X86::EFLAGS))
4448       MBB->addLiveIn(X86::EFLAGS);
4449   }
4450   return true;
4451 }
4452 
4453 /// Try to remove the load by folding it to a register
4454 /// operand at the use. We fold the load instructions if load defines a virtual
4455 /// register, the virtual register is used once in the same BB, and the
4456 /// instructions in-between do not load or store, and have no side effects.
4457 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4458                                               const MachineRegisterInfo *MRI,
4459                                               Register &FoldAsLoadDefReg,
4460                                               MachineInstr *&DefMI) const {
4461   // Check whether we can move DefMI here.
4462   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4463   assert(DefMI);
4464   bool SawStore = false;
4465   if (!DefMI->isSafeToMove(nullptr, SawStore))
4466     return nullptr;
4467 
4468   // Collect information about virtual register operands of MI.
4469   SmallVector<unsigned, 1> SrcOperandIds;
4470   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4471     MachineOperand &MO = MI.getOperand(i);
4472     if (!MO.isReg())
4473       continue;
4474     Register Reg = MO.getReg();
4475     if (Reg != FoldAsLoadDefReg)
4476       continue;
4477     // Do not fold if we have a subreg use or a def.
4478     if (MO.getSubReg() || MO.isDef())
4479       return nullptr;
4480     SrcOperandIds.push_back(i);
4481   }
4482   if (SrcOperandIds.empty())
4483     return nullptr;
4484 
4485   // Check whether we can fold the def into SrcOperandId.
4486   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4487     FoldAsLoadDefReg = 0;
4488     return FoldMI;
4489   }
4490 
4491   return nullptr;
4492 }
4493 
4494 /// Expand a single-def pseudo instruction to a two-addr
4495 /// instruction with two undef reads of the register being defined.
4496 /// This is used for mapping:
4497 ///   %xmm4 = V_SET0
4498 /// to:
4499 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4500 ///
4501 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4502                              const MCInstrDesc &Desc) {
4503   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4504   Register Reg = MIB.getReg(0);
4505   MIB->setDesc(Desc);
4506 
4507   // MachineInstr::addOperand() will insert explicit operands before any
4508   // implicit operands.
4509   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4510   // But we don't trust that.
4511   assert(MIB.getReg(1) == Reg &&
4512          MIB.getReg(2) == Reg && "Misplaced operand");
4513   return true;
4514 }
4515 
4516 /// Expand a single-def pseudo instruction to a two-addr
4517 /// instruction with two %k0 reads.
4518 /// This is used for mapping:
4519 ///   %k4 = K_SET1
4520 /// to:
4521 ///   %k4 = KXNORrr %k0, %k0
4522 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4523                             Register Reg) {
4524   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4525   MIB->setDesc(Desc);
4526   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4527   return true;
4528 }
4529 
4530 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4531                           bool MinusOne) {
4532   MachineBasicBlock &MBB = *MIB->getParent();
4533   const DebugLoc &DL = MIB->getDebugLoc();
4534   Register Reg = MIB.getReg(0);
4535 
4536   // Insert the XOR.
4537   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4538       .addReg(Reg, RegState::Undef)
4539       .addReg(Reg, RegState::Undef);
4540 
4541   // Turn the pseudo into an INC or DEC.
4542   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4543   MIB.addReg(Reg);
4544 
4545   return true;
4546 }
4547 
4548 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4549                                const TargetInstrInfo &TII,
4550                                const X86Subtarget &Subtarget) {
4551   MachineBasicBlock &MBB = *MIB->getParent();
4552   const DebugLoc &DL = MIB->getDebugLoc();
4553   int64_t Imm = MIB->getOperand(1).getImm();
4554   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4555   MachineBasicBlock::iterator I = MIB.getInstr();
4556 
4557   int StackAdjustment;
4558 
4559   if (Subtarget.is64Bit()) {
4560     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4561            MIB->getOpcode() == X86::MOV32ImmSExti8);
4562 
4563     // Can't use push/pop lowering if the function might write to the red zone.
4564     X86MachineFunctionInfo *X86FI =
4565         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4566     if (X86FI->getUsesRedZone()) {
4567       MIB->setDesc(TII.get(MIB->getOpcode() ==
4568                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4569       return true;
4570     }
4571 
4572     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4573     // widen the register if necessary.
4574     StackAdjustment = 8;
4575     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4576     MIB->setDesc(TII.get(X86::POP64r));
4577     MIB->getOperand(0)
4578         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4579   } else {
4580     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4581     StackAdjustment = 4;
4582     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4583     MIB->setDesc(TII.get(X86::POP32r));
4584   }
4585   MIB->removeOperand(1);
4586   MIB->addImplicitDefUseOperands(*MBB.getParent());
4587 
4588   // Build CFI if necessary.
4589   MachineFunction &MF = *MBB.getParent();
4590   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4591   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4592   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4593   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4594   if (EmitCFI) {
4595     TFL->BuildCFI(MBB, I, DL,
4596         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4597     TFL->BuildCFI(MBB, std::next(I), DL,
4598         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4599   }
4600 
4601   return true;
4602 }
4603 
4604 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4605 // code sequence is needed for other targets.
4606 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4607                                  const TargetInstrInfo &TII) {
4608   MachineBasicBlock &MBB = *MIB->getParent();
4609   const DebugLoc &DL = MIB->getDebugLoc();
4610   Register Reg = MIB.getReg(0);
4611   const GlobalValue *GV =
4612       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4613   auto Flags = MachineMemOperand::MOLoad |
4614                MachineMemOperand::MODereferenceable |
4615                MachineMemOperand::MOInvariant;
4616   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4617       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4618   MachineBasicBlock::iterator I = MIB.getInstr();
4619 
4620   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4621       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4622       .addMemOperand(MMO);
4623   MIB->setDebugLoc(DL);
4624   MIB->setDesc(TII.get(X86::MOV64rm));
4625   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4626 }
4627 
4628 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4629   MachineBasicBlock &MBB = *MIB->getParent();
4630   MachineFunction &MF = *MBB.getParent();
4631   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4632   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4633   unsigned XorOp =
4634       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4635   MIB->setDesc(TII.get(XorOp));
4636   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4637   return true;
4638 }
4639 
4640 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4641 // but not VLX. If it uses an extended register we need to use an instruction
4642 // that loads the lower 128/256-bit, but is available with only AVX512F.
4643 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4644                             const TargetRegisterInfo *TRI,
4645                             const MCInstrDesc &LoadDesc,
4646                             const MCInstrDesc &BroadcastDesc,
4647                             unsigned SubIdx) {
4648   Register DestReg = MIB.getReg(0);
4649   // Check if DestReg is XMM16-31 or YMM16-31.
4650   if (TRI->getEncodingValue(DestReg) < 16) {
4651     // We can use a normal VEX encoded load.
4652     MIB->setDesc(LoadDesc);
4653   } else {
4654     // Use a 128/256-bit VBROADCAST instruction.
4655     MIB->setDesc(BroadcastDesc);
4656     // Change the destination to a 512-bit register.
4657     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4658     MIB->getOperand(0).setReg(DestReg);
4659   }
4660   return true;
4661 }
4662 
4663 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4664 // but not VLX. If it uses an extended register we need to use an instruction
4665 // that stores the lower 128/256-bit, but is available with only AVX512F.
4666 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4667                              const TargetRegisterInfo *TRI,
4668                              const MCInstrDesc &StoreDesc,
4669                              const MCInstrDesc &ExtractDesc,
4670                              unsigned SubIdx) {
4671   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4672   // Check if DestReg is XMM16-31 or YMM16-31.
4673   if (TRI->getEncodingValue(SrcReg) < 16) {
4674     // We can use a normal VEX encoded store.
4675     MIB->setDesc(StoreDesc);
4676   } else {
4677     // Use a VEXTRACTF instruction.
4678     MIB->setDesc(ExtractDesc);
4679     // Change the destination to a 512-bit register.
4680     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4681     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4682     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4683   }
4684 
4685   return true;
4686 }
4687 
4688 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4689   MIB->setDesc(Desc);
4690   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4691   // Temporarily remove the immediate so we can add another source register.
4692   MIB->removeOperand(2);
4693   // Add the register. Don't copy the kill flag if there is one.
4694   MIB.addReg(MIB.getReg(1),
4695              getUndefRegState(MIB->getOperand(1).isUndef()));
4696   // Add back the immediate.
4697   MIB.addImm(ShiftAmt);
4698   return true;
4699 }
4700 
4701 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4702   bool HasAVX = Subtarget.hasAVX();
4703   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4704   switch (MI.getOpcode()) {
4705   case X86::MOV32r0:
4706     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4707   case X86::MOV32r1:
4708     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4709   case X86::MOV32r_1:
4710     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4711   case X86::MOV32ImmSExti8:
4712   case X86::MOV64ImmSExti8:
4713     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4714   case X86::SETB_C32r:
4715     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4716   case X86::SETB_C64r:
4717     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4718   case X86::MMX_SET0:
4719     return Expand2AddrUndef(MIB, get(X86::MMX_PXORrr));
4720   case X86::V_SET0:
4721   case X86::FsFLD0SS:
4722   case X86::FsFLD0SD:
4723   case X86::FsFLD0F128:
4724     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4725   case X86::AVX_SET0: {
4726     assert(HasAVX && "AVX not supported");
4727     const TargetRegisterInfo *TRI = &getRegisterInfo();
4728     Register SrcReg = MIB.getReg(0);
4729     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4730     MIB->getOperand(0).setReg(XReg);
4731     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4732     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4733     return true;
4734   }
4735   case X86::AVX512_128_SET0:
4736   case X86::AVX512_FsFLD0SH:
4737   case X86::AVX512_FsFLD0SS:
4738   case X86::AVX512_FsFLD0SD:
4739   case X86::AVX512_FsFLD0F128: {
4740     bool HasVLX = Subtarget.hasVLX();
4741     Register SrcReg = MIB.getReg(0);
4742     const TargetRegisterInfo *TRI = &getRegisterInfo();
4743     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4744       return Expand2AddrUndef(MIB,
4745                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4746     // Extended register without VLX. Use a larger XOR.
4747     SrcReg =
4748         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4749     MIB->getOperand(0).setReg(SrcReg);
4750     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4751   }
4752   case X86::AVX512_256_SET0:
4753   case X86::AVX512_512_SET0: {
4754     bool HasVLX = Subtarget.hasVLX();
4755     Register SrcReg = MIB.getReg(0);
4756     const TargetRegisterInfo *TRI = &getRegisterInfo();
4757     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4758       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4759       MIB->getOperand(0).setReg(XReg);
4760       Expand2AddrUndef(MIB,
4761                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4762       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4763       return true;
4764     }
4765     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4766       // No VLX so we must reference a zmm.
4767       unsigned ZReg =
4768         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4769       MIB->getOperand(0).setReg(ZReg);
4770     }
4771     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4772   }
4773   case X86::V_SETALLONES:
4774     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4775   case X86::AVX2_SETALLONES:
4776     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4777   case X86::AVX1_SETALLONES: {
4778     Register Reg = MIB.getReg(0);
4779     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4780     MIB->setDesc(get(X86::VCMPPSYrri));
4781     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4782     return true;
4783   }
4784   case X86::AVX512_512_SETALLONES: {
4785     Register Reg = MIB.getReg(0);
4786     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4787     // VPTERNLOGD needs 3 register inputs and an immediate.
4788     // 0xff will return 1s for any input.
4789     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4790        .addReg(Reg, RegState::Undef).addImm(0xff);
4791     return true;
4792   }
4793   case X86::AVX512_512_SEXT_MASK_32:
4794   case X86::AVX512_512_SEXT_MASK_64: {
4795     Register Reg = MIB.getReg(0);
4796     Register MaskReg = MIB.getReg(1);
4797     unsigned MaskState = getRegState(MIB->getOperand(1));
4798     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4799                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4800     MI.removeOperand(1);
4801     MIB->setDesc(get(Opc));
4802     // VPTERNLOG needs 3 register inputs and an immediate.
4803     // 0xff will return 1s for any input.
4804     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4805        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4806     return true;
4807   }
4808   case X86::VMOVAPSZ128rm_NOVLX:
4809     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4810                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4811   case X86::VMOVUPSZ128rm_NOVLX:
4812     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4813                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4814   case X86::VMOVAPSZ256rm_NOVLX:
4815     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4816                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4817   case X86::VMOVUPSZ256rm_NOVLX:
4818     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4819                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4820   case X86::VMOVAPSZ128mr_NOVLX:
4821     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4822                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4823   case X86::VMOVUPSZ128mr_NOVLX:
4824     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4825                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4826   case X86::VMOVAPSZ256mr_NOVLX:
4827     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4828                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4829   case X86::VMOVUPSZ256mr_NOVLX:
4830     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4831                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4832   case X86::MOV32ri64: {
4833     Register Reg = MIB.getReg(0);
4834     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4835     MI.setDesc(get(X86::MOV32ri));
4836     MIB->getOperand(0).setReg(Reg32);
4837     MIB.addReg(Reg, RegState::ImplicitDefine);
4838     return true;
4839   }
4840 
4841   // KNL does not recognize dependency-breaking idioms for mask registers,
4842   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4843   // Using %k0 as the undef input register is a performance heuristic based
4844   // on the assumption that %k0 is used less frequently than the other mask
4845   // registers, since it is not usable as a write mask.
4846   // FIXME: A more advanced approach would be to choose the best input mask
4847   // register based on context.
4848   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4849   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4850   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4851   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4852   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4853   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4854   case TargetOpcode::LOAD_STACK_GUARD:
4855     expandLoadStackGuard(MIB, *this);
4856     return true;
4857   case X86::XOR64_FP:
4858   case X86::XOR32_FP:
4859     return expandXorFP(MIB, *this);
4860   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4861   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4862   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4863   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4864   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4865   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4866   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4867   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4868   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4869   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4870   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4871   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4872   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4873   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4874   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4875   }
4876   return false;
4877 }
4878 
4879 /// Return true for all instructions that only update
4880 /// the first 32 or 64-bits of the destination register and leave the rest
4881 /// unmodified. This can be used to avoid folding loads if the instructions
4882 /// only update part of the destination register, and the non-updated part is
4883 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4884 /// instructions breaks the partial register dependency and it can improve
4885 /// performance. e.g.:
4886 ///
4887 ///   movss (%rdi), %xmm0
4888 ///   cvtss2sd %xmm0, %xmm0
4889 ///
4890 /// Instead of
4891 ///   cvtss2sd (%rdi), %xmm0
4892 ///
4893 /// FIXME: This should be turned into a TSFlags.
4894 ///
4895 static bool hasPartialRegUpdate(unsigned Opcode,
4896                                 const X86Subtarget &Subtarget,
4897                                 bool ForLoadFold = false) {
4898   switch (Opcode) {
4899   case X86::CVTSI2SSrr:
4900   case X86::CVTSI2SSrm:
4901   case X86::CVTSI642SSrr:
4902   case X86::CVTSI642SSrm:
4903   case X86::CVTSI2SDrr:
4904   case X86::CVTSI2SDrm:
4905   case X86::CVTSI642SDrr:
4906   case X86::CVTSI642SDrm:
4907     // Load folding won't effect the undef register update since the input is
4908     // a GPR.
4909     return !ForLoadFold;
4910   case X86::CVTSD2SSrr:
4911   case X86::CVTSD2SSrm:
4912   case X86::CVTSS2SDrr:
4913   case X86::CVTSS2SDrm:
4914   case X86::MOVHPDrm:
4915   case X86::MOVHPSrm:
4916   case X86::MOVLPDrm:
4917   case X86::MOVLPSrm:
4918   case X86::RCPSSr:
4919   case X86::RCPSSm:
4920   case X86::RCPSSr_Int:
4921   case X86::RCPSSm_Int:
4922   case X86::ROUNDSDr:
4923   case X86::ROUNDSDm:
4924   case X86::ROUNDSSr:
4925   case X86::ROUNDSSm:
4926   case X86::RSQRTSSr:
4927   case X86::RSQRTSSm:
4928   case X86::RSQRTSSr_Int:
4929   case X86::RSQRTSSm_Int:
4930   case X86::SQRTSSr:
4931   case X86::SQRTSSm:
4932   case X86::SQRTSSr_Int:
4933   case X86::SQRTSSm_Int:
4934   case X86::SQRTSDr:
4935   case X86::SQRTSDm:
4936   case X86::SQRTSDr_Int:
4937   case X86::SQRTSDm_Int:
4938     return true;
4939   // GPR
4940   case X86::POPCNT32rm:
4941   case X86::POPCNT32rr:
4942   case X86::POPCNT64rm:
4943   case X86::POPCNT64rr:
4944     return Subtarget.hasPOPCNTFalseDeps();
4945   case X86::LZCNT32rm:
4946   case X86::LZCNT32rr:
4947   case X86::LZCNT64rm:
4948   case X86::LZCNT64rr:
4949   case X86::TZCNT32rm:
4950   case X86::TZCNT32rr:
4951   case X86::TZCNT64rm:
4952   case X86::TZCNT64rr:
4953     return Subtarget.hasLZCNTFalseDeps();
4954   }
4955 
4956   return false;
4957 }
4958 
4959 /// Inform the BreakFalseDeps pass how many idle
4960 /// instructions we would like before a partial register update.
4961 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4962     const MachineInstr &MI, unsigned OpNum,
4963     const TargetRegisterInfo *TRI) const {
4964   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4965     return 0;
4966 
4967   // If MI is marked as reading Reg, the partial register update is wanted.
4968   const MachineOperand &MO = MI.getOperand(0);
4969   Register Reg = MO.getReg();
4970   if (Reg.isVirtual()) {
4971     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4972       return 0;
4973   } else {
4974     if (MI.readsRegister(Reg, TRI))
4975       return 0;
4976   }
4977 
4978   // If any instructions in the clearance range are reading Reg, insert a
4979   // dependency breaking instruction, which is inexpensive and is likely to
4980   // be hidden in other instruction's cycles.
4981   return PartialRegUpdateClearance;
4982 }
4983 
4984 // Return true for any instruction the copies the high bits of the first source
4985 // operand into the unused high bits of the destination operand.
4986 // Also returns true for instructions that have two inputs where one may
4987 // be undef and we want it to use the same register as the other input.
4988 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
4989                               bool ForLoadFold = false) {
4990   // Set the OpNum parameter to the first source operand.
4991   switch (Opcode) {
4992   case X86::MMX_PUNPCKHBWrr:
4993   case X86::MMX_PUNPCKHWDrr:
4994   case X86::MMX_PUNPCKHDQrr:
4995   case X86::MMX_PUNPCKLBWrr:
4996   case X86::MMX_PUNPCKLWDrr:
4997   case X86::MMX_PUNPCKLDQrr:
4998   case X86::MOVHLPSrr:
4999   case X86::PACKSSWBrr:
5000   case X86::PACKUSWBrr:
5001   case X86::PACKSSDWrr:
5002   case X86::PACKUSDWrr:
5003   case X86::PUNPCKHBWrr:
5004   case X86::PUNPCKLBWrr:
5005   case X86::PUNPCKHWDrr:
5006   case X86::PUNPCKLWDrr:
5007   case X86::PUNPCKHDQrr:
5008   case X86::PUNPCKLDQrr:
5009   case X86::PUNPCKHQDQrr:
5010   case X86::PUNPCKLQDQrr:
5011   case X86::SHUFPDrri:
5012   case X86::SHUFPSrri:
5013     // These instructions are sometimes used with an undef first or second
5014     // source. Return true here so BreakFalseDeps will assign this source to the
5015     // same register as the first source to avoid a false dependency.
5016     // Operand 1 of these instructions is tied so they're separate from their
5017     // VEX counterparts.
5018     return OpNum == 2 && !ForLoadFold;
5019 
5020   case X86::VMOVLHPSrr:
5021   case X86::VMOVLHPSZrr:
5022   case X86::VPACKSSWBrr:
5023   case X86::VPACKUSWBrr:
5024   case X86::VPACKSSDWrr:
5025   case X86::VPACKUSDWrr:
5026   case X86::VPACKSSWBZ128rr:
5027   case X86::VPACKUSWBZ128rr:
5028   case X86::VPACKSSDWZ128rr:
5029   case X86::VPACKUSDWZ128rr:
5030   case X86::VPERM2F128rr:
5031   case X86::VPERM2I128rr:
5032   case X86::VSHUFF32X4Z256rri:
5033   case X86::VSHUFF32X4Zrri:
5034   case X86::VSHUFF64X2Z256rri:
5035   case X86::VSHUFF64X2Zrri:
5036   case X86::VSHUFI32X4Z256rri:
5037   case X86::VSHUFI32X4Zrri:
5038   case X86::VSHUFI64X2Z256rri:
5039   case X86::VSHUFI64X2Zrri:
5040   case X86::VPUNPCKHBWrr:
5041   case X86::VPUNPCKLBWrr:
5042   case X86::VPUNPCKHBWYrr:
5043   case X86::VPUNPCKLBWYrr:
5044   case X86::VPUNPCKHBWZ128rr:
5045   case X86::VPUNPCKLBWZ128rr:
5046   case X86::VPUNPCKHBWZ256rr:
5047   case X86::VPUNPCKLBWZ256rr:
5048   case X86::VPUNPCKHBWZrr:
5049   case X86::VPUNPCKLBWZrr:
5050   case X86::VPUNPCKHWDrr:
5051   case X86::VPUNPCKLWDrr:
5052   case X86::VPUNPCKHWDYrr:
5053   case X86::VPUNPCKLWDYrr:
5054   case X86::VPUNPCKHWDZ128rr:
5055   case X86::VPUNPCKLWDZ128rr:
5056   case X86::VPUNPCKHWDZ256rr:
5057   case X86::VPUNPCKLWDZ256rr:
5058   case X86::VPUNPCKHWDZrr:
5059   case X86::VPUNPCKLWDZrr:
5060   case X86::VPUNPCKHDQrr:
5061   case X86::VPUNPCKLDQrr:
5062   case X86::VPUNPCKHDQYrr:
5063   case X86::VPUNPCKLDQYrr:
5064   case X86::VPUNPCKHDQZ128rr:
5065   case X86::VPUNPCKLDQZ128rr:
5066   case X86::VPUNPCKHDQZ256rr:
5067   case X86::VPUNPCKLDQZ256rr:
5068   case X86::VPUNPCKHDQZrr:
5069   case X86::VPUNPCKLDQZrr:
5070   case X86::VPUNPCKHQDQrr:
5071   case X86::VPUNPCKLQDQrr:
5072   case X86::VPUNPCKHQDQYrr:
5073   case X86::VPUNPCKLQDQYrr:
5074   case X86::VPUNPCKHQDQZ128rr:
5075   case X86::VPUNPCKLQDQZ128rr:
5076   case X86::VPUNPCKHQDQZ256rr:
5077   case X86::VPUNPCKLQDQZ256rr:
5078   case X86::VPUNPCKHQDQZrr:
5079   case X86::VPUNPCKLQDQZrr:
5080     // These instructions are sometimes used with an undef first or second
5081     // source. Return true here so BreakFalseDeps will assign this source to the
5082     // same register as the first source to avoid a false dependency.
5083     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5084 
5085   case X86::VCVTSI2SSrr:
5086   case X86::VCVTSI2SSrm:
5087   case X86::VCVTSI2SSrr_Int:
5088   case X86::VCVTSI2SSrm_Int:
5089   case X86::VCVTSI642SSrr:
5090   case X86::VCVTSI642SSrm:
5091   case X86::VCVTSI642SSrr_Int:
5092   case X86::VCVTSI642SSrm_Int:
5093   case X86::VCVTSI2SDrr:
5094   case X86::VCVTSI2SDrm:
5095   case X86::VCVTSI2SDrr_Int:
5096   case X86::VCVTSI2SDrm_Int:
5097   case X86::VCVTSI642SDrr:
5098   case X86::VCVTSI642SDrm:
5099   case X86::VCVTSI642SDrr_Int:
5100   case X86::VCVTSI642SDrm_Int:
5101   // AVX-512
5102   case X86::VCVTSI2SSZrr:
5103   case X86::VCVTSI2SSZrm:
5104   case X86::VCVTSI2SSZrr_Int:
5105   case X86::VCVTSI2SSZrrb_Int:
5106   case X86::VCVTSI2SSZrm_Int:
5107   case X86::VCVTSI642SSZrr:
5108   case X86::VCVTSI642SSZrm:
5109   case X86::VCVTSI642SSZrr_Int:
5110   case X86::VCVTSI642SSZrrb_Int:
5111   case X86::VCVTSI642SSZrm_Int:
5112   case X86::VCVTSI2SDZrr:
5113   case X86::VCVTSI2SDZrm:
5114   case X86::VCVTSI2SDZrr_Int:
5115   case X86::VCVTSI2SDZrm_Int:
5116   case X86::VCVTSI642SDZrr:
5117   case X86::VCVTSI642SDZrm:
5118   case X86::VCVTSI642SDZrr_Int:
5119   case X86::VCVTSI642SDZrrb_Int:
5120   case X86::VCVTSI642SDZrm_Int:
5121   case X86::VCVTUSI2SSZrr:
5122   case X86::VCVTUSI2SSZrm:
5123   case X86::VCVTUSI2SSZrr_Int:
5124   case X86::VCVTUSI2SSZrrb_Int:
5125   case X86::VCVTUSI2SSZrm_Int:
5126   case X86::VCVTUSI642SSZrr:
5127   case X86::VCVTUSI642SSZrm:
5128   case X86::VCVTUSI642SSZrr_Int:
5129   case X86::VCVTUSI642SSZrrb_Int:
5130   case X86::VCVTUSI642SSZrm_Int:
5131   case X86::VCVTUSI2SDZrr:
5132   case X86::VCVTUSI2SDZrm:
5133   case X86::VCVTUSI2SDZrr_Int:
5134   case X86::VCVTUSI2SDZrm_Int:
5135   case X86::VCVTUSI642SDZrr:
5136   case X86::VCVTUSI642SDZrm:
5137   case X86::VCVTUSI642SDZrr_Int:
5138   case X86::VCVTUSI642SDZrrb_Int:
5139   case X86::VCVTUSI642SDZrm_Int:
5140   case X86::VCVTSI2SHZrr:
5141   case X86::VCVTSI2SHZrm:
5142   case X86::VCVTSI2SHZrr_Int:
5143   case X86::VCVTSI2SHZrrb_Int:
5144   case X86::VCVTSI2SHZrm_Int:
5145   case X86::VCVTSI642SHZrr:
5146   case X86::VCVTSI642SHZrm:
5147   case X86::VCVTSI642SHZrr_Int:
5148   case X86::VCVTSI642SHZrrb_Int:
5149   case X86::VCVTSI642SHZrm_Int:
5150   case X86::VCVTUSI2SHZrr:
5151   case X86::VCVTUSI2SHZrm:
5152   case X86::VCVTUSI2SHZrr_Int:
5153   case X86::VCVTUSI2SHZrrb_Int:
5154   case X86::VCVTUSI2SHZrm_Int:
5155   case X86::VCVTUSI642SHZrr:
5156   case X86::VCVTUSI642SHZrm:
5157   case X86::VCVTUSI642SHZrr_Int:
5158   case X86::VCVTUSI642SHZrrb_Int:
5159   case X86::VCVTUSI642SHZrm_Int:
5160     // Load folding won't effect the undef register update since the input is
5161     // a GPR.
5162     return OpNum == 1 && !ForLoadFold;
5163   case X86::VCVTSD2SSrr:
5164   case X86::VCVTSD2SSrm:
5165   case X86::VCVTSD2SSrr_Int:
5166   case X86::VCVTSD2SSrm_Int:
5167   case X86::VCVTSS2SDrr:
5168   case X86::VCVTSS2SDrm:
5169   case X86::VCVTSS2SDrr_Int:
5170   case X86::VCVTSS2SDrm_Int:
5171   case X86::VRCPSSr:
5172   case X86::VRCPSSr_Int:
5173   case X86::VRCPSSm:
5174   case X86::VRCPSSm_Int:
5175   case X86::VROUNDSDr:
5176   case X86::VROUNDSDm:
5177   case X86::VROUNDSDr_Int:
5178   case X86::VROUNDSDm_Int:
5179   case X86::VROUNDSSr:
5180   case X86::VROUNDSSm:
5181   case X86::VROUNDSSr_Int:
5182   case X86::VROUNDSSm_Int:
5183   case X86::VRSQRTSSr:
5184   case X86::VRSQRTSSr_Int:
5185   case X86::VRSQRTSSm:
5186   case X86::VRSQRTSSm_Int:
5187   case X86::VSQRTSSr:
5188   case X86::VSQRTSSr_Int:
5189   case X86::VSQRTSSm:
5190   case X86::VSQRTSSm_Int:
5191   case X86::VSQRTSDr:
5192   case X86::VSQRTSDr_Int:
5193   case X86::VSQRTSDm:
5194   case X86::VSQRTSDm_Int:
5195   // AVX-512
5196   case X86::VCVTSD2SSZrr:
5197   case X86::VCVTSD2SSZrr_Int:
5198   case X86::VCVTSD2SSZrrb_Int:
5199   case X86::VCVTSD2SSZrm:
5200   case X86::VCVTSD2SSZrm_Int:
5201   case X86::VCVTSS2SDZrr:
5202   case X86::VCVTSS2SDZrr_Int:
5203   case X86::VCVTSS2SDZrrb_Int:
5204   case X86::VCVTSS2SDZrm:
5205   case X86::VCVTSS2SDZrm_Int:
5206   case X86::VGETEXPSDZr:
5207   case X86::VGETEXPSDZrb:
5208   case X86::VGETEXPSDZm:
5209   case X86::VGETEXPSSZr:
5210   case X86::VGETEXPSSZrb:
5211   case X86::VGETEXPSSZm:
5212   case X86::VGETMANTSDZrri:
5213   case X86::VGETMANTSDZrrib:
5214   case X86::VGETMANTSDZrmi:
5215   case X86::VGETMANTSSZrri:
5216   case X86::VGETMANTSSZrrib:
5217   case X86::VGETMANTSSZrmi:
5218   case X86::VRNDSCALESDZr:
5219   case X86::VRNDSCALESDZr_Int:
5220   case X86::VRNDSCALESDZrb_Int:
5221   case X86::VRNDSCALESDZm:
5222   case X86::VRNDSCALESDZm_Int:
5223   case X86::VRNDSCALESSZr:
5224   case X86::VRNDSCALESSZr_Int:
5225   case X86::VRNDSCALESSZrb_Int:
5226   case X86::VRNDSCALESSZm:
5227   case X86::VRNDSCALESSZm_Int:
5228   case X86::VRCP14SDZrr:
5229   case X86::VRCP14SDZrm:
5230   case X86::VRCP14SSZrr:
5231   case X86::VRCP14SSZrm:
5232   case X86::VRCPSHZrr:
5233   case X86::VRCPSHZrm:
5234   case X86::VRSQRTSHZrr:
5235   case X86::VRSQRTSHZrm:
5236   case X86::VREDUCESHZrmi:
5237   case X86::VREDUCESHZrri:
5238   case X86::VREDUCESHZrrib:
5239   case X86::VGETEXPSHZr:
5240   case X86::VGETEXPSHZrb:
5241   case X86::VGETEXPSHZm:
5242   case X86::VGETMANTSHZrri:
5243   case X86::VGETMANTSHZrrib:
5244   case X86::VGETMANTSHZrmi:
5245   case X86::VRNDSCALESHZr:
5246   case X86::VRNDSCALESHZr_Int:
5247   case X86::VRNDSCALESHZrb_Int:
5248   case X86::VRNDSCALESHZm:
5249   case X86::VRNDSCALESHZm_Int:
5250   case X86::VSQRTSHZr:
5251   case X86::VSQRTSHZr_Int:
5252   case X86::VSQRTSHZrb_Int:
5253   case X86::VSQRTSHZm:
5254   case X86::VSQRTSHZm_Int:
5255   case X86::VRCP28SDZr:
5256   case X86::VRCP28SDZrb:
5257   case X86::VRCP28SDZm:
5258   case X86::VRCP28SSZr:
5259   case X86::VRCP28SSZrb:
5260   case X86::VRCP28SSZm:
5261   case X86::VREDUCESSZrmi:
5262   case X86::VREDUCESSZrri:
5263   case X86::VREDUCESSZrrib:
5264   case X86::VRSQRT14SDZrr:
5265   case X86::VRSQRT14SDZrm:
5266   case X86::VRSQRT14SSZrr:
5267   case X86::VRSQRT14SSZrm:
5268   case X86::VRSQRT28SDZr:
5269   case X86::VRSQRT28SDZrb:
5270   case X86::VRSQRT28SDZm:
5271   case X86::VRSQRT28SSZr:
5272   case X86::VRSQRT28SSZrb:
5273   case X86::VRSQRT28SSZm:
5274   case X86::VSQRTSSZr:
5275   case X86::VSQRTSSZr_Int:
5276   case X86::VSQRTSSZrb_Int:
5277   case X86::VSQRTSSZm:
5278   case X86::VSQRTSSZm_Int:
5279   case X86::VSQRTSDZr:
5280   case X86::VSQRTSDZr_Int:
5281   case X86::VSQRTSDZrb_Int:
5282   case X86::VSQRTSDZm:
5283   case X86::VSQRTSDZm_Int:
5284   case X86::VCVTSD2SHZrr:
5285   case X86::VCVTSD2SHZrr_Int:
5286   case X86::VCVTSD2SHZrrb_Int:
5287   case X86::VCVTSD2SHZrm:
5288   case X86::VCVTSD2SHZrm_Int:
5289   case X86::VCVTSS2SHZrr:
5290   case X86::VCVTSS2SHZrr_Int:
5291   case X86::VCVTSS2SHZrrb_Int:
5292   case X86::VCVTSS2SHZrm:
5293   case X86::VCVTSS2SHZrm_Int:
5294   case X86::VCVTSH2SDZrr:
5295   case X86::VCVTSH2SDZrr_Int:
5296   case X86::VCVTSH2SDZrrb_Int:
5297   case X86::VCVTSH2SDZrm:
5298   case X86::VCVTSH2SDZrm_Int:
5299   case X86::VCVTSH2SSZrr:
5300   case X86::VCVTSH2SSZrr_Int:
5301   case X86::VCVTSH2SSZrrb_Int:
5302   case X86::VCVTSH2SSZrm:
5303   case X86::VCVTSH2SSZrm_Int:
5304     return OpNum == 1;
5305   case X86::VMOVSSZrrk:
5306   case X86::VMOVSDZrrk:
5307     return OpNum == 3 && !ForLoadFold;
5308   case X86::VMOVSSZrrkz:
5309   case X86::VMOVSDZrrkz:
5310     return OpNum == 2 && !ForLoadFold;
5311   }
5312 
5313   return false;
5314 }
5315 
5316 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5317 /// before certain undef register reads.
5318 ///
5319 /// This catches the VCVTSI2SD family of instructions:
5320 ///
5321 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5322 ///
5323 /// We should to be careful *not* to catch VXOR idioms which are presumably
5324 /// handled specially in the pipeline:
5325 ///
5326 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5327 ///
5328 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5329 /// high bits that are passed-through are not live.
5330 unsigned
5331 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5332                                    const TargetRegisterInfo *TRI) const {
5333   const MachineOperand &MO = MI.getOperand(OpNum);
5334   if (Register::isPhysicalRegister(MO.getReg()) &&
5335       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5336     return UndefRegClearance;
5337 
5338   return 0;
5339 }
5340 
5341 void X86InstrInfo::breakPartialRegDependency(
5342     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5343   Register Reg = MI.getOperand(OpNum).getReg();
5344   // If MI kills this register, the false dependence is already broken.
5345   if (MI.killsRegister(Reg, TRI))
5346     return;
5347 
5348   if (X86::VR128RegClass.contains(Reg)) {
5349     // These instructions are all floating point domain, so xorps is the best
5350     // choice.
5351     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5352     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5353         .addReg(Reg, RegState::Undef)
5354         .addReg(Reg, RegState::Undef);
5355     MI.addRegisterKilled(Reg, TRI, true);
5356   } else if (X86::VR256RegClass.contains(Reg)) {
5357     // Use vxorps to clear the full ymm register.
5358     // It wants to read and write the xmm sub-register.
5359     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5360     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5361         .addReg(XReg, RegState::Undef)
5362         .addReg(XReg, RegState::Undef)
5363         .addReg(Reg, RegState::ImplicitDefine);
5364     MI.addRegisterKilled(Reg, TRI, true);
5365   } else if (X86::GR64RegClass.contains(Reg)) {
5366     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5367     // as well.
5368     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5369     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5370         .addReg(XReg, RegState::Undef)
5371         .addReg(XReg, RegState::Undef)
5372         .addReg(Reg, RegState::ImplicitDefine);
5373     MI.addRegisterKilled(Reg, TRI, true);
5374   } else if (X86::GR32RegClass.contains(Reg)) {
5375     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5376         .addReg(Reg, RegState::Undef)
5377         .addReg(Reg, RegState::Undef);
5378     MI.addRegisterKilled(Reg, TRI, true);
5379   }
5380 }
5381 
5382 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5383                         int PtrOffset = 0) {
5384   unsigned NumAddrOps = MOs.size();
5385 
5386   if (NumAddrOps < 4) {
5387     // FrameIndex only - add an immediate offset (whether its zero or not).
5388     for (unsigned i = 0; i != NumAddrOps; ++i)
5389       MIB.add(MOs[i]);
5390     addOffset(MIB, PtrOffset);
5391   } else {
5392     // General Memory Addressing - we need to add any offset to an existing
5393     // offset.
5394     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5395     for (unsigned i = 0; i != NumAddrOps; ++i) {
5396       const MachineOperand &MO = MOs[i];
5397       if (i == 3 && PtrOffset != 0) {
5398         MIB.addDisp(MO, PtrOffset);
5399       } else {
5400         MIB.add(MO);
5401       }
5402     }
5403   }
5404 }
5405 
5406 static void updateOperandRegConstraints(MachineFunction &MF,
5407                                         MachineInstr &NewMI,
5408                                         const TargetInstrInfo &TII) {
5409   MachineRegisterInfo &MRI = MF.getRegInfo();
5410   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5411 
5412   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5413     MachineOperand &MO = NewMI.getOperand(Idx);
5414     // We only need to update constraints on virtual register operands.
5415     if (!MO.isReg())
5416       continue;
5417     Register Reg = MO.getReg();
5418     if (!Reg.isVirtual())
5419       continue;
5420 
5421     auto *NewRC = MRI.constrainRegClass(
5422         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5423     if (!NewRC) {
5424       LLVM_DEBUG(
5425           dbgs() << "WARNING: Unable to update register constraint for operand "
5426                  << Idx << " of instruction:\n";
5427           NewMI.dump(); dbgs() << "\n");
5428     }
5429   }
5430 }
5431 
5432 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5433                                      ArrayRef<MachineOperand> MOs,
5434                                      MachineBasicBlock::iterator InsertPt,
5435                                      MachineInstr &MI,
5436                                      const TargetInstrInfo &TII) {
5437   // Create the base instruction with the memory operand as the first part.
5438   // Omit the implicit operands, something BuildMI can't do.
5439   MachineInstr *NewMI =
5440       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5441   MachineInstrBuilder MIB(MF, NewMI);
5442   addOperands(MIB, MOs);
5443 
5444   // Loop over the rest of the ri operands, converting them over.
5445   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5446   for (unsigned i = 0; i != NumOps; ++i) {
5447     MachineOperand &MO = MI.getOperand(i + 2);
5448     MIB.add(MO);
5449   }
5450   for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), NumOps + 2))
5451     MIB.add(MO);
5452 
5453   updateOperandRegConstraints(MF, *NewMI, TII);
5454 
5455   MachineBasicBlock *MBB = InsertPt->getParent();
5456   MBB->insert(InsertPt, NewMI);
5457 
5458   return MIB;
5459 }
5460 
5461 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5462                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5463                               MachineBasicBlock::iterator InsertPt,
5464                               MachineInstr &MI, const TargetInstrInfo &TII,
5465                               int PtrOffset = 0) {
5466   // Omit the implicit operands, something BuildMI can't do.
5467   MachineInstr *NewMI =
5468       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5469   MachineInstrBuilder MIB(MF, NewMI);
5470 
5471   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5472     MachineOperand &MO = MI.getOperand(i);
5473     if (i == OpNo) {
5474       assert(MO.isReg() && "Expected to fold into reg operand!");
5475       addOperands(MIB, MOs, PtrOffset);
5476     } else {
5477       MIB.add(MO);
5478     }
5479   }
5480 
5481   updateOperandRegConstraints(MF, *NewMI, TII);
5482 
5483   // Copy the NoFPExcept flag from the instruction we're fusing.
5484   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5485     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5486 
5487   MachineBasicBlock *MBB = InsertPt->getParent();
5488   MBB->insert(InsertPt, NewMI);
5489 
5490   return MIB;
5491 }
5492 
5493 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5494                                 ArrayRef<MachineOperand> MOs,
5495                                 MachineBasicBlock::iterator InsertPt,
5496                                 MachineInstr &MI) {
5497   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5498                                     MI.getDebugLoc(), TII.get(Opcode));
5499   addOperands(MIB, MOs);
5500   return MIB.addImm(0);
5501 }
5502 
5503 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5504     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5505     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5506     unsigned Size, Align Alignment) const {
5507   switch (MI.getOpcode()) {
5508   case X86::INSERTPSrr:
5509   case X86::VINSERTPSrr:
5510   case X86::VINSERTPSZrr:
5511     // Attempt to convert the load of inserted vector into a fold load
5512     // of a single float.
5513     if (OpNum == 2) {
5514       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5515       unsigned ZMask = Imm & 15;
5516       unsigned DstIdx = (Imm >> 4) & 3;
5517       unsigned SrcIdx = (Imm >> 6) & 3;
5518 
5519       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5520       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5521       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5522       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5523         int PtrOffset = SrcIdx * 4;
5524         unsigned NewImm = (DstIdx << 4) | ZMask;
5525         unsigned NewOpCode =
5526             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5527             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5528                                                     X86::INSERTPSrm;
5529         MachineInstr *NewMI =
5530             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5531         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5532         return NewMI;
5533       }
5534     }
5535     break;
5536   case X86::MOVHLPSrr:
5537   case X86::VMOVHLPSrr:
5538   case X86::VMOVHLPSZrr:
5539     // Move the upper 64-bits of the second operand to the lower 64-bits.
5540     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5541     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5542     if (OpNum == 2) {
5543       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5544       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5545       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5546       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5547         unsigned NewOpCode =
5548             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5549             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5550                                                    X86::MOVLPSrm;
5551         MachineInstr *NewMI =
5552             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5553         return NewMI;
5554       }
5555     }
5556     break;
5557   case X86::UNPCKLPDrr:
5558     // If we won't be able to fold this to the memory form of UNPCKL, use
5559     // MOVHPD instead. Done as custom because we can't have this in the load
5560     // table twice.
5561     if (OpNum == 2) {
5562       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5563       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5564       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5565       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5566         MachineInstr *NewMI =
5567             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5568         return NewMI;
5569       }
5570     }
5571     break;
5572   }
5573 
5574   return nullptr;
5575 }
5576 
5577 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5578                                                MachineInstr &MI) {
5579   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5580       !MI.getOperand(1).isReg())
5581     return false;
5582 
5583   // The are two cases we need to handle depending on where in the pipeline
5584   // the folding attempt is being made.
5585   // -Register has the undef flag set.
5586   // -Register is produced by the IMPLICIT_DEF instruction.
5587 
5588   if (MI.getOperand(1).isUndef())
5589     return true;
5590 
5591   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5592   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5593   return VRegDef && VRegDef->isImplicitDef();
5594 }
5595 
5596 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5597     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5598     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5599     unsigned Size, Align Alignment, bool AllowCommute) const {
5600   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5601   bool isTwoAddrFold = false;
5602 
5603   // For CPUs that favor the register form of a call or push,
5604   // do not fold loads into calls or pushes, unless optimizing for size
5605   // aggressively.
5606   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5607       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5608        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5609        MI.getOpcode() == X86::PUSH64r))
5610     return nullptr;
5611 
5612   // Avoid partial and undef register update stalls unless optimizing for size.
5613   if (!MF.getFunction().hasOptSize() &&
5614       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5615        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5616     return nullptr;
5617 
5618   unsigned NumOps = MI.getDesc().getNumOperands();
5619   bool isTwoAddr =
5620       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5621 
5622   // FIXME: AsmPrinter doesn't know how to handle
5623   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5624   if (MI.getOpcode() == X86::ADD32ri &&
5625       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5626     return nullptr;
5627 
5628   // GOTTPOFF relocation loads can only be folded into add instructions.
5629   // FIXME: Need to exclude other relocations that only support specific
5630   // instructions.
5631   if (MOs.size() == X86::AddrNumOperands &&
5632       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5633       MI.getOpcode() != X86::ADD64rr)
5634     return nullptr;
5635 
5636   MachineInstr *NewMI = nullptr;
5637 
5638   // Attempt to fold any custom cases we have.
5639   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5640           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5641     return CustomMI;
5642 
5643   const X86MemoryFoldTableEntry *I = nullptr;
5644 
5645   // Folding a memory location into the two-address part of a two-address
5646   // instruction is different than folding it other places.  It requires
5647   // replacing the *two* registers with the memory location.
5648   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5649       MI.getOperand(1).isReg() &&
5650       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5651     I = lookupTwoAddrFoldTable(MI.getOpcode());
5652     isTwoAddrFold = true;
5653   } else {
5654     if (OpNum == 0) {
5655       if (MI.getOpcode() == X86::MOV32r0) {
5656         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5657         if (NewMI)
5658           return NewMI;
5659       }
5660     }
5661 
5662     I = lookupFoldTable(MI.getOpcode(), OpNum);
5663   }
5664 
5665   if (I != nullptr) {
5666     unsigned Opcode = I->DstOp;
5667     bool FoldedLoad =
5668         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5669     bool FoldedStore =
5670         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5671     MaybeAlign MinAlign =
5672         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5673     if (MinAlign && Alignment < *MinAlign)
5674       return nullptr;
5675     bool NarrowToMOV32rm = false;
5676     if (Size) {
5677       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5678       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5679                                                   &RI, MF);
5680       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5681       // Check if it's safe to fold the load. If the size of the object is
5682       // narrower than the load width, then it's not.
5683       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5684       if (FoldedLoad && Size < RCSize) {
5685         // If this is a 64-bit load, but the spill slot is 32, then we can do
5686         // a 32-bit load which is implicitly zero-extended. This likely is
5687         // due to live interval analysis remat'ing a load from stack slot.
5688         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5689           return nullptr;
5690         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5691           return nullptr;
5692         Opcode = X86::MOV32rm;
5693         NarrowToMOV32rm = true;
5694       }
5695       // For stores, make sure the size of the object is equal to the size of
5696       // the store. If the object is larger, the extra bits would be garbage. If
5697       // the object is smaller we might overwrite another object or fault.
5698       if (FoldedStore && Size != RCSize)
5699         return nullptr;
5700     }
5701 
5702     if (isTwoAddrFold)
5703       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5704     else
5705       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5706 
5707     if (NarrowToMOV32rm) {
5708       // If this is the special case where we use a MOV32rm to load a 32-bit
5709       // value and zero-extend the top bits. Change the destination register
5710       // to a 32-bit one.
5711       Register DstReg = NewMI->getOperand(0).getReg();
5712       if (DstReg.isPhysical())
5713         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5714       else
5715         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5716     }
5717     return NewMI;
5718   }
5719 
5720   // If the instruction and target operand are commutable, commute the
5721   // instruction and try again.
5722   if (AllowCommute) {
5723     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5724     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5725       bool HasDef = MI.getDesc().getNumDefs();
5726       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5727       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5728       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5729       bool Tied1 =
5730           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5731       bool Tied2 =
5732           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5733 
5734       // If either of the commutable operands are tied to the destination
5735       // then we can not commute + fold.
5736       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5737           (HasDef && Reg0 == Reg2 && Tied2))
5738         return nullptr;
5739 
5740       MachineInstr *CommutedMI =
5741           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5742       if (!CommutedMI) {
5743         // Unable to commute.
5744         return nullptr;
5745       }
5746       if (CommutedMI != &MI) {
5747         // New instruction. We can't fold from this.
5748         CommutedMI->eraseFromParent();
5749         return nullptr;
5750       }
5751 
5752       // Attempt to fold with the commuted version of the instruction.
5753       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5754                                     Alignment, /*AllowCommute=*/false);
5755       if (NewMI)
5756         return NewMI;
5757 
5758       // Folding failed again - undo the commute before returning.
5759       MachineInstr *UncommutedMI =
5760           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5761       if (!UncommutedMI) {
5762         // Unable to commute.
5763         return nullptr;
5764       }
5765       if (UncommutedMI != &MI) {
5766         // New instruction. It doesn't need to be kept.
5767         UncommutedMI->eraseFromParent();
5768         return nullptr;
5769       }
5770 
5771       // Return here to prevent duplicate fuse failure report.
5772       return nullptr;
5773     }
5774   }
5775 
5776   // No fusion
5777   if (PrintFailedFusing && !MI.isCopy())
5778     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5779   return nullptr;
5780 }
5781 
5782 MachineInstr *
5783 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5784                                     ArrayRef<unsigned> Ops,
5785                                     MachineBasicBlock::iterator InsertPt,
5786                                     int FrameIndex, LiveIntervals *LIS,
5787                                     VirtRegMap *VRM) const {
5788   // Check switch flag
5789   if (NoFusing)
5790     return nullptr;
5791 
5792   // Avoid partial and undef register update stalls unless optimizing for size.
5793   if (!MF.getFunction().hasOptSize() &&
5794       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5795        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5796     return nullptr;
5797 
5798   // Don't fold subreg spills, or reloads that use a high subreg.
5799   for (auto Op : Ops) {
5800     MachineOperand &MO = MI.getOperand(Op);
5801     auto SubReg = MO.getSubReg();
5802     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5803       return nullptr;
5804   }
5805 
5806   const MachineFrameInfo &MFI = MF.getFrameInfo();
5807   unsigned Size = MFI.getObjectSize(FrameIndex);
5808   Align Alignment = MFI.getObjectAlign(FrameIndex);
5809   // If the function stack isn't realigned we don't want to fold instructions
5810   // that need increased alignment.
5811   if (!RI.hasStackRealignment(MF))
5812     Alignment =
5813         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5814   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5815     unsigned NewOpc = 0;
5816     unsigned RCSize = 0;
5817     switch (MI.getOpcode()) {
5818     default: return nullptr;
5819     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5820     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5821     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5822     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5823     }
5824     // Check if it's safe to fold the load. If the size of the object is
5825     // narrower than the load width, then it's not.
5826     if (Size < RCSize)
5827       return nullptr;
5828     // Change to CMPXXri r, 0 first.
5829     MI.setDesc(get(NewOpc));
5830     MI.getOperand(1).ChangeToImmediate(0);
5831   } else if (Ops.size() != 1)
5832     return nullptr;
5833 
5834   return foldMemoryOperandImpl(MF, MI, Ops[0],
5835                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5836                                Size, Alignment, /*AllowCommute=*/true);
5837 }
5838 
5839 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5840 /// because the latter uses contents that wouldn't be defined in the folded
5841 /// version.  For instance, this transformation isn't legal:
5842 ///   movss (%rdi), %xmm0
5843 ///   addps %xmm0, %xmm0
5844 /// ->
5845 ///   addps (%rdi), %xmm0
5846 ///
5847 /// But this one is:
5848 ///   movss (%rdi), %xmm0
5849 ///   addss %xmm0, %xmm0
5850 /// ->
5851 ///   addss (%rdi), %xmm0
5852 ///
5853 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5854                                              const MachineInstr &UserMI,
5855                                              const MachineFunction &MF) {
5856   unsigned Opc = LoadMI.getOpcode();
5857   unsigned UserOpc = UserMI.getOpcode();
5858   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5859   const TargetRegisterClass *RC =
5860       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5861   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5862 
5863   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5864        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5865        Opc == X86::VMOVSSZrm_alt) &&
5866       RegSize > 32) {
5867     // These instructions only load 32 bits, we can't fold them if the
5868     // destination register is wider than 32 bits (4 bytes), and its user
5869     // instruction isn't scalar (SS).
5870     switch (UserOpc) {
5871     case X86::CVTSS2SDrr_Int:
5872     case X86::VCVTSS2SDrr_Int:
5873     case X86::VCVTSS2SDZrr_Int:
5874     case X86::VCVTSS2SDZrr_Intk:
5875     case X86::VCVTSS2SDZrr_Intkz:
5876     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5877     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5878     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5879     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5880     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5881     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5882     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5883     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5884     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5885     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5886     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5887     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5888     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5889     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5890     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5891     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5892     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5893     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5894     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5895     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5896     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5897     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5898     case X86::VCMPSSZrr_Intk:
5899     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5900     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5901     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5902     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5903     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5904     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5905     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5906     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5907     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5908     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5909     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5910     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5911     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5912     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5913     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5914     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5915     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5916     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5917     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5918     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5919     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5920     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5921     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5922     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5923     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5924     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5925     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5926     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5927     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5928     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5929     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5930     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5931     case X86::VFIXUPIMMSSZrri:
5932     case X86::VFIXUPIMMSSZrrik:
5933     case X86::VFIXUPIMMSSZrrikz:
5934     case X86::VFPCLASSSSZrr:
5935     case X86::VFPCLASSSSZrrk:
5936     case X86::VGETEXPSSZr:
5937     case X86::VGETEXPSSZrk:
5938     case X86::VGETEXPSSZrkz:
5939     case X86::VGETMANTSSZrri:
5940     case X86::VGETMANTSSZrrik:
5941     case X86::VGETMANTSSZrrikz:
5942     case X86::VRANGESSZrri:
5943     case X86::VRANGESSZrrik:
5944     case X86::VRANGESSZrrikz:
5945     case X86::VRCP14SSZrr:
5946     case X86::VRCP14SSZrrk:
5947     case X86::VRCP14SSZrrkz:
5948     case X86::VRCP28SSZr:
5949     case X86::VRCP28SSZrk:
5950     case X86::VRCP28SSZrkz:
5951     case X86::VREDUCESSZrri:
5952     case X86::VREDUCESSZrrik:
5953     case X86::VREDUCESSZrrikz:
5954     case X86::VRNDSCALESSZr_Int:
5955     case X86::VRNDSCALESSZr_Intk:
5956     case X86::VRNDSCALESSZr_Intkz:
5957     case X86::VRSQRT14SSZrr:
5958     case X86::VRSQRT14SSZrrk:
5959     case X86::VRSQRT14SSZrrkz:
5960     case X86::VRSQRT28SSZr:
5961     case X86::VRSQRT28SSZrk:
5962     case X86::VRSQRT28SSZrkz:
5963     case X86::VSCALEFSSZrr:
5964     case X86::VSCALEFSSZrrk:
5965     case X86::VSCALEFSSZrrkz:
5966       return false;
5967     default:
5968       return true;
5969     }
5970   }
5971 
5972   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5973        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5974        Opc == X86::VMOVSDZrm_alt) &&
5975       RegSize > 64) {
5976     // These instructions only load 64 bits, we can't fold them if the
5977     // destination register is wider than 64 bits (8 bytes), and its user
5978     // instruction isn't scalar (SD).
5979     switch (UserOpc) {
5980     case X86::CVTSD2SSrr_Int:
5981     case X86::VCVTSD2SSrr_Int:
5982     case X86::VCVTSD2SSZrr_Int:
5983     case X86::VCVTSD2SSZrr_Intk:
5984     case X86::VCVTSD2SSZrr_Intkz:
5985     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
5986     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
5987     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
5988     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
5989     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
5990     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
5991     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
5992     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
5993     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
5994     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
5995     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
5996     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5997     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5998     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5999     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6000     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6001     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6002     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
6003     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6004     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
6005     case X86::VCMPSDZrr_Intk:
6006     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
6007     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
6008     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
6009     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
6010     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
6011     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
6012     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
6013     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
6014     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6015     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6016     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6017     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6018     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6019     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6020     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6021     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6022     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6023     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6024     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6025     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6026     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
6027     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
6028     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
6029     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
6030     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
6031     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
6032     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
6033     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
6034     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
6035     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
6036     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
6037     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
6038     case X86::VFIXUPIMMSDZrri:
6039     case X86::VFIXUPIMMSDZrrik:
6040     case X86::VFIXUPIMMSDZrrikz:
6041     case X86::VFPCLASSSDZrr:
6042     case X86::VFPCLASSSDZrrk:
6043     case X86::VGETEXPSDZr:
6044     case X86::VGETEXPSDZrk:
6045     case X86::VGETEXPSDZrkz:
6046     case X86::VGETMANTSDZrri:
6047     case X86::VGETMANTSDZrrik:
6048     case X86::VGETMANTSDZrrikz:
6049     case X86::VRANGESDZrri:
6050     case X86::VRANGESDZrrik:
6051     case X86::VRANGESDZrrikz:
6052     case X86::VRCP14SDZrr:
6053     case X86::VRCP14SDZrrk:
6054     case X86::VRCP14SDZrrkz:
6055     case X86::VRCP28SDZr:
6056     case X86::VRCP28SDZrk:
6057     case X86::VRCP28SDZrkz:
6058     case X86::VREDUCESDZrri:
6059     case X86::VREDUCESDZrrik:
6060     case X86::VREDUCESDZrrikz:
6061     case X86::VRNDSCALESDZr_Int:
6062     case X86::VRNDSCALESDZr_Intk:
6063     case X86::VRNDSCALESDZr_Intkz:
6064     case X86::VRSQRT14SDZrr:
6065     case X86::VRSQRT14SDZrrk:
6066     case X86::VRSQRT14SDZrrkz:
6067     case X86::VRSQRT28SDZr:
6068     case X86::VRSQRT28SDZrk:
6069     case X86::VRSQRT28SDZrkz:
6070     case X86::VSCALEFSDZrr:
6071     case X86::VSCALEFSDZrrk:
6072     case X86::VSCALEFSDZrrkz:
6073       return false;
6074     default:
6075       return true;
6076     }
6077   }
6078 
6079   if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
6080     // These instructions only load 16 bits, we can't fold them if the
6081     // destination register is wider than 16 bits (2 bytes), and its user
6082     // instruction isn't scalar (SH).
6083     switch (UserOpc) {
6084     case X86::VADDSHZrr_Int:
6085     case X86::VCMPSHZrr_Int:
6086     case X86::VDIVSHZrr_Int:
6087     case X86::VMAXSHZrr_Int:
6088     case X86::VMINSHZrr_Int:
6089     case X86::VMULSHZrr_Int:
6090     case X86::VSUBSHZrr_Int:
6091     case X86::VADDSHZrr_Intk: case X86::VADDSHZrr_Intkz:
6092     case X86::VCMPSHZrr_Intk:
6093     case X86::VDIVSHZrr_Intk: case X86::VDIVSHZrr_Intkz:
6094     case X86::VMAXSHZrr_Intk: case X86::VMAXSHZrr_Intkz:
6095     case X86::VMINSHZrr_Intk: case X86::VMINSHZrr_Intkz:
6096     case X86::VMULSHZrr_Intk: case X86::VMULSHZrr_Intkz:
6097     case X86::VSUBSHZrr_Intk: case X86::VSUBSHZrr_Intkz:
6098     case X86::VFMADD132SHZr_Int: case X86::VFNMADD132SHZr_Int:
6099     case X86::VFMADD213SHZr_Int: case X86::VFNMADD213SHZr_Int:
6100     case X86::VFMADD231SHZr_Int: case X86::VFNMADD231SHZr_Int:
6101     case X86::VFMSUB132SHZr_Int: case X86::VFNMSUB132SHZr_Int:
6102     case X86::VFMSUB213SHZr_Int: case X86::VFNMSUB213SHZr_Int:
6103     case X86::VFMSUB231SHZr_Int: case X86::VFNMSUB231SHZr_Int:
6104     case X86::VFMADD132SHZr_Intk: case X86::VFNMADD132SHZr_Intk:
6105     case X86::VFMADD213SHZr_Intk: case X86::VFNMADD213SHZr_Intk:
6106     case X86::VFMADD231SHZr_Intk: case X86::VFNMADD231SHZr_Intk:
6107     case X86::VFMSUB132SHZr_Intk: case X86::VFNMSUB132SHZr_Intk:
6108     case X86::VFMSUB213SHZr_Intk: case X86::VFNMSUB213SHZr_Intk:
6109     case X86::VFMSUB231SHZr_Intk: case X86::VFNMSUB231SHZr_Intk:
6110     case X86::VFMADD132SHZr_Intkz: case X86::VFNMADD132SHZr_Intkz:
6111     case X86::VFMADD213SHZr_Intkz: case X86::VFNMADD213SHZr_Intkz:
6112     case X86::VFMADD231SHZr_Intkz: case X86::VFNMADD231SHZr_Intkz:
6113     case X86::VFMSUB132SHZr_Intkz: case X86::VFNMSUB132SHZr_Intkz:
6114     case X86::VFMSUB213SHZr_Intkz: case X86::VFNMSUB213SHZr_Intkz:
6115     case X86::VFMSUB231SHZr_Intkz: case X86::VFNMSUB231SHZr_Intkz:
6116       return false;
6117     default:
6118       return true;
6119     }
6120   }
6121 
6122   return false;
6123 }
6124 
6125 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6126     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6127     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6128     LiveIntervals *LIS) const {
6129 
6130   // TODO: Support the case where LoadMI loads a wide register, but MI
6131   // only uses a subreg.
6132   for (auto Op : Ops) {
6133     if (MI.getOperand(Op).getSubReg())
6134       return nullptr;
6135   }
6136 
6137   // If loading from a FrameIndex, fold directly from the FrameIndex.
6138   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6139   int FrameIndex;
6140   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6141     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6142       return nullptr;
6143     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6144   }
6145 
6146   // Check switch flag
6147   if (NoFusing) return nullptr;
6148 
6149   // Avoid partial and undef register update stalls unless optimizing for size.
6150   if (!MF.getFunction().hasOptSize() &&
6151       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6152        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6153     return nullptr;
6154 
6155   // Determine the alignment of the load.
6156   Align Alignment;
6157   if (LoadMI.hasOneMemOperand())
6158     Alignment = (*LoadMI.memoperands_begin())->getAlign();
6159   else
6160     switch (LoadMI.getOpcode()) {
6161     case X86::AVX512_512_SET0:
6162     case X86::AVX512_512_SETALLONES:
6163       Alignment = Align(64);
6164       break;
6165     case X86::AVX2_SETALLONES:
6166     case X86::AVX1_SETALLONES:
6167     case X86::AVX_SET0:
6168     case X86::AVX512_256_SET0:
6169       Alignment = Align(32);
6170       break;
6171     case X86::V_SET0:
6172     case X86::V_SETALLONES:
6173     case X86::AVX512_128_SET0:
6174     case X86::FsFLD0F128:
6175     case X86::AVX512_FsFLD0F128:
6176       Alignment = Align(16);
6177       break;
6178     case X86::MMX_SET0:
6179     case X86::FsFLD0SD:
6180     case X86::AVX512_FsFLD0SD:
6181       Alignment = Align(8);
6182       break;
6183     case X86::FsFLD0SS:
6184     case X86::AVX512_FsFLD0SS:
6185       Alignment = Align(4);
6186       break;
6187     case X86::AVX512_FsFLD0SH:
6188       Alignment = Align(2);
6189       break;
6190     default:
6191       return nullptr;
6192     }
6193   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6194     unsigned NewOpc = 0;
6195     switch (MI.getOpcode()) {
6196     default: return nullptr;
6197     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6198     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6199     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6200     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6201     }
6202     // Change to CMPXXri r, 0 first.
6203     MI.setDesc(get(NewOpc));
6204     MI.getOperand(1).ChangeToImmediate(0);
6205   } else if (Ops.size() != 1)
6206     return nullptr;
6207 
6208   // Make sure the subregisters match.
6209   // Otherwise we risk changing the size of the load.
6210   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6211     return nullptr;
6212 
6213   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6214   switch (LoadMI.getOpcode()) {
6215   case X86::MMX_SET0:
6216   case X86::V_SET0:
6217   case X86::V_SETALLONES:
6218   case X86::AVX2_SETALLONES:
6219   case X86::AVX1_SETALLONES:
6220   case X86::AVX_SET0:
6221   case X86::AVX512_128_SET0:
6222   case X86::AVX512_256_SET0:
6223   case X86::AVX512_512_SET0:
6224   case X86::AVX512_512_SETALLONES:
6225   case X86::AVX512_FsFLD0SH:
6226   case X86::FsFLD0SD:
6227   case X86::AVX512_FsFLD0SD:
6228   case X86::FsFLD0SS:
6229   case X86::AVX512_FsFLD0SS:
6230   case X86::FsFLD0F128:
6231   case X86::AVX512_FsFLD0F128: {
6232     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6233     // Create a constant-pool entry and operands to load from it.
6234 
6235     // Medium and large mode can't fold loads this way.
6236     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6237         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6238       return nullptr;
6239 
6240     // x86-32 PIC requires a PIC base register for constant pools.
6241     unsigned PICBase = 0;
6242     // Since we're using Small or Kernel code model, we can always use
6243     // RIP-relative addressing for a smaller encoding.
6244     if (Subtarget.is64Bit()) {
6245       PICBase = X86::RIP;
6246     } else if (MF.getTarget().isPositionIndependent()) {
6247       // FIXME: PICBase = getGlobalBaseReg(&MF);
6248       // This doesn't work for several reasons.
6249       // 1. GlobalBaseReg may have been spilled.
6250       // 2. It may not be live at MI.
6251       return nullptr;
6252     }
6253 
6254     // Create a constant-pool entry.
6255     MachineConstantPool &MCP = *MF.getConstantPool();
6256     Type *Ty;
6257     unsigned Opc = LoadMI.getOpcode();
6258     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6259       Ty = Type::getFloatTy(MF.getFunction().getContext());
6260     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6261       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6262     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6263       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6264     else if (Opc == X86::AVX512_FsFLD0SH)
6265       Ty = Type::getHalfTy(MF.getFunction().getContext());
6266     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6267       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6268                                 16);
6269     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6270              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6271       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6272                                 8);
6273     else if (Opc == X86::MMX_SET0)
6274       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6275                                 2);
6276     else
6277       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6278                                 4);
6279 
6280     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6281                       Opc == X86::AVX512_512_SETALLONES ||
6282                       Opc == X86::AVX1_SETALLONES);
6283     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6284                                     Constant::getNullValue(Ty);
6285     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6286 
6287     // Create operands to load from the constant pool entry.
6288     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6289     MOs.push_back(MachineOperand::CreateImm(1));
6290     MOs.push_back(MachineOperand::CreateReg(0, false));
6291     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6292     MOs.push_back(MachineOperand::CreateReg(0, false));
6293     break;
6294   }
6295   default: {
6296     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6297       return nullptr;
6298 
6299     // Folding a normal load. Just copy the load's address operands.
6300     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6301                LoadMI.operands_begin() + NumOps);
6302     break;
6303   }
6304   }
6305   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6306                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6307 }
6308 
6309 static SmallVector<MachineMemOperand *, 2>
6310 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6311   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6312 
6313   for (MachineMemOperand *MMO : MMOs) {
6314     if (!MMO->isLoad())
6315       continue;
6316 
6317     if (!MMO->isStore()) {
6318       // Reuse the MMO.
6319       LoadMMOs.push_back(MMO);
6320     } else {
6321       // Clone the MMO and unset the store flag.
6322       LoadMMOs.push_back(MF.getMachineMemOperand(
6323           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6324     }
6325   }
6326 
6327   return LoadMMOs;
6328 }
6329 
6330 static SmallVector<MachineMemOperand *, 2>
6331 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6332   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6333 
6334   for (MachineMemOperand *MMO : MMOs) {
6335     if (!MMO->isStore())
6336       continue;
6337 
6338     if (!MMO->isLoad()) {
6339       // Reuse the MMO.
6340       StoreMMOs.push_back(MMO);
6341     } else {
6342       // Clone the MMO and unset the load flag.
6343       StoreMMOs.push_back(MF.getMachineMemOperand(
6344           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6345     }
6346   }
6347 
6348   return StoreMMOs;
6349 }
6350 
6351 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6352                                    const TargetRegisterClass *RC,
6353                                    const X86Subtarget &STI) {
6354   assert(STI.hasAVX512() && "Expected at least AVX512!");
6355   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6356   assert((SpillSize == 64 || STI.hasVLX()) &&
6357          "Can't broadcast less than 64 bytes without AVX512VL!");
6358 
6359   switch (I->Flags & TB_BCAST_MASK) {
6360   default: llvm_unreachable("Unexpected broadcast type!");
6361   case TB_BCAST_D:
6362     switch (SpillSize) {
6363     default: llvm_unreachable("Unknown spill size");
6364     case 16: return X86::VPBROADCASTDZ128rm;
6365     case 32: return X86::VPBROADCASTDZ256rm;
6366     case 64: return X86::VPBROADCASTDZrm;
6367     }
6368     break;
6369   case TB_BCAST_Q:
6370     switch (SpillSize) {
6371     default: llvm_unreachable("Unknown spill size");
6372     case 16: return X86::VPBROADCASTQZ128rm;
6373     case 32: return X86::VPBROADCASTQZ256rm;
6374     case 64: return X86::VPBROADCASTQZrm;
6375     }
6376     break;
6377   case TB_BCAST_SS:
6378     switch (SpillSize) {
6379     default: llvm_unreachable("Unknown spill size");
6380     case 16: return X86::VBROADCASTSSZ128rm;
6381     case 32: return X86::VBROADCASTSSZ256rm;
6382     case 64: return X86::VBROADCASTSSZrm;
6383     }
6384     break;
6385   case TB_BCAST_SD:
6386     switch (SpillSize) {
6387     default: llvm_unreachable("Unknown spill size");
6388     case 16: return X86::VMOVDDUPZ128rm;
6389     case 32: return X86::VBROADCASTSDZ256rm;
6390     case 64: return X86::VBROADCASTSDZrm;
6391     }
6392     break;
6393   }
6394 }
6395 
6396 bool X86InstrInfo::unfoldMemoryOperand(
6397     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6398     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6399   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6400   if (I == nullptr)
6401     return false;
6402   unsigned Opc = I->DstOp;
6403   unsigned Index = I->Flags & TB_INDEX_MASK;
6404   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6405   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6406   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6407   if (UnfoldLoad && !FoldedLoad)
6408     return false;
6409   UnfoldLoad &= FoldedLoad;
6410   if (UnfoldStore && !FoldedStore)
6411     return false;
6412   UnfoldStore &= FoldedStore;
6413 
6414   const MCInstrDesc &MCID = get(Opc);
6415 
6416   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6417   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6418   // TODO: Check if 32-byte or greater accesses are slow too?
6419   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6420       Subtarget.isUnalignedMem16Slow())
6421     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6422     // conservatively assume the address is unaligned. That's bad for
6423     // performance.
6424     return false;
6425   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6426   SmallVector<MachineOperand,2> BeforeOps;
6427   SmallVector<MachineOperand,2> AfterOps;
6428   SmallVector<MachineOperand,4> ImpOps;
6429   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6430     MachineOperand &Op = MI.getOperand(i);
6431     if (i >= Index && i < Index + X86::AddrNumOperands)
6432       AddrOps.push_back(Op);
6433     else if (Op.isReg() && Op.isImplicit())
6434       ImpOps.push_back(Op);
6435     else if (i < Index)
6436       BeforeOps.push_back(Op);
6437     else if (i > Index)
6438       AfterOps.push_back(Op);
6439   }
6440 
6441   // Emit the load or broadcast instruction.
6442   if (UnfoldLoad) {
6443     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6444 
6445     unsigned Opc;
6446     if (FoldedBCast) {
6447       Opc = getBroadcastOpcode(I, RC, Subtarget);
6448     } else {
6449       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6450       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6451       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6452     }
6453 
6454     DebugLoc DL;
6455     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6456     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6457       MIB.add(AddrOps[i]);
6458     MIB.setMemRefs(MMOs);
6459     NewMIs.push_back(MIB);
6460 
6461     if (UnfoldStore) {
6462       // Address operands cannot be marked isKill.
6463       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6464         MachineOperand &MO = NewMIs[0]->getOperand(i);
6465         if (MO.isReg())
6466           MO.setIsKill(false);
6467       }
6468     }
6469   }
6470 
6471   // Emit the data processing instruction.
6472   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6473   MachineInstrBuilder MIB(MF, DataMI);
6474 
6475   if (FoldedStore)
6476     MIB.addReg(Reg, RegState::Define);
6477   for (MachineOperand &BeforeOp : BeforeOps)
6478     MIB.add(BeforeOp);
6479   if (FoldedLoad)
6480     MIB.addReg(Reg);
6481   for (MachineOperand &AfterOp : AfterOps)
6482     MIB.add(AfterOp);
6483   for (MachineOperand &ImpOp : ImpOps) {
6484     MIB.addReg(ImpOp.getReg(),
6485                getDefRegState(ImpOp.isDef()) |
6486                RegState::Implicit |
6487                getKillRegState(ImpOp.isKill()) |
6488                getDeadRegState(ImpOp.isDead()) |
6489                getUndefRegState(ImpOp.isUndef()));
6490   }
6491   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6492   switch (DataMI->getOpcode()) {
6493   default: break;
6494   case X86::CMP64ri32:
6495   case X86::CMP64ri8:
6496   case X86::CMP32ri:
6497   case X86::CMP32ri8:
6498   case X86::CMP16ri:
6499   case X86::CMP16ri8:
6500   case X86::CMP8ri: {
6501     MachineOperand &MO0 = DataMI->getOperand(0);
6502     MachineOperand &MO1 = DataMI->getOperand(1);
6503     if (MO1.isImm() && MO1.getImm() == 0) {
6504       unsigned NewOpc;
6505       switch (DataMI->getOpcode()) {
6506       default: llvm_unreachable("Unreachable!");
6507       case X86::CMP64ri8:
6508       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6509       case X86::CMP32ri8:
6510       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6511       case X86::CMP16ri8:
6512       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6513       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6514       }
6515       DataMI->setDesc(get(NewOpc));
6516       MO1.ChangeToRegister(MO0.getReg(), false);
6517     }
6518   }
6519   }
6520   NewMIs.push_back(DataMI);
6521 
6522   // Emit the store instruction.
6523   if (UnfoldStore) {
6524     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6525     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6526     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6527     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6528     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6529     DebugLoc DL;
6530     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6531     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6532       MIB.add(AddrOps[i]);
6533     MIB.addReg(Reg, RegState::Kill);
6534     MIB.setMemRefs(MMOs);
6535     NewMIs.push_back(MIB);
6536   }
6537 
6538   return true;
6539 }
6540 
6541 bool
6542 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6543                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6544   if (!N->isMachineOpcode())
6545     return false;
6546 
6547   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6548   if (I == nullptr)
6549     return false;
6550   unsigned Opc = I->DstOp;
6551   unsigned Index = I->Flags & TB_INDEX_MASK;
6552   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6553   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6554   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6555   const MCInstrDesc &MCID = get(Opc);
6556   MachineFunction &MF = DAG.getMachineFunction();
6557   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6558   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6559   unsigned NumDefs = MCID.NumDefs;
6560   std::vector<SDValue> AddrOps;
6561   std::vector<SDValue> BeforeOps;
6562   std::vector<SDValue> AfterOps;
6563   SDLoc dl(N);
6564   unsigned NumOps = N->getNumOperands();
6565   for (unsigned i = 0; i != NumOps-1; ++i) {
6566     SDValue Op = N->getOperand(i);
6567     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6568       AddrOps.push_back(Op);
6569     else if (i < Index-NumDefs)
6570       BeforeOps.push_back(Op);
6571     else if (i > Index-NumDefs)
6572       AfterOps.push_back(Op);
6573   }
6574   SDValue Chain = N->getOperand(NumOps-1);
6575   AddrOps.push_back(Chain);
6576 
6577   // Emit the load instruction.
6578   SDNode *Load = nullptr;
6579   if (FoldedLoad) {
6580     EVT VT = *TRI.legalclasstypes_begin(*RC);
6581     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6582     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6583         Subtarget.isUnalignedMem16Slow())
6584       // Do not introduce a slow unaligned load.
6585       return false;
6586     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6587     // memory access is slow above.
6588 
6589     unsigned Opc;
6590     if (FoldedBCast) {
6591       Opc = getBroadcastOpcode(I, RC, Subtarget);
6592     } else {
6593       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6594       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6595       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6596     }
6597 
6598     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6599     NewNodes.push_back(Load);
6600 
6601     // Preserve memory reference information.
6602     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6603   }
6604 
6605   // Emit the data processing instruction.
6606   std::vector<EVT> VTs;
6607   const TargetRegisterClass *DstRC = nullptr;
6608   if (MCID.getNumDefs() > 0) {
6609     DstRC = getRegClass(MCID, 0, &RI, MF);
6610     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6611   }
6612   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6613     EVT VT = N->getValueType(i);
6614     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6615       VTs.push_back(VT);
6616   }
6617   if (Load)
6618     BeforeOps.push_back(SDValue(Load, 0));
6619   llvm::append_range(BeforeOps, AfterOps);
6620   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6621   switch (Opc) {
6622     default: break;
6623     case X86::CMP64ri32:
6624     case X86::CMP64ri8:
6625     case X86::CMP32ri:
6626     case X86::CMP32ri8:
6627     case X86::CMP16ri:
6628     case X86::CMP16ri8:
6629     case X86::CMP8ri:
6630       if (isNullConstant(BeforeOps[1])) {
6631         switch (Opc) {
6632           default: llvm_unreachable("Unreachable!");
6633           case X86::CMP64ri8:
6634           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6635           case X86::CMP32ri8:
6636           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6637           case X86::CMP16ri8:
6638           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6639           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6640         }
6641         BeforeOps[1] = BeforeOps[0];
6642       }
6643   }
6644   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6645   NewNodes.push_back(NewNode);
6646 
6647   // Emit the store instruction.
6648   if (FoldedStore) {
6649     AddrOps.pop_back();
6650     AddrOps.push_back(SDValue(NewNode, 0));
6651     AddrOps.push_back(Chain);
6652     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6653     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6654         Subtarget.isUnalignedMem16Slow())
6655       // Do not introduce a slow unaligned store.
6656       return false;
6657     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6658     // memory access is slow above.
6659     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6660     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6661     SDNode *Store =
6662         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6663                            dl, MVT::Other, AddrOps);
6664     NewNodes.push_back(Store);
6665 
6666     // Preserve memory reference information.
6667     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6668   }
6669 
6670   return true;
6671 }
6672 
6673 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6674                                       bool UnfoldLoad, bool UnfoldStore,
6675                                       unsigned *LoadRegIndex) const {
6676   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6677   if (I == nullptr)
6678     return 0;
6679   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6680   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6681   if (UnfoldLoad && !FoldedLoad)
6682     return 0;
6683   if (UnfoldStore && !FoldedStore)
6684     return 0;
6685   if (LoadRegIndex)
6686     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6687   return I->DstOp;
6688 }
6689 
6690 bool
6691 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6692                                      int64_t &Offset1, int64_t &Offset2) const {
6693   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6694     return false;
6695   unsigned Opc1 = Load1->getMachineOpcode();
6696   unsigned Opc2 = Load2->getMachineOpcode();
6697   switch (Opc1) {
6698   default: return false;
6699   case X86::MOV8rm:
6700   case X86::MOV16rm:
6701   case X86::MOV32rm:
6702   case X86::MOV64rm:
6703   case X86::LD_Fp32m:
6704   case X86::LD_Fp64m:
6705   case X86::LD_Fp80m:
6706   case X86::MOVSSrm:
6707   case X86::MOVSSrm_alt:
6708   case X86::MOVSDrm:
6709   case X86::MOVSDrm_alt:
6710   case X86::MMX_MOVD64rm:
6711   case X86::MMX_MOVQ64rm:
6712   case X86::MOVAPSrm:
6713   case X86::MOVUPSrm:
6714   case X86::MOVAPDrm:
6715   case X86::MOVUPDrm:
6716   case X86::MOVDQArm:
6717   case X86::MOVDQUrm:
6718   // AVX load instructions
6719   case X86::VMOVSSrm:
6720   case X86::VMOVSSrm_alt:
6721   case X86::VMOVSDrm:
6722   case X86::VMOVSDrm_alt:
6723   case X86::VMOVAPSrm:
6724   case X86::VMOVUPSrm:
6725   case X86::VMOVAPDrm:
6726   case X86::VMOVUPDrm:
6727   case X86::VMOVDQArm:
6728   case X86::VMOVDQUrm:
6729   case X86::VMOVAPSYrm:
6730   case X86::VMOVUPSYrm:
6731   case X86::VMOVAPDYrm:
6732   case X86::VMOVUPDYrm:
6733   case X86::VMOVDQAYrm:
6734   case X86::VMOVDQUYrm:
6735   // AVX512 load instructions
6736   case X86::VMOVSSZrm:
6737   case X86::VMOVSSZrm_alt:
6738   case X86::VMOVSDZrm:
6739   case X86::VMOVSDZrm_alt:
6740   case X86::VMOVAPSZ128rm:
6741   case X86::VMOVUPSZ128rm:
6742   case X86::VMOVAPSZ128rm_NOVLX:
6743   case X86::VMOVUPSZ128rm_NOVLX:
6744   case X86::VMOVAPDZ128rm:
6745   case X86::VMOVUPDZ128rm:
6746   case X86::VMOVDQU8Z128rm:
6747   case X86::VMOVDQU16Z128rm:
6748   case X86::VMOVDQA32Z128rm:
6749   case X86::VMOVDQU32Z128rm:
6750   case X86::VMOVDQA64Z128rm:
6751   case X86::VMOVDQU64Z128rm:
6752   case X86::VMOVAPSZ256rm:
6753   case X86::VMOVUPSZ256rm:
6754   case X86::VMOVAPSZ256rm_NOVLX:
6755   case X86::VMOVUPSZ256rm_NOVLX:
6756   case X86::VMOVAPDZ256rm:
6757   case X86::VMOVUPDZ256rm:
6758   case X86::VMOVDQU8Z256rm:
6759   case X86::VMOVDQU16Z256rm:
6760   case X86::VMOVDQA32Z256rm:
6761   case X86::VMOVDQU32Z256rm:
6762   case X86::VMOVDQA64Z256rm:
6763   case X86::VMOVDQU64Z256rm:
6764   case X86::VMOVAPSZrm:
6765   case X86::VMOVUPSZrm:
6766   case X86::VMOVAPDZrm:
6767   case X86::VMOVUPDZrm:
6768   case X86::VMOVDQU8Zrm:
6769   case X86::VMOVDQU16Zrm:
6770   case X86::VMOVDQA32Zrm:
6771   case X86::VMOVDQU32Zrm:
6772   case X86::VMOVDQA64Zrm:
6773   case X86::VMOVDQU64Zrm:
6774   case X86::KMOVBkm:
6775   case X86::KMOVWkm:
6776   case X86::KMOVDkm:
6777   case X86::KMOVQkm:
6778     break;
6779   }
6780   switch (Opc2) {
6781   default: return false;
6782   case X86::MOV8rm:
6783   case X86::MOV16rm:
6784   case X86::MOV32rm:
6785   case X86::MOV64rm:
6786   case X86::LD_Fp32m:
6787   case X86::LD_Fp64m:
6788   case X86::LD_Fp80m:
6789   case X86::MOVSSrm:
6790   case X86::MOVSSrm_alt:
6791   case X86::MOVSDrm:
6792   case X86::MOVSDrm_alt:
6793   case X86::MMX_MOVD64rm:
6794   case X86::MMX_MOVQ64rm:
6795   case X86::MOVAPSrm:
6796   case X86::MOVUPSrm:
6797   case X86::MOVAPDrm:
6798   case X86::MOVUPDrm:
6799   case X86::MOVDQArm:
6800   case X86::MOVDQUrm:
6801   // AVX load instructions
6802   case X86::VMOVSSrm:
6803   case X86::VMOVSSrm_alt:
6804   case X86::VMOVSDrm:
6805   case X86::VMOVSDrm_alt:
6806   case X86::VMOVAPSrm:
6807   case X86::VMOVUPSrm:
6808   case X86::VMOVAPDrm:
6809   case X86::VMOVUPDrm:
6810   case X86::VMOVDQArm:
6811   case X86::VMOVDQUrm:
6812   case X86::VMOVAPSYrm:
6813   case X86::VMOVUPSYrm:
6814   case X86::VMOVAPDYrm:
6815   case X86::VMOVUPDYrm:
6816   case X86::VMOVDQAYrm:
6817   case X86::VMOVDQUYrm:
6818   // AVX512 load instructions
6819   case X86::VMOVSSZrm:
6820   case X86::VMOVSSZrm_alt:
6821   case X86::VMOVSDZrm:
6822   case X86::VMOVSDZrm_alt:
6823   case X86::VMOVAPSZ128rm:
6824   case X86::VMOVUPSZ128rm:
6825   case X86::VMOVAPSZ128rm_NOVLX:
6826   case X86::VMOVUPSZ128rm_NOVLX:
6827   case X86::VMOVAPDZ128rm:
6828   case X86::VMOVUPDZ128rm:
6829   case X86::VMOVDQU8Z128rm:
6830   case X86::VMOVDQU16Z128rm:
6831   case X86::VMOVDQA32Z128rm:
6832   case X86::VMOVDQU32Z128rm:
6833   case X86::VMOVDQA64Z128rm:
6834   case X86::VMOVDQU64Z128rm:
6835   case X86::VMOVAPSZ256rm:
6836   case X86::VMOVUPSZ256rm:
6837   case X86::VMOVAPSZ256rm_NOVLX:
6838   case X86::VMOVUPSZ256rm_NOVLX:
6839   case X86::VMOVAPDZ256rm:
6840   case X86::VMOVUPDZ256rm:
6841   case X86::VMOVDQU8Z256rm:
6842   case X86::VMOVDQU16Z256rm:
6843   case X86::VMOVDQA32Z256rm:
6844   case X86::VMOVDQU32Z256rm:
6845   case X86::VMOVDQA64Z256rm:
6846   case X86::VMOVDQU64Z256rm:
6847   case X86::VMOVAPSZrm:
6848   case X86::VMOVUPSZrm:
6849   case X86::VMOVAPDZrm:
6850   case X86::VMOVUPDZrm:
6851   case X86::VMOVDQU8Zrm:
6852   case X86::VMOVDQU16Zrm:
6853   case X86::VMOVDQA32Zrm:
6854   case X86::VMOVDQU32Zrm:
6855   case X86::VMOVDQA64Zrm:
6856   case X86::VMOVDQU64Zrm:
6857   case X86::KMOVBkm:
6858   case X86::KMOVWkm:
6859   case X86::KMOVDkm:
6860   case X86::KMOVQkm:
6861     break;
6862   }
6863 
6864   // Lambda to check if both the loads have the same value for an operand index.
6865   auto HasSameOp = [&](int I) {
6866     return Load1->getOperand(I) == Load2->getOperand(I);
6867   };
6868 
6869   // All operands except the displacement should match.
6870   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6871       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6872     return false;
6873 
6874   // Chain Operand must be the same.
6875   if (!HasSameOp(5))
6876     return false;
6877 
6878   // Now let's examine if the displacements are constants.
6879   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6880   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6881   if (!Disp1 || !Disp2)
6882     return false;
6883 
6884   Offset1 = Disp1->getSExtValue();
6885   Offset2 = Disp2->getSExtValue();
6886   return true;
6887 }
6888 
6889 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6890                                            int64_t Offset1, int64_t Offset2,
6891                                            unsigned NumLoads) const {
6892   assert(Offset2 > Offset1);
6893   if ((Offset2 - Offset1) / 8 > 64)
6894     return false;
6895 
6896   unsigned Opc1 = Load1->getMachineOpcode();
6897   unsigned Opc2 = Load2->getMachineOpcode();
6898   if (Opc1 != Opc2)
6899     return false;  // FIXME: overly conservative?
6900 
6901   switch (Opc1) {
6902   default: break;
6903   case X86::LD_Fp32m:
6904   case X86::LD_Fp64m:
6905   case X86::LD_Fp80m:
6906   case X86::MMX_MOVD64rm:
6907   case X86::MMX_MOVQ64rm:
6908     return false;
6909   }
6910 
6911   EVT VT = Load1->getValueType(0);
6912   switch (VT.getSimpleVT().SimpleTy) {
6913   default:
6914     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6915     // have 16 of them to play with.
6916     if (Subtarget.is64Bit()) {
6917       if (NumLoads >= 3)
6918         return false;
6919     } else if (NumLoads) {
6920       return false;
6921     }
6922     break;
6923   case MVT::i8:
6924   case MVT::i16:
6925   case MVT::i32:
6926   case MVT::i64:
6927   case MVT::f32:
6928   case MVT::f64:
6929     if (NumLoads)
6930       return false;
6931     break;
6932   }
6933 
6934   return true;
6935 }
6936 
6937 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
6938                                         const MachineBasicBlock *MBB,
6939                                         const MachineFunction &MF) const {
6940 
6941   // ENDBR instructions should not be scheduled around.
6942   unsigned Opcode = MI.getOpcode();
6943   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
6944       Opcode == X86::LDTILECFG)
6945     return true;
6946 
6947   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
6948 }
6949 
6950 bool X86InstrInfo::
6951 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6952   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6953   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6954   Cond[0].setImm(GetOppositeBranchCondition(CC));
6955   return false;
6956 }
6957 
6958 bool X86InstrInfo::
6959 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6960   // FIXME: Return false for x87 stack register classes for now. We can't
6961   // allow any loads of these registers before FpGet_ST0_80.
6962   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6963            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6964            RC == &X86::RFP80RegClass);
6965 }
6966 
6967 /// Return a virtual register initialized with the
6968 /// the global base register value. Output instructions required to
6969 /// initialize the register in the function entry block, if necessary.
6970 ///
6971 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6972 ///
6973 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6974   assert((!Subtarget.is64Bit() ||
6975           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6976           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6977          "X86-64 PIC uses RIP relative addressing");
6978 
6979   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6980   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
6981   if (GlobalBaseReg != 0)
6982     return GlobalBaseReg;
6983 
6984   // Create the register. The code to initialize it is inserted
6985   // later, by the CGBR pass (below).
6986   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6987   GlobalBaseReg = RegInfo.createVirtualRegister(
6988       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6989   X86FI->setGlobalBaseReg(GlobalBaseReg);
6990   return GlobalBaseReg;
6991 }
6992 
6993 // These are the replaceable SSE instructions. Some of these have Int variants
6994 // that we don't include here. We don't want to replace instructions selected
6995 // by intrinsics.
6996 static const uint16_t ReplaceableInstrs[][3] = {
6997   //PackedSingle     PackedDouble    PackedInt
6998   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6999   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7000   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7001   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7002   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7003   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
7004   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
7005   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
7006   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
7007   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
7008   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
7009   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
7010   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7011   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7012   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7013   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7014   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7015   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7016   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7017   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7018   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7019   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
7020   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
7021   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
7022   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
7023   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
7024   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
7025   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
7026   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
7027   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
7028   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
7029   // AVX 128-bit support
7030   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7031   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7032   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7033   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7034   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7035   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
7036   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
7037   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
7038   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
7039   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
7040   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
7041   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
7042   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7043   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7044   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7045   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7046   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7047   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7048   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7049   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7050   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7051   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
7052   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
7053   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
7054   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
7055   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
7056   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
7057   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
7058   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
7059   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
7060   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
7061   // AVX 256-bit support
7062   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7063   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7064   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7065   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7066   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7067   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7068   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
7069   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
7070   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
7071   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
7072   // AVX512 support
7073   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7074   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7075   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
7076   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7077   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
7078   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
7079   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
7080   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
7081   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
7082   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
7083   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
7084   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
7085   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
7086   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
7087   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
7088   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
7089   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
7090   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
7091   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
7092   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
7093   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
7094   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
7095   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
7096   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
7097   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
7098   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
7099   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
7100   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
7101   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
7102   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
7103   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
7104   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
7105   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
7106   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
7107   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
7108   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
7109   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
7110   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
7111   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
7112   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
7113   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
7114   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
7115   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
7116   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
7117   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
7118   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
7119   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
7120   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
7121   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
7122   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
7123   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
7124   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
7125   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
7126   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
7127   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
7128   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
7129   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
7130   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
7131   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
7132   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
7133   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
7134   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
7135   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
7136   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
7137   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
7138   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
7139   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
7140   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
7141   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
7142   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
7143   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
7144   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
7145   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
7146   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
7147   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
7148   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
7149   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
7150   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
7151   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
7152   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
7153   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
7154   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
7155   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
7156   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
7157   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
7158   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
7159   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
7160   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
7161   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
7162   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
7163   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
7164   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
7165 };
7166 
7167 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7168   //PackedSingle       PackedDouble       PackedInt
7169   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7170   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7171   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7172   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7173   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7174   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7175   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7176   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7177   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7178   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7179   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7180   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7181   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
7182   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
7183   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7184   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7185   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7186   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7187   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7188   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7189   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7190   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7191   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7192   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7193   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7194   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7195   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7196   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7197   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7198   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7199   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7200 };
7201 
7202 static const uint16_t ReplaceableInstrsFP[][3] = {
7203   //PackedSingle         PackedDouble
7204   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7205   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7206   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7207   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7208   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7209   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7210   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7211   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7212   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7213 };
7214 
7215 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7216   //PackedSingle       PackedDouble       PackedInt
7217   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7218   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7219   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7220   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7221 };
7222 
7223 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7224   // Two integer columns for 64-bit and 32-bit elements.
7225   //PackedSingle        PackedDouble        PackedInt             PackedInt
7226   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7227   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7228   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7229   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7230   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7231   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7232   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7233   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7234   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7235   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7236   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7237   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7238   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7239   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7240   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7241 };
7242 
7243 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7244   // Two integer columns for 64-bit and 32-bit elements.
7245   //PackedSingle        PackedDouble        PackedInt           PackedInt
7246   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7247   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7248   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7249   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7250   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7251   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7252   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7253   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7254   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7255   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7256   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7257   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7258   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7259   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7260   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7261   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7262   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7263   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7264   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7265   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7266   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7267   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7268   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7269   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7270 };
7271 
7272 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7273   // Two integer columns for 64-bit and 32-bit elements.
7274   //PackedSingle          PackedDouble
7275   //PackedInt             PackedInt
7276   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7277     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7278   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7279     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7280   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7281     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7282   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7283     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7284   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7285     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7286   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7287     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7288   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7289     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7290   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7291     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7292   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7293     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7294   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7295     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7296   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7297     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7298   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7299     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7300   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7301     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7302   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7303     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7304   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7305     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7306   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7307     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7308   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7309     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7310   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7311     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7312   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7313     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7314   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7315     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7316   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7317     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7318   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7319     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7320   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7321     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7322   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7323     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7324   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7325     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7326   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7327     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7328   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7329     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7330   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7331     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7332   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7333     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7334   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7335     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7336   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7337     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7338   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7339     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7340   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7341     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7342   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7343     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7344   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7345     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7346   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7347     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7348   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7349     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7350   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7351     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7352   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7353     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7354   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7355     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7356   { X86::VORPSZrmk,       X86::VORPDZrmk,
7357     X86::VPORQZrmk,       X86::VPORDZrmk       },
7358   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7359     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7360   { X86::VORPSZrrk,       X86::VORPDZrrk,
7361     X86::VPORQZrrk,       X86::VPORDZrrk       },
7362   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7363     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7364   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7365     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7366   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7367     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7368   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7369     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7370   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7371     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7372   // Broadcast loads can be handled the same as masked operations to avoid
7373   // changing element size.
7374   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7375     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7376   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7377     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7378   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7379     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7380   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7381     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7382   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7383     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7384   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7385     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7386   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7387     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7388   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7389     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7390   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7391     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7392   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7393     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7394   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7395     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7396   { X86::VORPSZrmb,       X86::VORPDZrmb,
7397     X86::VPORQZrmb,       X86::VPORDZrmb       },
7398   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7399     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7400   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7401     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7402   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7403     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7404   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7405     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7406   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7407     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7408   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7409     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7410   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7411     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7412   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7413     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7414   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7415     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7416   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7417     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7418   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7419     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7420   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7421     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7422   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7423     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7424   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7425     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7426   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7427     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7428   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7429     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7430   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7431     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7432   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7433     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7434   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7435     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7436   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7437     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7438   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7439     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7440   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7441     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7442   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7443     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7444   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7445     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7446   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7447     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7448   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7449     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7450   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7451     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7452 };
7453 
7454 // NOTE: These should only be used by the custom domain methods.
7455 static const uint16_t ReplaceableBlendInstrs[][3] = {
7456   //PackedSingle             PackedDouble             PackedInt
7457   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7458   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7459   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7460   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7461   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7462   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7463 };
7464 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7465   //PackedSingle             PackedDouble             PackedInt
7466   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7467   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7468   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7469   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7470 };
7471 
7472 // Special table for changing EVEX logic instructions to VEX.
7473 // TODO: Should we run EVEX->VEX earlier?
7474 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7475   // Two integer columns for 64-bit and 32-bit elements.
7476   //PackedSingle     PackedDouble     PackedInt           PackedInt
7477   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7478   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7479   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7480   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7481   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7482   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7483   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7484   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7485   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7486   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7487   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7488   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7489   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7490   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7491   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7492   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7493 };
7494 
7495 // FIXME: Some shuffle and unpack instructions have equivalents in different
7496 // domains, but they require a bit more work than just switching opcodes.
7497 
7498 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7499                               ArrayRef<uint16_t[3]> Table) {
7500   for (const uint16_t (&Row)[3] : Table)
7501     if (Row[domain-1] == opcode)
7502       return Row;
7503   return nullptr;
7504 }
7505 
7506 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7507                                     ArrayRef<uint16_t[4]> Table) {
7508   // If this is the integer domain make sure to check both integer columns.
7509   for (const uint16_t (&Row)[4] : Table)
7510     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7511       return Row;
7512   return nullptr;
7513 }
7514 
7515 // Helper to attempt to widen/narrow blend masks.
7516 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7517                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7518   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7519          "Illegal blend mask scale");
7520   unsigned NewMask = 0;
7521 
7522   if ((OldWidth % NewWidth) == 0) {
7523     unsigned Scale = OldWidth / NewWidth;
7524     unsigned SubMask = (1u << Scale) - 1;
7525     for (unsigned i = 0; i != NewWidth; ++i) {
7526       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7527       if (Sub == SubMask)
7528         NewMask |= (1u << i);
7529       else if (Sub != 0x0)
7530         return false;
7531     }
7532   } else {
7533     unsigned Scale = NewWidth / OldWidth;
7534     unsigned SubMask = (1u << Scale) - 1;
7535     for (unsigned i = 0; i != OldWidth; ++i) {
7536       if (OldMask & (1 << i)) {
7537         NewMask |= (SubMask << (i * Scale));
7538       }
7539     }
7540   }
7541 
7542   if (pNewMask)
7543     *pNewMask = NewMask;
7544   return true;
7545 }
7546 
7547 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7548   unsigned Opcode = MI.getOpcode();
7549   unsigned NumOperands = MI.getDesc().getNumOperands();
7550 
7551   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7552     uint16_t validDomains = 0;
7553     if (MI.getOperand(NumOperands - 1).isImm()) {
7554       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7555       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7556         validDomains |= 0x2; // PackedSingle
7557       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7558         validDomains |= 0x4; // PackedDouble
7559       if (!Is256 || Subtarget.hasAVX2())
7560         validDomains |= 0x8; // PackedInt
7561     }
7562     return validDomains;
7563   };
7564 
7565   switch (Opcode) {
7566   case X86::BLENDPDrmi:
7567   case X86::BLENDPDrri:
7568   case X86::VBLENDPDrmi:
7569   case X86::VBLENDPDrri:
7570     return GetBlendDomains(2, false);
7571   case X86::VBLENDPDYrmi:
7572   case X86::VBLENDPDYrri:
7573     return GetBlendDomains(4, true);
7574   case X86::BLENDPSrmi:
7575   case X86::BLENDPSrri:
7576   case X86::VBLENDPSrmi:
7577   case X86::VBLENDPSrri:
7578   case X86::VPBLENDDrmi:
7579   case X86::VPBLENDDrri:
7580     return GetBlendDomains(4, false);
7581   case X86::VBLENDPSYrmi:
7582   case X86::VBLENDPSYrri:
7583   case X86::VPBLENDDYrmi:
7584   case X86::VPBLENDDYrri:
7585     return GetBlendDomains(8, true);
7586   case X86::PBLENDWrmi:
7587   case X86::PBLENDWrri:
7588   case X86::VPBLENDWrmi:
7589   case X86::VPBLENDWrri:
7590   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7591   case X86::VPBLENDWYrmi:
7592   case X86::VPBLENDWYrri:
7593     return GetBlendDomains(8, false);
7594   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7595   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7596   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7597   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7598   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7599   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7600   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7601   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7602   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7603   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7604   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7605   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7606   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7607   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7608   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7609   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7610     // If we don't have DQI see if we can still switch from an EVEX integer
7611     // instruction to a VEX floating point instruction.
7612     if (Subtarget.hasDQI())
7613       return 0;
7614 
7615     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7616       return 0;
7617     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7618       return 0;
7619     // Register forms will have 3 operands. Memory form will have more.
7620     if (NumOperands == 3 &&
7621         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7622       return 0;
7623 
7624     // All domains are valid.
7625     return 0xe;
7626   case X86::MOVHLPSrr:
7627     // We can swap domains when both inputs are the same register.
7628     // FIXME: This doesn't catch all the cases we would like. If the input
7629     // register isn't KILLed by the instruction, the two address instruction
7630     // pass puts a COPY on one input. The other input uses the original
7631     // register. This prevents the same physical register from being used by
7632     // both inputs.
7633     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7634         MI.getOperand(0).getSubReg() == 0 &&
7635         MI.getOperand(1).getSubReg() == 0 &&
7636         MI.getOperand(2).getSubReg() == 0)
7637       return 0x6;
7638     return 0;
7639   case X86::SHUFPDrri:
7640     return 0x6;
7641   }
7642   return 0;
7643 }
7644 
7645 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7646                                             unsigned Domain) const {
7647   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7648   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7649   assert(dom && "Not an SSE instruction");
7650 
7651   unsigned Opcode = MI.getOpcode();
7652   unsigned NumOperands = MI.getDesc().getNumOperands();
7653 
7654   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7655     if (MI.getOperand(NumOperands - 1).isImm()) {
7656       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7657       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7658       unsigned NewImm = Imm;
7659 
7660       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7661       if (!table)
7662         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7663 
7664       if (Domain == 1) { // PackedSingle
7665         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7666       } else if (Domain == 2) { // PackedDouble
7667         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7668       } else if (Domain == 3) { // PackedInt
7669         if (Subtarget.hasAVX2()) {
7670           // If we are already VPBLENDW use that, else use VPBLENDD.
7671           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7672             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7673             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7674           }
7675         } else {
7676           assert(!Is256 && "128-bit vector expected");
7677           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7678         }
7679       }
7680 
7681       assert(table && table[Domain - 1] && "Unknown domain op");
7682       MI.setDesc(get(table[Domain - 1]));
7683       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7684     }
7685     return true;
7686   };
7687 
7688   switch (Opcode) {
7689   case X86::BLENDPDrmi:
7690   case X86::BLENDPDrri:
7691   case X86::VBLENDPDrmi:
7692   case X86::VBLENDPDrri:
7693     return SetBlendDomain(2, false);
7694   case X86::VBLENDPDYrmi:
7695   case X86::VBLENDPDYrri:
7696     return SetBlendDomain(4, true);
7697   case X86::BLENDPSrmi:
7698   case X86::BLENDPSrri:
7699   case X86::VBLENDPSrmi:
7700   case X86::VBLENDPSrri:
7701   case X86::VPBLENDDrmi:
7702   case X86::VPBLENDDrri:
7703     return SetBlendDomain(4, false);
7704   case X86::VBLENDPSYrmi:
7705   case X86::VBLENDPSYrri:
7706   case X86::VPBLENDDYrmi:
7707   case X86::VPBLENDDYrri:
7708     return SetBlendDomain(8, true);
7709   case X86::PBLENDWrmi:
7710   case X86::PBLENDWrri:
7711   case X86::VPBLENDWrmi:
7712   case X86::VPBLENDWrri:
7713     return SetBlendDomain(8, false);
7714   case X86::VPBLENDWYrmi:
7715   case X86::VPBLENDWYrri:
7716     return SetBlendDomain(16, true);
7717   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7718   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7719   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7720   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7721   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7722   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7723   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7724   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7725   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7726   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7727   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7728   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7729   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7730   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7731   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7732   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7733     // Without DQI, convert EVEX instructions to VEX instructions.
7734     if (Subtarget.hasDQI())
7735       return false;
7736 
7737     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7738                                          ReplaceableCustomAVX512LogicInstrs);
7739     assert(table && "Instruction not found in table?");
7740     // Don't change integer Q instructions to D instructions and
7741     // use D intructions if we started with a PS instruction.
7742     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7743       Domain = 4;
7744     MI.setDesc(get(table[Domain - 1]));
7745     return true;
7746   }
7747   case X86::UNPCKHPDrr:
7748   case X86::MOVHLPSrr:
7749     // We just need to commute the instruction which will switch the domains.
7750     if (Domain != dom && Domain != 3 &&
7751         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7752         MI.getOperand(0).getSubReg() == 0 &&
7753         MI.getOperand(1).getSubReg() == 0 &&
7754         MI.getOperand(2).getSubReg() == 0) {
7755       commuteInstruction(MI, false);
7756       return true;
7757     }
7758     // We must always return true for MOVHLPSrr.
7759     if (Opcode == X86::MOVHLPSrr)
7760       return true;
7761     break;
7762   case X86::SHUFPDrri: {
7763     if (Domain == 1) {
7764       unsigned Imm = MI.getOperand(3).getImm();
7765       unsigned NewImm = 0x44;
7766       if (Imm & 1) NewImm |= 0x0a;
7767       if (Imm & 2) NewImm |= 0xa0;
7768       MI.getOperand(3).setImm(NewImm);
7769       MI.setDesc(get(X86::SHUFPSrri));
7770     }
7771     return true;
7772   }
7773   }
7774   return false;
7775 }
7776 
7777 std::pair<uint16_t, uint16_t>
7778 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7779   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7780   unsigned opcode = MI.getOpcode();
7781   uint16_t validDomains = 0;
7782   if (domain) {
7783     // Attempt to match for custom instructions.
7784     validDomains = getExecutionDomainCustom(MI);
7785     if (validDomains)
7786       return std::make_pair(domain, validDomains);
7787 
7788     if (lookup(opcode, domain, ReplaceableInstrs)) {
7789       validDomains = 0xe;
7790     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7791       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7792     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7793       validDomains = 0x6;
7794     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7795       // Insert/extract instructions should only effect domain if AVX2
7796       // is enabled.
7797       if (!Subtarget.hasAVX2())
7798         return std::make_pair(0, 0);
7799       validDomains = 0xe;
7800     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7801       validDomains = 0xe;
7802     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7803                                                   ReplaceableInstrsAVX512DQ)) {
7804       validDomains = 0xe;
7805     } else if (Subtarget.hasDQI()) {
7806       if (const uint16_t *table = lookupAVX512(opcode, domain,
7807                                              ReplaceableInstrsAVX512DQMasked)) {
7808         if (domain == 1 || (domain == 3 && table[3] == opcode))
7809           validDomains = 0xa;
7810         else
7811           validDomains = 0xc;
7812       }
7813     }
7814   }
7815   return std::make_pair(domain, validDomains);
7816 }
7817 
7818 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7819   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7820   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7821   assert(dom && "Not an SSE instruction");
7822 
7823   // Attempt to match for custom instructions.
7824   if (setExecutionDomainCustom(MI, Domain))
7825     return;
7826 
7827   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7828   if (!table) { // try the other table
7829     assert((Subtarget.hasAVX2() || Domain < 3) &&
7830            "256-bit vector operations only available in AVX2");
7831     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7832   }
7833   if (!table) { // try the FP table
7834     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7835     assert((!table || Domain < 3) &&
7836            "Can only select PackedSingle or PackedDouble");
7837   }
7838   if (!table) { // try the other table
7839     assert(Subtarget.hasAVX2() &&
7840            "256-bit insert/extract only available in AVX2");
7841     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7842   }
7843   if (!table) { // try the AVX512 table
7844     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7845     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7846     // Don't change integer Q instructions to D instructions.
7847     if (table && Domain == 3 && table[3] == MI.getOpcode())
7848       Domain = 4;
7849   }
7850   if (!table) { // try the AVX512DQ table
7851     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7852     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7853     // Don't change integer Q instructions to D instructions and
7854     // use D instructions if we started with a PS instruction.
7855     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7856       Domain = 4;
7857   }
7858   if (!table) { // try the AVX512DQMasked table
7859     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7860     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7861     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7862       Domain = 4;
7863   }
7864   assert(table && "Cannot change domain");
7865   MI.setDesc(get(table[Domain - 1]));
7866 }
7867 
7868 /// Return the noop instruction to use for a noop.
7869 MCInst X86InstrInfo::getNop() const {
7870   MCInst Nop;
7871   Nop.setOpcode(X86::NOOP);
7872   return Nop;
7873 }
7874 
7875 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7876   switch (opc) {
7877   default: return false;
7878   case X86::DIVPDrm:
7879   case X86::DIVPDrr:
7880   case X86::DIVPSrm:
7881   case X86::DIVPSrr:
7882   case X86::DIVSDrm:
7883   case X86::DIVSDrm_Int:
7884   case X86::DIVSDrr:
7885   case X86::DIVSDrr_Int:
7886   case X86::DIVSSrm:
7887   case X86::DIVSSrm_Int:
7888   case X86::DIVSSrr:
7889   case X86::DIVSSrr_Int:
7890   case X86::SQRTPDm:
7891   case X86::SQRTPDr:
7892   case X86::SQRTPSm:
7893   case X86::SQRTPSr:
7894   case X86::SQRTSDm:
7895   case X86::SQRTSDm_Int:
7896   case X86::SQRTSDr:
7897   case X86::SQRTSDr_Int:
7898   case X86::SQRTSSm:
7899   case X86::SQRTSSm_Int:
7900   case X86::SQRTSSr:
7901   case X86::SQRTSSr_Int:
7902   // AVX instructions with high latency
7903   case X86::VDIVPDrm:
7904   case X86::VDIVPDrr:
7905   case X86::VDIVPDYrm:
7906   case X86::VDIVPDYrr:
7907   case X86::VDIVPSrm:
7908   case X86::VDIVPSrr:
7909   case X86::VDIVPSYrm:
7910   case X86::VDIVPSYrr:
7911   case X86::VDIVSDrm:
7912   case X86::VDIVSDrm_Int:
7913   case X86::VDIVSDrr:
7914   case X86::VDIVSDrr_Int:
7915   case X86::VDIVSSrm:
7916   case X86::VDIVSSrm_Int:
7917   case X86::VDIVSSrr:
7918   case X86::VDIVSSrr_Int:
7919   case X86::VSQRTPDm:
7920   case X86::VSQRTPDr:
7921   case X86::VSQRTPDYm:
7922   case X86::VSQRTPDYr:
7923   case X86::VSQRTPSm:
7924   case X86::VSQRTPSr:
7925   case X86::VSQRTPSYm:
7926   case X86::VSQRTPSYr:
7927   case X86::VSQRTSDm:
7928   case X86::VSQRTSDm_Int:
7929   case X86::VSQRTSDr:
7930   case X86::VSQRTSDr_Int:
7931   case X86::VSQRTSSm:
7932   case X86::VSQRTSSm_Int:
7933   case X86::VSQRTSSr:
7934   case X86::VSQRTSSr_Int:
7935   // AVX512 instructions with high latency
7936   case X86::VDIVPDZ128rm:
7937   case X86::VDIVPDZ128rmb:
7938   case X86::VDIVPDZ128rmbk:
7939   case X86::VDIVPDZ128rmbkz:
7940   case X86::VDIVPDZ128rmk:
7941   case X86::VDIVPDZ128rmkz:
7942   case X86::VDIVPDZ128rr:
7943   case X86::VDIVPDZ128rrk:
7944   case X86::VDIVPDZ128rrkz:
7945   case X86::VDIVPDZ256rm:
7946   case X86::VDIVPDZ256rmb:
7947   case X86::VDIVPDZ256rmbk:
7948   case X86::VDIVPDZ256rmbkz:
7949   case X86::VDIVPDZ256rmk:
7950   case X86::VDIVPDZ256rmkz:
7951   case X86::VDIVPDZ256rr:
7952   case X86::VDIVPDZ256rrk:
7953   case X86::VDIVPDZ256rrkz:
7954   case X86::VDIVPDZrrb:
7955   case X86::VDIVPDZrrbk:
7956   case X86::VDIVPDZrrbkz:
7957   case X86::VDIVPDZrm:
7958   case X86::VDIVPDZrmb:
7959   case X86::VDIVPDZrmbk:
7960   case X86::VDIVPDZrmbkz:
7961   case X86::VDIVPDZrmk:
7962   case X86::VDIVPDZrmkz:
7963   case X86::VDIVPDZrr:
7964   case X86::VDIVPDZrrk:
7965   case X86::VDIVPDZrrkz:
7966   case X86::VDIVPSZ128rm:
7967   case X86::VDIVPSZ128rmb:
7968   case X86::VDIVPSZ128rmbk:
7969   case X86::VDIVPSZ128rmbkz:
7970   case X86::VDIVPSZ128rmk:
7971   case X86::VDIVPSZ128rmkz:
7972   case X86::VDIVPSZ128rr:
7973   case X86::VDIVPSZ128rrk:
7974   case X86::VDIVPSZ128rrkz:
7975   case X86::VDIVPSZ256rm:
7976   case X86::VDIVPSZ256rmb:
7977   case X86::VDIVPSZ256rmbk:
7978   case X86::VDIVPSZ256rmbkz:
7979   case X86::VDIVPSZ256rmk:
7980   case X86::VDIVPSZ256rmkz:
7981   case X86::VDIVPSZ256rr:
7982   case X86::VDIVPSZ256rrk:
7983   case X86::VDIVPSZ256rrkz:
7984   case X86::VDIVPSZrrb:
7985   case X86::VDIVPSZrrbk:
7986   case X86::VDIVPSZrrbkz:
7987   case X86::VDIVPSZrm:
7988   case X86::VDIVPSZrmb:
7989   case X86::VDIVPSZrmbk:
7990   case X86::VDIVPSZrmbkz:
7991   case X86::VDIVPSZrmk:
7992   case X86::VDIVPSZrmkz:
7993   case X86::VDIVPSZrr:
7994   case X86::VDIVPSZrrk:
7995   case X86::VDIVPSZrrkz:
7996   case X86::VDIVSDZrm:
7997   case X86::VDIVSDZrr:
7998   case X86::VDIVSDZrm_Int:
7999   case X86::VDIVSDZrm_Intk:
8000   case X86::VDIVSDZrm_Intkz:
8001   case X86::VDIVSDZrr_Int:
8002   case X86::VDIVSDZrr_Intk:
8003   case X86::VDIVSDZrr_Intkz:
8004   case X86::VDIVSDZrrb_Int:
8005   case X86::VDIVSDZrrb_Intk:
8006   case X86::VDIVSDZrrb_Intkz:
8007   case X86::VDIVSSZrm:
8008   case X86::VDIVSSZrr:
8009   case X86::VDIVSSZrm_Int:
8010   case X86::VDIVSSZrm_Intk:
8011   case X86::VDIVSSZrm_Intkz:
8012   case X86::VDIVSSZrr_Int:
8013   case X86::VDIVSSZrr_Intk:
8014   case X86::VDIVSSZrr_Intkz:
8015   case X86::VDIVSSZrrb_Int:
8016   case X86::VDIVSSZrrb_Intk:
8017   case X86::VDIVSSZrrb_Intkz:
8018   case X86::VSQRTPDZ128m:
8019   case X86::VSQRTPDZ128mb:
8020   case X86::VSQRTPDZ128mbk:
8021   case X86::VSQRTPDZ128mbkz:
8022   case X86::VSQRTPDZ128mk:
8023   case X86::VSQRTPDZ128mkz:
8024   case X86::VSQRTPDZ128r:
8025   case X86::VSQRTPDZ128rk:
8026   case X86::VSQRTPDZ128rkz:
8027   case X86::VSQRTPDZ256m:
8028   case X86::VSQRTPDZ256mb:
8029   case X86::VSQRTPDZ256mbk:
8030   case X86::VSQRTPDZ256mbkz:
8031   case X86::VSQRTPDZ256mk:
8032   case X86::VSQRTPDZ256mkz:
8033   case X86::VSQRTPDZ256r:
8034   case X86::VSQRTPDZ256rk:
8035   case X86::VSQRTPDZ256rkz:
8036   case X86::VSQRTPDZm:
8037   case X86::VSQRTPDZmb:
8038   case X86::VSQRTPDZmbk:
8039   case X86::VSQRTPDZmbkz:
8040   case X86::VSQRTPDZmk:
8041   case X86::VSQRTPDZmkz:
8042   case X86::VSQRTPDZr:
8043   case X86::VSQRTPDZrb:
8044   case X86::VSQRTPDZrbk:
8045   case X86::VSQRTPDZrbkz:
8046   case X86::VSQRTPDZrk:
8047   case X86::VSQRTPDZrkz:
8048   case X86::VSQRTPSZ128m:
8049   case X86::VSQRTPSZ128mb:
8050   case X86::VSQRTPSZ128mbk:
8051   case X86::VSQRTPSZ128mbkz:
8052   case X86::VSQRTPSZ128mk:
8053   case X86::VSQRTPSZ128mkz:
8054   case X86::VSQRTPSZ128r:
8055   case X86::VSQRTPSZ128rk:
8056   case X86::VSQRTPSZ128rkz:
8057   case X86::VSQRTPSZ256m:
8058   case X86::VSQRTPSZ256mb:
8059   case X86::VSQRTPSZ256mbk:
8060   case X86::VSQRTPSZ256mbkz:
8061   case X86::VSQRTPSZ256mk:
8062   case X86::VSQRTPSZ256mkz:
8063   case X86::VSQRTPSZ256r:
8064   case X86::VSQRTPSZ256rk:
8065   case X86::VSQRTPSZ256rkz:
8066   case X86::VSQRTPSZm:
8067   case X86::VSQRTPSZmb:
8068   case X86::VSQRTPSZmbk:
8069   case X86::VSQRTPSZmbkz:
8070   case X86::VSQRTPSZmk:
8071   case X86::VSQRTPSZmkz:
8072   case X86::VSQRTPSZr:
8073   case X86::VSQRTPSZrb:
8074   case X86::VSQRTPSZrbk:
8075   case X86::VSQRTPSZrbkz:
8076   case X86::VSQRTPSZrk:
8077   case X86::VSQRTPSZrkz:
8078   case X86::VSQRTSDZm:
8079   case X86::VSQRTSDZm_Int:
8080   case X86::VSQRTSDZm_Intk:
8081   case X86::VSQRTSDZm_Intkz:
8082   case X86::VSQRTSDZr:
8083   case X86::VSQRTSDZr_Int:
8084   case X86::VSQRTSDZr_Intk:
8085   case X86::VSQRTSDZr_Intkz:
8086   case X86::VSQRTSDZrb_Int:
8087   case X86::VSQRTSDZrb_Intk:
8088   case X86::VSQRTSDZrb_Intkz:
8089   case X86::VSQRTSSZm:
8090   case X86::VSQRTSSZm_Int:
8091   case X86::VSQRTSSZm_Intk:
8092   case X86::VSQRTSSZm_Intkz:
8093   case X86::VSQRTSSZr:
8094   case X86::VSQRTSSZr_Int:
8095   case X86::VSQRTSSZr_Intk:
8096   case X86::VSQRTSSZr_Intkz:
8097   case X86::VSQRTSSZrb_Int:
8098   case X86::VSQRTSSZrb_Intk:
8099   case X86::VSQRTSSZrb_Intkz:
8100 
8101   case X86::VGATHERDPDYrm:
8102   case X86::VGATHERDPDZ128rm:
8103   case X86::VGATHERDPDZ256rm:
8104   case X86::VGATHERDPDZrm:
8105   case X86::VGATHERDPDrm:
8106   case X86::VGATHERDPSYrm:
8107   case X86::VGATHERDPSZ128rm:
8108   case X86::VGATHERDPSZ256rm:
8109   case X86::VGATHERDPSZrm:
8110   case X86::VGATHERDPSrm:
8111   case X86::VGATHERPF0DPDm:
8112   case X86::VGATHERPF0DPSm:
8113   case X86::VGATHERPF0QPDm:
8114   case X86::VGATHERPF0QPSm:
8115   case X86::VGATHERPF1DPDm:
8116   case X86::VGATHERPF1DPSm:
8117   case X86::VGATHERPF1QPDm:
8118   case X86::VGATHERPF1QPSm:
8119   case X86::VGATHERQPDYrm:
8120   case X86::VGATHERQPDZ128rm:
8121   case X86::VGATHERQPDZ256rm:
8122   case X86::VGATHERQPDZrm:
8123   case X86::VGATHERQPDrm:
8124   case X86::VGATHERQPSYrm:
8125   case X86::VGATHERQPSZ128rm:
8126   case X86::VGATHERQPSZ256rm:
8127   case X86::VGATHERQPSZrm:
8128   case X86::VGATHERQPSrm:
8129   case X86::VPGATHERDDYrm:
8130   case X86::VPGATHERDDZ128rm:
8131   case X86::VPGATHERDDZ256rm:
8132   case X86::VPGATHERDDZrm:
8133   case X86::VPGATHERDDrm:
8134   case X86::VPGATHERDQYrm:
8135   case X86::VPGATHERDQZ128rm:
8136   case X86::VPGATHERDQZ256rm:
8137   case X86::VPGATHERDQZrm:
8138   case X86::VPGATHERDQrm:
8139   case X86::VPGATHERQDYrm:
8140   case X86::VPGATHERQDZ128rm:
8141   case X86::VPGATHERQDZ256rm:
8142   case X86::VPGATHERQDZrm:
8143   case X86::VPGATHERQDrm:
8144   case X86::VPGATHERQQYrm:
8145   case X86::VPGATHERQQZ128rm:
8146   case X86::VPGATHERQQZ256rm:
8147   case X86::VPGATHERQQZrm:
8148   case X86::VPGATHERQQrm:
8149   case X86::VSCATTERDPDZ128mr:
8150   case X86::VSCATTERDPDZ256mr:
8151   case X86::VSCATTERDPDZmr:
8152   case X86::VSCATTERDPSZ128mr:
8153   case X86::VSCATTERDPSZ256mr:
8154   case X86::VSCATTERDPSZmr:
8155   case X86::VSCATTERPF0DPDm:
8156   case X86::VSCATTERPF0DPSm:
8157   case X86::VSCATTERPF0QPDm:
8158   case X86::VSCATTERPF0QPSm:
8159   case X86::VSCATTERPF1DPDm:
8160   case X86::VSCATTERPF1DPSm:
8161   case X86::VSCATTERPF1QPDm:
8162   case X86::VSCATTERPF1QPSm:
8163   case X86::VSCATTERQPDZ128mr:
8164   case X86::VSCATTERQPDZ256mr:
8165   case X86::VSCATTERQPDZmr:
8166   case X86::VSCATTERQPSZ128mr:
8167   case X86::VSCATTERQPSZ256mr:
8168   case X86::VSCATTERQPSZmr:
8169   case X86::VPSCATTERDDZ128mr:
8170   case X86::VPSCATTERDDZ256mr:
8171   case X86::VPSCATTERDDZmr:
8172   case X86::VPSCATTERDQZ128mr:
8173   case X86::VPSCATTERDQZ256mr:
8174   case X86::VPSCATTERDQZmr:
8175   case X86::VPSCATTERQDZ128mr:
8176   case X86::VPSCATTERQDZ256mr:
8177   case X86::VPSCATTERQDZmr:
8178   case X86::VPSCATTERQQZ128mr:
8179   case X86::VPSCATTERQQZ256mr:
8180   case X86::VPSCATTERQQZmr:
8181     return true;
8182   }
8183 }
8184 
8185 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8186                                          const MachineRegisterInfo *MRI,
8187                                          const MachineInstr &DefMI,
8188                                          unsigned DefIdx,
8189                                          const MachineInstr &UseMI,
8190                                          unsigned UseIdx) const {
8191   return isHighLatencyDef(DefMI.getOpcode());
8192 }
8193 
8194 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8195                                            const MachineBasicBlock *MBB) const {
8196   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8197          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8198 
8199   // Integer binary math/logic instructions have a third source operand:
8200   // the EFLAGS register. That operand must be both defined here and never
8201   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8202   // not change anything because rearranging the operands could affect other
8203   // instructions that depend on the exact status flags (zero, sign, etc.)
8204   // that are set by using these particular operands with this operation.
8205   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8206   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8207          "Implicit def isn't flags?");
8208   if (FlagDef && !FlagDef->isDead())
8209     return false;
8210 
8211   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8212 }
8213 
8214 // TODO: There are many more machine instruction opcodes to match:
8215 //       1. Other data types (integer, vectors)
8216 //       2. Other math / logic operations (xor, or)
8217 //       3. Other forms of the same operation (intrinsics and other variants)
8218 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8219   switch (Inst.getOpcode()) {
8220   case X86::AND8rr:
8221   case X86::AND16rr:
8222   case X86::AND32rr:
8223   case X86::AND64rr:
8224   case X86::OR8rr:
8225   case X86::OR16rr:
8226   case X86::OR32rr:
8227   case X86::OR64rr:
8228   case X86::XOR8rr:
8229   case X86::XOR16rr:
8230   case X86::XOR32rr:
8231   case X86::XOR64rr:
8232   case X86::IMUL16rr:
8233   case X86::IMUL32rr:
8234   case X86::IMUL64rr:
8235   case X86::PANDrr:
8236   case X86::PORrr:
8237   case X86::PXORrr:
8238   case X86::ANDPDrr:
8239   case X86::ANDPSrr:
8240   case X86::ORPDrr:
8241   case X86::ORPSrr:
8242   case X86::XORPDrr:
8243   case X86::XORPSrr:
8244   case X86::PADDBrr:
8245   case X86::PADDWrr:
8246   case X86::PADDDrr:
8247   case X86::PADDQrr:
8248   case X86::PMULLWrr:
8249   case X86::PMULLDrr:
8250   case X86::PMAXSBrr:
8251   case X86::PMAXSDrr:
8252   case X86::PMAXSWrr:
8253   case X86::PMAXUBrr:
8254   case X86::PMAXUDrr:
8255   case X86::PMAXUWrr:
8256   case X86::PMINSBrr:
8257   case X86::PMINSDrr:
8258   case X86::PMINSWrr:
8259   case X86::PMINUBrr:
8260   case X86::PMINUDrr:
8261   case X86::PMINUWrr:
8262   case X86::VPANDrr:
8263   case X86::VPANDYrr:
8264   case X86::VPANDDZ128rr:
8265   case X86::VPANDDZ256rr:
8266   case X86::VPANDDZrr:
8267   case X86::VPANDQZ128rr:
8268   case X86::VPANDQZ256rr:
8269   case X86::VPANDQZrr:
8270   case X86::VPORrr:
8271   case X86::VPORYrr:
8272   case X86::VPORDZ128rr:
8273   case X86::VPORDZ256rr:
8274   case X86::VPORDZrr:
8275   case X86::VPORQZ128rr:
8276   case X86::VPORQZ256rr:
8277   case X86::VPORQZrr:
8278   case X86::VPXORrr:
8279   case X86::VPXORYrr:
8280   case X86::VPXORDZ128rr:
8281   case X86::VPXORDZ256rr:
8282   case X86::VPXORDZrr:
8283   case X86::VPXORQZ128rr:
8284   case X86::VPXORQZ256rr:
8285   case X86::VPXORQZrr:
8286   case X86::VANDPDrr:
8287   case X86::VANDPSrr:
8288   case X86::VANDPDYrr:
8289   case X86::VANDPSYrr:
8290   case X86::VANDPDZ128rr:
8291   case X86::VANDPSZ128rr:
8292   case X86::VANDPDZ256rr:
8293   case X86::VANDPSZ256rr:
8294   case X86::VANDPDZrr:
8295   case X86::VANDPSZrr:
8296   case X86::VORPDrr:
8297   case X86::VORPSrr:
8298   case X86::VORPDYrr:
8299   case X86::VORPSYrr:
8300   case X86::VORPDZ128rr:
8301   case X86::VORPSZ128rr:
8302   case X86::VORPDZ256rr:
8303   case X86::VORPSZ256rr:
8304   case X86::VORPDZrr:
8305   case X86::VORPSZrr:
8306   case X86::VXORPDrr:
8307   case X86::VXORPSrr:
8308   case X86::VXORPDYrr:
8309   case X86::VXORPSYrr:
8310   case X86::VXORPDZ128rr:
8311   case X86::VXORPSZ128rr:
8312   case X86::VXORPDZ256rr:
8313   case X86::VXORPSZ256rr:
8314   case X86::VXORPDZrr:
8315   case X86::VXORPSZrr:
8316   case X86::KADDBrr:
8317   case X86::KADDWrr:
8318   case X86::KADDDrr:
8319   case X86::KADDQrr:
8320   case X86::KANDBrr:
8321   case X86::KANDWrr:
8322   case X86::KANDDrr:
8323   case X86::KANDQrr:
8324   case X86::KORBrr:
8325   case X86::KORWrr:
8326   case X86::KORDrr:
8327   case X86::KORQrr:
8328   case X86::KXORBrr:
8329   case X86::KXORWrr:
8330   case X86::KXORDrr:
8331   case X86::KXORQrr:
8332   case X86::VPADDBrr:
8333   case X86::VPADDWrr:
8334   case X86::VPADDDrr:
8335   case X86::VPADDQrr:
8336   case X86::VPADDBYrr:
8337   case X86::VPADDWYrr:
8338   case X86::VPADDDYrr:
8339   case X86::VPADDQYrr:
8340   case X86::VPADDBZ128rr:
8341   case X86::VPADDWZ128rr:
8342   case X86::VPADDDZ128rr:
8343   case X86::VPADDQZ128rr:
8344   case X86::VPADDBZ256rr:
8345   case X86::VPADDWZ256rr:
8346   case X86::VPADDDZ256rr:
8347   case X86::VPADDQZ256rr:
8348   case X86::VPADDBZrr:
8349   case X86::VPADDWZrr:
8350   case X86::VPADDDZrr:
8351   case X86::VPADDQZrr:
8352   case X86::VPMULLWrr:
8353   case X86::VPMULLWYrr:
8354   case X86::VPMULLWZ128rr:
8355   case X86::VPMULLWZ256rr:
8356   case X86::VPMULLWZrr:
8357   case X86::VPMULLDrr:
8358   case X86::VPMULLDYrr:
8359   case X86::VPMULLDZ128rr:
8360   case X86::VPMULLDZ256rr:
8361   case X86::VPMULLDZrr:
8362   case X86::VPMULLQZ128rr:
8363   case X86::VPMULLQZ256rr:
8364   case X86::VPMULLQZrr:
8365   case X86::VPMAXSBrr:
8366   case X86::VPMAXSBYrr:
8367   case X86::VPMAXSBZ128rr:
8368   case X86::VPMAXSBZ256rr:
8369   case X86::VPMAXSBZrr:
8370   case X86::VPMAXSDrr:
8371   case X86::VPMAXSDYrr:
8372   case X86::VPMAXSDZ128rr:
8373   case X86::VPMAXSDZ256rr:
8374   case X86::VPMAXSDZrr:
8375   case X86::VPMAXSQZ128rr:
8376   case X86::VPMAXSQZ256rr:
8377   case X86::VPMAXSQZrr:
8378   case X86::VPMAXSWrr:
8379   case X86::VPMAXSWYrr:
8380   case X86::VPMAXSWZ128rr:
8381   case X86::VPMAXSWZ256rr:
8382   case X86::VPMAXSWZrr:
8383   case X86::VPMAXUBrr:
8384   case X86::VPMAXUBYrr:
8385   case X86::VPMAXUBZ128rr:
8386   case X86::VPMAXUBZ256rr:
8387   case X86::VPMAXUBZrr:
8388   case X86::VPMAXUDrr:
8389   case X86::VPMAXUDYrr:
8390   case X86::VPMAXUDZ128rr:
8391   case X86::VPMAXUDZ256rr:
8392   case X86::VPMAXUDZrr:
8393   case X86::VPMAXUQZ128rr:
8394   case X86::VPMAXUQZ256rr:
8395   case X86::VPMAXUQZrr:
8396   case X86::VPMAXUWrr:
8397   case X86::VPMAXUWYrr:
8398   case X86::VPMAXUWZ128rr:
8399   case X86::VPMAXUWZ256rr:
8400   case X86::VPMAXUWZrr:
8401   case X86::VPMINSBrr:
8402   case X86::VPMINSBYrr:
8403   case X86::VPMINSBZ128rr:
8404   case X86::VPMINSBZ256rr:
8405   case X86::VPMINSBZrr:
8406   case X86::VPMINSDrr:
8407   case X86::VPMINSDYrr:
8408   case X86::VPMINSDZ128rr:
8409   case X86::VPMINSDZ256rr:
8410   case X86::VPMINSDZrr:
8411   case X86::VPMINSQZ128rr:
8412   case X86::VPMINSQZ256rr:
8413   case X86::VPMINSQZrr:
8414   case X86::VPMINSWrr:
8415   case X86::VPMINSWYrr:
8416   case X86::VPMINSWZ128rr:
8417   case X86::VPMINSWZ256rr:
8418   case X86::VPMINSWZrr:
8419   case X86::VPMINUBrr:
8420   case X86::VPMINUBYrr:
8421   case X86::VPMINUBZ128rr:
8422   case X86::VPMINUBZ256rr:
8423   case X86::VPMINUBZrr:
8424   case X86::VPMINUDrr:
8425   case X86::VPMINUDYrr:
8426   case X86::VPMINUDZ128rr:
8427   case X86::VPMINUDZ256rr:
8428   case X86::VPMINUDZrr:
8429   case X86::VPMINUQZ128rr:
8430   case X86::VPMINUQZ256rr:
8431   case X86::VPMINUQZrr:
8432   case X86::VPMINUWrr:
8433   case X86::VPMINUWYrr:
8434   case X86::VPMINUWZ128rr:
8435   case X86::VPMINUWZ256rr:
8436   case X86::VPMINUWZrr:
8437   // Normal min/max instructions are not commutative because of NaN and signed
8438   // zero semantics, but these are. Thus, there's no need to check for global
8439   // relaxed math; the instructions themselves have the properties we need.
8440   case X86::MAXCPDrr:
8441   case X86::MAXCPSrr:
8442   case X86::MAXCSDrr:
8443   case X86::MAXCSSrr:
8444   case X86::MINCPDrr:
8445   case X86::MINCPSrr:
8446   case X86::MINCSDrr:
8447   case X86::MINCSSrr:
8448   case X86::VMAXCPDrr:
8449   case X86::VMAXCPSrr:
8450   case X86::VMAXCPDYrr:
8451   case X86::VMAXCPSYrr:
8452   case X86::VMAXCPDZ128rr:
8453   case X86::VMAXCPSZ128rr:
8454   case X86::VMAXCPDZ256rr:
8455   case X86::VMAXCPSZ256rr:
8456   case X86::VMAXCPDZrr:
8457   case X86::VMAXCPSZrr:
8458   case X86::VMAXCSDrr:
8459   case X86::VMAXCSSrr:
8460   case X86::VMAXCSDZrr:
8461   case X86::VMAXCSSZrr:
8462   case X86::VMINCPDrr:
8463   case X86::VMINCPSrr:
8464   case X86::VMINCPDYrr:
8465   case X86::VMINCPSYrr:
8466   case X86::VMINCPDZ128rr:
8467   case X86::VMINCPSZ128rr:
8468   case X86::VMINCPDZ256rr:
8469   case X86::VMINCPSZ256rr:
8470   case X86::VMINCPDZrr:
8471   case X86::VMINCPSZrr:
8472   case X86::VMINCSDrr:
8473   case X86::VMINCSSrr:
8474   case X86::VMINCSDZrr:
8475   case X86::VMINCSSZrr:
8476   case X86::VMAXCPHZ128rr:
8477   case X86::VMAXCPHZ256rr:
8478   case X86::VMAXCPHZrr:
8479   case X86::VMAXCSHZrr:
8480   case X86::VMINCPHZ128rr:
8481   case X86::VMINCPHZ256rr:
8482   case X86::VMINCPHZrr:
8483   case X86::VMINCSHZrr:
8484     return true;
8485   case X86::ADDPDrr:
8486   case X86::ADDPSrr:
8487   case X86::ADDSDrr:
8488   case X86::ADDSSrr:
8489   case X86::MULPDrr:
8490   case X86::MULPSrr:
8491   case X86::MULSDrr:
8492   case X86::MULSSrr:
8493   case X86::VADDPDrr:
8494   case X86::VADDPSrr:
8495   case X86::VADDPDYrr:
8496   case X86::VADDPSYrr:
8497   case X86::VADDPDZ128rr:
8498   case X86::VADDPSZ128rr:
8499   case X86::VADDPDZ256rr:
8500   case X86::VADDPSZ256rr:
8501   case X86::VADDPDZrr:
8502   case X86::VADDPSZrr:
8503   case X86::VADDSDrr:
8504   case X86::VADDSSrr:
8505   case X86::VADDSDZrr:
8506   case X86::VADDSSZrr:
8507   case X86::VMULPDrr:
8508   case X86::VMULPSrr:
8509   case X86::VMULPDYrr:
8510   case X86::VMULPSYrr:
8511   case X86::VMULPDZ128rr:
8512   case X86::VMULPSZ128rr:
8513   case X86::VMULPDZ256rr:
8514   case X86::VMULPSZ256rr:
8515   case X86::VMULPDZrr:
8516   case X86::VMULPSZrr:
8517   case X86::VMULSDrr:
8518   case X86::VMULSSrr:
8519   case X86::VMULSDZrr:
8520   case X86::VMULSSZrr:
8521   case X86::VADDPHZ128rr:
8522   case X86::VADDPHZ256rr:
8523   case X86::VADDPHZrr:
8524   case X86::VADDSHZrr:
8525   case X86::VMULPHZ128rr:
8526   case X86::VMULPHZ256rr:
8527   case X86::VMULPHZrr:
8528   case X86::VMULSHZrr:
8529     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8530            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8531   default:
8532     return false;
8533   }
8534 }
8535 
8536 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8537 /// register then, if possible, describe the value in terms of the source
8538 /// register.
8539 static Optional<ParamLoadedValue>
8540 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8541                          const TargetRegisterInfo *TRI) {
8542   Register DestReg = MI.getOperand(0).getReg();
8543   Register SrcReg = MI.getOperand(1).getReg();
8544 
8545   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8546 
8547   // If the described register is the destination, just return the source.
8548   if (DestReg == DescribedReg)
8549     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8550 
8551   // If the described register is a sub-register of the destination register,
8552   // then pick out the source register's corresponding sub-register.
8553   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8554     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8555     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8556   }
8557 
8558   // The remaining case to consider is when the described register is a
8559   // super-register of the destination register. MOV8rr and MOV16rr does not
8560   // write to any of the other bytes in the register, meaning that we'd have to
8561   // describe the value using a combination of the source register and the
8562   // non-overlapping bits in the described register, which is not currently
8563   // possible.
8564   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8565       !TRI->isSuperRegister(DestReg, DescribedReg))
8566     return None;
8567 
8568   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8569   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8570 }
8571 
8572 Optional<ParamLoadedValue>
8573 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8574   const MachineOperand *Op = nullptr;
8575   DIExpression *Expr = nullptr;
8576 
8577   const TargetRegisterInfo *TRI = &getRegisterInfo();
8578 
8579   switch (MI.getOpcode()) {
8580   case X86::LEA32r:
8581   case X86::LEA64r:
8582   case X86::LEA64_32r: {
8583     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8584     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8585       return None;
8586 
8587     // Operand 4 could be global address. For now we do not support
8588     // such situation.
8589     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8590       return None;
8591 
8592     const MachineOperand &Op1 = MI.getOperand(1);
8593     const MachineOperand &Op2 = MI.getOperand(3);
8594     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8595                            Register::isPhysicalRegister(Op2.getReg())));
8596 
8597     // Omit situations like:
8598     // %rsi = lea %rsi, 4, ...
8599     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8600         Op2.getReg() == MI.getOperand(0).getReg())
8601       return None;
8602     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8603               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8604              (Op2.getReg() != X86::NoRegister &&
8605               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8606       return None;
8607 
8608     int64_t Coef = MI.getOperand(2).getImm();
8609     int64_t Offset = MI.getOperand(4).getImm();
8610     SmallVector<uint64_t, 8> Ops;
8611 
8612     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8613       Op = &Op1;
8614     } else if (Op1.isFI())
8615       Op = &Op1;
8616 
8617     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8618       Ops.push_back(dwarf::DW_OP_constu);
8619       Ops.push_back(Coef + 1);
8620       Ops.push_back(dwarf::DW_OP_mul);
8621     } else {
8622       if (Op && Op2.getReg() != X86::NoRegister) {
8623         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8624         if (dwarfReg < 0)
8625           return None;
8626         else if (dwarfReg < 32) {
8627           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8628           Ops.push_back(0);
8629         } else {
8630           Ops.push_back(dwarf::DW_OP_bregx);
8631           Ops.push_back(dwarfReg);
8632           Ops.push_back(0);
8633         }
8634       } else if (!Op) {
8635         assert(Op2.getReg() != X86::NoRegister);
8636         Op = &Op2;
8637       }
8638 
8639       if (Coef > 1) {
8640         assert(Op2.getReg() != X86::NoRegister);
8641         Ops.push_back(dwarf::DW_OP_constu);
8642         Ops.push_back(Coef);
8643         Ops.push_back(dwarf::DW_OP_mul);
8644       }
8645 
8646       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8647           Op2.getReg() != X86::NoRegister) {
8648         Ops.push_back(dwarf::DW_OP_plus);
8649       }
8650     }
8651 
8652     DIExpression::appendOffset(Ops, Offset);
8653     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8654 
8655     return ParamLoadedValue(*Op, Expr);;
8656   }
8657   case X86::MOV8ri:
8658   case X86::MOV16ri:
8659     // TODO: Handle MOV8ri and MOV16ri.
8660     return None;
8661   case X86::MOV32ri:
8662   case X86::MOV64ri:
8663   case X86::MOV64ri32:
8664     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8665     // 64-bit parameters, so we need to consider super-registers.
8666     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8667       return None;
8668     return ParamLoadedValue(MI.getOperand(1), Expr);
8669   case X86::MOV8rr:
8670   case X86::MOV16rr:
8671   case X86::MOV32rr:
8672   case X86::MOV64rr:
8673     return describeMOVrrLoadedValue(MI, Reg, TRI);
8674   case X86::XOR32rr: {
8675     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8676     // super-registers.
8677     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8678       return None;
8679     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8680       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8681     return None;
8682   }
8683   case X86::MOVSX64rr32: {
8684     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8685     // cases like this:
8686     //
8687     //  $ebx = [...]
8688     //  $rdi = MOVSX64rr32 $ebx
8689     //  $esi = MOV32rr $edi
8690     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8691       return None;
8692 
8693     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8694 
8695     // If the described register is the destination register we need to
8696     // sign-extend the source register from 32 bits. The other case we handle
8697     // is when the described register is the 32-bit sub-register of the
8698     // destination register, in case we just need to return the source
8699     // register.
8700     if (Reg == MI.getOperand(0).getReg())
8701       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8702     else
8703       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8704              "Unhandled sub-register case for MOVSX64rr32");
8705 
8706     return ParamLoadedValue(MI.getOperand(1), Expr);
8707   }
8708   default:
8709     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8710     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8711   }
8712 }
8713 
8714 /// This is an architecture-specific helper function of reassociateOps.
8715 /// Set special operand attributes for new instructions after reassociation.
8716 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8717                                          MachineInstr &OldMI2,
8718                                          MachineInstr &NewMI1,
8719                                          MachineInstr &NewMI2) const {
8720   // Propagate FP flags from the original instructions.
8721   // But clear poison-generating flags because those may not be valid now.
8722   // TODO: There should be a helper function for copying only fast-math-flags.
8723   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8724   NewMI1.setFlags(IntersectedFlags);
8725   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8726   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8727   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8728 
8729   NewMI2.setFlags(IntersectedFlags);
8730   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8731   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8732   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8733 
8734   // Integer instructions may define an implicit EFLAGS dest register operand.
8735   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8736   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8737 
8738   assert(!OldFlagDef1 == !OldFlagDef2 &&
8739          "Unexpected instruction type for reassociation");
8740 
8741   if (!OldFlagDef1 || !OldFlagDef2)
8742     return;
8743 
8744   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8745          "Must have dead EFLAGS operand in reassociable instruction");
8746 
8747   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8748   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8749 
8750   assert(NewFlagDef1 && NewFlagDef2 &&
8751          "Unexpected operand in reassociable instruction");
8752 
8753   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8754   // of this pass or other passes. The EFLAGS operands must be dead in these new
8755   // instructions because the EFLAGS operands in the original instructions must
8756   // be dead in order for reassociation to occur.
8757   NewFlagDef1->setIsDead();
8758   NewFlagDef2->setIsDead();
8759 }
8760 
8761 std::pair<unsigned, unsigned>
8762 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8763   return std::make_pair(TF, 0u);
8764 }
8765 
8766 ArrayRef<std::pair<unsigned, const char *>>
8767 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8768   using namespace X86II;
8769   static const std::pair<unsigned, const char *> TargetFlags[] = {
8770       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8771       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8772       {MO_GOT, "x86-got"},
8773       {MO_GOTOFF, "x86-gotoff"},
8774       {MO_GOTPCREL, "x86-gotpcrel"},
8775       {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
8776       {MO_PLT, "x86-plt"},
8777       {MO_TLSGD, "x86-tlsgd"},
8778       {MO_TLSLD, "x86-tlsld"},
8779       {MO_TLSLDM, "x86-tlsldm"},
8780       {MO_GOTTPOFF, "x86-gottpoff"},
8781       {MO_INDNTPOFF, "x86-indntpoff"},
8782       {MO_TPOFF, "x86-tpoff"},
8783       {MO_DTPOFF, "x86-dtpoff"},
8784       {MO_NTPOFF, "x86-ntpoff"},
8785       {MO_GOTNTPOFF, "x86-gotntpoff"},
8786       {MO_DLLIMPORT, "x86-dllimport"},
8787       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8788       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8789       {MO_TLVP, "x86-tlvp"},
8790       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8791       {MO_SECREL, "x86-secrel"},
8792       {MO_COFFSTUB, "x86-coffstub"}};
8793   return makeArrayRef(TargetFlags);
8794 }
8795 
8796 namespace {
8797   /// Create Global Base Reg pass. This initializes the PIC
8798   /// global base register for x86-32.
8799   struct CGBR : public MachineFunctionPass {
8800     static char ID;
8801     CGBR() : MachineFunctionPass(ID) {}
8802 
8803     bool runOnMachineFunction(MachineFunction &MF) override {
8804       const X86TargetMachine *TM =
8805         static_cast<const X86TargetMachine *>(&MF.getTarget());
8806       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8807 
8808       // Don't do anything in the 64-bit small and kernel code models. They use
8809       // RIP-relative addressing for everything.
8810       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8811                             TM->getCodeModel() == CodeModel::Kernel))
8812         return false;
8813 
8814       // Only emit a global base reg in PIC mode.
8815       if (!TM->isPositionIndependent())
8816         return false;
8817 
8818       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8819       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
8820 
8821       // If we didn't need a GlobalBaseReg, don't insert code.
8822       if (GlobalBaseReg == 0)
8823         return false;
8824 
8825       // Insert the set of GlobalBaseReg into the first MBB of the function
8826       MachineBasicBlock &FirstMBB = MF.front();
8827       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8828       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8829       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8830       const X86InstrInfo *TII = STI.getInstrInfo();
8831 
8832       Register PC;
8833       if (STI.isPICStyleGOT())
8834         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8835       else
8836         PC = GlobalBaseReg;
8837 
8838       if (STI.is64Bit()) {
8839         if (TM->getCodeModel() == CodeModel::Medium) {
8840           // In the medium code model, use a RIP-relative LEA to materialize the
8841           // GOT.
8842           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8843               .addReg(X86::RIP)
8844               .addImm(0)
8845               .addReg(0)
8846               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8847               .addReg(0);
8848         } else if (TM->getCodeModel() == CodeModel::Large) {
8849           // In the large code model, we are aiming for this code, though the
8850           // register allocation may vary:
8851           //   leaq .LN$pb(%rip), %rax
8852           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8853           //   addq %rcx, %rax
8854           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8855           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8856           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8857           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8858               .addReg(X86::RIP)
8859               .addImm(0)
8860               .addReg(0)
8861               .addSym(MF.getPICBaseSymbol())
8862               .addReg(0);
8863           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8864           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8865               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8866                                  X86II::MO_PIC_BASE_OFFSET);
8867           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8868               .addReg(PBReg, RegState::Kill)
8869               .addReg(GOTReg, RegState::Kill);
8870         } else {
8871           llvm_unreachable("unexpected code model");
8872         }
8873       } else {
8874         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8875         // only used in JIT code emission as displacement to pc.
8876         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8877 
8878         // If we're using vanilla 'GOT' PIC style, we should use relative
8879         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8880         if (STI.isPICStyleGOT()) {
8881           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8882           // %some_register
8883           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8884               .addReg(PC)
8885               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8886                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8887         }
8888       }
8889 
8890       return true;
8891     }
8892 
8893     StringRef getPassName() const override {
8894       return "X86 PIC Global Base Reg Initialization";
8895     }
8896 
8897     void getAnalysisUsage(AnalysisUsage &AU) const override {
8898       AU.setPreservesCFG();
8899       MachineFunctionPass::getAnalysisUsage(AU);
8900     }
8901   };
8902 } // namespace
8903 
8904 char CGBR::ID = 0;
8905 FunctionPass*
8906 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8907 
8908 namespace {
8909   struct LDTLSCleanup : public MachineFunctionPass {
8910     static char ID;
8911     LDTLSCleanup() : MachineFunctionPass(ID) {}
8912 
8913     bool runOnMachineFunction(MachineFunction &MF) override {
8914       if (skipFunction(MF.getFunction()))
8915         return false;
8916 
8917       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8918       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8919         // No point folding accesses if there isn't at least two.
8920         return false;
8921       }
8922 
8923       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8924       return VisitNode(DT->getRootNode(), 0);
8925     }
8926 
8927     // Visit the dominator subtree rooted at Node in pre-order.
8928     // If TLSBaseAddrReg is non-null, then use that to replace any
8929     // TLS_base_addr instructions. Otherwise, create the register
8930     // when the first such instruction is seen, and then use it
8931     // as we encounter more instructions.
8932     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8933       MachineBasicBlock *BB = Node->getBlock();
8934       bool Changed = false;
8935 
8936       // Traverse the current block.
8937       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8938            ++I) {
8939         switch (I->getOpcode()) {
8940           case X86::TLS_base_addr32:
8941           case X86::TLS_base_addr64:
8942             if (TLSBaseAddrReg)
8943               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8944             else
8945               I = SetRegister(*I, &TLSBaseAddrReg);
8946             Changed = true;
8947             break;
8948           default:
8949             break;
8950         }
8951       }
8952 
8953       // Visit the children of this block in the dominator tree.
8954       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
8955         Changed |= VisitNode(*I, TLSBaseAddrReg);
8956       }
8957 
8958       return Changed;
8959     }
8960 
8961     // Replace the TLS_base_addr instruction I with a copy from
8962     // TLSBaseAddrReg, returning the new instruction.
8963     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8964                                          unsigned TLSBaseAddrReg) {
8965       MachineFunction *MF = I.getParent()->getParent();
8966       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8967       const bool is64Bit = STI.is64Bit();
8968       const X86InstrInfo *TII = STI.getInstrInfo();
8969 
8970       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8971       MachineInstr *Copy =
8972           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8973                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8974               .addReg(TLSBaseAddrReg);
8975 
8976       // Erase the TLS_base_addr instruction.
8977       I.eraseFromParent();
8978 
8979       return Copy;
8980     }
8981 
8982     // Create a virtual register in *TLSBaseAddrReg, and populate it by
8983     // inserting a copy instruction after I. Returns the new instruction.
8984     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8985       MachineFunction *MF = I.getParent()->getParent();
8986       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8987       const bool is64Bit = STI.is64Bit();
8988       const X86InstrInfo *TII = STI.getInstrInfo();
8989 
8990       // Create a virtual register for the TLS base address.
8991       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8992       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8993                                                       ? &X86::GR64RegClass
8994                                                       : &X86::GR32RegClass);
8995 
8996       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8997       MachineInstr *Next = I.getNextNode();
8998       MachineInstr *Copy =
8999           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
9000                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9001               .addReg(is64Bit ? X86::RAX : X86::EAX);
9002 
9003       return Copy;
9004     }
9005 
9006     StringRef getPassName() const override {
9007       return "Local Dynamic TLS Access Clean-up";
9008     }
9009 
9010     void getAnalysisUsage(AnalysisUsage &AU) const override {
9011       AU.setPreservesCFG();
9012       AU.addRequired<MachineDominatorTree>();
9013       MachineFunctionPass::getAnalysisUsage(AU);
9014     }
9015   };
9016 }
9017 
9018 char LDTLSCleanup::ID = 0;
9019 FunctionPass*
9020 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
9021 
9022 /// Constants defining how certain sequences should be outlined.
9023 ///
9024 /// \p MachineOutlinerDefault implies that the function is called with a call
9025 /// instruction, and a return must be emitted for the outlined function frame.
9026 ///
9027 /// That is,
9028 ///
9029 /// I1                                 OUTLINED_FUNCTION:
9030 /// I2 --> call OUTLINED_FUNCTION       I1
9031 /// I3                                  I2
9032 ///                                     I3
9033 ///                                     ret
9034 ///
9035 /// * Call construction overhead: 1 (call instruction)
9036 /// * Frame construction overhead: 1 (return instruction)
9037 ///
9038 /// \p MachineOutlinerTailCall implies that the function is being tail called.
9039 /// A jump is emitted instead of a call, and the return is already present in
9040 /// the outlined sequence. That is,
9041 ///
9042 /// I1                                 OUTLINED_FUNCTION:
9043 /// I2 --> jmp OUTLINED_FUNCTION       I1
9044 /// ret                                I2
9045 ///                                    ret
9046 ///
9047 /// * Call construction overhead: 1 (jump instruction)
9048 /// * Frame construction overhead: 0 (don't need to return)
9049 ///
9050 enum MachineOutlinerClass {
9051   MachineOutlinerDefault,
9052   MachineOutlinerTailCall
9053 };
9054 
9055 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
9056     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
9057   unsigned SequenceSize =
9058       std::accumulate(RepeatedSequenceLocs[0].front(),
9059                       std::next(RepeatedSequenceLocs[0].back()), 0,
9060                       [](unsigned Sum, const MachineInstr &MI) {
9061                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
9062                         // we can't tell the cost.  Just assume each instruction
9063                         // is one byte.
9064                         if (MI.isDebugInstr() || MI.isKill())
9065                           return Sum;
9066                         return Sum + 1;
9067                       });
9068 
9069   // We check to see if CFI Instructions are present, and if they are
9070   // we find the number of CFI Instructions in the candidates.
9071   unsigned CFICount = 0;
9072   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
9073   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
9074        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
9075     if (MBBI->isCFIInstruction())
9076       CFICount++;
9077     MBBI++;
9078   }
9079 
9080   // We compare the number of found CFI Instructions to  the number of CFI
9081   // instructions in the parent function for each candidate.  We must check this
9082   // since if we outline one of the CFI instructions in a function, we have to
9083   // outline them all for correctness. If we do not, the address offsets will be
9084   // incorrect between the two sections of the program.
9085   for (outliner::Candidate &C : RepeatedSequenceLocs) {
9086     std::vector<MCCFIInstruction> CFIInstructions =
9087         C.getMF()->getFrameInstructions();
9088 
9089     if (CFICount > 0 && CFICount != CFIInstructions.size())
9090       return outliner::OutlinedFunction();
9091   }
9092 
9093   // FIXME: Use real size in bytes for call and ret instructions.
9094   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
9095     for (outliner::Candidate &C : RepeatedSequenceLocs)
9096       C.setCallInfo(MachineOutlinerTailCall, 1);
9097 
9098     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
9099                                       0, // Number of bytes to emit frame.
9100                                       MachineOutlinerTailCall // Type of frame.
9101     );
9102   }
9103 
9104   if (CFICount > 0)
9105     return outliner::OutlinedFunction();
9106 
9107   for (outliner::Candidate &C : RepeatedSequenceLocs)
9108     C.setCallInfo(MachineOutlinerDefault, 1);
9109 
9110   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
9111                                     MachineOutlinerDefault);
9112 }
9113 
9114 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
9115                                            bool OutlineFromLinkOnceODRs) const {
9116   const Function &F = MF.getFunction();
9117 
9118   // Does the function use a red zone? If it does, then we can't risk messing
9119   // with the stack.
9120   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
9121     // It could have a red zone. If it does, then we don't want to touch it.
9122     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9123     if (!X86FI || X86FI->getUsesRedZone())
9124       return false;
9125   }
9126 
9127   // If we *don't* want to outline from things that could potentially be deduped
9128   // then return false.
9129   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
9130       return false;
9131 
9132   // This function is viable for outlining, so return true.
9133   return true;
9134 }
9135 
9136 outliner::InstrType
9137 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
9138   MachineInstr &MI = *MIT;
9139   // Don't allow debug values to impact outlining type.
9140   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
9141     return outliner::InstrType::Invisible;
9142 
9143   // At this point, KILL instructions don't really tell us much so we can go
9144   // ahead and skip over them.
9145   if (MI.isKill())
9146     return outliner::InstrType::Invisible;
9147 
9148   // Is this a tail call? If yes, we can outline as a tail call.
9149   if (isTailCall(MI))
9150     return outliner::InstrType::Legal;
9151 
9152   // Is this the terminator of a basic block?
9153   if (MI.isTerminator() || MI.isReturn()) {
9154 
9155     // Does its parent have any successors in its MachineFunction?
9156     if (MI.getParent()->succ_empty())
9157       return outliner::InstrType::Legal;
9158 
9159     // It does, so we can't tail call it.
9160     return outliner::InstrType::Illegal;
9161   }
9162 
9163   // Don't outline anything that modifies or reads from the stack pointer.
9164   //
9165   // FIXME: There are instructions which are being manually built without
9166   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
9167   // able to remove the extra checks once those are fixed up. For example,
9168   // sometimes we might get something like %rax = POP64r 1. This won't be
9169   // caught by modifiesRegister or readsRegister even though the instruction
9170   // really ought to be formed so that modifiesRegister/readsRegister would
9171   // catch it.
9172   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
9173       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
9174       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
9175     return outliner::InstrType::Illegal;
9176 
9177   // Outlined calls change the instruction pointer, so don't read from it.
9178   if (MI.readsRegister(X86::RIP, &RI) ||
9179       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
9180       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
9181     return outliner::InstrType::Illegal;
9182 
9183   // Positions can't safely be outlined.
9184   if (MI.isPosition())
9185     return outliner::InstrType::Illegal;
9186 
9187   // Make sure none of the operands of this instruction do anything tricky.
9188   for (const MachineOperand &MOP : MI.operands())
9189     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
9190         MOP.isTargetIndex())
9191       return outliner::InstrType::Illegal;
9192 
9193   return outliner::InstrType::Legal;
9194 }
9195 
9196 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
9197                                           MachineFunction &MF,
9198                                           const outliner::OutlinedFunction &OF)
9199                                           const {
9200   // If we're a tail call, we already have a return, so don't do anything.
9201   if (OF.FrameConstructionID == MachineOutlinerTailCall)
9202     return;
9203 
9204   // We're a normal call, so our sequence doesn't have a return instruction.
9205   // Add it in.
9206   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RET64));
9207   MBB.insert(MBB.end(), retq);
9208 }
9209 
9210 MachineBasicBlock::iterator
9211 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9212                                  MachineBasicBlock::iterator &It,
9213                                  MachineFunction &MF,
9214                                  outliner::Candidate &C) const {
9215   // Is it a tail call?
9216   if (C.CallConstructionID == MachineOutlinerTailCall) {
9217     // Yes, just insert a JMP.
9218     It = MBB.insert(It,
9219                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9220                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9221   } else {
9222     // No, insert a call.
9223     It = MBB.insert(It,
9224                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9225                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9226   }
9227 
9228   return It;
9229 }
9230 
9231 #define GET_INSTRINFO_HELPERS
9232 #include "X86GenInstrInfo.inc"
9233