1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86.h" 16 #include "X86InstrBuilder.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/LLVMContext.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineConstantPool.h" 24 #include "llvm/CodeGen/MachineDominators.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/LiveVariables.h" 29 #include "llvm/MC/MCAsmInfo.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetOptions.h" 36 #include <limits> 37 38 #define GET_INSTRINFO_CTOR 39 #include "X86GenInstrInfo.inc" 40 41 using namespace llvm; 42 43 static cl::opt<bool> 44 NoFusing("disable-spill-fusing", 45 cl::desc("Disable fusing of spill code into instructions")); 46 static cl::opt<bool> 47 PrintFailedFusing("print-failed-fuse-candidates", 48 cl::desc("Print instructions that the allocator wants to" 49 " fuse, but the X86 backend currently can't"), 50 cl::Hidden); 51 static cl::opt<bool> 52 ReMatPICStubLoad("remat-pic-stub-load", 53 cl::desc("Re-materialize load from stub in PIC mode"), 54 cl::init(false), cl::Hidden); 55 56 enum { 57 // Select which memory operand is being unfolded. 58 // (stored in bits 0 - 3) 59 TB_INDEX_0 = 0, 60 TB_INDEX_1 = 1, 61 TB_INDEX_2 = 2, 62 TB_INDEX_3 = 3, 63 TB_INDEX_MASK = 0xf, 64 65 // Do not insert the reverse map (MemOp -> RegOp) into the table. 66 // This may be needed because there is a many -> one mapping. 67 TB_NO_REVERSE = 1 << 4, 68 69 // Do not insert the forward map (RegOp -> MemOp) into the table. 70 // This is needed for Native Client, which prohibits branch 71 // instructions from using a memory operand. 72 TB_NO_FORWARD = 1 << 5, 73 74 TB_FOLDED_LOAD = 1 << 6, 75 TB_FOLDED_STORE = 1 << 7, 76 77 // Minimum alignment required for load/store. 78 // Used for RegOp->MemOp conversion. 79 // (stored in bits 8 - 15) 80 TB_ALIGN_SHIFT = 8, 81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 84 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 85 }; 86 87 struct X86OpTblEntry { 88 uint16_t RegOp; 89 uint16_t MemOp; 90 uint16_t Flags; 91 }; 92 93 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 95 ? X86::ADJCALLSTACKDOWN64 96 : X86::ADJCALLSTACKDOWN32), 97 (tm.getSubtarget<X86Subtarget>().is64Bit() 98 ? X86::ADJCALLSTACKUP64 99 : X86::ADJCALLSTACKUP32)), 100 TM(tm), RI(tm, *this) { 101 102 static const X86OpTblEntry OpTbl2Addr[] = { 103 { X86::ADC32ri, X86::ADC32mi, 0 }, 104 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 105 { X86::ADC32rr, X86::ADC32mr, 0 }, 106 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 107 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 108 { X86::ADC64rr, X86::ADC64mr, 0 }, 109 { X86::ADD16ri, X86::ADD16mi, 0 }, 110 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 113 { X86::ADD16rr, X86::ADD16mr, 0 }, 114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 115 { X86::ADD32ri, X86::ADD32mi, 0 }, 116 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 119 { X86::ADD32rr, X86::ADD32mr, 0 }, 120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 121 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 122 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 125 { X86::ADD64rr, X86::ADD64mr, 0 }, 126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 127 { X86::ADD8ri, X86::ADD8mi, 0 }, 128 { X86::ADD8rr, X86::ADD8mr, 0 }, 129 { X86::AND16ri, X86::AND16mi, 0 }, 130 { X86::AND16ri8, X86::AND16mi8, 0 }, 131 { X86::AND16rr, X86::AND16mr, 0 }, 132 { X86::AND32ri, X86::AND32mi, 0 }, 133 { X86::AND32ri8, X86::AND32mi8, 0 }, 134 { X86::AND32rr, X86::AND32mr, 0 }, 135 { X86::AND64ri32, X86::AND64mi32, 0 }, 136 { X86::AND64ri8, X86::AND64mi8, 0 }, 137 { X86::AND64rr, X86::AND64mr, 0 }, 138 { X86::AND8ri, X86::AND8mi, 0 }, 139 { X86::AND8rr, X86::AND8mr, 0 }, 140 { X86::DEC16r, X86::DEC16m, 0 }, 141 { X86::DEC32r, X86::DEC32m, 0 }, 142 { X86::DEC64_16r, X86::DEC64_16m, 0 }, 143 { X86::DEC64_32r, X86::DEC64_32m, 0 }, 144 { X86::DEC64r, X86::DEC64m, 0 }, 145 { X86::DEC8r, X86::DEC8m, 0 }, 146 { X86::INC16r, X86::INC16m, 0 }, 147 { X86::INC32r, X86::INC32m, 0 }, 148 { X86::INC64_16r, X86::INC64_16m, 0 }, 149 { X86::INC64_32r, X86::INC64_32m, 0 }, 150 { X86::INC64r, X86::INC64m, 0 }, 151 { X86::INC8r, X86::INC8m, 0 }, 152 { X86::NEG16r, X86::NEG16m, 0 }, 153 { X86::NEG32r, X86::NEG32m, 0 }, 154 { X86::NEG64r, X86::NEG64m, 0 }, 155 { X86::NEG8r, X86::NEG8m, 0 }, 156 { X86::NOT16r, X86::NOT16m, 0 }, 157 { X86::NOT32r, X86::NOT32m, 0 }, 158 { X86::NOT64r, X86::NOT64m, 0 }, 159 { X86::NOT8r, X86::NOT8m, 0 }, 160 { X86::OR16ri, X86::OR16mi, 0 }, 161 { X86::OR16ri8, X86::OR16mi8, 0 }, 162 { X86::OR16rr, X86::OR16mr, 0 }, 163 { X86::OR32ri, X86::OR32mi, 0 }, 164 { X86::OR32ri8, X86::OR32mi8, 0 }, 165 { X86::OR32rr, X86::OR32mr, 0 }, 166 { X86::OR64ri32, X86::OR64mi32, 0 }, 167 { X86::OR64ri8, X86::OR64mi8, 0 }, 168 { X86::OR64rr, X86::OR64mr, 0 }, 169 { X86::OR8ri, X86::OR8mi, 0 }, 170 { X86::OR8rr, X86::OR8mr, 0 }, 171 { X86::ROL16r1, X86::ROL16m1, 0 }, 172 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 173 { X86::ROL16ri, X86::ROL16mi, 0 }, 174 { X86::ROL32r1, X86::ROL32m1, 0 }, 175 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 176 { X86::ROL32ri, X86::ROL32mi, 0 }, 177 { X86::ROL64r1, X86::ROL64m1, 0 }, 178 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 179 { X86::ROL64ri, X86::ROL64mi, 0 }, 180 { X86::ROL8r1, X86::ROL8m1, 0 }, 181 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 182 { X86::ROL8ri, X86::ROL8mi, 0 }, 183 { X86::ROR16r1, X86::ROR16m1, 0 }, 184 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 185 { X86::ROR16ri, X86::ROR16mi, 0 }, 186 { X86::ROR32r1, X86::ROR32m1, 0 }, 187 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 188 { X86::ROR32ri, X86::ROR32mi, 0 }, 189 { X86::ROR64r1, X86::ROR64m1, 0 }, 190 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 191 { X86::ROR64ri, X86::ROR64mi, 0 }, 192 { X86::ROR8r1, X86::ROR8m1, 0 }, 193 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 194 { X86::ROR8ri, X86::ROR8mi, 0 }, 195 { X86::SAR16r1, X86::SAR16m1, 0 }, 196 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 197 { X86::SAR16ri, X86::SAR16mi, 0 }, 198 { X86::SAR32r1, X86::SAR32m1, 0 }, 199 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 200 { X86::SAR32ri, X86::SAR32mi, 0 }, 201 { X86::SAR64r1, X86::SAR64m1, 0 }, 202 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 203 { X86::SAR64ri, X86::SAR64mi, 0 }, 204 { X86::SAR8r1, X86::SAR8m1, 0 }, 205 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 206 { X86::SAR8ri, X86::SAR8mi, 0 }, 207 { X86::SBB32ri, X86::SBB32mi, 0 }, 208 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 209 { X86::SBB32rr, X86::SBB32mr, 0 }, 210 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 211 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 212 { X86::SBB64rr, X86::SBB64mr, 0 }, 213 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 214 { X86::SHL16ri, X86::SHL16mi, 0 }, 215 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 216 { X86::SHL32ri, X86::SHL32mi, 0 }, 217 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 218 { X86::SHL64ri, X86::SHL64mi, 0 }, 219 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 220 { X86::SHL8ri, X86::SHL8mi, 0 }, 221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 227 { X86::SHR16r1, X86::SHR16m1, 0 }, 228 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 229 { X86::SHR16ri, X86::SHR16mi, 0 }, 230 { X86::SHR32r1, X86::SHR32m1, 0 }, 231 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 232 { X86::SHR32ri, X86::SHR32mi, 0 }, 233 { X86::SHR64r1, X86::SHR64m1, 0 }, 234 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 235 { X86::SHR64ri, X86::SHR64mi, 0 }, 236 { X86::SHR8r1, X86::SHR8m1, 0 }, 237 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 238 { X86::SHR8ri, X86::SHR8mi, 0 }, 239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 245 { X86::SUB16ri, X86::SUB16mi, 0 }, 246 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 247 { X86::SUB16rr, X86::SUB16mr, 0 }, 248 { X86::SUB32ri, X86::SUB32mi, 0 }, 249 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 250 { X86::SUB32rr, X86::SUB32mr, 0 }, 251 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 252 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 253 { X86::SUB64rr, X86::SUB64mr, 0 }, 254 { X86::SUB8ri, X86::SUB8mi, 0 }, 255 { X86::SUB8rr, X86::SUB8mr, 0 }, 256 { X86::XOR16ri, X86::XOR16mi, 0 }, 257 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 258 { X86::XOR16rr, X86::XOR16mr, 0 }, 259 { X86::XOR32ri, X86::XOR32mi, 0 }, 260 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 261 { X86::XOR32rr, X86::XOR32mr, 0 }, 262 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 263 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 264 { X86::XOR64rr, X86::XOR64mr, 0 }, 265 { X86::XOR8ri, X86::XOR8mi, 0 }, 266 { X86::XOR8rr, X86::XOR8mr, 0 } 267 }; 268 269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 270 unsigned RegOp = OpTbl2Addr[i].RegOp; 271 unsigned MemOp = OpTbl2Addr[i].MemOp; 272 unsigned Flags = OpTbl2Addr[i].Flags; 273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 274 RegOp, MemOp, 275 // Index 0, folded load and store, no alignment requirement. 276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 277 } 278 279 static const X86OpTblEntry OpTbl0[] = { 280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 357 // AVX 128-bit versions of foldable instructions 358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 371 // AVX 256-bit foldable instructions 372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE } 378 }; 379 380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 381 unsigned RegOp = OpTbl0[i].RegOp; 382 unsigned MemOp = OpTbl0[i].MemOp; 383 unsigned Flags = OpTbl0[i].Flags; 384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 385 RegOp, MemOp, TB_INDEX_0 | Flags); 386 } 387 388 static const X86OpTblEntry OpTbl1[] = { 389 { X86::CMP16rr, X86::CMP16rm, 0 }, 390 { X86::CMP32rr, X86::CMP32rm, 0 }, 391 { X86::CMP64rr, X86::CMP64rm, 0 }, 392 { X86::CMP8rr, X86::CMP8rm, 0 }, 393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE }, 404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE }, 405 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 407 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 413 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 414 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 415 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 416 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 417 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 418 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 419 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 420 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 421 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 422 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 423 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 424 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 425 { X86::MOV16rr, X86::MOV16rm, 0 }, 426 { X86::MOV32rr, X86::MOV32rm, 0 }, 427 { X86::MOV64rr, X86::MOV64rm, 0 }, 428 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 429 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 430 { X86::MOV8rr, X86::MOV8rm, 0 }, 431 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 432 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 433 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 434 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 435 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 436 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 437 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 438 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 439 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 440 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 441 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 442 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 443 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 444 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 445 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 446 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 447 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 455 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 456 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 457 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 458 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 459 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 460 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 461 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 462 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 463 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 464 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 465 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 466 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 467 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 468 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 469 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 470 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 }, 471 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 472 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 }, 473 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 474 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 475 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 476 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 477 { X86::TEST16rr, X86::TEST16rm, 0 }, 478 { X86::TEST32rr, X86::TEST32rm, 0 }, 479 { X86::TEST64rr, X86::TEST64rm, 0 }, 480 { X86::TEST8rr, X86::TEST8rm, 0 }, 481 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 482 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 483 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 484 // AVX 128-bit versions of foldable instructions 485 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 486 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 487 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 488 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 489 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 490 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 491 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 492 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 493 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 494 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 495 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 496 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 497 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 498 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 499 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 500 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 501 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE }, 502 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE }, 503 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 504 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 505 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 506 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 507 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 508 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 509 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 510 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 511 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 512 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 513 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 }, 514 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 515 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 }, 516 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 517 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 518 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 }, 519 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 }, 520 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 }, 521 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 }, 522 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 }, 523 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 }, 524 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 }, 525 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 }, 526 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 }, 527 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 }, 528 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 }, 529 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 }, 530 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 }, 531 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 }, 532 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 }, 533 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 }, 534 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 535 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 536 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 537 538 // AVX 256-bit foldable instructions 539 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 540 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 541 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 542 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 543 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 544 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 }, 545 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 }, 546 547 // AVX2 foldable instructions 548 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 }, 549 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 }, 550 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 }, 551 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 }, 552 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 }, 553 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 }, 554 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 }, 555 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 }, 556 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 }, 557 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 }, 558 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 }, 559 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 }, 560 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 }, 561 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 }, 562 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 563 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 564 }; 565 566 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 567 unsigned RegOp = OpTbl1[i].RegOp; 568 unsigned MemOp = OpTbl1[i].MemOp; 569 unsigned Flags = OpTbl1[i].Flags; 570 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 571 RegOp, MemOp, 572 // Index 1, folded load 573 Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 574 } 575 576 static const X86OpTblEntry OpTbl2[] = { 577 { X86::ADC32rr, X86::ADC32rm, 0 }, 578 { X86::ADC64rr, X86::ADC64rm, 0 }, 579 { X86::ADD16rr, X86::ADD16rm, 0 }, 580 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 581 { X86::ADD32rr, X86::ADD32rm, 0 }, 582 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 583 { X86::ADD64rr, X86::ADD64rm, 0 }, 584 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 585 { X86::ADD8rr, X86::ADD8rm, 0 }, 586 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 587 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 588 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 589 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 590 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 591 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 592 { X86::AND16rr, X86::AND16rm, 0 }, 593 { X86::AND32rr, X86::AND32rm, 0 }, 594 { X86::AND64rr, X86::AND64rm, 0 }, 595 { X86::AND8rr, X86::AND8rm, 0 }, 596 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 597 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 598 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 599 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 600 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 601 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 602 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 603 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 604 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 605 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 606 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 607 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 608 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 609 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 610 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 611 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 612 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 613 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 614 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 615 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 616 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 617 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 618 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 619 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 620 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 621 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 622 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 623 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 624 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 625 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 626 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 627 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 628 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 629 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 630 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 631 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 632 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 633 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 634 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 635 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 636 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 637 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 638 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 639 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 640 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 641 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 642 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 643 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 644 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 645 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 646 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 647 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 648 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 649 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 650 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 651 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 652 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 653 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 654 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 655 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 656 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 657 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 658 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 659 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 660 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 661 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 662 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 663 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 664 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 665 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 666 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 667 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 668 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 669 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 670 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 671 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 672 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 673 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 674 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 675 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 676 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 677 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 678 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 679 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 680 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 681 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 682 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 683 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 684 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 }, 685 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 686 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 }, 687 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 688 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 689 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 690 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 691 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 692 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 }, 693 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 694 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 }, 695 { X86::MINSDrr, X86::MINSDrm, 0 }, 696 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 697 { X86::MINSSrr, X86::MINSSrm, 0 }, 698 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 699 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 700 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 701 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 702 { X86::MULSDrr, X86::MULSDrm, 0 }, 703 { X86::MULSSrr, X86::MULSSrm, 0 }, 704 { X86::OR16rr, X86::OR16rm, 0 }, 705 { X86::OR32rr, X86::OR32rm, 0 }, 706 { X86::OR64rr, X86::OR64rm, 0 }, 707 { X86::OR8rr, X86::OR8rm, 0 }, 708 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 709 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 710 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 711 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 712 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 713 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 714 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 715 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 716 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 717 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 718 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 719 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 720 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 721 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 722 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 723 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 724 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 725 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 726 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 727 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 728 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 729 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 730 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 731 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 732 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 733 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 734 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 735 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 736 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 737 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 738 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 739 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 740 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 741 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 742 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 743 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 744 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 745 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 746 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 747 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 748 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 749 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 750 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 751 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 752 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 753 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 754 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 755 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 756 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 757 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 758 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 759 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 760 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 761 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 762 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 763 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 764 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 765 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 766 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 767 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 768 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 769 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 770 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 771 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 772 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 773 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 774 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 775 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 776 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 777 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 778 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 779 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 780 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 781 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 782 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 783 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 784 { X86::SBB32rr, X86::SBB32rm, 0 }, 785 { X86::SBB64rr, X86::SBB64rm, 0 }, 786 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 787 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 788 { X86::SUB16rr, X86::SUB16rm, 0 }, 789 { X86::SUB32rr, X86::SUB32rm, 0 }, 790 { X86::SUB64rr, X86::SUB64rm, 0 }, 791 { X86::SUB8rr, X86::SUB8rm, 0 }, 792 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 793 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 794 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 795 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 796 // FIXME: TEST*rr -> swapped operand of TEST*mr. 797 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 798 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 799 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 800 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 801 { X86::XOR16rr, X86::XOR16rm, 0 }, 802 { X86::XOR32rr, X86::XOR32rm, 0 }, 803 { X86::XOR64rr, X86::XOR64rm, 0 }, 804 { X86::XOR8rr, X86::XOR8rm, 0 }, 805 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 806 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 807 // AVX 128-bit versions of foldable instructions 808 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 809 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 810 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 811 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 812 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 813 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 814 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 815 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 816 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 817 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 818 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 819 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 820 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, TB_ALIGN_16 }, 821 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 }, 822 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 823 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 824 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 825 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 }, 826 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 }, 827 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 828 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 829 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 }, 830 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 }, 831 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 }, 832 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 }, 833 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 }, 834 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 }, 835 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 }, 836 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 }, 837 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 }, 838 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 }, 839 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 }, 840 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 }, 841 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 842 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 843 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 }, 844 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 }, 845 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 846 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 847 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 848 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 849 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 850 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 851 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 852 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 853 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 854 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 855 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 }, 856 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 }, 857 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 }, 858 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 }, 859 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 860 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 861 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 }, 862 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 }, 863 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 }, 864 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 }, 865 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 866 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 }, 867 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 868 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 }, 869 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 }, 870 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 }, 871 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 }, 872 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 }, 873 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 874 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 }, 875 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 876 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 }, 877 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 }, 878 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 }, 879 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 }, 880 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 881 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 882 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 }, 883 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 }, 884 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 }, 885 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 }, 886 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 }, 887 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 }, 888 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 }, 889 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 }, 890 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 }, 891 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 }, 892 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 }, 893 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 }, 894 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 }, 895 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 }, 896 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 }, 897 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 }, 898 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 }, 899 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 }, 900 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 }, 901 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 }, 902 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 }, 903 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 }, 904 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 }, 905 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 }, 906 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 }, 907 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 }, 908 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 }, 909 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 }, 910 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 }, 911 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 }, 912 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 }, 913 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 }, 914 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 }, 915 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 }, 916 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 }, 917 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 }, 918 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 }, 919 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 }, 920 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 }, 921 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 }, 922 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 }, 923 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 }, 924 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 }, 925 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 }, 926 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 }, 927 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 }, 928 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 }, 929 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 }, 930 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 }, 931 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 }, 932 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 }, 933 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 }, 934 { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 }, 935 { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 }, 936 { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 }, 937 { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 }, 938 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 }, 939 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 }, 940 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 }, 941 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 }, 942 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 }, 943 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 }, 944 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 }, 945 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 }, 946 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 }, 947 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 }, 948 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 }, 949 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 }, 950 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 }, 951 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 }, 952 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 }, 953 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 }, 954 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 }, 955 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 }, 956 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 }, 957 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 }, 958 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 }, 959 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 }, 960 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 }, 961 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 }, 962 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 }, 963 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 }, 964 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 965 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 966 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 }, 967 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 }, 968 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 }, 969 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 }, 970 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 }, 971 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 }, 972 // AVX 256-bit foldable instructions 973 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 }, 974 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 }, 975 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 }, 976 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 }, 977 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 }, 978 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 }, 979 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 }, 980 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 }, 981 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 }, 982 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 }, 983 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 }, 984 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 }, 985 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 }, 986 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 }, 987 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 }, 988 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 }, 989 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 }, 990 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 }, 991 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 }, 992 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 }, 993 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 }, 994 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 }, 995 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 }, 996 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 }, 997 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 }, 998 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 }, 999 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 }, 1000 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 }, 1001 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 }, 1002 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 }, 1003 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 }, 1004 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 }, 1005 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 }, 1006 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 }, 1007 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 }, 1008 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 }, 1009 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 }, 1010 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 }, 1011 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 }, 1012 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 }, 1013 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 }, 1014 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 }, 1015 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 }, 1016 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 }, 1017 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 }, 1018 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 }, 1019 // AVX2 foldable instructions 1020 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 }, 1021 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 }, 1022 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 }, 1023 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 }, 1024 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 }, 1025 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 }, 1026 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 }, 1027 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 }, 1028 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 }, 1029 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 }, 1030 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 }, 1031 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 }, 1032 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 }, 1033 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 }, 1034 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 }, 1035 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 }, 1036 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 }, 1037 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 }, 1038 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 }, 1039 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 }, 1040 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 }, 1041 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 }, 1042 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 }, 1043 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 }, 1044 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 }, 1045 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 }, 1046 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 }, 1047 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 }, 1048 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 }, 1049 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 }, 1050 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 }, 1051 { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 }, 1052 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 }, 1053 { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 }, 1054 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 }, 1055 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 }, 1056 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 }, 1057 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 }, 1058 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 }, 1059 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 }, 1060 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 }, 1061 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 }, 1062 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 }, 1063 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 }, 1064 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 }, 1065 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 }, 1066 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 }, 1067 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 }, 1068 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 }, 1069 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 }, 1070 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 }, 1071 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 }, 1072 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 }, 1073 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 }, 1074 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 }, 1075 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 }, 1076 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 }, 1077 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 }, 1078 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 }, 1079 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 }, 1080 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 }, 1081 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 }, 1082 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 }, 1083 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 }, 1084 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 }, 1085 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 }, 1086 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 }, 1087 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 }, 1088 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 }, 1089 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 }, 1090 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 }, 1091 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 }, 1092 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 }, 1093 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 }, 1094 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 }, 1095 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 }, 1096 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 }, 1097 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 }, 1098 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 }, 1099 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 }, 1100 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 }, 1101 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 }, 1102 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 }, 1103 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 }, 1104 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 }, 1105 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 }, 1106 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 }, 1107 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 }, 1108 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 }, 1109 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 }, 1110 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 }, 1111 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 }, 1112 // FIXME: add AVX 256-bit foldable instructions 1113 }; 1114 1115 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1116 unsigned RegOp = OpTbl2[i].RegOp; 1117 unsigned MemOp = OpTbl2[i].MemOp; 1118 unsigned Flags = OpTbl2[i].Flags; 1119 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1120 RegOp, MemOp, 1121 // Index 2, folded load 1122 Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1123 } 1124 1125 static const X86OpTblEntry OpTbl3[] = { 1126 // FMA foldable instructions 1127 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 }, 1128 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 }, 1129 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 }, 1130 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 }, 1131 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 }, 1132 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 }, 1133 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 }, 1134 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 }, 1135 1136 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 }, 1137 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 }, 1138 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 }, 1139 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 }, 1140 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 }, 1141 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 }, 1142 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 }, 1143 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 }, 1144 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 }, 1145 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 }, 1146 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 }, 1147 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 }, 1148 1149 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 }, 1150 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 }, 1151 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 }, 1152 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 }, 1153 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 }, 1154 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 }, 1155 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 }, 1156 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 }, 1157 1158 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 }, 1159 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 }, 1160 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 }, 1161 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 }, 1162 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 }, 1163 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 }, 1164 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 }, 1165 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 }, 1166 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 }, 1167 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 }, 1168 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 }, 1169 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 }, 1170 1171 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 }, 1172 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 }, 1173 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 }, 1174 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 }, 1175 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 }, 1176 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 }, 1177 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 }, 1178 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 }, 1179 1180 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 }, 1181 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 }, 1182 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 }, 1183 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 }, 1184 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 }, 1185 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 }, 1186 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 }, 1187 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 }, 1188 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 }, 1189 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 }, 1190 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 }, 1191 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 }, 1192 1193 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 }, 1194 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 }, 1195 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 }, 1196 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 }, 1197 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 }, 1198 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 }, 1199 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 }, 1200 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 }, 1201 1202 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 }, 1203 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 }, 1204 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 }, 1205 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 }, 1206 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 }, 1207 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 }, 1208 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 }, 1209 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 }, 1210 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 }, 1211 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 }, 1212 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 }, 1213 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 }, 1214 1215 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 }, 1216 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 }, 1217 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 }, 1218 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 }, 1219 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 }, 1220 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 }, 1221 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 }, 1222 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 }, 1223 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 }, 1224 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 }, 1225 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 }, 1226 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 }, 1227 1228 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 }, 1229 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 }, 1230 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 }, 1231 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 }, 1232 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 }, 1233 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 }, 1234 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 }, 1235 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 }, 1236 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 }, 1237 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 }, 1238 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 }, 1239 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 }, 1240 }; 1241 1242 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1243 unsigned RegOp = OpTbl3[i].RegOp; 1244 unsigned MemOp = OpTbl3[i].MemOp; 1245 unsigned Flags = OpTbl3[i].Flags; 1246 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1247 RegOp, MemOp, 1248 // Index 3, folded load 1249 Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1250 } 1251 1252 } 1253 1254 void 1255 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1256 MemOp2RegOpTableType &M2RTable, 1257 unsigned RegOp, unsigned MemOp, unsigned Flags) { 1258 if ((Flags & TB_NO_FORWARD) == 0) { 1259 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1260 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1261 } 1262 if ((Flags & TB_NO_REVERSE) == 0) { 1263 assert(!M2RTable.count(MemOp) && 1264 "Duplicated entries in unfolding maps?"); 1265 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1266 } 1267 } 1268 1269 bool 1270 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1271 unsigned &SrcReg, unsigned &DstReg, 1272 unsigned &SubIdx) const { 1273 switch (MI.getOpcode()) { 1274 default: break; 1275 case X86::MOVSX16rr8: 1276 case X86::MOVZX16rr8: 1277 case X86::MOVSX32rr8: 1278 case X86::MOVZX32rr8: 1279 case X86::MOVSX64rr8: 1280 case X86::MOVZX64rr8: 1281 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1282 // It's not always legal to reference the low 8-bit of the larger 1283 // register in 32-bit mode. 1284 return false; 1285 case X86::MOVSX32rr16: 1286 case X86::MOVZX32rr16: 1287 case X86::MOVSX64rr16: 1288 case X86::MOVZX64rr16: 1289 case X86::MOVSX64rr32: 1290 case X86::MOVZX64rr32: { 1291 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1292 // Be conservative. 1293 return false; 1294 SrcReg = MI.getOperand(1).getReg(); 1295 DstReg = MI.getOperand(0).getReg(); 1296 switch (MI.getOpcode()) { 1297 default: llvm_unreachable("Unreachable!"); 1298 case X86::MOVSX16rr8: 1299 case X86::MOVZX16rr8: 1300 case X86::MOVSX32rr8: 1301 case X86::MOVZX32rr8: 1302 case X86::MOVSX64rr8: 1303 case X86::MOVZX64rr8: 1304 SubIdx = X86::sub_8bit; 1305 break; 1306 case X86::MOVSX32rr16: 1307 case X86::MOVZX32rr16: 1308 case X86::MOVSX64rr16: 1309 case X86::MOVZX64rr16: 1310 SubIdx = X86::sub_16bit; 1311 break; 1312 case X86::MOVSX64rr32: 1313 case X86::MOVZX64rr32: 1314 SubIdx = X86::sub_32bit; 1315 break; 1316 } 1317 return true; 1318 } 1319 } 1320 return false; 1321 } 1322 1323 /// isFrameOperand - Return true and the FrameIndex if the specified 1324 /// operand and follow operands form a reference to the stack frame. 1325 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1326 int &FrameIndex) const { 1327 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 1328 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 1329 MI->getOperand(Op+1).getImm() == 1 && 1330 MI->getOperand(Op+2).getReg() == 0 && 1331 MI->getOperand(Op+3).getImm() == 0) { 1332 FrameIndex = MI->getOperand(Op).getIndex(); 1333 return true; 1334 } 1335 return false; 1336 } 1337 1338 static bool isFrameLoadOpcode(int Opcode) { 1339 switch (Opcode) { 1340 default: 1341 return false; 1342 case X86::MOV8rm: 1343 case X86::MOV16rm: 1344 case X86::MOV32rm: 1345 case X86::MOV64rm: 1346 case X86::LD_Fp64m: 1347 case X86::MOVSSrm: 1348 case X86::MOVSDrm: 1349 case X86::MOVAPSrm: 1350 case X86::MOVAPDrm: 1351 case X86::MOVDQArm: 1352 case X86::VMOVSSrm: 1353 case X86::VMOVSDrm: 1354 case X86::VMOVAPSrm: 1355 case X86::VMOVAPDrm: 1356 case X86::VMOVDQArm: 1357 case X86::VMOVAPSYrm: 1358 case X86::VMOVAPDYrm: 1359 case X86::VMOVDQAYrm: 1360 case X86::MMX_MOVD64rm: 1361 case X86::MMX_MOVQ64rm: 1362 return true; 1363 } 1364 } 1365 1366 static bool isFrameStoreOpcode(int Opcode) { 1367 switch (Opcode) { 1368 default: break; 1369 case X86::MOV8mr: 1370 case X86::MOV16mr: 1371 case X86::MOV32mr: 1372 case X86::MOV64mr: 1373 case X86::ST_FpP64m: 1374 case X86::MOVSSmr: 1375 case X86::MOVSDmr: 1376 case X86::MOVAPSmr: 1377 case X86::MOVAPDmr: 1378 case X86::MOVDQAmr: 1379 case X86::VMOVSSmr: 1380 case X86::VMOVSDmr: 1381 case X86::VMOVAPSmr: 1382 case X86::VMOVAPDmr: 1383 case X86::VMOVDQAmr: 1384 case X86::VMOVAPSYmr: 1385 case X86::VMOVAPDYmr: 1386 case X86::VMOVDQAYmr: 1387 case X86::MMX_MOVD64mr: 1388 case X86::MMX_MOVQ64mr: 1389 case X86::MMX_MOVNTQmr: 1390 return true; 1391 } 1392 return false; 1393 } 1394 1395 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1396 int &FrameIndex) const { 1397 if (isFrameLoadOpcode(MI->getOpcode())) 1398 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1399 return MI->getOperand(0).getReg(); 1400 return 0; 1401 } 1402 1403 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1404 int &FrameIndex) const { 1405 if (isFrameLoadOpcode(MI->getOpcode())) { 1406 unsigned Reg; 1407 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1408 return Reg; 1409 // Check for post-frame index elimination operations 1410 const MachineMemOperand *Dummy; 1411 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1412 } 1413 return 0; 1414 } 1415 1416 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1417 int &FrameIndex) const { 1418 if (isFrameStoreOpcode(MI->getOpcode())) 1419 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1420 isFrameOperand(MI, 0, FrameIndex)) 1421 return MI->getOperand(X86::AddrNumOperands).getReg(); 1422 return 0; 1423 } 1424 1425 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1426 int &FrameIndex) const { 1427 if (isFrameStoreOpcode(MI->getOpcode())) { 1428 unsigned Reg; 1429 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1430 return Reg; 1431 // Check for post-frame index elimination operations 1432 const MachineMemOperand *Dummy; 1433 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1434 } 1435 return 0; 1436 } 1437 1438 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1439 /// X86::MOVPC32r. 1440 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1441 // Don't waste compile time scanning use-def chains of physregs. 1442 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1443 return false; 1444 bool isPICBase = false; 1445 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1446 E = MRI.def_end(); I != E; ++I) { 1447 MachineInstr *DefMI = I.getOperand().getParent(); 1448 if (DefMI->getOpcode() != X86::MOVPC32r) 1449 return false; 1450 assert(!isPICBase && "More than one PIC base?"); 1451 isPICBase = true; 1452 } 1453 return isPICBase; 1454 } 1455 1456 bool 1457 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1458 AliasAnalysis *AA) const { 1459 switch (MI->getOpcode()) { 1460 default: break; 1461 case X86::MOV8rm: 1462 case X86::MOV16rm: 1463 case X86::MOV32rm: 1464 case X86::MOV64rm: 1465 case X86::LD_Fp64m: 1466 case X86::MOVSSrm: 1467 case X86::MOVSDrm: 1468 case X86::MOVAPSrm: 1469 case X86::MOVUPSrm: 1470 case X86::MOVAPDrm: 1471 case X86::MOVDQArm: 1472 case X86::VMOVSSrm: 1473 case X86::VMOVSDrm: 1474 case X86::VMOVAPSrm: 1475 case X86::VMOVUPSrm: 1476 case X86::VMOVAPDrm: 1477 case X86::VMOVDQArm: 1478 case X86::VMOVAPSYrm: 1479 case X86::VMOVUPSYrm: 1480 case X86::VMOVAPDYrm: 1481 case X86::VMOVDQAYrm: 1482 case X86::MMX_MOVD64rm: 1483 case X86::MMX_MOVQ64rm: 1484 case X86::FsVMOVAPSrm: 1485 case X86::FsVMOVAPDrm: 1486 case X86::FsMOVAPSrm: 1487 case X86::FsMOVAPDrm: { 1488 // Loads from constant pools are trivially rematerializable. 1489 if (MI->getOperand(1).isReg() && 1490 MI->getOperand(2).isImm() && 1491 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1492 MI->isInvariantLoad(AA)) { 1493 unsigned BaseReg = MI->getOperand(1).getReg(); 1494 if (BaseReg == 0 || BaseReg == X86::RIP) 1495 return true; 1496 // Allow re-materialization of PIC load. 1497 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 1498 return false; 1499 const MachineFunction &MF = *MI->getParent()->getParent(); 1500 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1501 return regIsPICBase(BaseReg, MRI); 1502 } 1503 return false; 1504 } 1505 1506 case X86::LEA32r: 1507 case X86::LEA64r: { 1508 if (MI->getOperand(2).isImm() && 1509 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1510 !MI->getOperand(4).isReg()) { 1511 // lea fi#, lea GV, etc. are all rematerializable. 1512 if (!MI->getOperand(1).isReg()) 1513 return true; 1514 unsigned BaseReg = MI->getOperand(1).getReg(); 1515 if (BaseReg == 0) 1516 return true; 1517 // Allow re-materialization of lea PICBase + x. 1518 const MachineFunction &MF = *MI->getParent()->getParent(); 1519 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1520 return regIsPICBase(BaseReg, MRI); 1521 } 1522 return false; 1523 } 1524 } 1525 1526 // All other instructions marked M_REMATERIALIZABLE are always trivially 1527 // rematerializable. 1528 return true; 1529 } 1530 1531 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 1532 /// would clobber the EFLAGS condition register. Note the result may be 1533 /// conservative. If it cannot definitely determine the safety after visiting 1534 /// a few instructions in each direction it assumes it's not safe. 1535 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1536 MachineBasicBlock::iterator I) { 1537 MachineBasicBlock::iterator E = MBB.end(); 1538 1539 // For compile time consideration, if we are not able to determine the 1540 // safety after visiting 4 instructions in each direction, we will assume 1541 // it's not safe. 1542 MachineBasicBlock::iterator Iter = I; 1543 for (unsigned i = 0; Iter != E && i < 4; ++i) { 1544 bool SeenDef = false; 1545 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1546 MachineOperand &MO = Iter->getOperand(j); 1547 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1548 SeenDef = true; 1549 if (!MO.isReg()) 1550 continue; 1551 if (MO.getReg() == X86::EFLAGS) { 1552 if (MO.isUse()) 1553 return false; 1554 SeenDef = true; 1555 } 1556 } 1557 1558 if (SeenDef) 1559 // This instruction defines EFLAGS, no need to look any further. 1560 return true; 1561 ++Iter; 1562 // Skip over DBG_VALUE. 1563 while (Iter != E && Iter->isDebugValue()) 1564 ++Iter; 1565 } 1566 1567 // It is safe to clobber EFLAGS at the end of a block of no successor has it 1568 // live in. 1569 if (Iter == E) { 1570 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1571 SE = MBB.succ_end(); SI != SE; ++SI) 1572 if ((*SI)->isLiveIn(X86::EFLAGS)) 1573 return false; 1574 return true; 1575 } 1576 1577 MachineBasicBlock::iterator B = MBB.begin(); 1578 Iter = I; 1579 for (unsigned i = 0; i < 4; ++i) { 1580 // If we make it to the beginning of the block, it's safe to clobber 1581 // EFLAGS iff EFLAGS is not live-in. 1582 if (Iter == B) 1583 return !MBB.isLiveIn(X86::EFLAGS); 1584 1585 --Iter; 1586 // Skip over DBG_VALUE. 1587 while (Iter != B && Iter->isDebugValue()) 1588 --Iter; 1589 1590 bool SawKill = false; 1591 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1592 MachineOperand &MO = Iter->getOperand(j); 1593 // A register mask may clobber EFLAGS, but we should still look for a 1594 // live EFLAGS def. 1595 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1596 SawKill = true; 1597 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1598 if (MO.isDef()) return MO.isDead(); 1599 if (MO.isKill()) SawKill = true; 1600 } 1601 } 1602 1603 if (SawKill) 1604 // This instruction kills EFLAGS and doesn't redefine it, so 1605 // there's no need to look further. 1606 return true; 1607 } 1608 1609 // Conservative answer. 1610 return false; 1611 } 1612 1613 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1614 MachineBasicBlock::iterator I, 1615 unsigned DestReg, unsigned SubIdx, 1616 const MachineInstr *Orig, 1617 const TargetRegisterInfo &TRI) const { 1618 DebugLoc DL = Orig->getDebugLoc(); 1619 1620 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1621 // Re-materialize them as movri instructions to avoid side effects. 1622 bool Clone = true; 1623 unsigned Opc = Orig->getOpcode(); 1624 switch (Opc) { 1625 default: break; 1626 case X86::MOV8r0: 1627 case X86::MOV16r0: 1628 case X86::MOV32r0: 1629 case X86::MOV64r0: { 1630 if (!isSafeToClobberEFLAGS(MBB, I)) { 1631 switch (Opc) { 1632 default: llvm_unreachable("Unreachable!"); 1633 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1634 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1635 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1636 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1637 } 1638 Clone = false; 1639 } 1640 break; 1641 } 1642 } 1643 1644 if (Clone) { 1645 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1646 MBB.insert(I, MI); 1647 } else { 1648 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1649 } 1650 1651 MachineInstr *NewMI = prior(I); 1652 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1653 } 1654 1655 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1656 /// is not marked dead. 1657 static bool hasLiveCondCodeDef(MachineInstr *MI) { 1658 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1659 MachineOperand &MO = MI->getOperand(i); 1660 if (MO.isReg() && MO.isDef() && 1661 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1662 return true; 1663 } 1664 } 1665 return false; 1666 } 1667 1668 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1669 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1670 /// to a 32-bit superregister and then truncating back down to a 16-bit 1671 /// subregister. 1672 MachineInstr * 1673 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1674 MachineFunction::iterator &MFI, 1675 MachineBasicBlock::iterator &MBBI, 1676 LiveVariables *LV) const { 1677 MachineInstr *MI = MBBI; 1678 unsigned Dest = MI->getOperand(0).getReg(); 1679 unsigned Src = MI->getOperand(1).getReg(); 1680 bool isDead = MI->getOperand(0).isDead(); 1681 bool isKill = MI->getOperand(1).isKill(); 1682 1683 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1684 ? X86::LEA64_32r : X86::LEA32r; 1685 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1686 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1687 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1688 1689 // Build and insert into an implicit UNDEF value. This is OK because 1690 // well be shifting and then extracting the lower 16-bits. 1691 // This has the potential to cause partial register stall. e.g. 1692 // movw (%rbp,%rcx,2), %dx 1693 // leal -65(%rdx), %esi 1694 // But testing has shown this *does* help performance in 64-bit mode (at 1695 // least on modern x86 machines). 1696 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1697 MachineInstr *InsMI = 1698 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1699 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1700 .addReg(Src, getKillRegState(isKill)); 1701 1702 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1703 get(Opc), leaOutReg); 1704 switch (MIOpc) { 1705 default: llvm_unreachable("Unreachable!"); 1706 case X86::SHL16ri: { 1707 unsigned ShAmt = MI->getOperand(2).getImm(); 1708 MIB.addReg(0).addImm(1 << ShAmt) 1709 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1710 break; 1711 } 1712 case X86::INC16r: 1713 case X86::INC64_16r: 1714 addRegOffset(MIB, leaInReg, true, 1); 1715 break; 1716 case X86::DEC16r: 1717 case X86::DEC64_16r: 1718 addRegOffset(MIB, leaInReg, true, -1); 1719 break; 1720 case X86::ADD16ri: 1721 case X86::ADD16ri8: 1722 case X86::ADD16ri_DB: 1723 case X86::ADD16ri8_DB: 1724 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1725 break; 1726 case X86::ADD16rr: 1727 case X86::ADD16rr_DB: { 1728 unsigned Src2 = MI->getOperand(2).getReg(); 1729 bool isKill2 = MI->getOperand(2).isKill(); 1730 unsigned leaInReg2 = 0; 1731 MachineInstr *InsMI2 = 0; 1732 if (Src == Src2) { 1733 // ADD16rr %reg1028<kill>, %reg1028 1734 // just a single insert_subreg. 1735 addRegReg(MIB, leaInReg, true, leaInReg, false); 1736 } else { 1737 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1738 // Build and insert into an implicit UNDEF value. This is OK because 1739 // well be shifting and then extracting the lower 16-bits. 1740 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1741 InsMI2 = 1742 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1743 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1744 .addReg(Src2, getKillRegState(isKill2)); 1745 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1746 } 1747 if (LV && isKill2 && InsMI2) 1748 LV->replaceKillInstruction(Src2, MI, InsMI2); 1749 break; 1750 } 1751 } 1752 1753 MachineInstr *NewMI = MIB; 1754 MachineInstr *ExtMI = 1755 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1756 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1757 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1758 1759 if (LV) { 1760 // Update live variables 1761 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1762 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1763 if (isKill) 1764 LV->replaceKillInstruction(Src, MI, InsMI); 1765 if (isDead) 1766 LV->replaceKillInstruction(Dest, MI, ExtMI); 1767 } 1768 1769 return ExtMI; 1770 } 1771 1772 /// convertToThreeAddress - This method must be implemented by targets that 1773 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1774 /// may be able to convert a two-address instruction into a true 1775 /// three-address instruction on demand. This allows the X86 target (for 1776 /// example) to convert ADD and SHL instructions into LEA instructions if they 1777 /// would require register copies due to two-addressness. 1778 /// 1779 /// This method returns a null pointer if the transformation cannot be 1780 /// performed, otherwise it returns the new instruction. 1781 /// 1782 MachineInstr * 1783 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1784 MachineBasicBlock::iterator &MBBI, 1785 LiveVariables *LV) const { 1786 MachineInstr *MI = MBBI; 1787 MachineFunction &MF = *MI->getParent()->getParent(); 1788 // All instructions input are two-addr instructions. Get the known operands. 1789 unsigned Dest = MI->getOperand(0).getReg(); 1790 unsigned Src = MI->getOperand(1).getReg(); 1791 bool isDead = MI->getOperand(0).isDead(); 1792 bool isKill = MI->getOperand(1).isKill(); 1793 1794 MachineInstr *NewMI = NULL; 1795 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1796 // we have better subtarget support, enable the 16-bit LEA generation here. 1797 // 16-bit LEA is also slow on Core2. 1798 bool DisableLEA16 = true; 1799 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1800 1801 unsigned MIOpc = MI->getOpcode(); 1802 switch (MIOpc) { 1803 case X86::SHUFPSrri: { 1804 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1805 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1806 1807 unsigned B = MI->getOperand(1).getReg(); 1808 unsigned C = MI->getOperand(2).getReg(); 1809 if (B != C) return 0; 1810 unsigned A = MI->getOperand(0).getReg(); 1811 unsigned M = MI->getOperand(3).getImm(); 1812 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1813 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1814 .addReg(B, getKillRegState(isKill)).addImm(M); 1815 break; 1816 } 1817 case X86::SHUFPDrri: { 1818 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 1819 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1820 1821 unsigned B = MI->getOperand(1).getReg(); 1822 unsigned C = MI->getOperand(2).getReg(); 1823 if (B != C) return 0; 1824 unsigned A = MI->getOperand(0).getReg(); 1825 unsigned M = MI->getOperand(3).getImm(); 1826 1827 // Convert to PSHUFD mask. 1828 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 1829 1830 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1831 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1832 .addReg(B, getKillRegState(isKill)).addImm(M); 1833 break; 1834 } 1835 case X86::SHL64ri: { 1836 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1837 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1838 // the flags produced by a shift yet, so this is safe. 1839 unsigned ShAmt = MI->getOperand(2).getImm(); 1840 if (ShAmt == 0 || ShAmt >= 4) return 0; 1841 1842 // LEA can't handle RSP. 1843 if (TargetRegisterInfo::isVirtualRegister(Src) && 1844 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass)) 1845 return 0; 1846 1847 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1848 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1849 .addReg(0).addImm(1 << ShAmt) 1850 .addReg(Src, getKillRegState(isKill)) 1851 .addImm(0).addReg(0); 1852 break; 1853 } 1854 case X86::SHL32ri: { 1855 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1856 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1857 // the flags produced by a shift yet, so this is safe. 1858 unsigned ShAmt = MI->getOperand(2).getImm(); 1859 if (ShAmt == 0 || ShAmt >= 4) return 0; 1860 1861 // LEA can't handle ESP. 1862 if (TargetRegisterInfo::isVirtualRegister(Src) && 1863 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass)) 1864 return 0; 1865 1866 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1867 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1868 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1869 .addReg(0).addImm(1 << ShAmt) 1870 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0); 1871 break; 1872 } 1873 case X86::SHL16ri: { 1874 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1875 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1876 // the flags produced by a shift yet, so this is safe. 1877 unsigned ShAmt = MI->getOperand(2).getImm(); 1878 if (ShAmt == 0 || ShAmt >= 4) return 0; 1879 1880 if (DisableLEA16) 1881 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1882 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1883 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1884 .addReg(0).addImm(1 << ShAmt) 1885 .addReg(Src, getKillRegState(isKill)) 1886 .addImm(0).addReg(0); 1887 break; 1888 } 1889 default: { 1890 // The following opcodes also sets the condition code register(s). Only 1891 // convert them to equivalent lea if the condition code register def's 1892 // are dead! 1893 if (hasLiveCondCodeDef(MI)) 1894 return 0; 1895 1896 switch (MIOpc) { 1897 default: return 0; 1898 case X86::INC64r: 1899 case X86::INC32r: 1900 case X86::INC64_32r: { 1901 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1902 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1903 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1904 const TargetRegisterClass *RC = MIOpc == X86::INC64r ? 1905 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 1906 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 1907 1908 // LEA can't handle RSP. 1909 if (TargetRegisterInfo::isVirtualRegister(Src) && 1910 !MF.getRegInfo().constrainRegClass(Src, RC)) 1911 return 0; 1912 1913 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1914 .addReg(Dest, RegState::Define | 1915 getDeadRegState(isDead)), 1916 Src, isKill, 1); 1917 break; 1918 } 1919 case X86::INC16r: 1920 case X86::INC64_16r: 1921 if (DisableLEA16) 1922 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1923 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1924 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1925 .addReg(Dest, RegState::Define | 1926 getDeadRegState(isDead)), 1927 Src, isKill, 1); 1928 break; 1929 case X86::DEC64r: 1930 case X86::DEC32r: 1931 case X86::DEC64_32r: { 1932 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1933 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1934 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1935 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ? 1936 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 1937 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 1938 // LEA can't handle RSP. 1939 if (TargetRegisterInfo::isVirtualRegister(Src) && 1940 !MF.getRegInfo().constrainRegClass(Src, RC)) 1941 return 0; 1942 1943 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1944 .addReg(Dest, RegState::Define | 1945 getDeadRegState(isDead)), 1946 Src, isKill, -1); 1947 break; 1948 } 1949 case X86::DEC16r: 1950 case X86::DEC64_16r: 1951 if (DisableLEA16) 1952 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1953 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1954 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1955 .addReg(Dest, RegState::Define | 1956 getDeadRegState(isDead)), 1957 Src, isKill, -1); 1958 break; 1959 case X86::ADD64rr: 1960 case X86::ADD64rr_DB: 1961 case X86::ADD32rr: 1962 case X86::ADD32rr_DB: { 1963 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1964 unsigned Opc; 1965 const TargetRegisterClass *RC; 1966 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) { 1967 Opc = X86::LEA64r; 1968 RC = &X86::GR64_NOSPRegClass; 1969 } else { 1970 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1971 RC = &X86::GR32_NOSPRegClass; 1972 } 1973 1974 1975 unsigned Src2 = MI->getOperand(2).getReg(); 1976 bool isKill2 = MI->getOperand(2).isKill(); 1977 1978 // LEA can't handle RSP. 1979 if (TargetRegisterInfo::isVirtualRegister(Src2) && 1980 !MF.getRegInfo().constrainRegClass(Src2, RC)) 1981 return 0; 1982 1983 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1984 .addReg(Dest, RegState::Define | 1985 getDeadRegState(isDead)), 1986 Src, isKill, Src2, isKill2); 1987 1988 // Preserve undefness of the operands. 1989 bool isUndef = MI->getOperand(1).isUndef(); 1990 bool isUndef2 = MI->getOperand(2).isUndef(); 1991 NewMI->getOperand(1).setIsUndef(isUndef); 1992 NewMI->getOperand(3).setIsUndef(isUndef2); 1993 1994 if (LV && isKill2) 1995 LV->replaceKillInstruction(Src2, MI, NewMI); 1996 break; 1997 } 1998 case X86::ADD16rr: 1999 case X86::ADD16rr_DB: { 2000 if (DisableLEA16) 2001 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2002 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2003 unsigned Src2 = MI->getOperand(2).getReg(); 2004 bool isKill2 = MI->getOperand(2).isKill(); 2005 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2006 .addReg(Dest, RegState::Define | 2007 getDeadRegState(isDead)), 2008 Src, isKill, Src2, isKill2); 2009 if (LV && isKill2) 2010 LV->replaceKillInstruction(Src2, MI, NewMI); 2011 break; 2012 } 2013 case X86::ADD64ri32: 2014 case X86::ADD64ri8: 2015 case X86::ADD64ri32_DB: 2016 case X86::ADD64ri8_DB: 2017 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2018 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2019 .addReg(Dest, RegState::Define | 2020 getDeadRegState(isDead)), 2021 Src, isKill, MI->getOperand(2).getImm()); 2022 break; 2023 case X86::ADD32ri: 2024 case X86::ADD32ri8: 2025 case X86::ADD32ri_DB: 2026 case X86::ADD32ri8_DB: { 2027 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2028 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2029 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2030 .addReg(Dest, RegState::Define | 2031 getDeadRegState(isDead)), 2032 Src, isKill, MI->getOperand(2).getImm()); 2033 break; 2034 } 2035 case X86::ADD16ri: 2036 case X86::ADD16ri8: 2037 case X86::ADD16ri_DB: 2038 case X86::ADD16ri8_DB: 2039 if (DisableLEA16) 2040 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2041 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2042 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2043 .addReg(Dest, RegState::Define | 2044 getDeadRegState(isDead)), 2045 Src, isKill, MI->getOperand(2).getImm()); 2046 break; 2047 } 2048 } 2049 } 2050 2051 if (!NewMI) return 0; 2052 2053 if (LV) { // Update live variables 2054 if (isKill) 2055 LV->replaceKillInstruction(Src, MI, NewMI); 2056 if (isDead) 2057 LV->replaceKillInstruction(Dest, MI, NewMI); 2058 } 2059 2060 MFI->insert(MBBI, NewMI); // Insert the new inst 2061 return NewMI; 2062 } 2063 2064 /// commuteInstruction - We have a few instructions that must be hacked on to 2065 /// commute them. 2066 /// 2067 MachineInstr * 2068 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2069 switch (MI->getOpcode()) { 2070 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2071 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2072 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2073 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2074 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2075 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2076 unsigned Opc; 2077 unsigned Size; 2078 switch (MI->getOpcode()) { 2079 default: llvm_unreachable("Unreachable!"); 2080 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2081 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2082 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2083 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2084 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2085 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2086 } 2087 unsigned Amt = MI->getOperand(3).getImm(); 2088 if (NewMI) { 2089 MachineFunction &MF = *MI->getParent()->getParent(); 2090 MI = MF.CloneMachineInstr(MI); 2091 NewMI = false; 2092 } 2093 MI->setDesc(get(Opc)); 2094 MI->getOperand(3).setImm(Size-Amt); 2095 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 2096 } 2097 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2098 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2099 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2100 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2101 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2102 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2103 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2104 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2105 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2106 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2107 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2108 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2109 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2110 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2111 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2112 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2113 unsigned Opc; 2114 switch (MI->getOpcode()) { 2115 default: llvm_unreachable("Unreachable!"); 2116 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2117 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2118 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2119 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2120 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2121 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2122 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2123 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2124 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2125 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2126 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2127 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2128 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2129 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2130 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2131 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2132 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2133 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2134 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2135 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2136 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2137 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2138 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2139 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2140 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2141 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2142 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2143 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2144 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2145 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2146 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2147 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2148 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2149 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2150 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2151 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2152 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2153 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2154 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2155 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2156 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2157 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2158 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2159 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2160 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2161 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2162 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2163 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2164 } 2165 if (NewMI) { 2166 MachineFunction &MF = *MI->getParent()->getParent(); 2167 MI = MF.CloneMachineInstr(MI); 2168 NewMI = false; 2169 } 2170 MI->setDesc(get(Opc)); 2171 // Fallthrough intended. 2172 } 2173 default: 2174 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 2175 } 2176 } 2177 2178 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2179 switch (BrOpc) { 2180 default: return X86::COND_INVALID; 2181 case X86::JE_4: return X86::COND_E; 2182 case X86::JNE_4: return X86::COND_NE; 2183 case X86::JL_4: return X86::COND_L; 2184 case X86::JLE_4: return X86::COND_LE; 2185 case X86::JG_4: return X86::COND_G; 2186 case X86::JGE_4: return X86::COND_GE; 2187 case X86::JB_4: return X86::COND_B; 2188 case X86::JBE_4: return X86::COND_BE; 2189 case X86::JA_4: return X86::COND_A; 2190 case X86::JAE_4: return X86::COND_AE; 2191 case X86::JS_4: return X86::COND_S; 2192 case X86::JNS_4: return X86::COND_NS; 2193 case X86::JP_4: return X86::COND_P; 2194 case X86::JNP_4: return X86::COND_NP; 2195 case X86::JO_4: return X86::COND_O; 2196 case X86::JNO_4: return X86::COND_NO; 2197 } 2198 } 2199 2200 /// getCondFromSETOpc - return condition code of a SET opcode. 2201 static X86::CondCode getCondFromSETOpc(unsigned Opc) { 2202 switch (Opc) { 2203 default: return X86::COND_INVALID; 2204 case X86::SETAr: case X86::SETAm: return X86::COND_A; 2205 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2206 case X86::SETBr: case X86::SETBm: return X86::COND_B; 2207 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2208 case X86::SETEr: case X86::SETEm: return X86::COND_E; 2209 case X86::SETGr: case X86::SETGm: return X86::COND_G; 2210 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2211 case X86::SETLr: case X86::SETLm: return X86::COND_L; 2212 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2213 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2214 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2215 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2216 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2217 case X86::SETOr: case X86::SETOm: return X86::COND_O; 2218 case X86::SETPr: case X86::SETPm: return X86::COND_P; 2219 case X86::SETSr: case X86::SETSm: return X86::COND_S; 2220 } 2221 } 2222 2223 /// getCondFromCmovOpc - return condition code of a CMov opcode. 2224 static X86::CondCode getCondFromCMovOpc(unsigned Opc) { 2225 switch (Opc) { 2226 default: return X86::COND_INVALID; 2227 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2228 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2229 return X86::COND_A; 2230 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2231 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2232 return X86::COND_AE; 2233 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2234 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2235 return X86::COND_B; 2236 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2237 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2238 return X86::COND_BE; 2239 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2240 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2241 return X86::COND_E; 2242 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2243 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2244 return X86::COND_G; 2245 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2246 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2247 return X86::COND_GE; 2248 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2249 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2250 return X86::COND_L; 2251 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2252 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2253 return X86::COND_LE; 2254 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2255 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2256 return X86::COND_NE; 2257 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2258 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2259 return X86::COND_NO; 2260 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2261 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2262 return X86::COND_NP; 2263 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2264 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2265 return X86::COND_NS; 2266 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2267 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2268 return X86::COND_O; 2269 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2270 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2271 return X86::COND_P; 2272 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2273 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2274 return X86::COND_S; 2275 } 2276 } 2277 2278 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2279 switch (CC) { 2280 default: llvm_unreachable("Illegal condition code!"); 2281 case X86::COND_E: return X86::JE_4; 2282 case X86::COND_NE: return X86::JNE_4; 2283 case X86::COND_L: return X86::JL_4; 2284 case X86::COND_LE: return X86::JLE_4; 2285 case X86::COND_G: return X86::JG_4; 2286 case X86::COND_GE: return X86::JGE_4; 2287 case X86::COND_B: return X86::JB_4; 2288 case X86::COND_BE: return X86::JBE_4; 2289 case X86::COND_A: return X86::JA_4; 2290 case X86::COND_AE: return X86::JAE_4; 2291 case X86::COND_S: return X86::JS_4; 2292 case X86::COND_NS: return X86::JNS_4; 2293 case X86::COND_P: return X86::JP_4; 2294 case X86::COND_NP: return X86::JNP_4; 2295 case X86::COND_O: return X86::JO_4; 2296 case X86::COND_NO: return X86::JNO_4; 2297 } 2298 } 2299 2300 /// GetOppositeBranchCondition - Return the inverse of the specified condition, 2301 /// e.g. turning COND_E to COND_NE. 2302 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2303 switch (CC) { 2304 default: llvm_unreachable("Illegal condition code!"); 2305 case X86::COND_E: return X86::COND_NE; 2306 case X86::COND_NE: return X86::COND_E; 2307 case X86::COND_L: return X86::COND_GE; 2308 case X86::COND_LE: return X86::COND_G; 2309 case X86::COND_G: return X86::COND_LE; 2310 case X86::COND_GE: return X86::COND_L; 2311 case X86::COND_B: return X86::COND_AE; 2312 case X86::COND_BE: return X86::COND_A; 2313 case X86::COND_A: return X86::COND_BE; 2314 case X86::COND_AE: return X86::COND_B; 2315 case X86::COND_S: return X86::COND_NS; 2316 case X86::COND_NS: return X86::COND_S; 2317 case X86::COND_P: return X86::COND_NP; 2318 case X86::COND_NP: return X86::COND_P; 2319 case X86::COND_O: return X86::COND_NO; 2320 case X86::COND_NO: return X86::COND_O; 2321 } 2322 } 2323 2324 /// getSwappedCondition - assume the flags are set by MI(a,b), return 2325 /// the condition code if we modify the instructions such that flags are 2326 /// set by MI(b,a). 2327 static X86::CondCode getSwappedCondition(X86::CondCode CC) { 2328 switch (CC) { 2329 default: return X86::COND_INVALID; 2330 case X86::COND_E: return X86::COND_E; 2331 case X86::COND_NE: return X86::COND_NE; 2332 case X86::COND_L: return X86::COND_G; 2333 case X86::COND_LE: return X86::COND_GE; 2334 case X86::COND_G: return X86::COND_L; 2335 case X86::COND_GE: return X86::COND_LE; 2336 case X86::COND_B: return X86::COND_A; 2337 case X86::COND_BE: return X86::COND_AE; 2338 case X86::COND_A: return X86::COND_B; 2339 case X86::COND_AE: return X86::COND_BE; 2340 } 2341 } 2342 2343 /// getSETFromCond - Return a set opcode for the given condition and 2344 /// whether it has memory operand. 2345 static unsigned getSETFromCond(X86::CondCode CC, 2346 bool HasMemoryOperand) { 2347 static const uint16_t Opc[16][2] = { 2348 { X86::SETAr, X86::SETAm }, 2349 { X86::SETAEr, X86::SETAEm }, 2350 { X86::SETBr, X86::SETBm }, 2351 { X86::SETBEr, X86::SETBEm }, 2352 { X86::SETEr, X86::SETEm }, 2353 { X86::SETGr, X86::SETGm }, 2354 { X86::SETGEr, X86::SETGEm }, 2355 { X86::SETLr, X86::SETLm }, 2356 { X86::SETLEr, X86::SETLEm }, 2357 { X86::SETNEr, X86::SETNEm }, 2358 { X86::SETNOr, X86::SETNOm }, 2359 { X86::SETNPr, X86::SETNPm }, 2360 { X86::SETNSr, X86::SETNSm }, 2361 { X86::SETOr, X86::SETOm }, 2362 { X86::SETPr, X86::SETPm }, 2363 { X86::SETSr, X86::SETSm } 2364 }; 2365 2366 assert(CC < 16 && "Can only handle standard cond codes"); 2367 return Opc[CC][HasMemoryOperand ? 1 : 0]; 2368 } 2369 2370 /// getCMovFromCond - Return a cmov opcode for the given condition, 2371 /// register size in bytes, and operand type. 2372 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, 2373 bool HasMemoryOperand) { 2374 static const uint16_t Opc[32][3] = { 2375 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2376 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2377 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2378 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2379 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2380 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2381 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2382 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2383 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2384 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2385 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2386 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2387 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2388 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2389 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2390 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2391 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2392 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2393 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2394 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2395 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2396 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2397 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2398 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2399 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2400 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2401 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2402 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2403 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2404 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2405 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2406 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2407 }; 2408 2409 assert(CC < 16 && "Can only handle standard cond codes"); 2410 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2411 switch(RegBytes) { 2412 default: llvm_unreachable("Illegal register size!"); 2413 case 2: return Opc[Idx][0]; 2414 case 4: return Opc[Idx][1]; 2415 case 8: return Opc[Idx][2]; 2416 } 2417 } 2418 2419 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2420 if (!MI->isTerminator()) return false; 2421 2422 // Conditional branch is a special case. 2423 if (MI->isBranch() && !MI->isBarrier()) 2424 return true; 2425 if (!MI->isPredicable()) 2426 return true; 2427 return !isPredicated(MI); 2428 } 2429 2430 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2431 MachineBasicBlock *&TBB, 2432 MachineBasicBlock *&FBB, 2433 SmallVectorImpl<MachineOperand> &Cond, 2434 bool AllowModify) const { 2435 // Start from the bottom of the block and work up, examining the 2436 // terminator instructions. 2437 MachineBasicBlock::iterator I = MBB.end(); 2438 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2439 while (I != MBB.begin()) { 2440 --I; 2441 if (I->isDebugValue()) 2442 continue; 2443 2444 // Working from the bottom, when we see a non-terminator instruction, we're 2445 // done. 2446 if (!isUnpredicatedTerminator(I)) 2447 break; 2448 2449 // A terminator that isn't a branch can't easily be handled by this 2450 // analysis. 2451 if (!I->isBranch()) 2452 return true; 2453 2454 // Handle unconditional branches. 2455 if (I->getOpcode() == X86::JMP_4) { 2456 UnCondBrIter = I; 2457 2458 if (!AllowModify) { 2459 TBB = I->getOperand(0).getMBB(); 2460 continue; 2461 } 2462 2463 // If the block has any instructions after a JMP, delete them. 2464 while (llvm::next(I) != MBB.end()) 2465 llvm::next(I)->eraseFromParent(); 2466 2467 Cond.clear(); 2468 FBB = 0; 2469 2470 // Delete the JMP if it's equivalent to a fall-through. 2471 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2472 TBB = 0; 2473 I->eraseFromParent(); 2474 I = MBB.end(); 2475 UnCondBrIter = MBB.end(); 2476 continue; 2477 } 2478 2479 // TBB is used to indicate the unconditional destination. 2480 TBB = I->getOperand(0).getMBB(); 2481 continue; 2482 } 2483 2484 // Handle conditional branches. 2485 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2486 if (BranchCode == X86::COND_INVALID) 2487 return true; // Can't handle indirect branch. 2488 2489 // Working from the bottom, handle the first conditional branch. 2490 if (Cond.empty()) { 2491 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2492 if (AllowModify && UnCondBrIter != MBB.end() && 2493 MBB.isLayoutSuccessor(TargetBB)) { 2494 // If we can modify the code and it ends in something like: 2495 // 2496 // jCC L1 2497 // jmp L2 2498 // L1: 2499 // ... 2500 // L2: 2501 // 2502 // Then we can change this to: 2503 // 2504 // jnCC L2 2505 // L1: 2506 // ... 2507 // L2: 2508 // 2509 // Which is a bit more efficient. 2510 // We conditionally jump to the fall-through block. 2511 BranchCode = GetOppositeBranchCondition(BranchCode); 2512 unsigned JNCC = GetCondBranchFromCond(BranchCode); 2513 MachineBasicBlock::iterator OldInst = I; 2514 2515 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2516 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2517 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2518 .addMBB(TargetBB); 2519 2520 OldInst->eraseFromParent(); 2521 UnCondBrIter->eraseFromParent(); 2522 2523 // Restart the analysis. 2524 UnCondBrIter = MBB.end(); 2525 I = MBB.end(); 2526 continue; 2527 } 2528 2529 FBB = TBB; 2530 TBB = I->getOperand(0).getMBB(); 2531 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2532 continue; 2533 } 2534 2535 // Handle subsequent conditional branches. Only handle the case where all 2536 // conditional branches branch to the same destination and their condition 2537 // opcodes fit one of the special multi-branch idioms. 2538 assert(Cond.size() == 1); 2539 assert(TBB); 2540 2541 // Only handle the case where all conditional branches branch to the same 2542 // destination. 2543 if (TBB != I->getOperand(0).getMBB()) 2544 return true; 2545 2546 // If the conditions are the same, we can leave them alone. 2547 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2548 if (OldBranchCode == BranchCode) 2549 continue; 2550 2551 // If they differ, see if they fit one of the known patterns. Theoretically, 2552 // we could handle more patterns here, but we shouldn't expect to see them 2553 // if instruction selection has done a reasonable job. 2554 if ((OldBranchCode == X86::COND_NP && 2555 BranchCode == X86::COND_E) || 2556 (OldBranchCode == X86::COND_E && 2557 BranchCode == X86::COND_NP)) 2558 BranchCode = X86::COND_NP_OR_E; 2559 else if ((OldBranchCode == X86::COND_P && 2560 BranchCode == X86::COND_NE) || 2561 (OldBranchCode == X86::COND_NE && 2562 BranchCode == X86::COND_P)) 2563 BranchCode = X86::COND_NE_OR_P; 2564 else 2565 return true; 2566 2567 // Update the MachineOperand. 2568 Cond[0].setImm(BranchCode); 2569 } 2570 2571 return false; 2572 } 2573 2574 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2575 MachineBasicBlock::iterator I = MBB.end(); 2576 unsigned Count = 0; 2577 2578 while (I != MBB.begin()) { 2579 --I; 2580 if (I->isDebugValue()) 2581 continue; 2582 if (I->getOpcode() != X86::JMP_4 && 2583 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2584 break; 2585 // Remove the branch. 2586 I->eraseFromParent(); 2587 I = MBB.end(); 2588 ++Count; 2589 } 2590 2591 return Count; 2592 } 2593 2594 unsigned 2595 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2596 MachineBasicBlock *FBB, 2597 const SmallVectorImpl<MachineOperand> &Cond, 2598 DebugLoc DL) const { 2599 // Shouldn't be a fall through. 2600 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2601 assert((Cond.size() == 1 || Cond.size() == 0) && 2602 "X86 branch conditions have one component!"); 2603 2604 if (Cond.empty()) { 2605 // Unconditional branch? 2606 assert(!FBB && "Unconditional branch with multiple successors!"); 2607 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2608 return 1; 2609 } 2610 2611 // Conditional branch. 2612 unsigned Count = 0; 2613 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2614 switch (CC) { 2615 case X86::COND_NP_OR_E: 2616 // Synthesize NP_OR_E with two branches. 2617 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2618 ++Count; 2619 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2620 ++Count; 2621 break; 2622 case X86::COND_NE_OR_P: 2623 // Synthesize NE_OR_P with two branches. 2624 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2625 ++Count; 2626 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2627 ++Count; 2628 break; 2629 default: { 2630 unsigned Opc = GetCondBranchFromCond(CC); 2631 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2632 ++Count; 2633 } 2634 } 2635 if (FBB) { 2636 // Two-way Conditional branch. Insert the second branch. 2637 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2638 ++Count; 2639 } 2640 return Count; 2641 } 2642 2643 bool X86InstrInfo:: 2644 canInsertSelect(const MachineBasicBlock &MBB, 2645 const SmallVectorImpl<MachineOperand> &Cond, 2646 unsigned TrueReg, unsigned FalseReg, 2647 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2648 // Not all subtargets have cmov instructions. 2649 if (!TM.getSubtarget<X86Subtarget>().hasCMov()) 2650 return false; 2651 if (Cond.size() != 1) 2652 return false; 2653 // We cannot do the composite conditions, at least not in SSA form. 2654 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2655 return false; 2656 2657 // Check register classes. 2658 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2659 const TargetRegisterClass *RC = 2660 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2661 if (!RC) 2662 return false; 2663 2664 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2665 if (X86::GR16RegClass.hasSubClassEq(RC) || 2666 X86::GR32RegClass.hasSubClassEq(RC) || 2667 X86::GR64RegClass.hasSubClassEq(RC)) { 2668 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2669 // Bridge. Probably Ivy Bridge as well. 2670 CondCycles = 2; 2671 TrueCycles = 2; 2672 FalseCycles = 2; 2673 return true; 2674 } 2675 2676 // Can't do vectors. 2677 return false; 2678 } 2679 2680 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 2681 MachineBasicBlock::iterator I, DebugLoc DL, 2682 unsigned DstReg, 2683 const SmallVectorImpl<MachineOperand> &Cond, 2684 unsigned TrueReg, unsigned FalseReg) const { 2685 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2686 assert(Cond.size() == 1 && "Invalid Cond array"); 2687 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 2688 MRI.getRegClass(DstReg)->getSize(), 2689 false/*HasMemoryOperand*/); 2690 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 2691 } 2692 2693 /// isHReg - Test if the given register is a physical h register. 2694 static bool isHReg(unsigned Reg) { 2695 return X86::GR8_ABCD_HRegClass.contains(Reg); 2696 } 2697 2698 // Try and copy between VR128/VR64 and GR64 registers. 2699 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 2700 bool HasAVX) { 2701 // SrcReg(VR128) -> DestReg(GR64) 2702 // SrcReg(VR64) -> DestReg(GR64) 2703 // SrcReg(GR64) -> DestReg(VR128) 2704 // SrcReg(GR64) -> DestReg(VR64) 2705 2706 if (X86::GR64RegClass.contains(DestReg)) { 2707 if (X86::VR128RegClass.contains(SrcReg)) 2708 // Copy from a VR128 register to a GR64 register. 2709 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr; 2710 if (X86::VR64RegClass.contains(SrcReg)) 2711 // Copy from a VR64 register to a GR64 register. 2712 return X86::MOVSDto64rr; 2713 } else if (X86::GR64RegClass.contains(SrcReg)) { 2714 // Copy from a GR64 register to a VR128 register. 2715 if (X86::VR128RegClass.contains(DestReg)) 2716 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr; 2717 // Copy from a GR64 register to a VR64 register. 2718 if (X86::VR64RegClass.contains(DestReg)) 2719 return X86::MOV64toSDrr; 2720 } 2721 2722 // SrcReg(FR32) -> DestReg(GR32) 2723 // SrcReg(GR32) -> DestReg(FR32) 2724 2725 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg)) 2726 // Copy from a FR32 register to a GR32 register. 2727 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr; 2728 2729 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 2730 // Copy from a GR32 register to a FR32 register. 2731 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr; 2732 2733 return 0; 2734 } 2735 2736 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 2737 MachineBasicBlock::iterator MI, DebugLoc DL, 2738 unsigned DestReg, unsigned SrcReg, 2739 bool KillSrc) const { 2740 // First deal with the normal symmetric copies. 2741 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2742 unsigned Opc; 2743 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 2744 Opc = X86::MOV64rr; 2745 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 2746 Opc = X86::MOV32rr; 2747 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 2748 Opc = X86::MOV16rr; 2749 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 2750 // Copying to or from a physical H register on x86-64 requires a NOREX 2751 // move. Otherwise use a normal move. 2752 if ((isHReg(DestReg) || isHReg(SrcReg)) && 2753 TM.getSubtarget<X86Subtarget>().is64Bit()) { 2754 Opc = X86::MOV8rr_NOREX; 2755 // Both operands must be encodable without an REX prefix. 2756 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 2757 "8-bit H register can not be copied outside GR8_NOREX"); 2758 } else 2759 Opc = X86::MOV8rr; 2760 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 2761 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 2762 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 2763 Opc = X86::VMOVAPSYrr; 2764 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 2765 Opc = X86::MMX_MOVQ64rr; 2766 else 2767 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX); 2768 2769 if (Opc) { 2770 BuildMI(MBB, MI, DL, get(Opc), DestReg) 2771 .addReg(SrcReg, getKillRegState(KillSrc)); 2772 return; 2773 } 2774 2775 // Moving EFLAGS to / from another register requires a push and a pop. 2776 if (SrcReg == X86::EFLAGS) { 2777 if (X86::GR64RegClass.contains(DestReg)) { 2778 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 2779 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 2780 return; 2781 } 2782 if (X86::GR32RegClass.contains(DestReg)) { 2783 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 2784 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 2785 return; 2786 } 2787 } 2788 if (DestReg == X86::EFLAGS) { 2789 if (X86::GR64RegClass.contains(SrcReg)) { 2790 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 2791 .addReg(SrcReg, getKillRegState(KillSrc)); 2792 BuildMI(MBB, MI, DL, get(X86::POPF64)); 2793 return; 2794 } 2795 if (X86::GR32RegClass.contains(SrcReg)) { 2796 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2797 .addReg(SrcReg, getKillRegState(KillSrc)); 2798 BuildMI(MBB, MI, DL, get(X86::POPF32)); 2799 return; 2800 } 2801 } 2802 2803 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2804 << " to " << RI.getName(DestReg) << '\n'); 2805 llvm_unreachable("Cannot emit physreg copy instruction"); 2806 } 2807 2808 static unsigned getLoadStoreRegOpcode(unsigned Reg, 2809 const TargetRegisterClass *RC, 2810 bool isStackAligned, 2811 const TargetMachine &TM, 2812 bool load) { 2813 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2814 switch (RC->getSize()) { 2815 default: 2816 llvm_unreachable("Unknown spill size"); 2817 case 1: 2818 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 2819 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2820 // Copying to or from a physical H register on x86-64 requires a NOREX 2821 // move. Otherwise use a normal move. 2822 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 2823 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2824 return load ? X86::MOV8rm : X86::MOV8mr; 2825 case 2: 2826 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 2827 return load ? X86::MOV16rm : X86::MOV16mr; 2828 case 4: 2829 if (X86::GR32RegClass.hasSubClassEq(RC)) 2830 return load ? X86::MOV32rm : X86::MOV32mr; 2831 if (X86::FR32RegClass.hasSubClassEq(RC)) 2832 return load ? 2833 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 2834 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 2835 if (X86::RFP32RegClass.hasSubClassEq(RC)) 2836 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2837 llvm_unreachable("Unknown 4-byte regclass"); 2838 case 8: 2839 if (X86::GR64RegClass.hasSubClassEq(RC)) 2840 return load ? X86::MOV64rm : X86::MOV64mr; 2841 if (X86::FR64RegClass.hasSubClassEq(RC)) 2842 return load ? 2843 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 2844 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 2845 if (X86::VR64RegClass.hasSubClassEq(RC)) 2846 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2847 if (X86::RFP64RegClass.hasSubClassEq(RC)) 2848 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2849 llvm_unreachable("Unknown 8-byte regclass"); 2850 case 10: 2851 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 2852 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2853 case 16: { 2854 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); 2855 // If stack is realigned we can use aligned stores. 2856 if (isStackAligned) 2857 return load ? 2858 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 2859 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 2860 else 2861 return load ? 2862 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 2863 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 2864 } 2865 case 32: 2866 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 2867 // If stack is realigned we can use aligned stores. 2868 if (isStackAligned) 2869 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 2870 else 2871 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 2872 } 2873 } 2874 2875 static unsigned getStoreRegOpcode(unsigned SrcReg, 2876 const TargetRegisterClass *RC, 2877 bool isStackAligned, 2878 TargetMachine &TM) { 2879 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2880 } 2881 2882 2883 static unsigned getLoadRegOpcode(unsigned DestReg, 2884 const TargetRegisterClass *RC, 2885 bool isStackAligned, 2886 const TargetMachine &TM) { 2887 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2888 } 2889 2890 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2891 MachineBasicBlock::iterator MI, 2892 unsigned SrcReg, bool isKill, int FrameIdx, 2893 const TargetRegisterClass *RC, 2894 const TargetRegisterInfo *TRI) const { 2895 const MachineFunction &MF = *MBB.getParent(); 2896 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2897 "Stack slot too small for store"); 2898 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2899 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2900 RI.canRealignStack(MF); 2901 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2902 DebugLoc DL = MBB.findDebugLoc(MI); 2903 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2904 .addReg(SrcReg, getKillRegState(isKill)); 2905 } 2906 2907 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2908 bool isKill, 2909 SmallVectorImpl<MachineOperand> &Addr, 2910 const TargetRegisterClass *RC, 2911 MachineInstr::mmo_iterator MMOBegin, 2912 MachineInstr::mmo_iterator MMOEnd, 2913 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2914 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2915 bool isAligned = MMOBegin != MMOEnd && 2916 (*MMOBegin)->getAlignment() >= Alignment; 2917 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2918 DebugLoc DL; 2919 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2920 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2921 MIB.addOperand(Addr[i]); 2922 MIB.addReg(SrcReg, getKillRegState(isKill)); 2923 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2924 NewMIs.push_back(MIB); 2925 } 2926 2927 2928 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2929 MachineBasicBlock::iterator MI, 2930 unsigned DestReg, int FrameIdx, 2931 const TargetRegisterClass *RC, 2932 const TargetRegisterInfo *TRI) const { 2933 const MachineFunction &MF = *MBB.getParent(); 2934 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2935 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2936 RI.canRealignStack(MF); 2937 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2938 DebugLoc DL = MBB.findDebugLoc(MI); 2939 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2940 } 2941 2942 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2943 SmallVectorImpl<MachineOperand> &Addr, 2944 const TargetRegisterClass *RC, 2945 MachineInstr::mmo_iterator MMOBegin, 2946 MachineInstr::mmo_iterator MMOEnd, 2947 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2948 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2949 bool isAligned = MMOBegin != MMOEnd && 2950 (*MMOBegin)->getAlignment() >= Alignment; 2951 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2952 DebugLoc DL; 2953 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2954 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2955 MIB.addOperand(Addr[i]); 2956 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2957 NewMIs.push_back(MIB); 2958 } 2959 2960 bool X86InstrInfo:: 2961 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 2962 int &CmpMask, int &CmpValue) const { 2963 switch (MI->getOpcode()) { 2964 default: break; 2965 case X86::CMP64ri32: 2966 case X86::CMP64ri8: 2967 case X86::CMP32ri: 2968 case X86::CMP32ri8: 2969 case X86::CMP16ri: 2970 case X86::CMP16ri8: 2971 case X86::CMP8ri: 2972 SrcReg = MI->getOperand(0).getReg(); 2973 SrcReg2 = 0; 2974 CmpMask = ~0; 2975 CmpValue = MI->getOperand(1).getImm(); 2976 return true; 2977 // A SUB can be used to perform comparison. 2978 case X86::SUB64rm: 2979 case X86::SUB32rm: 2980 case X86::SUB16rm: 2981 case X86::SUB8rm: 2982 SrcReg = MI->getOperand(1).getReg(); 2983 SrcReg2 = 0; 2984 CmpMask = ~0; 2985 CmpValue = 0; 2986 return true; 2987 case X86::SUB64rr: 2988 case X86::SUB32rr: 2989 case X86::SUB16rr: 2990 case X86::SUB8rr: 2991 SrcReg = MI->getOperand(1).getReg(); 2992 SrcReg2 = MI->getOperand(2).getReg(); 2993 CmpMask = ~0; 2994 CmpValue = 0; 2995 return true; 2996 case X86::SUB64ri32: 2997 case X86::SUB64ri8: 2998 case X86::SUB32ri: 2999 case X86::SUB32ri8: 3000 case X86::SUB16ri: 3001 case X86::SUB16ri8: 3002 case X86::SUB8ri: 3003 SrcReg = MI->getOperand(1).getReg(); 3004 SrcReg2 = 0; 3005 CmpMask = ~0; 3006 CmpValue = MI->getOperand(2).getImm(); 3007 return true; 3008 case X86::CMP64rr: 3009 case X86::CMP32rr: 3010 case X86::CMP16rr: 3011 case X86::CMP8rr: 3012 SrcReg = MI->getOperand(0).getReg(); 3013 SrcReg2 = MI->getOperand(1).getReg(); 3014 CmpMask = ~0; 3015 CmpValue = 0; 3016 return true; 3017 case X86::TEST8rr: 3018 case X86::TEST16rr: 3019 case X86::TEST32rr: 3020 case X86::TEST64rr: 3021 SrcReg = MI->getOperand(0).getReg(); 3022 if (MI->getOperand(1).getReg() != SrcReg) return false; 3023 // Compare against zero. 3024 SrcReg2 = 0; 3025 CmpMask = ~0; 3026 CmpValue = 0; 3027 return true; 3028 } 3029 return false; 3030 } 3031 3032 /// isRedundantFlagInstr - check whether the first instruction, whose only 3033 /// purpose is to update flags, can be made redundant. 3034 /// CMPrr can be made redundant by SUBrr if the operands are the same. 3035 /// This function can be extended later on. 3036 /// SrcReg, SrcRegs: register operands for FlagI. 3037 /// ImmValue: immediate for FlagI if it takes an immediate. 3038 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3039 unsigned SrcReg2, int ImmValue, 3040 MachineInstr *OI) { 3041 if (((FlagI->getOpcode() == X86::CMP64rr && 3042 OI->getOpcode() == X86::SUB64rr) || 3043 (FlagI->getOpcode() == X86::CMP32rr && 3044 OI->getOpcode() == X86::SUB32rr)|| 3045 (FlagI->getOpcode() == X86::CMP16rr && 3046 OI->getOpcode() == X86::SUB16rr)|| 3047 (FlagI->getOpcode() == X86::CMP8rr && 3048 OI->getOpcode() == X86::SUB8rr)) && 3049 ((OI->getOperand(1).getReg() == SrcReg && 3050 OI->getOperand(2).getReg() == SrcReg2) || 3051 (OI->getOperand(1).getReg() == SrcReg2 && 3052 OI->getOperand(2).getReg() == SrcReg))) 3053 return true; 3054 3055 if (((FlagI->getOpcode() == X86::CMP64ri32 && 3056 OI->getOpcode() == X86::SUB64ri32) || 3057 (FlagI->getOpcode() == X86::CMP64ri8 && 3058 OI->getOpcode() == X86::SUB64ri8) || 3059 (FlagI->getOpcode() == X86::CMP32ri && 3060 OI->getOpcode() == X86::SUB32ri) || 3061 (FlagI->getOpcode() == X86::CMP32ri8 && 3062 OI->getOpcode() == X86::SUB32ri8) || 3063 (FlagI->getOpcode() == X86::CMP16ri && 3064 OI->getOpcode() == X86::SUB16ri) || 3065 (FlagI->getOpcode() == X86::CMP16ri8 && 3066 OI->getOpcode() == X86::SUB16ri8) || 3067 (FlagI->getOpcode() == X86::CMP8ri && 3068 OI->getOpcode() == X86::SUB8ri)) && 3069 OI->getOperand(1).getReg() == SrcReg && 3070 OI->getOperand(2).getImm() == ImmValue) 3071 return true; 3072 return false; 3073 } 3074 3075 /// isDefConvertible - check whether the definition can be converted 3076 /// to remove a comparison against zero. 3077 inline static bool isDefConvertible(MachineInstr *MI) { 3078 switch (MI->getOpcode()) { 3079 default: return false; 3080 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3081 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3082 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3083 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3084 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3085 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3086 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3087 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3088 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3089 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3090 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3091 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3092 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3093 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3094 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3095 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3096 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3097 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3098 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3099 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3100 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3101 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3102 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3103 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3104 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3105 return true; 3106 } 3107 } 3108 3109 /// optimizeCompareInstr - Check if there exists an earlier instruction that 3110 /// operates on the same source operands and sets flags in the same way as 3111 /// Compare; remove Compare if possible. 3112 bool X86InstrInfo:: 3113 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3114 int CmpMask, int CmpValue, 3115 const MachineRegisterInfo *MRI) const { 3116 // Check whether we can replace SUB with CMP. 3117 unsigned NewOpcode = 0; 3118 switch (CmpInstr->getOpcode()) { 3119 default: break; 3120 case X86::SUB64ri32: 3121 case X86::SUB64ri8: 3122 case X86::SUB32ri: 3123 case X86::SUB32ri8: 3124 case X86::SUB16ri: 3125 case X86::SUB16ri8: 3126 case X86::SUB8ri: 3127 case X86::SUB64rm: 3128 case X86::SUB32rm: 3129 case X86::SUB16rm: 3130 case X86::SUB8rm: 3131 case X86::SUB64rr: 3132 case X86::SUB32rr: 3133 case X86::SUB16rr: 3134 case X86::SUB8rr: { 3135 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3136 return false; 3137 // There is no use of the destination register, we can replace SUB with CMP. 3138 switch (CmpInstr->getOpcode()) { 3139 default: llvm_unreachable("Unreachable!"); 3140 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3141 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3142 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3143 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3144 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3145 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3146 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3147 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3148 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3149 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3150 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3151 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3152 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3153 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3154 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3155 } 3156 CmpInstr->setDesc(get(NewOpcode)); 3157 CmpInstr->RemoveOperand(0); 3158 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3159 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3160 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3161 return false; 3162 } 3163 } 3164 3165 // Get the unique definition of SrcReg. 3166 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3167 if (!MI) return false; 3168 3169 // CmpInstr is the first instruction of the BB. 3170 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3171 3172 // If we are comparing against zero, check whether we can use MI to update 3173 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3174 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3175 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() || 3176 !isDefConvertible(MI))) 3177 return false; 3178 3179 // We are searching for an earlier instruction that can make CmpInstr 3180 // redundant and that instruction will be saved in Sub. 3181 MachineInstr *Sub = NULL; 3182 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3183 3184 // We iterate backward, starting from the instruction before CmpInstr and 3185 // stop when reaching the definition of a source register or done with the BB. 3186 // RI points to the instruction before CmpInstr. 3187 // If the definition is in this basic block, RE points to the definition; 3188 // otherwise, RE is the rend of the basic block. 3189 MachineBasicBlock::reverse_iterator 3190 RI = MachineBasicBlock::reverse_iterator(I), 3191 RE = CmpInstr->getParent() == MI->getParent() ? 3192 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3193 CmpInstr->getParent()->rend(); 3194 MachineInstr *Movr0Inst = 0; 3195 for (; RI != RE; ++RI) { 3196 MachineInstr *Instr = &*RI; 3197 // Check whether CmpInstr can be made redundant by the current instruction. 3198 if (!IsCmpZero && 3199 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3200 Sub = Instr; 3201 break; 3202 } 3203 3204 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3205 Instr->readsRegister(X86::EFLAGS, TRI)) { 3206 // This instruction modifies or uses EFLAGS. 3207 3208 // MOV32r0 etc. are implemented with xor which clobbers condition code. 3209 // They are safe to move up, if the definition to EFLAGS is dead and 3210 // earlier instructions do not read or write EFLAGS. 3211 if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 || 3212 Instr->getOpcode() == X86::MOV16r0 || 3213 Instr->getOpcode() == X86::MOV32r0 || 3214 Instr->getOpcode() == X86::MOV64r0) && 3215 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3216 Movr0Inst = Instr; 3217 continue; 3218 } 3219 3220 // We can't remove CmpInstr. 3221 return false; 3222 } 3223 } 3224 3225 // Return false if no candidates exist. 3226 if (!IsCmpZero && !Sub) 3227 return false; 3228 3229 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3230 Sub->getOperand(2).getReg() == SrcReg); 3231 3232 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3233 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3234 // If we are done with the basic block, we need to check whether EFLAGS is 3235 // live-out. 3236 bool IsSafe = false; 3237 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3238 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3239 for (++I; I != E; ++I) { 3240 const MachineInstr &Instr = *I; 3241 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3242 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3243 // We should check the usage if this instruction uses and updates EFLAGS. 3244 if (!UseEFLAGS && ModifyEFLAGS) { 3245 // It is safe to remove CmpInstr if EFLAGS is updated again. 3246 IsSafe = true; 3247 break; 3248 } 3249 if (!UseEFLAGS && !ModifyEFLAGS) 3250 continue; 3251 3252 // EFLAGS is used by this instruction. 3253 X86::CondCode OldCC; 3254 bool OpcIsSET = false; 3255 if (IsCmpZero || IsSwapped) { 3256 // We decode the condition code from opcode. 3257 if (Instr.isBranch()) 3258 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3259 else { 3260 OldCC = getCondFromSETOpc(Instr.getOpcode()); 3261 if (OldCC != X86::COND_INVALID) 3262 OpcIsSET = true; 3263 else 3264 OldCC = getCondFromCMovOpc(Instr.getOpcode()); 3265 } 3266 if (OldCC == X86::COND_INVALID) return false; 3267 } 3268 if (IsCmpZero) { 3269 switch (OldCC) { 3270 default: break; 3271 case X86::COND_A: case X86::COND_AE: 3272 case X86::COND_B: case X86::COND_BE: 3273 case X86::COND_G: case X86::COND_GE: 3274 case X86::COND_L: case X86::COND_LE: 3275 case X86::COND_O: case X86::COND_NO: 3276 // CF and OF are used, we can't perform this optimization. 3277 return false; 3278 } 3279 } else if (IsSwapped) { 3280 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3281 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3282 // We swap the condition code and synthesize the new opcode. 3283 X86::CondCode NewCC = getSwappedCondition(OldCC); 3284 if (NewCC == X86::COND_INVALID) return false; 3285 3286 // Synthesize the new opcode. 3287 bool HasMemoryOperand = Instr.hasOneMemOperand(); 3288 unsigned NewOpc; 3289 if (Instr.isBranch()) 3290 NewOpc = GetCondBranchFromCond(NewCC); 3291 else if(OpcIsSET) 3292 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3293 else { 3294 unsigned DstReg = Instr.getOperand(0).getReg(); 3295 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3296 HasMemoryOperand); 3297 } 3298 3299 // Push the MachineInstr to OpsToUpdate. 3300 // If it is safe to remove CmpInstr, the condition code of these 3301 // instructions will be modified. 3302 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3303 } 3304 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3305 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3306 IsSafe = true; 3307 break; 3308 } 3309 } 3310 3311 // If EFLAGS is not killed nor re-defined, we should check whether it is 3312 // live-out. If it is live-out, do not optimize. 3313 if ((IsCmpZero || IsSwapped) && !IsSafe) { 3314 MachineBasicBlock *MBB = CmpInstr->getParent(); 3315 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3316 SE = MBB->succ_end(); SI != SE; ++SI) 3317 if ((*SI)->isLiveIn(X86::EFLAGS)) 3318 return false; 3319 } 3320 3321 // The instruction to be updated is either Sub or MI. 3322 Sub = IsCmpZero ? MI : Sub; 3323 // Move Movr0Inst to the place right before Sub. 3324 if (Movr0Inst) { 3325 Sub->getParent()->remove(Movr0Inst); 3326 Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst); 3327 } 3328 3329 // Make sure Sub instruction defines EFLAGS. 3330 assert(Sub->getNumOperands() >= 2 && 3331 Sub->getOperand(Sub->getNumOperands()-1).isReg() && 3332 Sub->getOperand(Sub->getNumOperands()-1).getReg() == X86::EFLAGS && 3333 "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND"); 3334 Sub->getOperand(Sub->getNumOperands()-1).setIsDef(true); 3335 CmpInstr->eraseFromParent(); 3336 3337 // Modify the condition code of instructions in OpsToUpdate. 3338 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3339 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3340 return true; 3341 } 3342 3343 /// optimizeLoadInstr - Try to remove the load by folding it to a register 3344 /// operand at the use. We fold the load instructions if load defines a virtual 3345 /// register, the virtual register is used once in the same BB, and the 3346 /// instructions in-between do not load or store, and have no side effects. 3347 MachineInstr* X86InstrInfo:: 3348 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3349 unsigned &FoldAsLoadDefReg, 3350 MachineInstr *&DefMI) const { 3351 if (FoldAsLoadDefReg == 0) 3352 return 0; 3353 // To be conservative, if there exists another load, clear the load candidate. 3354 if (MI->mayLoad()) { 3355 FoldAsLoadDefReg = 0; 3356 return 0; 3357 } 3358 3359 // Check whether we can move DefMI here. 3360 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3361 assert(DefMI); 3362 bool SawStore = false; 3363 if (!DefMI->isSafeToMove(this, 0, SawStore)) 3364 return 0; 3365 3366 // We try to commute MI if possible. 3367 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3368 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3369 // Collect information about virtual register operands of MI. 3370 unsigned SrcOperandId = 0; 3371 bool FoundSrcOperand = false; 3372 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3373 MachineOperand &MO = MI->getOperand(i); 3374 if (!MO.isReg()) 3375 continue; 3376 unsigned Reg = MO.getReg(); 3377 if (Reg != FoldAsLoadDefReg) 3378 continue; 3379 // Do not fold if we have a subreg use or a def or multiple uses. 3380 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3381 return 0; 3382 3383 SrcOperandId = i; 3384 FoundSrcOperand = true; 3385 } 3386 if (!FoundSrcOperand) return 0; 3387 3388 // Check whether we can fold the def into SrcOperandId. 3389 SmallVector<unsigned, 8> Ops; 3390 Ops.push_back(SrcOperandId); 3391 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3392 if (FoldMI) { 3393 FoldAsLoadDefReg = 0; 3394 return FoldMI; 3395 } 3396 3397 if (Idx == 1) { 3398 // MI was changed but it didn't help, commute it back! 3399 commuteInstruction(MI, false); 3400 return 0; 3401 } 3402 3403 // Check whether we can commute MI and enable folding. 3404 if (MI->isCommutable()) { 3405 MachineInstr *NewMI = commuteInstruction(MI, false); 3406 // Unable to commute. 3407 if (!NewMI) return 0; 3408 if (NewMI != MI) { 3409 // New instruction. It doesn't need to be kept. 3410 NewMI->eraseFromParent(); 3411 return 0; 3412 } 3413 } 3414 } 3415 return 0; 3416 } 3417 3418 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3419 /// instruction with two undef reads of the register being defined. This is 3420 /// used for mapping: 3421 /// %xmm4 = V_SET0 3422 /// to: 3423 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3424 /// 3425 static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) { 3426 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3427 unsigned Reg = MI->getOperand(0).getReg(); 3428 MI->setDesc(Desc); 3429 3430 // MachineInstr::addOperand() will insert explicit operands before any 3431 // implicit operands. 3432 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef) 3433 .addReg(Reg, RegState::Undef); 3434 // But we don't trust that. 3435 assert(MI->getOperand(1).getReg() == Reg && 3436 MI->getOperand(2).getReg() == Reg && "Misplaced operand"); 3437 return true; 3438 } 3439 3440 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3441 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3442 switch (MI->getOpcode()) { 3443 case X86::V_SET0: 3444 case X86::FsFLD0SS: 3445 case X86::FsFLD0SD: 3446 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3447 case X86::TEST8ri_NOREX: 3448 MI->setDesc(get(X86::TEST8ri)); 3449 return true; 3450 } 3451 return false; 3452 } 3453 3454 MachineInstr* 3455 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 3456 int FrameIx, uint64_t Offset, 3457 const MDNode *MDPtr, 3458 DebugLoc DL) const { 3459 X86AddressMode AM; 3460 AM.BaseType = X86AddressMode::FrameIndexBase; 3461 AM.Base.FrameIndex = FrameIx; 3462 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 3463 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 3464 return &*MIB; 3465 } 3466 3467 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 3468 const SmallVectorImpl<MachineOperand> &MOs, 3469 MachineInstr *MI, 3470 const TargetInstrInfo &TII) { 3471 // Create the base instruction with the memory operand as the first part. 3472 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3473 MI->getDebugLoc(), true); 3474 MachineInstrBuilder MIB(NewMI); 3475 unsigned NumAddrOps = MOs.size(); 3476 for (unsigned i = 0; i != NumAddrOps; ++i) 3477 MIB.addOperand(MOs[i]); 3478 if (NumAddrOps < 4) // FrameIndex only 3479 addOffset(MIB, 0); 3480 3481 // Loop over the rest of the ri operands, converting them over. 3482 unsigned NumOps = MI->getDesc().getNumOperands()-2; 3483 for (unsigned i = 0; i != NumOps; ++i) { 3484 MachineOperand &MO = MI->getOperand(i+2); 3485 MIB.addOperand(MO); 3486 } 3487 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 3488 MachineOperand &MO = MI->getOperand(i); 3489 MIB.addOperand(MO); 3490 } 3491 return MIB; 3492 } 3493 3494 static MachineInstr *FuseInst(MachineFunction &MF, 3495 unsigned Opcode, unsigned OpNo, 3496 const SmallVectorImpl<MachineOperand> &MOs, 3497 MachineInstr *MI, const TargetInstrInfo &TII) { 3498 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3499 MI->getDebugLoc(), true); 3500 MachineInstrBuilder MIB(NewMI); 3501 3502 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3503 MachineOperand &MO = MI->getOperand(i); 3504 if (i == OpNo) { 3505 assert(MO.isReg() && "Expected to fold into reg operand!"); 3506 unsigned NumAddrOps = MOs.size(); 3507 for (unsigned i = 0; i != NumAddrOps; ++i) 3508 MIB.addOperand(MOs[i]); 3509 if (NumAddrOps < 4) // FrameIndex only 3510 addOffset(MIB, 0); 3511 } else { 3512 MIB.addOperand(MO); 3513 } 3514 } 3515 return MIB; 3516 } 3517 3518 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 3519 const SmallVectorImpl<MachineOperand> &MOs, 3520 MachineInstr *MI) { 3521 MachineFunction &MF = *MI->getParent()->getParent(); 3522 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 3523 3524 unsigned NumAddrOps = MOs.size(); 3525 for (unsigned i = 0; i != NumAddrOps; ++i) 3526 MIB.addOperand(MOs[i]); 3527 if (NumAddrOps < 4) // FrameIndex only 3528 addOffset(MIB, 0); 3529 return MIB.addImm(0); 3530 } 3531 3532 MachineInstr* 3533 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3534 MachineInstr *MI, unsigned i, 3535 const SmallVectorImpl<MachineOperand> &MOs, 3536 unsigned Size, unsigned Align) const { 3537 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3538 bool isTwoAddrFold = false; 3539 unsigned NumOps = MI->getDesc().getNumOperands(); 3540 bool isTwoAddr = NumOps > 1 && 3541 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3542 3543 // FIXME: AsmPrinter doesn't know how to handle 3544 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3545 if (MI->getOpcode() == X86::ADD32ri && 3546 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3547 return NULL; 3548 3549 MachineInstr *NewMI = NULL; 3550 // Folding a memory location into the two-address part of a two-address 3551 // instruction is different than folding it other places. It requires 3552 // replacing the *two* registers with the memory location. 3553 if (isTwoAddr && NumOps >= 2 && i < 2 && 3554 MI->getOperand(0).isReg() && 3555 MI->getOperand(1).isReg() && 3556 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 3557 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3558 isTwoAddrFold = true; 3559 } else if (i == 0) { // If operand 0 3560 if (MI->getOpcode() == X86::MOV64r0) 3561 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 3562 else if (MI->getOpcode() == X86::MOV32r0) 3563 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 3564 else if (MI->getOpcode() == X86::MOV16r0) 3565 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 3566 else if (MI->getOpcode() == X86::MOV8r0) 3567 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 3568 if (NewMI) 3569 return NewMI; 3570 3571 OpcodeTablePtr = &RegOp2MemOpTable0; 3572 } else if (i == 1) { 3573 OpcodeTablePtr = &RegOp2MemOpTable1; 3574 } else if (i == 2) { 3575 OpcodeTablePtr = &RegOp2MemOpTable2; 3576 } else if (i == 3) { 3577 OpcodeTablePtr = &RegOp2MemOpTable3; 3578 } 3579 3580 // If table selected... 3581 if (OpcodeTablePtr) { 3582 // Find the Opcode to fuse 3583 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3584 OpcodeTablePtr->find(MI->getOpcode()); 3585 if (I != OpcodeTablePtr->end()) { 3586 unsigned Opcode = I->second.first; 3587 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 3588 if (Align < MinAlign) 3589 return NULL; 3590 bool NarrowToMOV32rm = false; 3591 if (Size) { 3592 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 3593 if (Size < RCSize) { 3594 // Check if it's safe to fold the load. If the size of the object is 3595 // narrower than the load width, then it's not. 3596 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 3597 return NULL; 3598 // If this is a 64-bit load, but the spill slot is 32, then we can do 3599 // a 32-bit load which is implicitly zero-extended. This likely is due 3600 // to liveintervalanalysis remat'ing a load from stack slot. 3601 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 3602 return NULL; 3603 Opcode = X86::MOV32rm; 3604 NarrowToMOV32rm = true; 3605 } 3606 } 3607 3608 if (isTwoAddrFold) 3609 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 3610 else 3611 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 3612 3613 if (NarrowToMOV32rm) { 3614 // If this is the special case where we use a MOV32rm to load a 32-bit 3615 // value and zero-extend the top bits. Change the destination register 3616 // to a 32-bit one. 3617 unsigned DstReg = NewMI->getOperand(0).getReg(); 3618 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 3619 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 3620 X86::sub_32bit)); 3621 else 3622 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 3623 } 3624 return NewMI; 3625 } 3626 } 3627 3628 // No fusion 3629 if (PrintFailedFusing && !MI->isCopy()) 3630 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 3631 return NULL; 3632 } 3633 3634 /// hasPartialRegUpdate - Return true for all instructions that only update 3635 /// the first 32 or 64-bits of the destination register and leave the rest 3636 /// unmodified. This can be used to avoid folding loads if the instructions 3637 /// only update part of the destination register, and the non-updated part is 3638 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 3639 /// instructions breaks the partial register dependency and it can improve 3640 /// performance. e.g.: 3641 /// 3642 /// movss (%rdi), %xmm0 3643 /// cvtss2sd %xmm0, %xmm0 3644 /// 3645 /// Instead of 3646 /// cvtss2sd (%rdi), %xmm0 3647 /// 3648 /// FIXME: This should be turned into a TSFlags. 3649 /// 3650 static bool hasPartialRegUpdate(unsigned Opcode) { 3651 switch (Opcode) { 3652 case X86::CVTSI2SSrr: 3653 case X86::CVTSI2SS64rr: 3654 case X86::CVTSI2SDrr: 3655 case X86::CVTSI2SD64rr: 3656 case X86::CVTSD2SSrr: 3657 case X86::Int_CVTSD2SSrr: 3658 case X86::CVTSS2SDrr: 3659 case X86::Int_CVTSS2SDrr: 3660 case X86::RCPSSr: 3661 case X86::RCPSSr_Int: 3662 case X86::ROUNDSDr: 3663 case X86::ROUNDSDr_Int: 3664 case X86::ROUNDSSr: 3665 case X86::ROUNDSSr_Int: 3666 case X86::RSQRTSSr: 3667 case X86::RSQRTSSr_Int: 3668 case X86::SQRTSSr: 3669 case X86::SQRTSSr_Int: 3670 // AVX encoded versions 3671 case X86::VCVTSD2SSrr: 3672 case X86::Int_VCVTSD2SSrr: 3673 case X86::VCVTSS2SDrr: 3674 case X86::Int_VCVTSS2SDrr: 3675 case X86::VRCPSSr: 3676 case X86::VROUNDSDr: 3677 case X86::VROUNDSDr_Int: 3678 case X86::VROUNDSSr: 3679 case X86::VROUNDSSr_Int: 3680 case X86::VRSQRTSSr: 3681 case X86::VSQRTSSr: 3682 return true; 3683 } 3684 3685 return false; 3686 } 3687 3688 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 3689 /// instructions we would like before a partial register update. 3690 unsigned X86InstrInfo:: 3691 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3692 const TargetRegisterInfo *TRI) const { 3693 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 3694 return 0; 3695 3696 // If MI is marked as reading Reg, the partial register update is wanted. 3697 const MachineOperand &MO = MI->getOperand(0); 3698 unsigned Reg = MO.getReg(); 3699 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3700 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 3701 return 0; 3702 } else { 3703 if (MI->readsRegister(Reg, TRI)) 3704 return 0; 3705 } 3706 3707 // If any of the preceding 16 instructions are reading Reg, insert a 3708 // dependency breaking instruction. The magic number is based on a few 3709 // Nehalem experiments. 3710 return 16; 3711 } 3712 3713 void X86InstrInfo:: 3714 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 3715 const TargetRegisterInfo *TRI) const { 3716 unsigned Reg = MI->getOperand(OpNum).getReg(); 3717 if (X86::VR128RegClass.contains(Reg)) { 3718 // These instructions are all floating point domain, so xorps is the best 3719 // choice. 3720 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3721 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 3722 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 3723 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3724 } else if (X86::VR256RegClass.contains(Reg)) { 3725 // Use vxorps to clear the full ymm register. 3726 // It wants to read and write the xmm sub-register. 3727 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 3728 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 3729 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 3730 .addReg(Reg, RegState::ImplicitDefine); 3731 } else 3732 return; 3733 MI->addRegisterKilled(Reg, TRI, true); 3734 } 3735 3736 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3737 MachineInstr *MI, 3738 const SmallVectorImpl<unsigned> &Ops, 3739 int FrameIndex) const { 3740 // Check switch flag 3741 if (NoFusing) return NULL; 3742 3743 // Unless optimizing for size, don't fold to avoid partial 3744 // register update stalls 3745 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) && 3746 hasPartialRegUpdate(MI->getOpcode())) 3747 return 0; 3748 3749 const MachineFrameInfo *MFI = MF.getFrameInfo(); 3750 unsigned Size = MFI->getObjectSize(FrameIndex); 3751 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 3752 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3753 unsigned NewOpc = 0; 3754 unsigned RCSize = 0; 3755 switch (MI->getOpcode()) { 3756 default: return NULL; 3757 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 3758 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 3759 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 3760 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 3761 } 3762 // Check if it's safe to fold the load. If the size of the object is 3763 // narrower than the load width, then it's not. 3764 if (Size < RCSize) 3765 return NULL; 3766 // Change to CMPXXri r, 0 first. 3767 MI->setDesc(get(NewOpc)); 3768 MI->getOperand(1).ChangeToImmediate(0); 3769 } else if (Ops.size() != 1) 3770 return NULL; 3771 3772 SmallVector<MachineOperand,4> MOs; 3773 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 3774 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 3775 } 3776 3777 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3778 MachineInstr *MI, 3779 const SmallVectorImpl<unsigned> &Ops, 3780 MachineInstr *LoadMI) const { 3781 // Check switch flag 3782 if (NoFusing) return NULL; 3783 3784 // Unless optimizing for size, don't fold to avoid partial 3785 // register update stalls 3786 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) && 3787 hasPartialRegUpdate(MI->getOpcode())) 3788 return 0; 3789 3790 // Determine the alignment of the load. 3791 unsigned Alignment = 0; 3792 if (LoadMI->hasOneMemOperand()) 3793 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 3794 else 3795 switch (LoadMI->getOpcode()) { 3796 case X86::AVX_SET0PSY: 3797 case X86::AVX_SET0PDY: 3798 case X86::AVX2_SETALLONES: 3799 case X86::AVX2_SET0: 3800 Alignment = 32; 3801 break; 3802 case X86::V_SET0: 3803 case X86::V_SETALLONES: 3804 case X86::AVX_SETALLONES: 3805 Alignment = 16; 3806 break; 3807 case X86::FsFLD0SD: 3808 Alignment = 8; 3809 break; 3810 case X86::FsFLD0SS: 3811 Alignment = 4; 3812 break; 3813 default: 3814 return 0; 3815 } 3816 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3817 unsigned NewOpc = 0; 3818 switch (MI->getOpcode()) { 3819 default: return NULL; 3820 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 3821 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 3822 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 3823 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 3824 } 3825 // Change to CMPXXri r, 0 first. 3826 MI->setDesc(get(NewOpc)); 3827 MI->getOperand(1).ChangeToImmediate(0); 3828 } else if (Ops.size() != 1) 3829 return NULL; 3830 3831 // Make sure the subregisters match. 3832 // Otherwise we risk changing the size of the load. 3833 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 3834 return NULL; 3835 3836 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 3837 switch (LoadMI->getOpcode()) { 3838 case X86::V_SET0: 3839 case X86::V_SETALLONES: 3840 case X86::AVX_SET0PSY: 3841 case X86::AVX_SET0PDY: 3842 case X86::AVX_SETALLONES: 3843 case X86::AVX2_SETALLONES: 3844 case X86::AVX2_SET0: 3845 case X86::FsFLD0SD: 3846 case X86::FsFLD0SS: { 3847 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 3848 // Create a constant-pool entry and operands to load from it. 3849 3850 // Medium and large mode can't fold loads this way. 3851 if (TM.getCodeModel() != CodeModel::Small && 3852 TM.getCodeModel() != CodeModel::Kernel) 3853 return NULL; 3854 3855 // x86-32 PIC requires a PIC base register for constant pools. 3856 unsigned PICBase = 0; 3857 if (TM.getRelocationModel() == Reloc::PIC_) { 3858 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 3859 PICBase = X86::RIP; 3860 else 3861 // FIXME: PICBase = getGlobalBaseReg(&MF); 3862 // This doesn't work for several reasons. 3863 // 1. GlobalBaseReg may have been spilled. 3864 // 2. It may not be live at MI. 3865 return NULL; 3866 } 3867 3868 // Create a constant-pool entry. 3869 MachineConstantPool &MCP = *MF.getConstantPool(); 3870 Type *Ty; 3871 unsigned Opc = LoadMI->getOpcode(); 3872 if (Opc == X86::FsFLD0SS) 3873 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 3874 else if (Opc == X86::FsFLD0SD) 3875 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 3876 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY) 3877 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8); 3878 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0) 3879 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 3880 else 3881 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 3882 3883 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES || 3884 Opc == X86::AVX2_SETALLONES); 3885 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 3886 Constant::getNullValue(Ty); 3887 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 3888 3889 // Create operands to load from the constant pool entry. 3890 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 3891 MOs.push_back(MachineOperand::CreateImm(1)); 3892 MOs.push_back(MachineOperand::CreateReg(0, false)); 3893 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 3894 MOs.push_back(MachineOperand::CreateReg(0, false)); 3895 break; 3896 } 3897 default: { 3898 // Folding a normal load. Just copy the load's address operands. 3899 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 3900 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 3901 MOs.push_back(LoadMI->getOperand(i)); 3902 break; 3903 } 3904 } 3905 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 3906 } 3907 3908 3909 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 3910 const SmallVectorImpl<unsigned> &Ops) const { 3911 // Check switch flag 3912 if (NoFusing) return 0; 3913 3914 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3915 switch (MI->getOpcode()) { 3916 default: return false; 3917 case X86::TEST8rr: 3918 case X86::TEST16rr: 3919 case X86::TEST32rr: 3920 case X86::TEST64rr: 3921 return true; 3922 case X86::ADD32ri: 3923 // FIXME: AsmPrinter doesn't know how to handle 3924 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3925 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3926 return false; 3927 break; 3928 } 3929 } 3930 3931 if (Ops.size() != 1) 3932 return false; 3933 3934 unsigned OpNum = Ops[0]; 3935 unsigned Opc = MI->getOpcode(); 3936 unsigned NumOps = MI->getDesc().getNumOperands(); 3937 bool isTwoAddr = NumOps > 1 && 3938 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3939 3940 // Folding a memory location into the two-address part of a two-address 3941 // instruction is different than folding it other places. It requires 3942 // replacing the *two* registers with the memory location. 3943 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3944 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 3945 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3946 } else if (OpNum == 0) { // If operand 0 3947 switch (Opc) { 3948 case X86::MOV8r0: 3949 case X86::MOV16r0: 3950 case X86::MOV32r0: 3951 case X86::MOV64r0: return true; 3952 default: break; 3953 } 3954 OpcodeTablePtr = &RegOp2MemOpTable0; 3955 } else if (OpNum == 1) { 3956 OpcodeTablePtr = &RegOp2MemOpTable1; 3957 } else if (OpNum == 2) { 3958 OpcodeTablePtr = &RegOp2MemOpTable2; 3959 } 3960 3961 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 3962 return true; 3963 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); 3964 } 3965 3966 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 3967 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 3968 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3969 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3970 MemOp2RegOpTable.find(MI->getOpcode()); 3971 if (I == MemOp2RegOpTable.end()) 3972 return false; 3973 unsigned Opc = I->second.first; 3974 unsigned Index = I->second.second & TB_INDEX_MASK; 3975 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 3976 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 3977 if (UnfoldLoad && !FoldedLoad) 3978 return false; 3979 UnfoldLoad &= FoldedLoad; 3980 if (UnfoldStore && !FoldedStore) 3981 return false; 3982 UnfoldStore &= FoldedStore; 3983 3984 const MCInstrDesc &MCID = get(Opc); 3985 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 3986 if (!MI->hasOneMemOperand() && 3987 RC == &X86::VR128RegClass && 3988 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 3989 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 3990 // conservatively assume the address is unaligned. That's bad for 3991 // performance. 3992 return false; 3993 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 3994 SmallVector<MachineOperand,2> BeforeOps; 3995 SmallVector<MachineOperand,2> AfterOps; 3996 SmallVector<MachineOperand,4> ImpOps; 3997 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3998 MachineOperand &Op = MI->getOperand(i); 3999 if (i >= Index && i < Index + X86::AddrNumOperands) 4000 AddrOps.push_back(Op); 4001 else if (Op.isReg() && Op.isImplicit()) 4002 ImpOps.push_back(Op); 4003 else if (i < Index) 4004 BeforeOps.push_back(Op); 4005 else if (i > Index) 4006 AfterOps.push_back(Op); 4007 } 4008 4009 // Emit the load instruction. 4010 if (UnfoldLoad) { 4011 std::pair<MachineInstr::mmo_iterator, 4012 MachineInstr::mmo_iterator> MMOs = 4013 MF.extractLoadMemRefs(MI->memoperands_begin(), 4014 MI->memoperands_end()); 4015 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4016 if (UnfoldStore) { 4017 // Address operands cannot be marked isKill. 4018 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4019 MachineOperand &MO = NewMIs[0]->getOperand(i); 4020 if (MO.isReg()) 4021 MO.setIsKill(false); 4022 } 4023 } 4024 } 4025 4026 // Emit the data processing instruction. 4027 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4028 MachineInstrBuilder MIB(DataMI); 4029 4030 if (FoldedStore) 4031 MIB.addReg(Reg, RegState::Define); 4032 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4033 MIB.addOperand(BeforeOps[i]); 4034 if (FoldedLoad) 4035 MIB.addReg(Reg); 4036 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4037 MIB.addOperand(AfterOps[i]); 4038 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4039 MachineOperand &MO = ImpOps[i]; 4040 MIB.addReg(MO.getReg(), 4041 getDefRegState(MO.isDef()) | 4042 RegState::Implicit | 4043 getKillRegState(MO.isKill()) | 4044 getDeadRegState(MO.isDead()) | 4045 getUndefRegState(MO.isUndef())); 4046 } 4047 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4048 switch (DataMI->getOpcode()) { 4049 default: break; 4050 case X86::CMP64ri32: 4051 case X86::CMP64ri8: 4052 case X86::CMP32ri: 4053 case X86::CMP32ri8: 4054 case X86::CMP16ri: 4055 case X86::CMP16ri8: 4056 case X86::CMP8ri: { 4057 MachineOperand &MO0 = DataMI->getOperand(0); 4058 MachineOperand &MO1 = DataMI->getOperand(1); 4059 if (MO1.getImm() == 0) { 4060 unsigned NewOpc; 4061 switch (DataMI->getOpcode()) { 4062 default: llvm_unreachable("Unreachable!"); 4063 case X86::CMP64ri8: 4064 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4065 case X86::CMP32ri8: 4066 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4067 case X86::CMP16ri8: 4068 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4069 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4070 } 4071 DataMI->setDesc(get(NewOpc)); 4072 MO1.ChangeToRegister(MO0.getReg(), false); 4073 } 4074 } 4075 } 4076 NewMIs.push_back(DataMI); 4077 4078 // Emit the store instruction. 4079 if (UnfoldStore) { 4080 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4081 std::pair<MachineInstr::mmo_iterator, 4082 MachineInstr::mmo_iterator> MMOs = 4083 MF.extractStoreMemRefs(MI->memoperands_begin(), 4084 MI->memoperands_end()); 4085 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4086 } 4087 4088 return true; 4089 } 4090 4091 bool 4092 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4093 SmallVectorImpl<SDNode*> &NewNodes) const { 4094 if (!N->isMachineOpcode()) 4095 return false; 4096 4097 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4098 MemOp2RegOpTable.find(N->getMachineOpcode()); 4099 if (I == MemOp2RegOpTable.end()) 4100 return false; 4101 unsigned Opc = I->second.first; 4102 unsigned Index = I->second.second & TB_INDEX_MASK; 4103 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4104 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4105 const MCInstrDesc &MCID = get(Opc); 4106 MachineFunction &MF = DAG.getMachineFunction(); 4107 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4108 unsigned NumDefs = MCID.NumDefs; 4109 std::vector<SDValue> AddrOps; 4110 std::vector<SDValue> BeforeOps; 4111 std::vector<SDValue> AfterOps; 4112 DebugLoc dl = N->getDebugLoc(); 4113 unsigned NumOps = N->getNumOperands(); 4114 for (unsigned i = 0; i != NumOps-1; ++i) { 4115 SDValue Op = N->getOperand(i); 4116 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4117 AddrOps.push_back(Op); 4118 else if (i < Index-NumDefs) 4119 BeforeOps.push_back(Op); 4120 else if (i > Index-NumDefs) 4121 AfterOps.push_back(Op); 4122 } 4123 SDValue Chain = N->getOperand(NumOps-1); 4124 AddrOps.push_back(Chain); 4125 4126 // Emit the load instruction. 4127 SDNode *Load = 0; 4128 if (FoldedLoad) { 4129 EVT VT = *RC->vt_begin(); 4130 std::pair<MachineInstr::mmo_iterator, 4131 MachineInstr::mmo_iterator> MMOs = 4132 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4133 cast<MachineSDNode>(N)->memoperands_end()); 4134 if (!(*MMOs.first) && 4135 RC == &X86::VR128RegClass && 4136 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4137 // Do not introduce a slow unaligned load. 4138 return false; 4139 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4140 bool isAligned = (*MMOs.first) && 4141 (*MMOs.first)->getAlignment() >= Alignment; 4142 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 4143 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 4144 NewNodes.push_back(Load); 4145 4146 // Preserve memory reference information. 4147 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4148 } 4149 4150 // Emit the data processing instruction. 4151 std::vector<EVT> VTs; 4152 const TargetRegisterClass *DstRC = 0; 4153 if (MCID.getNumDefs() > 0) { 4154 DstRC = getRegClass(MCID, 0, &RI, MF); 4155 VTs.push_back(*DstRC->vt_begin()); 4156 } 4157 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4158 EVT VT = N->getValueType(i); 4159 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4160 VTs.push_back(VT); 4161 } 4162 if (Load) 4163 BeforeOps.push_back(SDValue(Load, 0)); 4164 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4165 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 4166 BeforeOps.size()); 4167 NewNodes.push_back(NewNode); 4168 4169 // Emit the store instruction. 4170 if (FoldedStore) { 4171 AddrOps.pop_back(); 4172 AddrOps.push_back(SDValue(NewNode, 0)); 4173 AddrOps.push_back(Chain); 4174 std::pair<MachineInstr::mmo_iterator, 4175 MachineInstr::mmo_iterator> MMOs = 4176 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4177 cast<MachineSDNode>(N)->memoperands_end()); 4178 if (!(*MMOs.first) && 4179 RC == &X86::VR128RegClass && 4180 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4181 // Do not introduce a slow unaligned store. 4182 return false; 4183 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4184 bool isAligned = (*MMOs.first) && 4185 (*MMOs.first)->getAlignment() >= Alignment; 4186 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 4187 isAligned, TM), 4188 dl, MVT::Other, 4189 &AddrOps[0], AddrOps.size()); 4190 NewNodes.push_back(Store); 4191 4192 // Preserve memory reference information. 4193 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4194 } 4195 4196 return true; 4197 } 4198 4199 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4200 bool UnfoldLoad, bool UnfoldStore, 4201 unsigned *LoadRegIndex) const { 4202 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4203 MemOp2RegOpTable.find(Opc); 4204 if (I == MemOp2RegOpTable.end()) 4205 return 0; 4206 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4207 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4208 if (UnfoldLoad && !FoldedLoad) 4209 return 0; 4210 if (UnfoldStore && !FoldedStore) 4211 return 0; 4212 if (LoadRegIndex) 4213 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4214 return I->second.first; 4215 } 4216 4217 bool 4218 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4219 int64_t &Offset1, int64_t &Offset2) const { 4220 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4221 return false; 4222 unsigned Opc1 = Load1->getMachineOpcode(); 4223 unsigned Opc2 = Load2->getMachineOpcode(); 4224 switch (Opc1) { 4225 default: return false; 4226 case X86::MOV8rm: 4227 case X86::MOV16rm: 4228 case X86::MOV32rm: 4229 case X86::MOV64rm: 4230 case X86::LD_Fp32m: 4231 case X86::LD_Fp64m: 4232 case X86::LD_Fp80m: 4233 case X86::MOVSSrm: 4234 case X86::MOVSDrm: 4235 case X86::MMX_MOVD64rm: 4236 case X86::MMX_MOVQ64rm: 4237 case X86::FsMOVAPSrm: 4238 case X86::FsMOVAPDrm: 4239 case X86::MOVAPSrm: 4240 case X86::MOVUPSrm: 4241 case X86::MOVAPDrm: 4242 case X86::MOVDQArm: 4243 case X86::MOVDQUrm: 4244 // AVX load instructions 4245 case X86::VMOVSSrm: 4246 case X86::VMOVSDrm: 4247 case X86::FsVMOVAPSrm: 4248 case X86::FsVMOVAPDrm: 4249 case X86::VMOVAPSrm: 4250 case X86::VMOVUPSrm: 4251 case X86::VMOVAPDrm: 4252 case X86::VMOVDQArm: 4253 case X86::VMOVDQUrm: 4254 case X86::VMOVAPSYrm: 4255 case X86::VMOVUPSYrm: 4256 case X86::VMOVAPDYrm: 4257 case X86::VMOVDQAYrm: 4258 case X86::VMOVDQUYrm: 4259 break; 4260 } 4261 switch (Opc2) { 4262 default: return false; 4263 case X86::MOV8rm: 4264 case X86::MOV16rm: 4265 case X86::MOV32rm: 4266 case X86::MOV64rm: 4267 case X86::LD_Fp32m: 4268 case X86::LD_Fp64m: 4269 case X86::LD_Fp80m: 4270 case X86::MOVSSrm: 4271 case X86::MOVSDrm: 4272 case X86::MMX_MOVD64rm: 4273 case X86::MMX_MOVQ64rm: 4274 case X86::FsMOVAPSrm: 4275 case X86::FsMOVAPDrm: 4276 case X86::MOVAPSrm: 4277 case X86::MOVUPSrm: 4278 case X86::MOVAPDrm: 4279 case X86::MOVDQArm: 4280 case X86::MOVDQUrm: 4281 // AVX load instructions 4282 case X86::VMOVSSrm: 4283 case X86::VMOVSDrm: 4284 case X86::FsVMOVAPSrm: 4285 case X86::FsVMOVAPDrm: 4286 case X86::VMOVAPSrm: 4287 case X86::VMOVUPSrm: 4288 case X86::VMOVAPDrm: 4289 case X86::VMOVDQArm: 4290 case X86::VMOVDQUrm: 4291 case X86::VMOVAPSYrm: 4292 case X86::VMOVUPSYrm: 4293 case X86::VMOVAPDYrm: 4294 case X86::VMOVDQAYrm: 4295 case X86::VMOVDQUYrm: 4296 break; 4297 } 4298 4299 // Check if chain operands and base addresses match. 4300 if (Load1->getOperand(0) != Load2->getOperand(0) || 4301 Load1->getOperand(5) != Load2->getOperand(5)) 4302 return false; 4303 // Segment operands should match as well. 4304 if (Load1->getOperand(4) != Load2->getOperand(4)) 4305 return false; 4306 // Scale should be 1, Index should be Reg0. 4307 if (Load1->getOperand(1) == Load2->getOperand(1) && 4308 Load1->getOperand(2) == Load2->getOperand(2)) { 4309 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4310 return false; 4311 4312 // Now let's examine the displacements. 4313 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4314 isa<ConstantSDNode>(Load2->getOperand(3))) { 4315 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4316 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4317 return true; 4318 } 4319 } 4320 return false; 4321 } 4322 4323 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4324 int64_t Offset1, int64_t Offset2, 4325 unsigned NumLoads) const { 4326 assert(Offset2 > Offset1); 4327 if ((Offset2 - Offset1) / 8 > 64) 4328 return false; 4329 4330 unsigned Opc1 = Load1->getMachineOpcode(); 4331 unsigned Opc2 = Load2->getMachineOpcode(); 4332 if (Opc1 != Opc2) 4333 return false; // FIXME: overly conservative? 4334 4335 switch (Opc1) { 4336 default: break; 4337 case X86::LD_Fp32m: 4338 case X86::LD_Fp64m: 4339 case X86::LD_Fp80m: 4340 case X86::MMX_MOVD64rm: 4341 case X86::MMX_MOVQ64rm: 4342 return false; 4343 } 4344 4345 EVT VT = Load1->getValueType(0); 4346 switch (VT.getSimpleVT().SimpleTy) { 4347 default: 4348 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4349 // have 16 of them to play with. 4350 if (TM.getSubtargetImpl()->is64Bit()) { 4351 if (NumLoads >= 3) 4352 return false; 4353 } else if (NumLoads) { 4354 return false; 4355 } 4356 break; 4357 case MVT::i8: 4358 case MVT::i16: 4359 case MVT::i32: 4360 case MVT::i64: 4361 case MVT::f32: 4362 case MVT::f64: 4363 if (NumLoads) 4364 return false; 4365 break; 4366 } 4367 4368 return true; 4369 } 4370 4371 4372 bool X86InstrInfo:: 4373 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4374 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 4375 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 4376 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 4377 return true; 4378 Cond[0].setImm(GetOppositeBranchCondition(CC)); 4379 return false; 4380 } 4381 4382 bool X86InstrInfo:: 4383 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 4384 // FIXME: Return false for x87 stack register classes for now. We can't 4385 // allow any loads of these registers before FpGet_ST0_80. 4386 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 4387 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 4388 } 4389 4390 /// getGlobalBaseReg - Return a virtual register initialized with the 4391 /// the global base register value. Output instructions required to 4392 /// initialize the register in the function entry block, if necessary. 4393 /// 4394 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 4395 /// 4396 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 4397 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 4398 "X86-64 PIC uses RIP relative addressing"); 4399 4400 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 4401 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4402 if (GlobalBaseReg != 0) 4403 return GlobalBaseReg; 4404 4405 // Create the register. The code to initialize it is inserted 4406 // later, by the CGBR pass (below). 4407 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4408 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4409 X86FI->setGlobalBaseReg(GlobalBaseReg); 4410 return GlobalBaseReg; 4411 } 4412 4413 // These are the replaceable SSE instructions. Some of these have Int variants 4414 // that we don't include here. We don't want to replace instructions selected 4415 // by intrinsics. 4416 static const uint16_t ReplaceableInstrs[][3] = { 4417 //PackedSingle PackedDouble PackedInt 4418 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 4419 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 4420 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 4421 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 4422 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 4423 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 4424 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 4425 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 4426 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 4427 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 4428 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 4429 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 4430 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 4431 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 4432 // AVX 128-bit support 4433 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 4434 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 4435 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 4436 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 4437 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 4438 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 4439 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 4440 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 4441 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 4442 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 4443 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 4444 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 4445 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 4446 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 4447 // AVX 256-bit support 4448 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 4449 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 4450 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 4451 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 4452 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 4453 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 4454 }; 4455 4456 static const uint16_t ReplaceableInstrsAVX2[][3] = { 4457 //PackedSingle PackedDouble PackedInt 4458 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 4459 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 4460 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 4461 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 4462 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 4463 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 4464 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 4465 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 4466 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 4467 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 4468 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 4469 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 4470 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 4471 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr } 4472 }; 4473 4474 // FIXME: Some shuffle and unpack instructions have equivalents in different 4475 // domains, but they require a bit more work than just switching opcodes. 4476 4477 static const uint16_t *lookup(unsigned opcode, unsigned domain) { 4478 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 4479 if (ReplaceableInstrs[i][domain-1] == opcode) 4480 return ReplaceableInstrs[i]; 4481 return 0; 4482 } 4483 4484 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 4485 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 4486 if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 4487 return ReplaceableInstrsAVX2[i]; 4488 return 0; 4489 } 4490 4491 std::pair<uint16_t, uint16_t> 4492 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 4493 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4494 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2(); 4495 uint16_t validDomains = 0; 4496 if (domain && lookup(MI->getOpcode(), domain)) 4497 validDomains = 0xe; 4498 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 4499 validDomains = hasAVX2 ? 0xe : 0x6; 4500 return std::make_pair(domain, validDomains); 4501 } 4502 4503 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4504 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 4505 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4506 assert(dom && "Not an SSE instruction"); 4507 const uint16_t *table = lookup(MI->getOpcode(), dom); 4508 if (!table) { // try the other table 4509 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) && 4510 "256-bit vector operations only available in AVX2"); 4511 table = lookupAVX2(MI->getOpcode(), dom); 4512 } 4513 assert(table && "Cannot change domain"); 4514 MI->setDesc(get(table[Domain-1])); 4515 } 4516 4517 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 4518 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 4519 NopInst.setOpcode(X86::NOOP); 4520 } 4521 4522 bool X86InstrInfo::isHighLatencyDef(int opc) const { 4523 switch (opc) { 4524 default: return false; 4525 case X86::DIVSDrm: 4526 case X86::DIVSDrm_Int: 4527 case X86::DIVSDrr: 4528 case X86::DIVSDrr_Int: 4529 case X86::DIVSSrm: 4530 case X86::DIVSSrm_Int: 4531 case X86::DIVSSrr: 4532 case X86::DIVSSrr_Int: 4533 case X86::SQRTPDm: 4534 case X86::SQRTPDm_Int: 4535 case X86::SQRTPDr: 4536 case X86::SQRTPDr_Int: 4537 case X86::SQRTPSm: 4538 case X86::SQRTPSm_Int: 4539 case X86::SQRTPSr: 4540 case X86::SQRTPSr_Int: 4541 case X86::SQRTSDm: 4542 case X86::SQRTSDm_Int: 4543 case X86::SQRTSDr: 4544 case X86::SQRTSDr_Int: 4545 case X86::SQRTSSm: 4546 case X86::SQRTSSm_Int: 4547 case X86::SQRTSSr: 4548 case X86::SQRTSSr_Int: 4549 // AVX instructions with high latency 4550 case X86::VDIVSDrm: 4551 case X86::VDIVSDrm_Int: 4552 case X86::VDIVSDrr: 4553 case X86::VDIVSDrr_Int: 4554 case X86::VDIVSSrm: 4555 case X86::VDIVSSrm_Int: 4556 case X86::VDIVSSrr: 4557 case X86::VDIVSSrr_Int: 4558 case X86::VSQRTPDm: 4559 case X86::VSQRTPDm_Int: 4560 case X86::VSQRTPDr: 4561 case X86::VSQRTPDr_Int: 4562 case X86::VSQRTPSm: 4563 case X86::VSQRTPSm_Int: 4564 case X86::VSQRTPSr: 4565 case X86::VSQRTPSr_Int: 4566 case X86::VSQRTSDm: 4567 case X86::VSQRTSDm_Int: 4568 case X86::VSQRTSDr: 4569 case X86::VSQRTSSm: 4570 case X86::VSQRTSSm_Int: 4571 case X86::VSQRTSSr: 4572 return true; 4573 } 4574 } 4575 4576 bool X86InstrInfo:: 4577 hasHighOperandLatency(const InstrItineraryData *ItinData, 4578 const MachineRegisterInfo *MRI, 4579 const MachineInstr *DefMI, unsigned DefIdx, 4580 const MachineInstr *UseMI, unsigned UseIdx) const { 4581 return isHighLatencyDef(DefMI->getOpcode()); 4582 } 4583 4584 namespace { 4585 /// CGBR - Create Global Base Reg pass. This initializes the PIC 4586 /// global base register for x86-32. 4587 struct CGBR : public MachineFunctionPass { 4588 static char ID; 4589 CGBR() : MachineFunctionPass(ID) {} 4590 4591 virtual bool runOnMachineFunction(MachineFunction &MF) { 4592 const X86TargetMachine *TM = 4593 static_cast<const X86TargetMachine *>(&MF.getTarget()); 4594 4595 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 4596 "X86-64 PIC uses RIP relative addressing"); 4597 4598 // Only emit a global base reg in PIC mode. 4599 if (TM->getRelocationModel() != Reloc::PIC_) 4600 return false; 4601 4602 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 4603 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4604 4605 // If we didn't need a GlobalBaseReg, don't insert code. 4606 if (GlobalBaseReg == 0) 4607 return false; 4608 4609 // Insert the set of GlobalBaseReg into the first MBB of the function 4610 MachineBasicBlock &FirstMBB = MF.front(); 4611 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 4612 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 4613 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4614 const X86InstrInfo *TII = TM->getInstrInfo(); 4615 4616 unsigned PC; 4617 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 4618 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4619 else 4620 PC = GlobalBaseReg; 4621 4622 // Operand of MovePCtoStack is completely ignored by asm printer. It's 4623 // only used in JIT code emission as displacement to pc. 4624 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 4625 4626 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 4627 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 4628 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 4629 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 4630 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 4631 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 4632 X86II::MO_GOT_ABSOLUTE_ADDRESS); 4633 } 4634 4635 return true; 4636 } 4637 4638 virtual const char *getPassName() const { 4639 return "X86 PIC Global Base Reg Initialization"; 4640 } 4641 4642 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4643 AU.setPreservesCFG(); 4644 MachineFunctionPass::getAnalysisUsage(AU); 4645 } 4646 }; 4647 } 4648 4649 char CGBR::ID = 0; 4650 FunctionPass* 4651 llvm::createGlobalBaseRegPass() { return new CGBR(); } 4652 4653 namespace { 4654 struct LDTLSCleanup : public MachineFunctionPass { 4655 static char ID; 4656 LDTLSCleanup() : MachineFunctionPass(ID) {} 4657 4658 virtual bool runOnMachineFunction(MachineFunction &MF) { 4659 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 4660 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 4661 // No point folding accesses if there isn't at least two. 4662 return false; 4663 } 4664 4665 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 4666 return VisitNode(DT->getRootNode(), 0); 4667 } 4668 4669 // Visit the dominator subtree rooted at Node in pre-order. 4670 // If TLSBaseAddrReg is non-null, then use that to replace any 4671 // TLS_base_addr instructions. Otherwise, create the register 4672 // when the first such instruction is seen, and then use it 4673 // as we encounter more instructions. 4674 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 4675 MachineBasicBlock *BB = Node->getBlock(); 4676 bool Changed = false; 4677 4678 // Traverse the current block. 4679 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 4680 ++I) { 4681 switch (I->getOpcode()) { 4682 case X86::TLS_base_addr32: 4683 case X86::TLS_base_addr64: 4684 if (TLSBaseAddrReg) 4685 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 4686 else 4687 I = SetRegister(I, &TLSBaseAddrReg); 4688 Changed = true; 4689 break; 4690 default: 4691 break; 4692 } 4693 } 4694 4695 // Visit the children of this block in the dominator tree. 4696 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 4697 I != E; ++I) { 4698 Changed |= VisitNode(*I, TLSBaseAddrReg); 4699 } 4700 4701 return Changed; 4702 } 4703 4704 // Replace the TLS_base_addr instruction I with a copy from 4705 // TLSBaseAddrReg, returning the new instruction. 4706 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 4707 unsigned TLSBaseAddrReg) { 4708 MachineFunction *MF = I->getParent()->getParent(); 4709 const X86TargetMachine *TM = 4710 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4711 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4712 const X86InstrInfo *TII = TM->getInstrInfo(); 4713 4714 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 4715 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 4716 TII->get(TargetOpcode::COPY), 4717 is64Bit ? X86::RAX : X86::EAX) 4718 .addReg(TLSBaseAddrReg); 4719 4720 // Erase the TLS_base_addr instruction. 4721 I->eraseFromParent(); 4722 4723 return Copy; 4724 } 4725 4726 // Create a virtal register in *TLSBaseAddrReg, and populate it by 4727 // inserting a copy instruction after I. Returns the new instruction. 4728 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 4729 MachineFunction *MF = I->getParent()->getParent(); 4730 const X86TargetMachine *TM = 4731 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4732 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4733 const X86InstrInfo *TII = TM->getInstrInfo(); 4734 4735 // Create a virtual register for the TLS base address. 4736 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4737 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 4738 ? &X86::GR64RegClass 4739 : &X86::GR32RegClass); 4740 4741 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 4742 MachineInstr *Next = I->getNextNode(); 4743 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 4744 TII->get(TargetOpcode::COPY), 4745 *TLSBaseAddrReg) 4746 .addReg(is64Bit ? X86::RAX : X86::EAX); 4747 4748 return Copy; 4749 } 4750 4751 virtual const char *getPassName() const { 4752 return "Local Dynamic TLS Access Clean-up"; 4753 } 4754 4755 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4756 AU.setPreservesCFG(); 4757 AU.addRequired<MachineDominatorTree>(); 4758 MachineFunctionPass::getAnalysisUsage(AU); 4759 } 4760 }; 4761 } 4762 4763 char LDTLSCleanup::ID = 0; 4764 FunctionPass* 4765 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 4766