1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DebugInfoMetadata.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     Register &SrcReg, Register &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139   switch (MI.getOpcode()) {
140   default:
141     // By default, assume that the instruction is not data invariant.
142     return false;
143 
144     // Some target-independent operations that trivially lower to data-invariant
145     // instructions.
146   case TargetOpcode::COPY:
147   case TargetOpcode::INSERT_SUBREG:
148   case TargetOpcode::SUBREG_TO_REG:
149     return true;
150 
151   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152   // However, they set flags and are perhaps the most surprisingly constant
153   // time operations so we call them out here separately.
154   case X86::IMUL16rr:
155   case X86::IMUL16rri8:
156   case X86::IMUL16rri:
157   case X86::IMUL32rr:
158   case X86::IMUL32rri8:
159   case X86::IMUL32rri:
160   case X86::IMUL64rr:
161   case X86::IMUL64rri32:
162   case X86::IMUL64rri8:
163 
164   // Bit scanning and counting instructions that are somewhat surprisingly
165   // constant time as they scan across bits and do other fairly complex
166   // operations like popcnt, but are believed to be constant time on x86.
167   // However, these set flags.
168   case X86::BSF16rr:
169   case X86::BSF32rr:
170   case X86::BSF64rr:
171   case X86::BSR16rr:
172   case X86::BSR32rr:
173   case X86::BSR64rr:
174   case X86::LZCNT16rr:
175   case X86::LZCNT32rr:
176   case X86::LZCNT64rr:
177   case X86::POPCNT16rr:
178   case X86::POPCNT32rr:
179   case X86::POPCNT64rr:
180   case X86::TZCNT16rr:
181   case X86::TZCNT32rr:
182   case X86::TZCNT64rr:
183 
184   // Bit manipulation instructions are effectively combinations of basic
185   // arithmetic ops, and should still execute in constant time. These also
186   // set flags.
187   case X86::BLCFILL32rr:
188   case X86::BLCFILL64rr:
189   case X86::BLCI32rr:
190   case X86::BLCI64rr:
191   case X86::BLCIC32rr:
192   case X86::BLCIC64rr:
193   case X86::BLCMSK32rr:
194   case X86::BLCMSK64rr:
195   case X86::BLCS32rr:
196   case X86::BLCS64rr:
197   case X86::BLSFILL32rr:
198   case X86::BLSFILL64rr:
199   case X86::BLSI32rr:
200   case X86::BLSI64rr:
201   case X86::BLSIC32rr:
202   case X86::BLSIC64rr:
203   case X86::BLSMSK32rr:
204   case X86::BLSMSK64rr:
205   case X86::BLSR32rr:
206   case X86::BLSR64rr:
207   case X86::TZMSK32rr:
208   case X86::TZMSK64rr:
209 
210   // Bit extracting and clearing instructions should execute in constant time,
211   // and set flags.
212   case X86::BEXTR32rr:
213   case X86::BEXTR64rr:
214   case X86::BEXTRI32ri:
215   case X86::BEXTRI64ri:
216   case X86::BZHI32rr:
217   case X86::BZHI64rr:
218 
219   // Shift and rotate.
220   case X86::ROL8r1:
221   case X86::ROL16r1:
222   case X86::ROL32r1:
223   case X86::ROL64r1:
224   case X86::ROL8rCL:
225   case X86::ROL16rCL:
226   case X86::ROL32rCL:
227   case X86::ROL64rCL:
228   case X86::ROL8ri:
229   case X86::ROL16ri:
230   case X86::ROL32ri:
231   case X86::ROL64ri:
232   case X86::ROR8r1:
233   case X86::ROR16r1:
234   case X86::ROR32r1:
235   case X86::ROR64r1:
236   case X86::ROR8rCL:
237   case X86::ROR16rCL:
238   case X86::ROR32rCL:
239   case X86::ROR64rCL:
240   case X86::ROR8ri:
241   case X86::ROR16ri:
242   case X86::ROR32ri:
243   case X86::ROR64ri:
244   case X86::SAR8r1:
245   case X86::SAR16r1:
246   case X86::SAR32r1:
247   case X86::SAR64r1:
248   case X86::SAR8rCL:
249   case X86::SAR16rCL:
250   case X86::SAR32rCL:
251   case X86::SAR64rCL:
252   case X86::SAR8ri:
253   case X86::SAR16ri:
254   case X86::SAR32ri:
255   case X86::SAR64ri:
256   case X86::SHL8r1:
257   case X86::SHL16r1:
258   case X86::SHL32r1:
259   case X86::SHL64r1:
260   case X86::SHL8rCL:
261   case X86::SHL16rCL:
262   case X86::SHL32rCL:
263   case X86::SHL64rCL:
264   case X86::SHL8ri:
265   case X86::SHL16ri:
266   case X86::SHL32ri:
267   case X86::SHL64ri:
268   case X86::SHR8r1:
269   case X86::SHR16r1:
270   case X86::SHR32r1:
271   case X86::SHR64r1:
272   case X86::SHR8rCL:
273   case X86::SHR16rCL:
274   case X86::SHR32rCL:
275   case X86::SHR64rCL:
276   case X86::SHR8ri:
277   case X86::SHR16ri:
278   case X86::SHR32ri:
279   case X86::SHR64ri:
280   case X86::SHLD16rrCL:
281   case X86::SHLD32rrCL:
282   case X86::SHLD64rrCL:
283   case X86::SHLD16rri8:
284   case X86::SHLD32rri8:
285   case X86::SHLD64rri8:
286   case X86::SHRD16rrCL:
287   case X86::SHRD32rrCL:
288   case X86::SHRD64rrCL:
289   case X86::SHRD16rri8:
290   case X86::SHRD32rri8:
291   case X86::SHRD64rri8:
292 
293   // Basic arithmetic is constant time on the input but does set flags.
294   case X86::ADC8rr:
295   case X86::ADC8ri:
296   case X86::ADC16rr:
297   case X86::ADC16ri:
298   case X86::ADC16ri8:
299   case X86::ADC32rr:
300   case X86::ADC32ri:
301   case X86::ADC32ri8:
302   case X86::ADC64rr:
303   case X86::ADC64ri8:
304   case X86::ADC64ri32:
305   case X86::ADD8rr:
306   case X86::ADD8ri:
307   case X86::ADD16rr:
308   case X86::ADD16ri:
309   case X86::ADD16ri8:
310   case X86::ADD32rr:
311   case X86::ADD32ri:
312   case X86::ADD32ri8:
313   case X86::ADD64rr:
314   case X86::ADD64ri8:
315   case X86::ADD64ri32:
316   case X86::AND8rr:
317   case X86::AND8ri:
318   case X86::AND16rr:
319   case X86::AND16ri:
320   case X86::AND16ri8:
321   case X86::AND32rr:
322   case X86::AND32ri:
323   case X86::AND32ri8:
324   case X86::AND64rr:
325   case X86::AND64ri8:
326   case X86::AND64ri32:
327   case X86::OR8rr:
328   case X86::OR8ri:
329   case X86::OR16rr:
330   case X86::OR16ri:
331   case X86::OR16ri8:
332   case X86::OR32rr:
333   case X86::OR32ri:
334   case X86::OR32ri8:
335   case X86::OR64rr:
336   case X86::OR64ri8:
337   case X86::OR64ri32:
338   case X86::SBB8rr:
339   case X86::SBB8ri:
340   case X86::SBB16rr:
341   case X86::SBB16ri:
342   case X86::SBB16ri8:
343   case X86::SBB32rr:
344   case X86::SBB32ri:
345   case X86::SBB32ri8:
346   case X86::SBB64rr:
347   case X86::SBB64ri8:
348   case X86::SBB64ri32:
349   case X86::SUB8rr:
350   case X86::SUB8ri:
351   case X86::SUB16rr:
352   case X86::SUB16ri:
353   case X86::SUB16ri8:
354   case X86::SUB32rr:
355   case X86::SUB32ri:
356   case X86::SUB32ri8:
357   case X86::SUB64rr:
358   case X86::SUB64ri8:
359   case X86::SUB64ri32:
360   case X86::XOR8rr:
361   case X86::XOR8ri:
362   case X86::XOR16rr:
363   case X86::XOR16ri:
364   case X86::XOR16ri8:
365   case X86::XOR32rr:
366   case X86::XOR32ri:
367   case X86::XOR32ri8:
368   case X86::XOR64rr:
369   case X86::XOR64ri8:
370   case X86::XOR64ri32:
371   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372   case X86::ADCX32rr:
373   case X86::ADCX64rr:
374   case X86::ADOX32rr:
375   case X86::ADOX64rr:
376   case X86::ANDN32rr:
377   case X86::ANDN64rr:
378   // Unary arithmetic operations.
379   case X86::DEC8r:
380   case X86::DEC16r:
381   case X86::DEC32r:
382   case X86::DEC64r:
383   case X86::INC8r:
384   case X86::INC16r:
385   case X86::INC32r:
386   case X86::INC64r:
387   case X86::NEG8r:
388   case X86::NEG16r:
389   case X86::NEG32r:
390   case X86::NEG64r:
391 
392   // Unlike other arithmetic, NOT doesn't set EFLAGS.
393   case X86::NOT8r:
394   case X86::NOT16r:
395   case X86::NOT32r:
396   case X86::NOT64r:
397 
398   // Various move instructions used to zero or sign extend things. Note that we
399   // intentionally don't support the _NOREX variants as we can't handle that
400   // register constraint anyways.
401   case X86::MOVSX16rr8:
402   case X86::MOVSX32rr8:
403   case X86::MOVSX32rr16:
404   case X86::MOVSX64rr8:
405   case X86::MOVSX64rr16:
406   case X86::MOVSX64rr32:
407   case X86::MOVZX16rr8:
408   case X86::MOVZX32rr8:
409   case X86::MOVZX32rr16:
410   case X86::MOVZX64rr8:
411   case X86::MOVZX64rr16:
412   case X86::MOV32rr:
413 
414   // Arithmetic instructions that are both constant time and don't set flags.
415   case X86::RORX32ri:
416   case X86::RORX64ri:
417   case X86::SARX32rr:
418   case X86::SARX64rr:
419   case X86::SHLX32rr:
420   case X86::SHLX64rr:
421   case X86::SHRX32rr:
422   case X86::SHRX64rr:
423 
424   // LEA doesn't actually access memory, and its arithmetic is constant time.
425   case X86::LEA16r:
426   case X86::LEA32r:
427   case X86::LEA64_32r:
428   case X86::LEA64r:
429     return true;
430   }
431 }
432 
433 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434   switch (MI.getOpcode()) {
435   default:
436     // By default, assume that the load will immediately leak.
437     return false;
438 
439   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440   // However, they set flags and are perhaps the most surprisingly constant
441   // time operations so we call them out here separately.
442   case X86::IMUL16rm:
443   case X86::IMUL16rmi8:
444   case X86::IMUL16rmi:
445   case X86::IMUL32rm:
446   case X86::IMUL32rmi8:
447   case X86::IMUL32rmi:
448   case X86::IMUL64rm:
449   case X86::IMUL64rmi32:
450   case X86::IMUL64rmi8:
451 
452   // Bit scanning and counting instructions that are somewhat surprisingly
453   // constant time as they scan across bits and do other fairly complex
454   // operations like popcnt, but are believed to be constant time on x86.
455   // However, these set flags.
456   case X86::BSF16rm:
457   case X86::BSF32rm:
458   case X86::BSF64rm:
459   case X86::BSR16rm:
460   case X86::BSR32rm:
461   case X86::BSR64rm:
462   case X86::LZCNT16rm:
463   case X86::LZCNT32rm:
464   case X86::LZCNT64rm:
465   case X86::POPCNT16rm:
466   case X86::POPCNT32rm:
467   case X86::POPCNT64rm:
468   case X86::TZCNT16rm:
469   case X86::TZCNT32rm:
470   case X86::TZCNT64rm:
471 
472   // Bit manipulation instructions are effectively combinations of basic
473   // arithmetic ops, and should still execute in constant time. These also
474   // set flags.
475   case X86::BLCFILL32rm:
476   case X86::BLCFILL64rm:
477   case X86::BLCI32rm:
478   case X86::BLCI64rm:
479   case X86::BLCIC32rm:
480   case X86::BLCIC64rm:
481   case X86::BLCMSK32rm:
482   case X86::BLCMSK64rm:
483   case X86::BLCS32rm:
484   case X86::BLCS64rm:
485   case X86::BLSFILL32rm:
486   case X86::BLSFILL64rm:
487   case X86::BLSI32rm:
488   case X86::BLSI64rm:
489   case X86::BLSIC32rm:
490   case X86::BLSIC64rm:
491   case X86::BLSMSK32rm:
492   case X86::BLSMSK64rm:
493   case X86::BLSR32rm:
494   case X86::BLSR64rm:
495   case X86::TZMSK32rm:
496   case X86::TZMSK64rm:
497 
498   // Bit extracting and clearing instructions should execute in constant time,
499   // and set flags.
500   case X86::BEXTR32rm:
501   case X86::BEXTR64rm:
502   case X86::BEXTRI32mi:
503   case X86::BEXTRI64mi:
504   case X86::BZHI32rm:
505   case X86::BZHI64rm:
506 
507   // Basic arithmetic is constant time on the input but does set flags.
508   case X86::ADC8rm:
509   case X86::ADC16rm:
510   case X86::ADC32rm:
511   case X86::ADC64rm:
512   case X86::ADCX32rm:
513   case X86::ADCX64rm:
514   case X86::ADD8rm:
515   case X86::ADD16rm:
516   case X86::ADD32rm:
517   case X86::ADD64rm:
518   case X86::ADOX32rm:
519   case X86::ADOX64rm:
520   case X86::AND8rm:
521   case X86::AND16rm:
522   case X86::AND32rm:
523   case X86::AND64rm:
524   case X86::ANDN32rm:
525   case X86::ANDN64rm:
526   case X86::OR8rm:
527   case X86::OR16rm:
528   case X86::OR32rm:
529   case X86::OR64rm:
530   case X86::SBB8rm:
531   case X86::SBB16rm:
532   case X86::SBB32rm:
533   case X86::SBB64rm:
534   case X86::SUB8rm:
535   case X86::SUB16rm:
536   case X86::SUB32rm:
537   case X86::SUB64rm:
538   case X86::XOR8rm:
539   case X86::XOR16rm:
540   case X86::XOR32rm:
541   case X86::XOR64rm:
542 
543   // Integer multiply w/o affecting flags is still believed to be constant
544   // time on x86. Called out separately as this is among the most surprising
545   // instructions to exhibit that behavior.
546   case X86::MULX32rm:
547   case X86::MULX64rm:
548 
549   // Arithmetic instructions that are both constant time and don't set flags.
550   case X86::RORX32mi:
551   case X86::RORX64mi:
552   case X86::SARX32rm:
553   case X86::SARX64rm:
554   case X86::SHLX32rm:
555   case X86::SHLX64rm:
556   case X86::SHRX32rm:
557   case X86::SHRX64rm:
558 
559   // Conversions are believed to be constant time and don't set flags.
560   case X86::CVTTSD2SI64rm:
561   case X86::VCVTTSD2SI64rm:
562   case X86::VCVTTSD2SI64Zrm:
563   case X86::CVTTSD2SIrm:
564   case X86::VCVTTSD2SIrm:
565   case X86::VCVTTSD2SIZrm:
566   case X86::CVTTSS2SI64rm:
567   case X86::VCVTTSS2SI64rm:
568   case X86::VCVTTSS2SI64Zrm:
569   case X86::CVTTSS2SIrm:
570   case X86::VCVTTSS2SIrm:
571   case X86::VCVTTSS2SIZrm:
572   case X86::CVTSI2SDrm:
573   case X86::VCVTSI2SDrm:
574   case X86::VCVTSI2SDZrm:
575   case X86::CVTSI2SSrm:
576   case X86::VCVTSI2SSrm:
577   case X86::VCVTSI2SSZrm:
578   case X86::CVTSI642SDrm:
579   case X86::VCVTSI642SDrm:
580   case X86::VCVTSI642SDZrm:
581   case X86::CVTSI642SSrm:
582   case X86::VCVTSI642SSrm:
583   case X86::VCVTSI642SSZrm:
584   case X86::CVTSS2SDrm:
585   case X86::VCVTSS2SDrm:
586   case X86::VCVTSS2SDZrm:
587   case X86::CVTSD2SSrm:
588   case X86::VCVTSD2SSrm:
589   case X86::VCVTSD2SSZrm:
590   // AVX512 added unsigned integer conversions.
591   case X86::VCVTTSD2USI64Zrm:
592   case X86::VCVTTSD2USIZrm:
593   case X86::VCVTTSS2USI64Zrm:
594   case X86::VCVTTSS2USIZrm:
595   case X86::VCVTUSI2SDZrm:
596   case X86::VCVTUSI642SDZrm:
597   case X86::VCVTUSI2SSZrm:
598   case X86::VCVTUSI642SSZrm:
599 
600   // Loads to register don't set flags.
601   case X86::MOV8rm:
602   case X86::MOV8rm_NOREX:
603   case X86::MOV16rm:
604   case X86::MOV32rm:
605   case X86::MOV64rm:
606   case X86::MOVSX16rm8:
607   case X86::MOVSX32rm16:
608   case X86::MOVSX32rm8:
609   case X86::MOVSX32rm8_NOREX:
610   case X86::MOVSX64rm16:
611   case X86::MOVSX64rm32:
612   case X86::MOVSX64rm8:
613   case X86::MOVZX16rm8:
614   case X86::MOVZX32rm16:
615   case X86::MOVZX32rm8:
616   case X86::MOVZX32rm8_NOREX:
617   case X86::MOVZX64rm16:
618   case X86::MOVZX64rm8:
619     return true;
620   }
621 }
622 
623 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624   const MachineFunction *MF = MI.getParent()->getParent();
625   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626 
627   if (isFrameInstr(MI)) {
628     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629     SPAdj -= getFrameAdjustment(MI);
630     if (!isFrameSetup(MI))
631       SPAdj = -SPAdj;
632     return SPAdj;
633   }
634 
635   // To know whether a call adjusts the stack, we need information
636   // that is bound to the following ADJCALLSTACKUP pseudo.
637   // Look for the next ADJCALLSTACKUP that follows the call.
638   if (MI.isCall()) {
639     const MachineBasicBlock *MBB = MI.getParent();
640     auto I = ++MachineBasicBlock::const_iterator(MI);
641     for (auto E = MBB->end(); I != E; ++I) {
642       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643           I->isCall())
644         break;
645     }
646 
647     // If we could not find a frame destroy opcode, then it has already
648     // been simplified, so we don't care.
649     if (I->getOpcode() != getCallFrameDestroyOpcode())
650       return 0;
651 
652     return -(I->getOperand(1).getImm());
653   }
654 
655   // Currently handle only PUSHes we can reasonably expect to see
656   // in call sequences
657   switch (MI.getOpcode()) {
658   default:
659     return 0;
660   case X86::PUSH32i8:
661   case X86::PUSH32r:
662   case X86::PUSH32rmm:
663   case X86::PUSH32rmr:
664   case X86::PUSHi32:
665     return 4;
666   case X86::PUSH64i8:
667   case X86::PUSH64r:
668   case X86::PUSH64rmm:
669   case X86::PUSH64rmr:
670   case X86::PUSH64i32:
671     return 8;
672   }
673 }
674 
675 /// Return true and the FrameIndex if the specified
676 /// operand and follow operands form a reference to the stack frame.
677 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678                                   int &FrameIndex) const {
679   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682       MI.getOperand(Op + X86::AddrDisp).isImm() &&
683       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687     return true;
688   }
689   return false;
690 }
691 
692 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693   switch (Opcode) {
694   default:
695     return false;
696   case X86::MOV8rm:
697   case X86::KMOVBkm:
698     MemBytes = 1;
699     return true;
700   case X86::MOV16rm:
701   case X86::KMOVWkm:
702     MemBytes = 2;
703     return true;
704   case X86::MOV32rm:
705   case X86::MOVSSrm:
706   case X86::MOVSSrm_alt:
707   case X86::VMOVSSrm:
708   case X86::VMOVSSrm_alt:
709   case X86::VMOVSSZrm:
710   case X86::VMOVSSZrm_alt:
711   case X86::KMOVDkm:
712     MemBytes = 4;
713     return true;
714   case X86::MOV64rm:
715   case X86::LD_Fp64m:
716   case X86::MOVSDrm:
717   case X86::MOVSDrm_alt:
718   case X86::VMOVSDrm:
719   case X86::VMOVSDrm_alt:
720   case X86::VMOVSDZrm:
721   case X86::VMOVSDZrm_alt:
722   case X86::MMX_MOVD64rm:
723   case X86::MMX_MOVQ64rm:
724   case X86::KMOVQkm:
725     MemBytes = 8;
726     return true;
727   case X86::MOVAPSrm:
728   case X86::MOVUPSrm:
729   case X86::MOVAPDrm:
730   case X86::MOVUPDrm:
731   case X86::MOVDQArm:
732   case X86::MOVDQUrm:
733   case X86::VMOVAPSrm:
734   case X86::VMOVUPSrm:
735   case X86::VMOVAPDrm:
736   case X86::VMOVUPDrm:
737   case X86::VMOVDQArm:
738   case X86::VMOVDQUrm:
739   case X86::VMOVAPSZ128rm:
740   case X86::VMOVUPSZ128rm:
741   case X86::VMOVAPSZ128rm_NOVLX:
742   case X86::VMOVUPSZ128rm_NOVLX:
743   case X86::VMOVAPDZ128rm:
744   case X86::VMOVUPDZ128rm:
745   case X86::VMOVDQU8Z128rm:
746   case X86::VMOVDQU16Z128rm:
747   case X86::VMOVDQA32Z128rm:
748   case X86::VMOVDQU32Z128rm:
749   case X86::VMOVDQA64Z128rm:
750   case X86::VMOVDQU64Z128rm:
751     MemBytes = 16;
752     return true;
753   case X86::VMOVAPSYrm:
754   case X86::VMOVUPSYrm:
755   case X86::VMOVAPDYrm:
756   case X86::VMOVUPDYrm:
757   case X86::VMOVDQAYrm:
758   case X86::VMOVDQUYrm:
759   case X86::VMOVAPSZ256rm:
760   case X86::VMOVUPSZ256rm:
761   case X86::VMOVAPSZ256rm_NOVLX:
762   case X86::VMOVUPSZ256rm_NOVLX:
763   case X86::VMOVAPDZ256rm:
764   case X86::VMOVUPDZ256rm:
765   case X86::VMOVDQU8Z256rm:
766   case X86::VMOVDQU16Z256rm:
767   case X86::VMOVDQA32Z256rm:
768   case X86::VMOVDQU32Z256rm:
769   case X86::VMOVDQA64Z256rm:
770   case X86::VMOVDQU64Z256rm:
771     MemBytes = 32;
772     return true;
773   case X86::VMOVAPSZrm:
774   case X86::VMOVUPSZrm:
775   case X86::VMOVAPDZrm:
776   case X86::VMOVUPDZrm:
777   case X86::VMOVDQU8Zrm:
778   case X86::VMOVDQU16Zrm:
779   case X86::VMOVDQA32Zrm:
780   case X86::VMOVDQU32Zrm:
781   case X86::VMOVDQA64Zrm:
782   case X86::VMOVDQU64Zrm:
783     MemBytes = 64;
784     return true;
785   }
786 }
787 
788 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
789   switch (Opcode) {
790   default:
791     return false;
792   case X86::MOV8mr:
793   case X86::KMOVBmk:
794     MemBytes = 1;
795     return true;
796   case X86::MOV16mr:
797   case X86::KMOVWmk:
798     MemBytes = 2;
799     return true;
800   case X86::MOV32mr:
801   case X86::MOVSSmr:
802   case X86::VMOVSSmr:
803   case X86::VMOVSSZmr:
804   case X86::KMOVDmk:
805     MemBytes = 4;
806     return true;
807   case X86::MOV64mr:
808   case X86::ST_FpP64m:
809   case X86::MOVSDmr:
810   case X86::VMOVSDmr:
811   case X86::VMOVSDZmr:
812   case X86::MMX_MOVD64mr:
813   case X86::MMX_MOVQ64mr:
814   case X86::MMX_MOVNTQmr:
815   case X86::KMOVQmk:
816     MemBytes = 8;
817     return true;
818   case X86::MOVAPSmr:
819   case X86::MOVUPSmr:
820   case X86::MOVAPDmr:
821   case X86::MOVUPDmr:
822   case X86::MOVDQAmr:
823   case X86::MOVDQUmr:
824   case X86::VMOVAPSmr:
825   case X86::VMOVUPSmr:
826   case X86::VMOVAPDmr:
827   case X86::VMOVUPDmr:
828   case X86::VMOVDQAmr:
829   case X86::VMOVDQUmr:
830   case X86::VMOVUPSZ128mr:
831   case X86::VMOVAPSZ128mr:
832   case X86::VMOVUPSZ128mr_NOVLX:
833   case X86::VMOVAPSZ128mr_NOVLX:
834   case X86::VMOVUPDZ128mr:
835   case X86::VMOVAPDZ128mr:
836   case X86::VMOVDQA32Z128mr:
837   case X86::VMOVDQU32Z128mr:
838   case X86::VMOVDQA64Z128mr:
839   case X86::VMOVDQU64Z128mr:
840   case X86::VMOVDQU8Z128mr:
841   case X86::VMOVDQU16Z128mr:
842     MemBytes = 16;
843     return true;
844   case X86::VMOVUPSYmr:
845   case X86::VMOVAPSYmr:
846   case X86::VMOVUPDYmr:
847   case X86::VMOVAPDYmr:
848   case X86::VMOVDQUYmr:
849   case X86::VMOVDQAYmr:
850   case X86::VMOVUPSZ256mr:
851   case X86::VMOVAPSZ256mr:
852   case X86::VMOVUPSZ256mr_NOVLX:
853   case X86::VMOVAPSZ256mr_NOVLX:
854   case X86::VMOVUPDZ256mr:
855   case X86::VMOVAPDZ256mr:
856   case X86::VMOVDQU8Z256mr:
857   case X86::VMOVDQU16Z256mr:
858   case X86::VMOVDQA32Z256mr:
859   case X86::VMOVDQU32Z256mr:
860   case X86::VMOVDQA64Z256mr:
861   case X86::VMOVDQU64Z256mr:
862     MemBytes = 32;
863     return true;
864   case X86::VMOVUPSZmr:
865   case X86::VMOVAPSZmr:
866   case X86::VMOVUPDZmr:
867   case X86::VMOVAPDZmr:
868   case X86::VMOVDQU8Zmr:
869   case X86::VMOVDQU16Zmr:
870   case X86::VMOVDQA32Zmr:
871   case X86::VMOVDQU32Zmr:
872   case X86::VMOVDQA64Zmr:
873   case X86::VMOVDQU64Zmr:
874     MemBytes = 64;
875     return true;
876   }
877   return false;
878 }
879 
880 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
881                                            int &FrameIndex) const {
882   unsigned Dummy;
883   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
884 }
885 
886 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
887                                            int &FrameIndex,
888                                            unsigned &MemBytes) const {
889   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
890     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
891       return MI.getOperand(0).getReg();
892   return 0;
893 }
894 
895 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
896                                                  int &FrameIndex) const {
897   unsigned Dummy;
898   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
899     unsigned Reg;
900     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
901       return Reg;
902     // Check for post-frame index elimination operations
903     SmallVector<const MachineMemOperand *, 1> Accesses;
904     if (hasLoadFromStackSlot(MI, Accesses)) {
905       FrameIndex =
906           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
907               ->getFrameIndex();
908       return 1;
909     }
910   }
911   return 0;
912 }
913 
914 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
915                                           int &FrameIndex) const {
916   unsigned Dummy;
917   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
918 }
919 
920 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
921                                           int &FrameIndex,
922                                           unsigned &MemBytes) const {
923   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
924     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
925         isFrameOperand(MI, 0, FrameIndex))
926       return MI.getOperand(X86::AddrNumOperands).getReg();
927   return 0;
928 }
929 
930 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
931                                                 int &FrameIndex) const {
932   unsigned Dummy;
933   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
934     unsigned Reg;
935     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
936       return Reg;
937     // Check for post-frame index elimination operations
938     SmallVector<const MachineMemOperand *, 1> Accesses;
939     if (hasStoreToStackSlot(MI, Accesses)) {
940       FrameIndex =
941           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
942               ->getFrameIndex();
943       return 1;
944     }
945   }
946   return 0;
947 }
948 
949 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
950 static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
951   // Don't waste compile time scanning use-def chains of physregs.
952   if (!BaseReg.isVirtual())
953     return false;
954   bool isPICBase = false;
955   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
956          E = MRI.def_instr_end(); I != E; ++I) {
957     MachineInstr *DefMI = &*I;
958     if (DefMI->getOpcode() != X86::MOVPC32r)
959       return false;
960     assert(!isPICBase && "More than one PIC base?");
961     isPICBase = true;
962   }
963   return isPICBase;
964 }
965 
966 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
967                                                      AAResults *AA) const {
968   switch (MI.getOpcode()) {
969   default:
970     // This function should only be called for opcodes with the ReMaterializable
971     // flag set.
972     llvm_unreachable("Unknown rematerializable operation!");
973     break;
974 
975   case X86::LOAD_STACK_GUARD:
976   case X86::AVX1_SETALLONES:
977   case X86::AVX2_SETALLONES:
978   case X86::AVX512_128_SET0:
979   case X86::AVX512_256_SET0:
980   case X86::AVX512_512_SET0:
981   case X86::AVX512_512_SETALLONES:
982   case X86::AVX512_FsFLD0SD:
983   case X86::AVX512_FsFLD0SS:
984   case X86::AVX512_FsFLD0F128:
985   case X86::AVX_SET0:
986   case X86::FsFLD0SD:
987   case X86::FsFLD0SS:
988   case X86::FsFLD0F128:
989   case X86::KSET0D:
990   case X86::KSET0Q:
991   case X86::KSET0W:
992   case X86::KSET1D:
993   case X86::KSET1Q:
994   case X86::KSET1W:
995   case X86::MMX_SET0:
996   case X86::MOV32ImmSExti8:
997   case X86::MOV32r0:
998   case X86::MOV32r1:
999   case X86::MOV32r_1:
1000   case X86::MOV32ri64:
1001   case X86::MOV64ImmSExti8:
1002   case X86::V_SET0:
1003   case X86::V_SETALLONES:
1004   case X86::MOV16ri:
1005   case X86::MOV32ri:
1006   case X86::MOV64ri:
1007   case X86::MOV64ri32:
1008   case X86::MOV8ri:
1009     return true;
1010 
1011   case X86::MOV8rm:
1012   case X86::MOV8rm_NOREX:
1013   case X86::MOV16rm:
1014   case X86::MOV32rm:
1015   case X86::MOV64rm:
1016   case X86::MOVSSrm:
1017   case X86::MOVSSrm_alt:
1018   case X86::MOVSDrm:
1019   case X86::MOVSDrm_alt:
1020   case X86::MOVAPSrm:
1021   case X86::MOVUPSrm:
1022   case X86::MOVAPDrm:
1023   case X86::MOVUPDrm:
1024   case X86::MOVDQArm:
1025   case X86::MOVDQUrm:
1026   case X86::VMOVSSrm:
1027   case X86::VMOVSSrm_alt:
1028   case X86::VMOVSDrm:
1029   case X86::VMOVSDrm_alt:
1030   case X86::VMOVAPSrm:
1031   case X86::VMOVUPSrm:
1032   case X86::VMOVAPDrm:
1033   case X86::VMOVUPDrm:
1034   case X86::VMOVDQArm:
1035   case X86::VMOVDQUrm:
1036   case X86::VMOVAPSYrm:
1037   case X86::VMOVUPSYrm:
1038   case X86::VMOVAPDYrm:
1039   case X86::VMOVUPDYrm:
1040   case X86::VMOVDQAYrm:
1041   case X86::VMOVDQUYrm:
1042   case X86::MMX_MOVD64rm:
1043   case X86::MMX_MOVQ64rm:
1044   // AVX-512
1045   case X86::VMOVSSZrm:
1046   case X86::VMOVSSZrm_alt:
1047   case X86::VMOVSDZrm:
1048   case X86::VMOVSDZrm_alt:
1049   case X86::VMOVAPDZ128rm:
1050   case X86::VMOVAPDZ256rm:
1051   case X86::VMOVAPDZrm:
1052   case X86::VMOVAPSZ128rm:
1053   case X86::VMOVAPSZ256rm:
1054   case X86::VMOVAPSZ128rm_NOVLX:
1055   case X86::VMOVAPSZ256rm_NOVLX:
1056   case X86::VMOVAPSZrm:
1057   case X86::VMOVDQA32Z128rm:
1058   case X86::VMOVDQA32Z256rm:
1059   case X86::VMOVDQA32Zrm:
1060   case X86::VMOVDQA64Z128rm:
1061   case X86::VMOVDQA64Z256rm:
1062   case X86::VMOVDQA64Zrm:
1063   case X86::VMOVDQU16Z128rm:
1064   case X86::VMOVDQU16Z256rm:
1065   case X86::VMOVDQU16Zrm:
1066   case X86::VMOVDQU32Z128rm:
1067   case X86::VMOVDQU32Z256rm:
1068   case X86::VMOVDQU32Zrm:
1069   case X86::VMOVDQU64Z128rm:
1070   case X86::VMOVDQU64Z256rm:
1071   case X86::VMOVDQU64Zrm:
1072   case X86::VMOVDQU8Z128rm:
1073   case X86::VMOVDQU8Z256rm:
1074   case X86::VMOVDQU8Zrm:
1075   case X86::VMOVUPDZ128rm:
1076   case X86::VMOVUPDZ256rm:
1077   case X86::VMOVUPDZrm:
1078   case X86::VMOVUPSZ128rm:
1079   case X86::VMOVUPSZ256rm:
1080   case X86::VMOVUPSZ128rm_NOVLX:
1081   case X86::VMOVUPSZ256rm_NOVLX:
1082   case X86::VMOVUPSZrm: {
1083     // Loads from constant pools are trivially rematerializable.
1084     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1085         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1086         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1087         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1088         MI.isDereferenceableInvariantLoad(AA)) {
1089       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1090       if (BaseReg == 0 || BaseReg == X86::RIP)
1091         return true;
1092       // Allow re-materialization of PIC load.
1093       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1094         return false;
1095       const MachineFunction &MF = *MI.getParent()->getParent();
1096       const MachineRegisterInfo &MRI = MF.getRegInfo();
1097       return regIsPICBase(BaseReg, MRI);
1098     }
1099     return false;
1100   }
1101 
1102   case X86::LEA32r:
1103   case X86::LEA64r: {
1104     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1105         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1106         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1107         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1108       // lea fi#, lea GV, etc. are all rematerializable.
1109       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1110         return true;
1111       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1112       if (BaseReg == 0)
1113         return true;
1114       // Allow re-materialization of lea PICBase + x.
1115       const MachineFunction &MF = *MI.getParent()->getParent();
1116       const MachineRegisterInfo &MRI = MF.getRegInfo();
1117       return regIsPICBase(BaseReg, MRI);
1118     }
1119     return false;
1120   }
1121   }
1122 }
1123 
1124 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1125                                  MachineBasicBlock::iterator I,
1126                                  Register DestReg, unsigned SubIdx,
1127                                  const MachineInstr &Orig,
1128                                  const TargetRegisterInfo &TRI) const {
1129   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1130   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1131                             MachineBasicBlock::LQR_Dead) {
1132     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1133     // effects.
1134     int Value;
1135     switch (Orig.getOpcode()) {
1136     case X86::MOV32r0:  Value = 0; break;
1137     case X86::MOV32r1:  Value = 1; break;
1138     case X86::MOV32r_1: Value = -1; break;
1139     default:
1140       llvm_unreachable("Unexpected instruction!");
1141     }
1142 
1143     const DebugLoc &DL = Orig.getDebugLoc();
1144     BuildMI(MBB, I, DL, get(X86::MOV32ri))
1145         .add(Orig.getOperand(0))
1146         .addImm(Value);
1147   } else {
1148     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1149     MBB.insert(I, MI);
1150   }
1151 
1152   MachineInstr &NewMI = *std::prev(I);
1153   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1154 }
1155 
1156 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1157 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1158   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1159     MachineOperand &MO = MI.getOperand(i);
1160     if (MO.isReg() && MO.isDef() &&
1161         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1162       return true;
1163     }
1164   }
1165   return false;
1166 }
1167 
1168 /// Check whether the shift count for a machine operand is non-zero.
1169 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1170                                               unsigned ShiftAmtOperandIdx) {
1171   // The shift count is six bits with the REX.W prefix and five bits without.
1172   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1173   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1174   return Imm & ShiftCountMask;
1175 }
1176 
1177 /// Check whether the given shift count is appropriate
1178 /// can be represented by a LEA instruction.
1179 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1180   // Left shift instructions can be transformed into load-effective-address
1181   // instructions if we can encode them appropriately.
1182   // A LEA instruction utilizes a SIB byte to encode its scale factor.
1183   // The SIB.scale field is two bits wide which means that we can encode any
1184   // shift amount less than 4.
1185   return ShAmt < 4 && ShAmt > 0;
1186 }
1187 
1188 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1189                                   unsigned Opc, bool AllowSP, Register &NewSrc,
1190                                   bool &isKill, MachineOperand &ImplicitOp,
1191                                   LiveVariables *LV) const {
1192   MachineFunction &MF = *MI.getParent()->getParent();
1193   const TargetRegisterClass *RC;
1194   if (AllowSP) {
1195     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1196   } else {
1197     RC = Opc != X86::LEA32r ?
1198       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1199   }
1200   Register SrcReg = Src.getReg();
1201 
1202   // For both LEA64 and LEA32 the register already has essentially the right
1203   // type (32-bit or 64-bit) we may just need to forbid SP.
1204   if (Opc != X86::LEA64_32r) {
1205     NewSrc = SrcReg;
1206     isKill = Src.isKill();
1207     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1208 
1209     if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1210       return false;
1211 
1212     return true;
1213   }
1214 
1215   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1216   // another we need to add 64-bit registers to the final MI.
1217   if (SrcReg.isPhysical()) {
1218     ImplicitOp = Src;
1219     ImplicitOp.setImplicit();
1220 
1221     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1222     isKill = Src.isKill();
1223     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1224   } else {
1225     // Virtual register of the wrong class, we have to create a temporary 64-bit
1226     // vreg to feed into the LEA.
1227     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1228     MachineInstr *Copy =
1229         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1230             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1231             .add(Src);
1232 
1233     // Which is obviously going to be dead after we're done with it.
1234     isKill = true;
1235 
1236     if (LV)
1237       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1238   }
1239 
1240   // We've set all the parameters without issue.
1241   return true;
1242 }
1243 
1244 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
1245     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
1246     LiveVariables *LV, bool Is8BitOp) const {
1247   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1248   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1249   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1250               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1251          "Unexpected type for LEA transform");
1252 
1253   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1254   // something like this:
1255   //   Opcode = X86::LEA32r;
1256   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1257   //   OutRegLEA =
1258   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1259   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1260   if (!Subtarget.is64Bit())
1261     return nullptr;
1262 
1263   unsigned Opcode = X86::LEA64_32r;
1264   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1265   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1266 
1267   // Build and insert into an implicit UNDEF value. This is OK because
1268   // we will be shifting and then extracting the lower 8/16-bits.
1269   // This has the potential to cause partial register stall. e.g.
1270   //   movw    (%rbp,%rcx,2), %dx
1271   //   leal    -65(%rdx), %esi
1272   // But testing has shown this *does* help performance in 64-bit mode (at
1273   // least on modern x86 machines).
1274   MachineBasicBlock::iterator MBBI = MI.getIterator();
1275   Register Dest = MI.getOperand(0).getReg();
1276   Register Src = MI.getOperand(1).getReg();
1277   bool IsDead = MI.getOperand(0).isDead();
1278   bool IsKill = MI.getOperand(1).isKill();
1279   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1280   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1281   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1282   MachineInstr *InsMI =
1283       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1284           .addReg(InRegLEA, RegState::Define, SubReg)
1285           .addReg(Src, getKillRegState(IsKill));
1286 
1287   MachineInstrBuilder MIB =
1288       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1289   switch (MIOpc) {
1290   default: llvm_unreachable("Unreachable!");
1291   case X86::SHL8ri:
1292   case X86::SHL16ri: {
1293     unsigned ShAmt = MI.getOperand(2).getImm();
1294     MIB.addReg(0).addImm(1ULL << ShAmt)
1295        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1296     break;
1297   }
1298   case X86::INC8r:
1299   case X86::INC16r:
1300     addRegOffset(MIB, InRegLEA, true, 1);
1301     break;
1302   case X86::DEC8r:
1303   case X86::DEC16r:
1304     addRegOffset(MIB, InRegLEA, true, -1);
1305     break;
1306   case X86::ADD8ri:
1307   case X86::ADD8ri_DB:
1308   case X86::ADD16ri:
1309   case X86::ADD16ri8:
1310   case X86::ADD16ri_DB:
1311   case X86::ADD16ri8_DB:
1312     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1313     break;
1314   case X86::ADD8rr:
1315   case X86::ADD8rr_DB:
1316   case X86::ADD16rr:
1317   case X86::ADD16rr_DB: {
1318     Register Src2 = MI.getOperand(2).getReg();
1319     bool IsKill2 = MI.getOperand(2).isKill();
1320     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1321     unsigned InRegLEA2 = 0;
1322     MachineInstr *InsMI2 = nullptr;
1323     if (Src == Src2) {
1324       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1325       // just a single insert_subreg.
1326       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1327     } else {
1328       if (Subtarget.is64Bit())
1329         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1330       else
1331         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1332       // Build and insert into an implicit UNDEF value. This is OK because
1333       // we will be shifting and then extracting the lower 8/16-bits.
1334       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1335       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1336                    .addReg(InRegLEA2, RegState::Define, SubReg)
1337                    .addReg(Src2, getKillRegState(IsKill2));
1338       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1339     }
1340     if (LV && IsKill2 && InsMI2)
1341       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1342     break;
1343   }
1344   }
1345 
1346   MachineInstr *NewMI = MIB;
1347   MachineInstr *ExtMI =
1348       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1349           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1350           .addReg(OutRegLEA, RegState::Kill, SubReg);
1351 
1352   if (LV) {
1353     // Update live variables.
1354     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1355     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1356     if (IsKill)
1357       LV->replaceKillInstruction(Src, MI, *InsMI);
1358     if (IsDead)
1359       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1360   }
1361 
1362   return ExtMI;
1363 }
1364 
1365 /// This method must be implemented by targets that
1366 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1367 /// may be able to convert a two-address instruction into a true
1368 /// three-address instruction on demand.  This allows the X86 target (for
1369 /// example) to convert ADD and SHL instructions into LEA instructions if they
1370 /// would require register copies due to two-addressness.
1371 ///
1372 /// This method returns a null pointer if the transformation cannot be
1373 /// performed, otherwise it returns the new instruction.
1374 ///
1375 MachineInstr *
1376 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1377                                     MachineInstr &MI, LiveVariables *LV) const {
1378   // The following opcodes also sets the condition code register(s). Only
1379   // convert them to equivalent lea if the condition code register def's
1380   // are dead!
1381   if (hasLiveCondCodeDef(MI))
1382     return nullptr;
1383 
1384   MachineFunction &MF = *MI.getParent()->getParent();
1385   // All instructions input are two-addr instructions.  Get the known operands.
1386   const MachineOperand &Dest = MI.getOperand(0);
1387   const MachineOperand &Src = MI.getOperand(1);
1388 
1389   // Ideally, operations with undef should be folded before we get here, but we
1390   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1391   // Without this, we have to forward undef state to new register operands to
1392   // avoid machine verifier errors.
1393   if (Src.isUndef())
1394     return nullptr;
1395   if (MI.getNumOperands() > 2)
1396     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1397       return nullptr;
1398 
1399   MachineInstr *NewMI = nullptr;
1400   bool Is64Bit = Subtarget.is64Bit();
1401 
1402   bool Is8BitOp = false;
1403   unsigned MIOpc = MI.getOpcode();
1404   switch (MIOpc) {
1405   default: llvm_unreachable("Unreachable!");
1406   case X86::SHL64ri: {
1407     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1408     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1409     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1410 
1411     // LEA can't handle RSP.
1412     if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1413                                         Src.getReg(), &X86::GR64_NOSPRegClass))
1414       return nullptr;
1415 
1416     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1417                 .add(Dest)
1418                 .addReg(0)
1419                 .addImm(1ULL << ShAmt)
1420                 .add(Src)
1421                 .addImm(0)
1422                 .addReg(0);
1423     break;
1424   }
1425   case X86::SHL32ri: {
1426     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1427     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1428     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1429 
1430     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1431 
1432     // LEA can't handle ESP.
1433     bool isKill;
1434     Register SrcReg;
1435     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1436     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1437                         SrcReg, isKill, ImplicitOp, LV))
1438       return nullptr;
1439 
1440     MachineInstrBuilder MIB =
1441         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1442             .add(Dest)
1443             .addReg(0)
1444             .addImm(1ULL << ShAmt)
1445             .addReg(SrcReg, getKillRegState(isKill))
1446             .addImm(0)
1447             .addReg(0);
1448     if (ImplicitOp.getReg() != 0)
1449       MIB.add(ImplicitOp);
1450     NewMI = MIB;
1451 
1452     break;
1453   }
1454   case X86::SHL8ri:
1455     Is8BitOp = true;
1456     LLVM_FALLTHROUGH;
1457   case X86::SHL16ri: {
1458     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1459     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1460     if (!isTruncatedShiftCountForLEA(ShAmt))
1461       return nullptr;
1462     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1463   }
1464   case X86::INC64r:
1465   case X86::INC32r: {
1466     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1467     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1468         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1469     bool isKill;
1470     Register SrcReg;
1471     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1472     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1473                         ImplicitOp, LV))
1474       return nullptr;
1475 
1476     MachineInstrBuilder MIB =
1477         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1478             .add(Dest)
1479             .addReg(SrcReg, getKillRegState(isKill));
1480     if (ImplicitOp.getReg() != 0)
1481       MIB.add(ImplicitOp);
1482 
1483     NewMI = addOffset(MIB, 1);
1484     break;
1485   }
1486   case X86::DEC64r:
1487   case X86::DEC32r: {
1488     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1489     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1490         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1491 
1492     bool isKill;
1493     Register SrcReg;
1494     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1495     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1496                         ImplicitOp, LV))
1497       return nullptr;
1498 
1499     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1500                                   .add(Dest)
1501                                   .addReg(SrcReg, getKillRegState(isKill));
1502     if (ImplicitOp.getReg() != 0)
1503       MIB.add(ImplicitOp);
1504 
1505     NewMI = addOffset(MIB, -1);
1506 
1507     break;
1508   }
1509   case X86::DEC8r:
1510   case X86::INC8r:
1511     Is8BitOp = true;
1512     LLVM_FALLTHROUGH;
1513   case X86::DEC16r:
1514   case X86::INC16r:
1515     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1516   case X86::ADD64rr:
1517   case X86::ADD64rr_DB:
1518   case X86::ADD32rr:
1519   case X86::ADD32rr_DB: {
1520     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1521     unsigned Opc;
1522     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1523       Opc = X86::LEA64r;
1524     else
1525       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1526 
1527     bool isKill;
1528     Register SrcReg;
1529     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1530     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1531                         SrcReg, isKill, ImplicitOp, LV))
1532       return nullptr;
1533 
1534     const MachineOperand &Src2 = MI.getOperand(2);
1535     bool isKill2;
1536     Register SrcReg2;
1537     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1538     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1539                         SrcReg2, isKill2, ImplicitOp2, LV))
1540       return nullptr;
1541 
1542     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1543     if (ImplicitOp.getReg() != 0)
1544       MIB.add(ImplicitOp);
1545     if (ImplicitOp2.getReg() != 0)
1546       MIB.add(ImplicitOp2);
1547 
1548     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1549     if (LV && Src2.isKill())
1550       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1551     break;
1552   }
1553   case X86::ADD8rr:
1554   case X86::ADD8rr_DB:
1555     Is8BitOp = true;
1556     LLVM_FALLTHROUGH;
1557   case X86::ADD16rr:
1558   case X86::ADD16rr_DB:
1559     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1560   case X86::ADD64ri32:
1561   case X86::ADD64ri8:
1562   case X86::ADD64ri32_DB:
1563   case X86::ADD64ri8_DB:
1564     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1565     NewMI = addOffset(
1566         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1567         MI.getOperand(2));
1568     break;
1569   case X86::ADD32ri:
1570   case X86::ADD32ri8:
1571   case X86::ADD32ri_DB:
1572   case X86::ADD32ri8_DB: {
1573     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1574     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1575 
1576     bool isKill;
1577     Register SrcReg;
1578     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1579     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1580                         SrcReg, isKill, ImplicitOp, LV))
1581       return nullptr;
1582 
1583     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1584                                   .add(Dest)
1585                                   .addReg(SrcReg, getKillRegState(isKill));
1586     if (ImplicitOp.getReg() != 0)
1587       MIB.add(ImplicitOp);
1588 
1589     NewMI = addOffset(MIB, MI.getOperand(2));
1590     break;
1591   }
1592   case X86::ADD8ri:
1593   case X86::ADD8ri_DB:
1594     Is8BitOp = true;
1595     LLVM_FALLTHROUGH;
1596   case X86::ADD16ri:
1597   case X86::ADD16ri8:
1598   case X86::ADD16ri_DB:
1599   case X86::ADD16ri8_DB:
1600     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1601   case X86::SUB8ri:
1602   case X86::SUB16ri8:
1603   case X86::SUB16ri:
1604     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1605     return nullptr;
1606   case X86::SUB32ri8:
1607   case X86::SUB32ri: {
1608     if (!MI.getOperand(2).isImm())
1609       return nullptr;
1610     int64_t Imm = MI.getOperand(2).getImm();
1611     if (!isInt<32>(-Imm))
1612       return nullptr;
1613 
1614     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1615     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1616 
1617     bool isKill;
1618     Register SrcReg;
1619     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1620     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1621                         SrcReg, isKill, ImplicitOp, LV))
1622       return nullptr;
1623 
1624     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1625                                   .add(Dest)
1626                                   .addReg(SrcReg, getKillRegState(isKill));
1627     if (ImplicitOp.getReg() != 0)
1628       MIB.add(ImplicitOp);
1629 
1630     NewMI = addOffset(MIB, -Imm);
1631     break;
1632   }
1633 
1634   case X86::SUB64ri8:
1635   case X86::SUB64ri32: {
1636     if (!MI.getOperand(2).isImm())
1637       return nullptr;
1638     int64_t Imm = MI.getOperand(2).getImm();
1639     if (!isInt<32>(-Imm))
1640       return nullptr;
1641 
1642     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1643 
1644     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1645                                       get(X86::LEA64r)).add(Dest).add(Src);
1646     NewMI = addOffset(MIB, -Imm);
1647     break;
1648   }
1649 
1650   case X86::VMOVDQU8Z128rmk:
1651   case X86::VMOVDQU8Z256rmk:
1652   case X86::VMOVDQU8Zrmk:
1653   case X86::VMOVDQU16Z128rmk:
1654   case X86::VMOVDQU16Z256rmk:
1655   case X86::VMOVDQU16Zrmk:
1656   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1657   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1658   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1659   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1660   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1661   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1662   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1663   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1664   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1665   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1666   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1667   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1668   case X86::VBROADCASTSDZ256rmk:
1669   case X86::VBROADCASTSDZrmk:
1670   case X86::VBROADCASTSSZ128rmk:
1671   case X86::VBROADCASTSSZ256rmk:
1672   case X86::VBROADCASTSSZrmk:
1673   case X86::VPBROADCASTDZ128rmk:
1674   case X86::VPBROADCASTDZ256rmk:
1675   case X86::VPBROADCASTDZrmk:
1676   case X86::VPBROADCASTQZ128rmk:
1677   case X86::VPBROADCASTQZ256rmk:
1678   case X86::VPBROADCASTQZrmk: {
1679     unsigned Opc;
1680     switch (MIOpc) {
1681     default: llvm_unreachable("Unreachable!");
1682     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1683     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1684     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1685     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1686     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1687     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1688     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1689     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1690     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1691     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1692     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1693     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1694     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1695     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1696     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1697     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1698     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1699     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1700     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1701     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1702     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1703     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1704     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1705     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1706     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1707     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1708     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1709     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1710     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1711     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1712     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1713     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1714     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1715     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1716     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1717     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1718     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1719     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1720     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1721     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1722     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1723     }
1724 
1725     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1726               .add(Dest)
1727               .add(MI.getOperand(2))
1728               .add(Src)
1729               .add(MI.getOperand(3))
1730               .add(MI.getOperand(4))
1731               .add(MI.getOperand(5))
1732               .add(MI.getOperand(6))
1733               .add(MI.getOperand(7));
1734     break;
1735   }
1736 
1737   case X86::VMOVDQU8Z128rrk:
1738   case X86::VMOVDQU8Z256rrk:
1739   case X86::VMOVDQU8Zrrk:
1740   case X86::VMOVDQU16Z128rrk:
1741   case X86::VMOVDQU16Z256rrk:
1742   case X86::VMOVDQU16Zrrk:
1743   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1744   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1745   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1746   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1747   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1748   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1749   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1750   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1751   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1752   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1753   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1754   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1755     unsigned Opc;
1756     switch (MIOpc) {
1757     default: llvm_unreachable("Unreachable!");
1758     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1759     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1760     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1761     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1762     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1763     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1764     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1765     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1766     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1767     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1768     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1769     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1770     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1771     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1772     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1773     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1774     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1775     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1776     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1777     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1778     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1779     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1780     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1781     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1782     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1783     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1784     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1785     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1786     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1787     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1788     }
1789 
1790     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1791               .add(Dest)
1792               .add(MI.getOperand(2))
1793               .add(Src)
1794               .add(MI.getOperand(3));
1795     break;
1796   }
1797   }
1798 
1799   if (!NewMI) return nullptr;
1800 
1801   if (LV) {  // Update live variables
1802     if (Src.isKill())
1803       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1804     if (Dest.isDead())
1805       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1806   }
1807 
1808   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1809   return NewMI;
1810 }
1811 
1812 /// This determines which of three possible cases of a three source commute
1813 /// the source indexes correspond to taking into account any mask operands.
1814 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1815 /// possible.
1816 /// Case 0 - Possible to commute the first and second operands.
1817 /// Case 1 - Possible to commute the first and third operands.
1818 /// Case 2 - Possible to commute the second and third operands.
1819 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1820                                        unsigned SrcOpIdx2) {
1821   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1822   if (SrcOpIdx1 > SrcOpIdx2)
1823     std::swap(SrcOpIdx1, SrcOpIdx2);
1824 
1825   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1826   if (X86II::isKMasked(TSFlags)) {
1827     Op2++;
1828     Op3++;
1829   }
1830 
1831   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1832     return 0;
1833   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1834     return 1;
1835   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1836     return 2;
1837   llvm_unreachable("Unknown three src commute case.");
1838 }
1839 
1840 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1841     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1842     const X86InstrFMA3Group &FMA3Group) const {
1843 
1844   unsigned Opc = MI.getOpcode();
1845 
1846   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1847   // analysis. The commute optimization is legal only if all users of FMA*_Int
1848   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1849   // not implemented yet. So, just return 0 in that case.
1850   // When such analysis are available this place will be the right place for
1851   // calling it.
1852   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1853          "Intrinsic instructions can't commute operand 1");
1854 
1855   // Determine which case this commute is or if it can't be done.
1856   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1857                                          SrcOpIdx2);
1858   assert(Case < 3 && "Unexpected case number!");
1859 
1860   // Define the FMA forms mapping array that helps to map input FMA form
1861   // to output FMA form to preserve the operation semantics after
1862   // commuting the operands.
1863   const unsigned Form132Index = 0;
1864   const unsigned Form213Index = 1;
1865   const unsigned Form231Index = 2;
1866   static const unsigned FormMapping[][3] = {
1867     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1868     // FMA132 A, C, b; ==> FMA231 C, A, b;
1869     // FMA213 B, A, c; ==> FMA213 A, B, c;
1870     // FMA231 C, A, b; ==> FMA132 A, C, b;
1871     { Form231Index, Form213Index, Form132Index },
1872     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1873     // FMA132 A, c, B; ==> FMA132 B, c, A;
1874     // FMA213 B, a, C; ==> FMA231 C, a, B;
1875     // FMA231 C, a, B; ==> FMA213 B, a, C;
1876     { Form132Index, Form231Index, Form213Index },
1877     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1878     // FMA132 a, C, B; ==> FMA213 a, B, C;
1879     // FMA213 b, A, C; ==> FMA132 b, C, A;
1880     // FMA231 c, A, B; ==> FMA231 c, B, A;
1881     { Form213Index, Form132Index, Form231Index }
1882   };
1883 
1884   unsigned FMAForms[3];
1885   FMAForms[0] = FMA3Group.get132Opcode();
1886   FMAForms[1] = FMA3Group.get213Opcode();
1887   FMAForms[2] = FMA3Group.get231Opcode();
1888   unsigned FormIndex;
1889   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1890     if (Opc == FMAForms[FormIndex])
1891       break;
1892 
1893   // Everything is ready, just adjust the FMA opcode and return it.
1894   FormIndex = FormMapping[Case][FormIndex];
1895   return FMAForms[FormIndex];
1896 }
1897 
1898 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1899                              unsigned SrcOpIdx2) {
1900   // Determine which case this commute is or if it can't be done.
1901   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1902                                          SrcOpIdx2);
1903   assert(Case < 3 && "Unexpected case value!");
1904 
1905   // For each case we need to swap two pairs of bits in the final immediate.
1906   static const uint8_t SwapMasks[3][4] = {
1907     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1908     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1909     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1910   };
1911 
1912   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1913   // Clear out the bits we are swapping.
1914   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1915                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1916   // If the immediate had a bit of the pair set, then set the opposite bit.
1917   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1918   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1919   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1920   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1921   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1922 }
1923 
1924 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1925 // commuted.
1926 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1927 #define VPERM_CASES(Suffix) \
1928   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1929   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1930   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1931   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1932   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1933   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1934   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1935   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1936   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1937   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1938   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1939   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1940 
1941 #define VPERM_CASES_BROADCAST(Suffix) \
1942   VPERM_CASES(Suffix) \
1943   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1944   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1945   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1946   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1947   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1948   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1949 
1950   switch (Opcode) {
1951   default: return false;
1952   VPERM_CASES(B)
1953   VPERM_CASES_BROADCAST(D)
1954   VPERM_CASES_BROADCAST(PD)
1955   VPERM_CASES_BROADCAST(PS)
1956   VPERM_CASES_BROADCAST(Q)
1957   VPERM_CASES(W)
1958     return true;
1959   }
1960 #undef VPERM_CASES_BROADCAST
1961 #undef VPERM_CASES
1962 }
1963 
1964 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1965 // from the I opcode to the T opcode and vice versa.
1966 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1967 #define VPERM_CASES(Orig, New) \
1968   case X86::Orig##128rr:    return X86::New##128rr;   \
1969   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1970   case X86::Orig##128rm:    return X86::New##128rm;   \
1971   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1972   case X86::Orig##256rr:    return X86::New##256rr;   \
1973   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1974   case X86::Orig##256rm:    return X86::New##256rm;   \
1975   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1976   case X86::Orig##rr:       return X86::New##rr;      \
1977   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1978   case X86::Orig##rm:       return X86::New##rm;      \
1979   case X86::Orig##rmkz:     return X86::New##rmkz;
1980 
1981 #define VPERM_CASES_BROADCAST(Orig, New) \
1982   VPERM_CASES(Orig, New) \
1983   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1984   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1985   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1986   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1987   case X86::Orig##rmb:      return X86::New##rmb;      \
1988   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1989 
1990   switch (Opcode) {
1991   VPERM_CASES(VPERMI2B, VPERMT2B)
1992   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1993   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1994   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1995   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1996   VPERM_CASES(VPERMI2W, VPERMT2W)
1997   VPERM_CASES(VPERMT2B, VPERMI2B)
1998   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
1999   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2000   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2001   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
2002   VPERM_CASES(VPERMT2W, VPERMI2W)
2003   }
2004 
2005   llvm_unreachable("Unreachable!");
2006 #undef VPERM_CASES_BROADCAST
2007 #undef VPERM_CASES
2008 }
2009 
2010 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2011                                                    unsigned OpIdx1,
2012                                                    unsigned OpIdx2) const {
2013   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2014     if (NewMI)
2015       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2016     return MI;
2017   };
2018 
2019   switch (MI.getOpcode()) {
2020   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2021   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2022   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2023   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2024   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2025   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2026     unsigned Opc;
2027     unsigned Size;
2028     switch (MI.getOpcode()) {
2029     default: llvm_unreachable("Unreachable!");
2030     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2031     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2032     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2033     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2034     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2035     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2036     }
2037     unsigned Amt = MI.getOperand(3).getImm();
2038     auto &WorkingMI = cloneIfNew(MI);
2039     WorkingMI.setDesc(get(Opc));
2040     WorkingMI.getOperand(3).setImm(Size - Amt);
2041     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2042                                                    OpIdx1, OpIdx2);
2043   }
2044   case X86::PFSUBrr:
2045   case X86::PFSUBRrr: {
2046     // PFSUB  x, y: x = x - y
2047     // PFSUBR x, y: x = y - x
2048     unsigned Opc =
2049         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2050     auto &WorkingMI = cloneIfNew(MI);
2051     WorkingMI.setDesc(get(Opc));
2052     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2053                                                    OpIdx1, OpIdx2);
2054   }
2055   case X86::BLENDPDrri:
2056   case X86::BLENDPSrri:
2057   case X86::VBLENDPDrri:
2058   case X86::VBLENDPSrri:
2059     // If we're optimizing for size, try to use MOVSD/MOVSS.
2060     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2061       unsigned Mask, Opc;
2062       switch (MI.getOpcode()) {
2063       default: llvm_unreachable("Unreachable!");
2064       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
2065       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
2066       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2067       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2068       }
2069       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2070         auto &WorkingMI = cloneIfNew(MI);
2071         WorkingMI.setDesc(get(Opc));
2072         WorkingMI.RemoveOperand(3);
2073         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2074                                                        /*NewMI=*/false,
2075                                                        OpIdx1, OpIdx2);
2076       }
2077     }
2078     LLVM_FALLTHROUGH;
2079   case X86::PBLENDWrri:
2080   case X86::VBLENDPDYrri:
2081   case X86::VBLENDPSYrri:
2082   case X86::VPBLENDDrri:
2083   case X86::VPBLENDWrri:
2084   case X86::VPBLENDDYrri:
2085   case X86::VPBLENDWYrri:{
2086     int8_t Mask;
2087     switch (MI.getOpcode()) {
2088     default: llvm_unreachable("Unreachable!");
2089     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
2090     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
2091     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
2092     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
2093     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
2094     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
2095     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
2096     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
2097     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
2098     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
2099     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
2100     }
2101     // Only the least significant bits of Imm are used.
2102     // Using int8_t to ensure it will be sign extended to the int64_t that
2103     // setImm takes in order to match isel behavior.
2104     int8_t Imm = MI.getOperand(3).getImm() & Mask;
2105     auto &WorkingMI = cloneIfNew(MI);
2106     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2107     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2108                                                    OpIdx1, OpIdx2);
2109   }
2110   case X86::INSERTPSrr:
2111   case X86::VINSERTPSrr:
2112   case X86::VINSERTPSZrr: {
2113     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2114     unsigned ZMask = Imm & 15;
2115     unsigned DstIdx = (Imm >> 4) & 3;
2116     unsigned SrcIdx = (Imm >> 6) & 3;
2117 
2118     // We can commute insertps if we zero 2 of the elements, the insertion is
2119     // "inline" and we don't override the insertion with a zero.
2120     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2121         countPopulation(ZMask) == 2) {
2122       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2123       assert(AltIdx < 4 && "Illegal insertion index");
2124       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2125       auto &WorkingMI = cloneIfNew(MI);
2126       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2127       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2128                                                      OpIdx1, OpIdx2);
2129     }
2130     return nullptr;
2131   }
2132   case X86::MOVSDrr:
2133   case X86::MOVSSrr:
2134   case X86::VMOVSDrr:
2135   case X86::VMOVSSrr:{
2136     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2137     if (Subtarget.hasSSE41()) {
2138       unsigned Mask, Opc;
2139       switch (MI.getOpcode()) {
2140       default: llvm_unreachable("Unreachable!");
2141       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
2142       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
2143       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2144       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2145       }
2146 
2147       auto &WorkingMI = cloneIfNew(MI);
2148       WorkingMI.setDesc(get(Opc));
2149       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2150       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2151                                                      OpIdx1, OpIdx2);
2152     }
2153 
2154     // Convert to SHUFPD.
2155     assert(MI.getOpcode() == X86::MOVSDrr &&
2156            "Can only commute MOVSDrr without SSE4.1");
2157 
2158     auto &WorkingMI = cloneIfNew(MI);
2159     WorkingMI.setDesc(get(X86::SHUFPDrri));
2160     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2161     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2162                                                    OpIdx1, OpIdx2);
2163   }
2164   case X86::SHUFPDrri: {
2165     // Commute to MOVSD.
2166     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2167     auto &WorkingMI = cloneIfNew(MI);
2168     WorkingMI.setDesc(get(X86::MOVSDrr));
2169     WorkingMI.RemoveOperand(3);
2170     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2171                                                    OpIdx1, OpIdx2);
2172   }
2173   case X86::PCLMULQDQrr:
2174   case X86::VPCLMULQDQrr:
2175   case X86::VPCLMULQDQYrr:
2176   case X86::VPCLMULQDQZrr:
2177   case X86::VPCLMULQDQZ128rr:
2178   case X86::VPCLMULQDQZ256rr: {
2179     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2180     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2181     unsigned Imm = MI.getOperand(3).getImm();
2182     unsigned Src1Hi = Imm & 0x01;
2183     unsigned Src2Hi = Imm & 0x10;
2184     auto &WorkingMI = cloneIfNew(MI);
2185     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2186     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2187                                                    OpIdx1, OpIdx2);
2188   }
2189   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2190   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2191   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2192   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2193   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2194   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2195   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2196   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2197   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2198   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2199   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2200   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2201   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2202   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2203   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2204   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2205   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2206   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2207   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2208   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2209   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2210   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2211   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2212   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2213     // Flip comparison mode immediate (if necessary).
2214     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2215     Imm = X86::getSwappedVPCMPImm(Imm);
2216     auto &WorkingMI = cloneIfNew(MI);
2217     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2218     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2219                                                    OpIdx1, OpIdx2);
2220   }
2221   case X86::VPCOMBri: case X86::VPCOMUBri:
2222   case X86::VPCOMDri: case X86::VPCOMUDri:
2223   case X86::VPCOMQri: case X86::VPCOMUQri:
2224   case X86::VPCOMWri: case X86::VPCOMUWri: {
2225     // Flip comparison mode immediate (if necessary).
2226     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2227     Imm = X86::getSwappedVPCOMImm(Imm);
2228     auto &WorkingMI = cloneIfNew(MI);
2229     WorkingMI.getOperand(3).setImm(Imm);
2230     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2231                                                    OpIdx1, OpIdx2);
2232   }
2233   case X86::VCMPSDZrr:
2234   case X86::VCMPSSZrr:
2235   case X86::VCMPPDZrri:
2236   case X86::VCMPPSZrri:
2237   case X86::VCMPPDZ128rri:
2238   case X86::VCMPPSZ128rri:
2239   case X86::VCMPPDZ256rri:
2240   case X86::VCMPPSZ256rri:
2241   case X86::VCMPPDZrrik:
2242   case X86::VCMPPSZrrik:
2243   case X86::VCMPPDZ128rrik:
2244   case X86::VCMPPSZ128rrik:
2245   case X86::VCMPPDZ256rrik:
2246   case X86::VCMPPSZ256rrik: {
2247     unsigned Imm =
2248                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2249     Imm = X86::getSwappedVCMPImm(Imm);
2250     auto &WorkingMI = cloneIfNew(MI);
2251     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2252     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2253                                                    OpIdx1, OpIdx2);
2254   }
2255   case X86::VPERM2F128rr:
2256   case X86::VPERM2I128rr: {
2257     // Flip permute source immediate.
2258     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2259     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2260     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2261     auto &WorkingMI = cloneIfNew(MI);
2262     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2263     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2264                                                    OpIdx1, OpIdx2);
2265   }
2266   case X86::MOVHLPSrr:
2267   case X86::UNPCKHPDrr:
2268   case X86::VMOVHLPSrr:
2269   case X86::VUNPCKHPDrr:
2270   case X86::VMOVHLPSZrr:
2271   case X86::VUNPCKHPDZ128rr: {
2272     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2273 
2274     unsigned Opc = MI.getOpcode();
2275     switch (Opc) {
2276     default: llvm_unreachable("Unreachable!");
2277     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2278     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2279     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2280     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2281     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2282     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2283     }
2284     auto &WorkingMI = cloneIfNew(MI);
2285     WorkingMI.setDesc(get(Opc));
2286     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2287                                                    OpIdx1, OpIdx2);
2288   }
2289   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2290     auto &WorkingMI = cloneIfNew(MI);
2291     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2292     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2293     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2294     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2295                                                    OpIdx1, OpIdx2);
2296   }
2297   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2298   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2299   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2300   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2301   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2302   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2303   case X86::VPTERNLOGDZrrik:
2304   case X86::VPTERNLOGDZ128rrik:
2305   case X86::VPTERNLOGDZ256rrik:
2306   case X86::VPTERNLOGQZrrik:
2307   case X86::VPTERNLOGQZ128rrik:
2308   case X86::VPTERNLOGQZ256rrik:
2309   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2310   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2311   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2312   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2313   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2314   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2315   case X86::VPTERNLOGDZ128rmbi:
2316   case X86::VPTERNLOGDZ256rmbi:
2317   case X86::VPTERNLOGDZrmbi:
2318   case X86::VPTERNLOGQZ128rmbi:
2319   case X86::VPTERNLOGQZ256rmbi:
2320   case X86::VPTERNLOGQZrmbi:
2321   case X86::VPTERNLOGDZ128rmbikz:
2322   case X86::VPTERNLOGDZ256rmbikz:
2323   case X86::VPTERNLOGDZrmbikz:
2324   case X86::VPTERNLOGQZ128rmbikz:
2325   case X86::VPTERNLOGQZ256rmbikz:
2326   case X86::VPTERNLOGQZrmbikz: {
2327     auto &WorkingMI = cloneIfNew(MI);
2328     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2329     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2330                                                    OpIdx1, OpIdx2);
2331   }
2332   default: {
2333     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2334       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2335       auto &WorkingMI = cloneIfNew(MI);
2336       WorkingMI.setDesc(get(Opc));
2337       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2338                                                      OpIdx1, OpIdx2);
2339     }
2340 
2341     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2342                                                       MI.getDesc().TSFlags);
2343     if (FMA3Group) {
2344       unsigned Opc =
2345         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2346       auto &WorkingMI = cloneIfNew(MI);
2347       WorkingMI.setDesc(get(Opc));
2348       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2349                                                      OpIdx1, OpIdx2);
2350     }
2351 
2352     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2353   }
2354   }
2355 }
2356 
2357 bool
2358 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2359                                             unsigned &SrcOpIdx1,
2360                                             unsigned &SrcOpIdx2,
2361                                             bool IsIntrinsic) const {
2362   uint64_t TSFlags = MI.getDesc().TSFlags;
2363 
2364   unsigned FirstCommutableVecOp = 1;
2365   unsigned LastCommutableVecOp = 3;
2366   unsigned KMaskOp = -1U;
2367   if (X86II::isKMasked(TSFlags)) {
2368     // For k-zero-masked operations it is Ok to commute the first vector
2369     // operand. Unless this is an intrinsic instruction.
2370     // For regular k-masked operations a conservative choice is done as the
2371     // elements of the first vector operand, for which the corresponding bit
2372     // in the k-mask operand is set to 0, are copied to the result of the
2373     // instruction.
2374     // TODO/FIXME: The commute still may be legal if it is known that the
2375     // k-mask operand is set to either all ones or all zeroes.
2376     // It is also Ok to commute the 1st operand if all users of MI use only
2377     // the elements enabled by the k-mask operand. For example,
2378     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2379     //                                                     : v1[i];
2380     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2381     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2382 
2383     // The k-mask operand has index = 2 for masked and zero-masked operations.
2384     KMaskOp = 2;
2385 
2386     // The operand with index = 1 is used as a source for those elements for
2387     // which the corresponding bit in the k-mask is set to 0.
2388     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2389       FirstCommutableVecOp = 3;
2390 
2391     LastCommutableVecOp++;
2392   } else if (IsIntrinsic) {
2393     // Commuting the first operand of an intrinsic instruction isn't possible
2394     // unless we can prove that only the lowest element of the result is used.
2395     FirstCommutableVecOp = 2;
2396   }
2397 
2398   if (isMem(MI, LastCommutableVecOp))
2399     LastCommutableVecOp--;
2400 
2401   // Only the first RegOpsNum operands are commutable.
2402   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2403   // that the operand is not specified/fixed.
2404   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2405       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2406        SrcOpIdx1 == KMaskOp))
2407     return false;
2408   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2409       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2410        SrcOpIdx2 == KMaskOp))
2411     return false;
2412 
2413   // Look for two different register operands assumed to be commutable
2414   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2415   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2416       SrcOpIdx2 == CommuteAnyOperandIndex) {
2417     unsigned CommutableOpIdx2 = SrcOpIdx2;
2418 
2419     // At least one of operands to be commuted is not specified and
2420     // this method is free to choose appropriate commutable operands.
2421     if (SrcOpIdx1 == SrcOpIdx2)
2422       // Both of operands are not fixed. By default set one of commutable
2423       // operands to the last register operand of the instruction.
2424       CommutableOpIdx2 = LastCommutableVecOp;
2425     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2426       // Only one of operands is not fixed.
2427       CommutableOpIdx2 = SrcOpIdx1;
2428 
2429     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2430     // operand and assign its index to CommutableOpIdx1.
2431     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2432 
2433     unsigned CommutableOpIdx1;
2434     for (CommutableOpIdx1 = LastCommutableVecOp;
2435          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2436       // Just ignore and skip the k-mask operand.
2437       if (CommutableOpIdx1 == KMaskOp)
2438         continue;
2439 
2440       // The commuted operands must have different registers.
2441       // Otherwise, the commute transformation does not change anything and
2442       // is useless then.
2443       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2444         break;
2445     }
2446 
2447     // No appropriate commutable operands were found.
2448     if (CommutableOpIdx1 < FirstCommutableVecOp)
2449       return false;
2450 
2451     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2452     // to return those values.
2453     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2454                               CommutableOpIdx1, CommutableOpIdx2))
2455       return false;
2456   }
2457 
2458   return true;
2459 }
2460 
2461 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2462                                          unsigned &SrcOpIdx1,
2463                                          unsigned &SrcOpIdx2) const {
2464   const MCInstrDesc &Desc = MI.getDesc();
2465   if (!Desc.isCommutable())
2466     return false;
2467 
2468   switch (MI.getOpcode()) {
2469   case X86::CMPSDrr:
2470   case X86::CMPSSrr:
2471   case X86::CMPPDrri:
2472   case X86::CMPPSrri:
2473   case X86::VCMPSDrr:
2474   case X86::VCMPSSrr:
2475   case X86::VCMPPDrri:
2476   case X86::VCMPPSrri:
2477   case X86::VCMPPDYrri:
2478   case X86::VCMPPSYrri:
2479   case X86::VCMPSDZrr:
2480   case X86::VCMPSSZrr:
2481   case X86::VCMPPDZrri:
2482   case X86::VCMPPSZrri:
2483   case X86::VCMPPDZ128rri:
2484   case X86::VCMPPSZ128rri:
2485   case X86::VCMPPDZ256rri:
2486   case X86::VCMPPSZ256rri:
2487   case X86::VCMPPDZrrik:
2488   case X86::VCMPPSZrrik:
2489   case X86::VCMPPDZ128rrik:
2490   case X86::VCMPPSZ128rrik:
2491   case X86::VCMPPDZ256rrik:
2492   case X86::VCMPPSZ256rrik: {
2493     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2494 
2495     // Float comparison can be safely commuted for
2496     // Ordered/Unordered/Equal/NotEqual tests
2497     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2498     switch (Imm) {
2499     default:
2500       // EVEX versions can be commuted.
2501       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2502         break;
2503       return false;
2504     case 0x00: // EQUAL
2505     case 0x03: // UNORDERED
2506     case 0x04: // NOT EQUAL
2507     case 0x07: // ORDERED
2508       break;
2509     }
2510 
2511     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2512     // when masked).
2513     // Assign them to the returned operand indices here.
2514     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2515                                 2 + OpOffset);
2516   }
2517   case X86::MOVSSrr:
2518     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2519     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2520     // AVX implies sse4.1.
2521     if (Subtarget.hasSSE41())
2522       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2523     return false;
2524   case X86::SHUFPDrri:
2525     // We can commute this to MOVSD.
2526     if (MI.getOperand(3).getImm() == 0x02)
2527       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2528     return false;
2529   case X86::MOVHLPSrr:
2530   case X86::UNPCKHPDrr:
2531   case X86::VMOVHLPSrr:
2532   case X86::VUNPCKHPDrr:
2533   case X86::VMOVHLPSZrr:
2534   case X86::VUNPCKHPDZ128rr:
2535     if (Subtarget.hasSSE2())
2536       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2537     return false;
2538   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2539   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2540   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2541   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2542   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2543   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2544   case X86::VPTERNLOGDZrrik:
2545   case X86::VPTERNLOGDZ128rrik:
2546   case X86::VPTERNLOGDZ256rrik:
2547   case X86::VPTERNLOGQZrrik:
2548   case X86::VPTERNLOGQZ128rrik:
2549   case X86::VPTERNLOGQZ256rrik:
2550   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2551   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2552   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2553   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2554   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2555   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2556   case X86::VPTERNLOGDZ128rmbi:
2557   case X86::VPTERNLOGDZ256rmbi:
2558   case X86::VPTERNLOGDZrmbi:
2559   case X86::VPTERNLOGQZ128rmbi:
2560   case X86::VPTERNLOGQZ256rmbi:
2561   case X86::VPTERNLOGQZrmbi:
2562   case X86::VPTERNLOGDZ128rmbikz:
2563   case X86::VPTERNLOGDZ256rmbikz:
2564   case X86::VPTERNLOGDZrmbikz:
2565   case X86::VPTERNLOGQZ128rmbikz:
2566   case X86::VPTERNLOGQZ256rmbikz:
2567   case X86::VPTERNLOGQZrmbikz:
2568     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2569   case X86::VPDPWSSDYrr:
2570   case X86::VPDPWSSDrr:
2571   case X86::VPDPWSSDSYrr:
2572   case X86::VPDPWSSDSrr:
2573   case X86::VPDPWSSDZ128r:
2574   case X86::VPDPWSSDZ128rk:
2575   case X86::VPDPWSSDZ128rkz:
2576   case X86::VPDPWSSDZ256r:
2577   case X86::VPDPWSSDZ256rk:
2578   case X86::VPDPWSSDZ256rkz:
2579   case X86::VPDPWSSDZr:
2580   case X86::VPDPWSSDZrk:
2581   case X86::VPDPWSSDZrkz:
2582   case X86::VPDPWSSDSZ128r:
2583   case X86::VPDPWSSDSZ128rk:
2584   case X86::VPDPWSSDSZ128rkz:
2585   case X86::VPDPWSSDSZ256r:
2586   case X86::VPDPWSSDSZ256rk:
2587   case X86::VPDPWSSDSZ256rkz:
2588   case X86::VPDPWSSDSZr:
2589   case X86::VPDPWSSDSZrk:
2590   case X86::VPDPWSSDSZrkz:
2591   case X86::VPMADD52HUQZ128r:
2592   case X86::VPMADD52HUQZ128rk:
2593   case X86::VPMADD52HUQZ128rkz:
2594   case X86::VPMADD52HUQZ256r:
2595   case X86::VPMADD52HUQZ256rk:
2596   case X86::VPMADD52HUQZ256rkz:
2597   case X86::VPMADD52HUQZr:
2598   case X86::VPMADD52HUQZrk:
2599   case X86::VPMADD52HUQZrkz:
2600   case X86::VPMADD52LUQZ128r:
2601   case X86::VPMADD52LUQZ128rk:
2602   case X86::VPMADD52LUQZ128rkz:
2603   case X86::VPMADD52LUQZ256r:
2604   case X86::VPMADD52LUQZ256rk:
2605   case X86::VPMADD52LUQZ256rkz:
2606   case X86::VPMADD52LUQZr:
2607   case X86::VPMADD52LUQZrk:
2608   case X86::VPMADD52LUQZrkz: {
2609     unsigned CommutableOpIdx1 = 2;
2610     unsigned CommutableOpIdx2 = 3;
2611     if (X86II::isKMasked(Desc.TSFlags)) {
2612       // Skip the mask register.
2613       ++CommutableOpIdx1;
2614       ++CommutableOpIdx2;
2615     }
2616     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2617                               CommutableOpIdx1, CommutableOpIdx2))
2618       return false;
2619     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2620         !MI.getOperand(SrcOpIdx2).isReg())
2621       // No idea.
2622       return false;
2623     return true;
2624   }
2625 
2626   default:
2627     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2628                                                       MI.getDesc().TSFlags);
2629     if (FMA3Group)
2630       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2631                                            FMA3Group->isIntrinsic());
2632 
2633     // Handled masked instructions since we need to skip over the mask input
2634     // and the preserved input.
2635     if (X86II::isKMasked(Desc.TSFlags)) {
2636       // First assume that the first input is the mask operand and skip past it.
2637       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2638       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2639       // Check if the first input is tied. If there isn't one then we only
2640       // need to skip the mask operand which we did above.
2641       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2642                                              MCOI::TIED_TO) != -1)) {
2643         // If this is zero masking instruction with a tied operand, we need to
2644         // move the first index back to the first input since this must
2645         // be a 3 input instruction and we want the first two non-mask inputs.
2646         // Otherwise this is a 2 input instruction with a preserved input and
2647         // mask, so we need to move the indices to skip one more input.
2648         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2649           ++CommutableOpIdx1;
2650           ++CommutableOpIdx2;
2651         } else {
2652           --CommutableOpIdx1;
2653         }
2654       }
2655 
2656       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2657                                 CommutableOpIdx1, CommutableOpIdx2))
2658         return false;
2659 
2660       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2661           !MI.getOperand(SrcOpIdx2).isReg())
2662         // No idea.
2663         return false;
2664       return true;
2665     }
2666 
2667     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2668   }
2669   return false;
2670 }
2671 
2672 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2673   switch (MI.getOpcode()) {
2674   default: return X86::COND_INVALID;
2675   case X86::JCC_1:
2676     return static_cast<X86::CondCode>(
2677         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2678   }
2679 }
2680 
2681 /// Return condition code of a SETCC opcode.
2682 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2683   switch (MI.getOpcode()) {
2684   default: return X86::COND_INVALID;
2685   case X86::SETCCr: case X86::SETCCm:
2686     return static_cast<X86::CondCode>(
2687         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2688   }
2689 }
2690 
2691 /// Return condition code of a CMov opcode.
2692 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2693   switch (MI.getOpcode()) {
2694   default: return X86::COND_INVALID;
2695   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2696   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2697     return static_cast<X86::CondCode>(
2698         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2699   }
2700 }
2701 
2702 /// Return the inverse of the specified condition,
2703 /// e.g. turning COND_E to COND_NE.
2704 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2705   switch (CC) {
2706   default: llvm_unreachable("Illegal condition code!");
2707   case X86::COND_E:  return X86::COND_NE;
2708   case X86::COND_NE: return X86::COND_E;
2709   case X86::COND_L:  return X86::COND_GE;
2710   case X86::COND_LE: return X86::COND_G;
2711   case X86::COND_G:  return X86::COND_LE;
2712   case X86::COND_GE: return X86::COND_L;
2713   case X86::COND_B:  return X86::COND_AE;
2714   case X86::COND_BE: return X86::COND_A;
2715   case X86::COND_A:  return X86::COND_BE;
2716   case X86::COND_AE: return X86::COND_B;
2717   case X86::COND_S:  return X86::COND_NS;
2718   case X86::COND_NS: return X86::COND_S;
2719   case X86::COND_P:  return X86::COND_NP;
2720   case X86::COND_NP: return X86::COND_P;
2721   case X86::COND_O:  return X86::COND_NO;
2722   case X86::COND_NO: return X86::COND_O;
2723   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2724   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2725   }
2726 }
2727 
2728 /// Assuming the flags are set by MI(a,b), return the condition code if we
2729 /// modify the instructions such that flags are set by MI(b,a).
2730 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2731   switch (CC) {
2732   default: return X86::COND_INVALID;
2733   case X86::COND_E:  return X86::COND_E;
2734   case X86::COND_NE: return X86::COND_NE;
2735   case X86::COND_L:  return X86::COND_G;
2736   case X86::COND_LE: return X86::COND_GE;
2737   case X86::COND_G:  return X86::COND_L;
2738   case X86::COND_GE: return X86::COND_LE;
2739   case X86::COND_B:  return X86::COND_A;
2740   case X86::COND_BE: return X86::COND_AE;
2741   case X86::COND_A:  return X86::COND_B;
2742   case X86::COND_AE: return X86::COND_BE;
2743   }
2744 }
2745 
2746 std::pair<X86::CondCode, bool>
2747 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2748   X86::CondCode CC = X86::COND_INVALID;
2749   bool NeedSwap = false;
2750   switch (Predicate) {
2751   default: break;
2752   // Floating-point Predicates
2753   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2754   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2755   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2756   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2757   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2758   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2759   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2760   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2761   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2762   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2763   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2764   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2765   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2766   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2767 
2768   // Integer Predicates
2769   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2770   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2771   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2772   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2773   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2774   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2775   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2776   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2777   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2778   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2779   }
2780 
2781   return std::make_pair(CC, NeedSwap);
2782 }
2783 
2784 /// Return a setcc opcode based on whether it has memory operand.
2785 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2786   return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2787 }
2788 
2789 /// Return a cmov opcode for the given register size in bytes, and operand type.
2790 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2791   switch(RegBytes) {
2792   default: llvm_unreachable("Illegal register size!");
2793   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2794   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2795   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2796   }
2797 }
2798 
2799 /// Get the VPCMP immediate for the given condition.
2800 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2801   switch (CC) {
2802   default: llvm_unreachable("Unexpected SETCC condition");
2803   case ISD::SETNE:  return 4;
2804   case ISD::SETEQ:  return 0;
2805   case ISD::SETULT:
2806   case ISD::SETLT: return 1;
2807   case ISD::SETUGT:
2808   case ISD::SETGT: return 6;
2809   case ISD::SETUGE:
2810   case ISD::SETGE: return 5;
2811   case ISD::SETULE:
2812   case ISD::SETLE: return 2;
2813   }
2814 }
2815 
2816 /// Get the VPCMP immediate if the operands are swapped.
2817 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2818   switch (Imm) {
2819   default: llvm_unreachable("Unreachable!");
2820   case 0x01: Imm = 0x06; break; // LT  -> NLE
2821   case 0x02: Imm = 0x05; break; // LE  -> NLT
2822   case 0x05: Imm = 0x02; break; // NLT -> LE
2823   case 0x06: Imm = 0x01; break; // NLE -> LT
2824   case 0x00: // EQ
2825   case 0x03: // FALSE
2826   case 0x04: // NE
2827   case 0x07: // TRUE
2828     break;
2829   }
2830 
2831   return Imm;
2832 }
2833 
2834 /// Get the VPCOM immediate if the operands are swapped.
2835 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2836   switch (Imm) {
2837   default: llvm_unreachable("Unreachable!");
2838   case 0x00: Imm = 0x02; break; // LT -> GT
2839   case 0x01: Imm = 0x03; break; // LE -> GE
2840   case 0x02: Imm = 0x00; break; // GT -> LT
2841   case 0x03: Imm = 0x01; break; // GE -> LE
2842   case 0x04: // EQ
2843   case 0x05: // NE
2844   case 0x06: // FALSE
2845   case 0x07: // TRUE
2846     break;
2847   }
2848 
2849   return Imm;
2850 }
2851 
2852 /// Get the VCMP immediate if the operands are swapped.
2853 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2854   // Only need the lower 2 bits to distinquish.
2855   switch (Imm & 0x3) {
2856   default: llvm_unreachable("Unreachable!");
2857   case 0x00: case 0x03:
2858     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2859     break;
2860   case 0x01: case 0x02:
2861     // Need to toggle bits 3:0. Bit 4 stays the same.
2862     Imm ^= 0xf;
2863     break;
2864   }
2865 
2866   return Imm;
2867 }
2868 
2869 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2870   switch (MI.getOpcode()) {
2871   case X86::TCRETURNdi:
2872   case X86::TCRETURNri:
2873   case X86::TCRETURNmi:
2874   case X86::TCRETURNdi64:
2875   case X86::TCRETURNri64:
2876   case X86::TCRETURNmi64:
2877     return true;
2878   default:
2879     return false;
2880   }
2881 }
2882 
2883 bool X86InstrInfo::canMakeTailCallConditional(
2884     SmallVectorImpl<MachineOperand> &BranchCond,
2885     const MachineInstr &TailCall) const {
2886   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2887       TailCall.getOpcode() != X86::TCRETURNdi64) {
2888     // Only direct calls can be done with a conditional branch.
2889     return false;
2890   }
2891 
2892   const MachineFunction *MF = TailCall.getParent()->getParent();
2893   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2894     // Conditional tail calls confuse the Win64 unwinder.
2895     return false;
2896   }
2897 
2898   assert(BranchCond.size() == 1);
2899   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2900     // Can't make a conditional tail call with this condition.
2901     return false;
2902   }
2903 
2904   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2905   if (X86FI->getTCReturnAddrDelta() != 0 ||
2906       TailCall.getOperand(1).getImm() != 0) {
2907     // A conditional tail call cannot do any stack adjustment.
2908     return false;
2909   }
2910 
2911   return true;
2912 }
2913 
2914 void X86InstrInfo::replaceBranchWithTailCall(
2915     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2916     const MachineInstr &TailCall) const {
2917   assert(canMakeTailCallConditional(BranchCond, TailCall));
2918 
2919   MachineBasicBlock::iterator I = MBB.end();
2920   while (I != MBB.begin()) {
2921     --I;
2922     if (I->isDebugInstr())
2923       continue;
2924     if (!I->isBranch())
2925       assert(0 && "Can't find the branch to replace!");
2926 
2927     X86::CondCode CC = X86::getCondFromBranch(*I);
2928     assert(BranchCond.size() == 1);
2929     if (CC != BranchCond[0].getImm())
2930       continue;
2931 
2932     break;
2933   }
2934 
2935   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2936                                                          : X86::TCRETURNdi64cc;
2937 
2938   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2939   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2940   MIB.addImm(0); // Stack offset (not used).
2941   MIB->addOperand(BranchCond[0]); // Condition.
2942   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2943 
2944   // Add implicit uses and defs of all live regs potentially clobbered by the
2945   // call. This way they still appear live across the call.
2946   LivePhysRegs LiveRegs(getRegisterInfo());
2947   LiveRegs.addLiveOuts(MBB);
2948   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2949   LiveRegs.stepForward(*MIB, Clobbers);
2950   for (const auto &C : Clobbers) {
2951     MIB.addReg(C.first, RegState::Implicit);
2952     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2953   }
2954 
2955   I->eraseFromParent();
2956 }
2957 
2958 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2959 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2960 // fallthrough MBB cannot be identified.
2961 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2962                                             MachineBasicBlock *TBB) {
2963   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2964   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2965   // and fallthrough MBB. If we find more than one, we cannot identify the
2966   // fallthrough MBB and should return nullptr.
2967   MachineBasicBlock *FallthroughBB = nullptr;
2968   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2969     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2970       continue;
2971     // Return a nullptr if we found more than one fallthrough successor.
2972     if (FallthroughBB && FallthroughBB != TBB)
2973       return nullptr;
2974     FallthroughBB = *SI;
2975   }
2976   return FallthroughBB;
2977 }
2978 
2979 bool X86InstrInfo::AnalyzeBranchImpl(
2980     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2981     SmallVectorImpl<MachineOperand> &Cond,
2982     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2983 
2984   // Start from the bottom of the block and work up, examining the
2985   // terminator instructions.
2986   MachineBasicBlock::iterator I = MBB.end();
2987   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2988   while (I != MBB.begin()) {
2989     --I;
2990     if (I->isDebugInstr())
2991       continue;
2992 
2993     // Working from the bottom, when we see a non-terminator instruction, we're
2994     // done.
2995     if (!isUnpredicatedTerminator(*I))
2996       break;
2997 
2998     // A terminator that isn't a branch can't easily be handled by this
2999     // analysis.
3000     if (!I->isBranch())
3001       return true;
3002 
3003     // Handle unconditional branches.
3004     if (I->getOpcode() == X86::JMP_1) {
3005       UnCondBrIter = I;
3006 
3007       if (!AllowModify) {
3008         TBB = I->getOperand(0).getMBB();
3009         continue;
3010       }
3011 
3012       // If the block has any instructions after a JMP, delete them.
3013       while (std::next(I) != MBB.end())
3014         std::next(I)->eraseFromParent();
3015 
3016       Cond.clear();
3017       FBB = nullptr;
3018 
3019       // Delete the JMP if it's equivalent to a fall-through.
3020       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3021         TBB = nullptr;
3022         I->eraseFromParent();
3023         I = MBB.end();
3024         UnCondBrIter = MBB.end();
3025         continue;
3026       }
3027 
3028       // TBB is used to indicate the unconditional destination.
3029       TBB = I->getOperand(0).getMBB();
3030       continue;
3031     }
3032 
3033     // Handle conditional branches.
3034     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3035     if (BranchCode == X86::COND_INVALID)
3036       return true;  // Can't handle indirect branch.
3037 
3038     // In practice we should never have an undef eflags operand, if we do
3039     // abort here as we are not prepared to preserve the flag.
3040     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3041       return true;
3042 
3043     // Working from the bottom, handle the first conditional branch.
3044     if (Cond.empty()) {
3045       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3046       if (AllowModify && UnCondBrIter != MBB.end() &&
3047           MBB.isLayoutSuccessor(TargetBB)) {
3048         // If we can modify the code and it ends in something like:
3049         //
3050         //     jCC L1
3051         //     jmp L2
3052         //   L1:
3053         //     ...
3054         //   L2:
3055         //
3056         // Then we can change this to:
3057         //
3058         //     jnCC L2
3059         //   L1:
3060         //     ...
3061         //   L2:
3062         //
3063         // Which is a bit more efficient.
3064         // We conditionally jump to the fall-through block.
3065         BranchCode = GetOppositeBranchCondition(BranchCode);
3066         MachineBasicBlock::iterator OldInst = I;
3067 
3068         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3069           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3070           .addImm(BranchCode);
3071         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3072           .addMBB(TargetBB);
3073 
3074         OldInst->eraseFromParent();
3075         UnCondBrIter->eraseFromParent();
3076 
3077         // Restart the analysis.
3078         UnCondBrIter = MBB.end();
3079         I = MBB.end();
3080         continue;
3081       }
3082 
3083       FBB = TBB;
3084       TBB = I->getOperand(0).getMBB();
3085       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3086       CondBranches.push_back(&*I);
3087       continue;
3088     }
3089 
3090     // Handle subsequent conditional branches. Only handle the case where all
3091     // conditional branches branch to the same destination and their condition
3092     // opcodes fit one of the special multi-branch idioms.
3093     assert(Cond.size() == 1);
3094     assert(TBB);
3095 
3096     // If the conditions are the same, we can leave them alone.
3097     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3098     auto NewTBB = I->getOperand(0).getMBB();
3099     if (OldBranchCode == BranchCode && TBB == NewTBB)
3100       continue;
3101 
3102     // If they differ, see if they fit one of the known patterns. Theoretically,
3103     // we could handle more patterns here, but we shouldn't expect to see them
3104     // if instruction selection has done a reasonable job.
3105     if (TBB == NewTBB &&
3106                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3107                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3108       BranchCode = X86::COND_NE_OR_P;
3109     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3110                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3111       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3112         return true;
3113 
3114       // X86::COND_E_AND_NP usually has two different branch destinations.
3115       //
3116       // JP B1
3117       // JE B2
3118       // JMP B1
3119       // B1:
3120       // B2:
3121       //
3122       // Here this condition branches to B2 only if NP && E. It has another
3123       // equivalent form:
3124       //
3125       // JNE B1
3126       // JNP B2
3127       // JMP B1
3128       // B1:
3129       // B2:
3130       //
3131       // Similarly it branches to B2 only if E && NP. That is why this condition
3132       // is named with COND_E_AND_NP.
3133       BranchCode = X86::COND_E_AND_NP;
3134     } else
3135       return true;
3136 
3137     // Update the MachineOperand.
3138     Cond[0].setImm(BranchCode);
3139     CondBranches.push_back(&*I);
3140   }
3141 
3142   return false;
3143 }
3144 
3145 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3146                                  MachineBasicBlock *&TBB,
3147                                  MachineBasicBlock *&FBB,
3148                                  SmallVectorImpl<MachineOperand> &Cond,
3149                                  bool AllowModify) const {
3150   SmallVector<MachineInstr *, 4> CondBranches;
3151   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3152 }
3153 
3154 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3155                                           MachineBranchPredicate &MBP,
3156                                           bool AllowModify) const {
3157   using namespace std::placeholders;
3158 
3159   SmallVector<MachineOperand, 4> Cond;
3160   SmallVector<MachineInstr *, 4> CondBranches;
3161   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3162                         AllowModify))
3163     return true;
3164 
3165   if (Cond.size() != 1)
3166     return true;
3167 
3168   assert(MBP.TrueDest && "expected!");
3169 
3170   if (!MBP.FalseDest)
3171     MBP.FalseDest = MBB.getNextNode();
3172 
3173   const TargetRegisterInfo *TRI = &getRegisterInfo();
3174 
3175   MachineInstr *ConditionDef = nullptr;
3176   bool SingleUseCondition = true;
3177 
3178   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3179     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3180       ConditionDef = &*I;
3181       break;
3182     }
3183 
3184     if (I->readsRegister(X86::EFLAGS, TRI))
3185       SingleUseCondition = false;
3186   }
3187 
3188   if (!ConditionDef)
3189     return true;
3190 
3191   if (SingleUseCondition) {
3192     for (auto *Succ : MBB.successors())
3193       if (Succ->isLiveIn(X86::EFLAGS))
3194         SingleUseCondition = false;
3195   }
3196 
3197   MBP.ConditionDef = ConditionDef;
3198   MBP.SingleUseCondition = SingleUseCondition;
3199 
3200   // Currently we only recognize the simple pattern:
3201   //
3202   //   test %reg, %reg
3203   //   je %label
3204   //
3205   const unsigned TestOpcode =
3206       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3207 
3208   if (ConditionDef->getOpcode() == TestOpcode &&
3209       ConditionDef->getNumOperands() == 3 &&
3210       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3211       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3212     MBP.LHS = ConditionDef->getOperand(0);
3213     MBP.RHS = MachineOperand::CreateImm(0);
3214     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3215                         ? MachineBranchPredicate::PRED_NE
3216                         : MachineBranchPredicate::PRED_EQ;
3217     return false;
3218   }
3219 
3220   return true;
3221 }
3222 
3223 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3224                                     int *BytesRemoved) const {
3225   assert(!BytesRemoved && "code size not handled");
3226 
3227   MachineBasicBlock::iterator I = MBB.end();
3228   unsigned Count = 0;
3229 
3230   while (I != MBB.begin()) {
3231     --I;
3232     if (I->isDebugInstr())
3233       continue;
3234     if (I->getOpcode() != X86::JMP_1 &&
3235         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3236       break;
3237     // Remove the branch.
3238     I->eraseFromParent();
3239     I = MBB.end();
3240     ++Count;
3241   }
3242 
3243   return Count;
3244 }
3245 
3246 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3247                                     MachineBasicBlock *TBB,
3248                                     MachineBasicBlock *FBB,
3249                                     ArrayRef<MachineOperand> Cond,
3250                                     const DebugLoc &DL,
3251                                     int *BytesAdded) const {
3252   // Shouldn't be a fall through.
3253   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3254   assert((Cond.size() == 1 || Cond.size() == 0) &&
3255          "X86 branch conditions have one component!");
3256   assert(!BytesAdded && "code size not handled");
3257 
3258   if (Cond.empty()) {
3259     // Unconditional branch?
3260     assert(!FBB && "Unconditional branch with multiple successors!");
3261     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3262     return 1;
3263   }
3264 
3265   // If FBB is null, it is implied to be a fall-through block.
3266   bool FallThru = FBB == nullptr;
3267 
3268   // Conditional branch.
3269   unsigned Count = 0;
3270   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3271   switch (CC) {
3272   case X86::COND_NE_OR_P:
3273     // Synthesize NE_OR_P with two branches.
3274     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3275     ++Count;
3276     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3277     ++Count;
3278     break;
3279   case X86::COND_E_AND_NP:
3280     // Use the next block of MBB as FBB if it is null.
3281     if (FBB == nullptr) {
3282       FBB = getFallThroughMBB(&MBB, TBB);
3283       assert(FBB && "MBB cannot be the last block in function when the false "
3284                     "body is a fall-through.");
3285     }
3286     // Synthesize COND_E_AND_NP with two branches.
3287     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3288     ++Count;
3289     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3290     ++Count;
3291     break;
3292   default: {
3293     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3294     ++Count;
3295   }
3296   }
3297   if (!FallThru) {
3298     // Two-way Conditional branch. Insert the second branch.
3299     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3300     ++Count;
3301   }
3302   return Count;
3303 }
3304 
3305 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3306                                    ArrayRef<MachineOperand> Cond,
3307                                    Register DstReg, Register TrueReg,
3308                                    Register FalseReg, int &CondCycles,
3309                                    int &TrueCycles, int &FalseCycles) const {
3310   // Not all subtargets have cmov instructions.
3311   if (!Subtarget.hasCMov())
3312     return false;
3313   if (Cond.size() != 1)
3314     return false;
3315   // We cannot do the composite conditions, at least not in SSA form.
3316   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3317     return false;
3318 
3319   // Check register classes.
3320   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3321   const TargetRegisterClass *RC =
3322     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3323   if (!RC)
3324     return false;
3325 
3326   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3327   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3328       X86::GR32RegClass.hasSubClassEq(RC) ||
3329       X86::GR64RegClass.hasSubClassEq(RC)) {
3330     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3331     // Bridge. Probably Ivy Bridge as well.
3332     CondCycles = 2;
3333     TrueCycles = 2;
3334     FalseCycles = 2;
3335     return true;
3336   }
3337 
3338   // Can't do vectors.
3339   return false;
3340 }
3341 
3342 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3343                                 MachineBasicBlock::iterator I,
3344                                 const DebugLoc &DL, Register DstReg,
3345                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3346                                 Register FalseReg) const {
3347   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3348   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3349   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3350   assert(Cond.size() == 1 && "Invalid Cond array");
3351   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3352                                     false /*HasMemoryOperand*/);
3353   BuildMI(MBB, I, DL, get(Opc), DstReg)
3354       .addReg(FalseReg)
3355       .addReg(TrueReg)
3356       .addImm(Cond[0].getImm());
3357 }
3358 
3359 /// Test if the given register is a physical h register.
3360 static bool isHReg(unsigned Reg) {
3361   return X86::GR8_ABCD_HRegClass.contains(Reg);
3362 }
3363 
3364 // Try and copy between VR128/VR64 and GR64 registers.
3365 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3366                                         const X86Subtarget &Subtarget) {
3367   bool HasAVX = Subtarget.hasAVX();
3368   bool HasAVX512 = Subtarget.hasAVX512();
3369 
3370   // SrcReg(MaskReg) -> DestReg(GR64)
3371   // SrcReg(MaskReg) -> DestReg(GR32)
3372 
3373   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3374   if (X86::VK16RegClass.contains(SrcReg)) {
3375     if (X86::GR64RegClass.contains(DestReg)) {
3376       assert(Subtarget.hasBWI());
3377       return X86::KMOVQrk;
3378     }
3379     if (X86::GR32RegClass.contains(DestReg))
3380       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3381   }
3382 
3383   // SrcReg(GR64) -> DestReg(MaskReg)
3384   // SrcReg(GR32) -> DestReg(MaskReg)
3385 
3386   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3387   if (X86::VK16RegClass.contains(DestReg)) {
3388     if (X86::GR64RegClass.contains(SrcReg)) {
3389       assert(Subtarget.hasBWI());
3390       return X86::KMOVQkr;
3391     }
3392     if (X86::GR32RegClass.contains(SrcReg))
3393       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3394   }
3395 
3396 
3397   // SrcReg(VR128) -> DestReg(GR64)
3398   // SrcReg(VR64)  -> DestReg(GR64)
3399   // SrcReg(GR64)  -> DestReg(VR128)
3400   // SrcReg(GR64)  -> DestReg(VR64)
3401 
3402   if (X86::GR64RegClass.contains(DestReg)) {
3403     if (X86::VR128XRegClass.contains(SrcReg))
3404       // Copy from a VR128 register to a GR64 register.
3405       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3406              HasAVX    ? X86::VMOVPQIto64rr  :
3407                          X86::MOVPQIto64rr;
3408     if (X86::VR64RegClass.contains(SrcReg))
3409       // Copy from a VR64 register to a GR64 register.
3410       return X86::MMX_MOVD64from64rr;
3411   } else if (X86::GR64RegClass.contains(SrcReg)) {
3412     // Copy from a GR64 register to a VR128 register.
3413     if (X86::VR128XRegClass.contains(DestReg))
3414       return HasAVX512 ? X86::VMOV64toPQIZrr :
3415              HasAVX    ? X86::VMOV64toPQIrr  :
3416                          X86::MOV64toPQIrr;
3417     // Copy from a GR64 register to a VR64 register.
3418     if (X86::VR64RegClass.contains(DestReg))
3419       return X86::MMX_MOVD64to64rr;
3420   }
3421 
3422   // SrcReg(VR128) -> DestReg(GR32)
3423   // SrcReg(GR32)  -> DestReg(VR128)
3424 
3425   if (X86::GR32RegClass.contains(DestReg) &&
3426       X86::VR128XRegClass.contains(SrcReg))
3427     // Copy from a VR128 register to a GR32 register.
3428     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3429            HasAVX    ? X86::VMOVPDI2DIrr  :
3430                        X86::MOVPDI2DIrr;
3431 
3432   if (X86::VR128XRegClass.contains(DestReg) &&
3433       X86::GR32RegClass.contains(SrcReg))
3434     // Copy from a VR128 register to a VR128 register.
3435     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3436            HasAVX    ? X86::VMOVDI2PDIrr  :
3437                        X86::MOVDI2PDIrr;
3438   return 0;
3439 }
3440 
3441 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3442                                MachineBasicBlock::iterator MI,
3443                                const DebugLoc &DL, MCRegister DestReg,
3444                                MCRegister SrcReg, bool KillSrc) const {
3445   // First deal with the normal symmetric copies.
3446   bool HasAVX = Subtarget.hasAVX();
3447   bool HasVLX = Subtarget.hasVLX();
3448   unsigned Opc = 0;
3449   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3450     Opc = X86::MOV64rr;
3451   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3452     Opc = X86::MOV32rr;
3453   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3454     Opc = X86::MOV16rr;
3455   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3456     // Copying to or from a physical H register on x86-64 requires a NOREX
3457     // move.  Otherwise use a normal move.
3458     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3459         Subtarget.is64Bit()) {
3460       Opc = X86::MOV8rr_NOREX;
3461       // Both operands must be encodable without an REX prefix.
3462       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3463              "8-bit H register can not be copied outside GR8_NOREX");
3464     } else
3465       Opc = X86::MOV8rr;
3466   }
3467   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3468     Opc = X86::MMX_MOVQ64rr;
3469   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3470     if (HasVLX)
3471       Opc = X86::VMOVAPSZ128rr;
3472     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3473       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3474     else {
3475       // If this an extended register and we don't have VLX we need to use a
3476       // 512-bit move.
3477       Opc = X86::VMOVAPSZrr;
3478       const TargetRegisterInfo *TRI = &getRegisterInfo();
3479       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3480                                          &X86::VR512RegClass);
3481       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3482                                         &X86::VR512RegClass);
3483     }
3484   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3485     if (HasVLX)
3486       Opc = X86::VMOVAPSZ256rr;
3487     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3488       Opc = X86::VMOVAPSYrr;
3489     else {
3490       // If this an extended register and we don't have VLX we need to use a
3491       // 512-bit move.
3492       Opc = X86::VMOVAPSZrr;
3493       const TargetRegisterInfo *TRI = &getRegisterInfo();
3494       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3495                                          &X86::VR512RegClass);
3496       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3497                                         &X86::VR512RegClass);
3498     }
3499   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3500     Opc = X86::VMOVAPSZrr;
3501   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3502   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3503     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3504   if (!Opc)
3505     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3506 
3507   if (Opc) {
3508     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3509       .addReg(SrcReg, getKillRegState(KillSrc));
3510     return;
3511   }
3512 
3513   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3514     // FIXME: We use a fatal error here because historically LLVM has tried
3515     // lower some of these physreg copies and we want to ensure we get
3516     // reasonable bug reports if someone encounters a case no other testing
3517     // found. This path should be removed after the LLVM 7 release.
3518     report_fatal_error("Unable to copy EFLAGS physical register!");
3519   }
3520 
3521   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3522                     << RI.getName(DestReg) << '\n');
3523   report_fatal_error("Cannot emit physreg copy instruction");
3524 }
3525 
3526 Optional<DestSourcePair>
3527 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3528   if (MI.isMoveReg())
3529     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3530   return None;
3531 }
3532 
3533 static unsigned getLoadStoreRegOpcode(Register Reg,
3534                                       const TargetRegisterClass *RC,
3535                                       bool IsStackAligned,
3536                                       const X86Subtarget &STI, bool load) {
3537   bool HasAVX = STI.hasAVX();
3538   bool HasAVX512 = STI.hasAVX512();
3539   bool HasVLX = STI.hasVLX();
3540 
3541   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3542   default:
3543     llvm_unreachable("Unknown spill size");
3544   case 1:
3545     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3546     if (STI.is64Bit())
3547       // Copying to or from a physical H register on x86-64 requires a NOREX
3548       // move.  Otherwise use a normal move.
3549       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3550         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3551     return load ? X86::MOV8rm : X86::MOV8mr;
3552   case 2:
3553     if (X86::VK16RegClass.hasSubClassEq(RC))
3554       return load ? X86::KMOVWkm : X86::KMOVWmk;
3555     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3556     return load ? X86::MOV16rm : X86::MOV16mr;
3557   case 4:
3558     if (X86::GR32RegClass.hasSubClassEq(RC))
3559       return load ? X86::MOV32rm : X86::MOV32mr;
3560     if (X86::FR32XRegClass.hasSubClassEq(RC))
3561       return load ?
3562         (HasAVX512 ? X86::VMOVSSZrm_alt :
3563          HasAVX    ? X86::VMOVSSrm_alt :
3564                      X86::MOVSSrm_alt) :
3565         (HasAVX512 ? X86::VMOVSSZmr :
3566          HasAVX    ? X86::VMOVSSmr :
3567                      X86::MOVSSmr);
3568     if (X86::RFP32RegClass.hasSubClassEq(RC))
3569       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3570     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3571       assert(STI.hasBWI() && "KMOVD requires BWI");
3572       return load ? X86::KMOVDkm : X86::KMOVDmk;
3573     }
3574     // All of these mask pair classes have the same spill size, the same kind
3575     // of kmov instructions can be used with all of them.
3576     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3577         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3578         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3579         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3580         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3581       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3582     llvm_unreachable("Unknown 4-byte regclass");
3583   case 8:
3584     if (X86::GR64RegClass.hasSubClassEq(RC))
3585       return load ? X86::MOV64rm : X86::MOV64mr;
3586     if (X86::FR64XRegClass.hasSubClassEq(RC))
3587       return load ?
3588         (HasAVX512 ? X86::VMOVSDZrm_alt :
3589          HasAVX    ? X86::VMOVSDrm_alt :
3590                      X86::MOVSDrm_alt) :
3591         (HasAVX512 ? X86::VMOVSDZmr :
3592          HasAVX    ? X86::VMOVSDmr :
3593                      X86::MOVSDmr);
3594     if (X86::VR64RegClass.hasSubClassEq(RC))
3595       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3596     if (X86::RFP64RegClass.hasSubClassEq(RC))
3597       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3598     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3599       assert(STI.hasBWI() && "KMOVQ requires BWI");
3600       return load ? X86::KMOVQkm : X86::KMOVQmk;
3601     }
3602     llvm_unreachable("Unknown 8-byte regclass");
3603   case 10:
3604     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3605     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3606   case 16: {
3607     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3608       // If stack is realigned we can use aligned stores.
3609       if (IsStackAligned)
3610         return load ?
3611           (HasVLX    ? X86::VMOVAPSZ128rm :
3612            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3613            HasAVX    ? X86::VMOVAPSrm :
3614                        X86::MOVAPSrm):
3615           (HasVLX    ? X86::VMOVAPSZ128mr :
3616            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3617            HasAVX    ? X86::VMOVAPSmr :
3618                        X86::MOVAPSmr);
3619       else
3620         return load ?
3621           (HasVLX    ? X86::VMOVUPSZ128rm :
3622            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3623            HasAVX    ? X86::VMOVUPSrm :
3624                        X86::MOVUPSrm):
3625           (HasVLX    ? X86::VMOVUPSZ128mr :
3626            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3627            HasAVX    ? X86::VMOVUPSmr :
3628                        X86::MOVUPSmr);
3629     }
3630     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3631       if (STI.is64Bit())
3632         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3633       else
3634         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3635     }
3636     llvm_unreachable("Unknown 16-byte regclass");
3637   }
3638   case 32:
3639     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3640     // If stack is realigned we can use aligned stores.
3641     if (IsStackAligned)
3642       return load ?
3643         (HasVLX    ? X86::VMOVAPSZ256rm :
3644          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3645                      X86::VMOVAPSYrm) :
3646         (HasVLX    ? X86::VMOVAPSZ256mr :
3647          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3648                      X86::VMOVAPSYmr);
3649     else
3650       return load ?
3651         (HasVLX    ? X86::VMOVUPSZ256rm :
3652          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3653                      X86::VMOVUPSYrm) :
3654         (HasVLX    ? X86::VMOVUPSZ256mr :
3655          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3656                      X86::VMOVUPSYmr);
3657   case 64:
3658     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3659     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3660     if (IsStackAligned)
3661       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3662     else
3663       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3664   }
3665 }
3666 
3667 Optional<ExtAddrMode>
3668 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3669                                       const TargetRegisterInfo *TRI) const {
3670   const MCInstrDesc &Desc = MemI.getDesc();
3671   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3672   if (MemRefBegin < 0)
3673     return None;
3674 
3675   MemRefBegin += X86II::getOperandBias(Desc);
3676 
3677   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3678   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3679     return None;
3680 
3681   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3682   // Displacement can be symbolic
3683   if (!DispMO.isImm())
3684     return None;
3685 
3686   ExtAddrMode AM;
3687   AM.BaseReg = BaseOp.getReg();
3688   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3689   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3690   AM.Displacement = DispMO.getImm();
3691   return AM;
3692 }
3693 
3694 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3695                                            const Register Reg,
3696                                            int64_t &ImmVal) const {
3697   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3698     return false;
3699   // Mov Src can be a global address.
3700   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3701     return false;
3702   ImmVal = MI.getOperand(1).getImm();
3703   return true;
3704 }
3705 
3706 bool X86InstrInfo::preservesZeroValueInReg(
3707     const MachineInstr *MI, const Register NullValueReg,
3708     const TargetRegisterInfo *TRI) const {
3709   if (!MI->modifiesRegister(NullValueReg, TRI))
3710     return true;
3711   switch (MI->getOpcode()) {
3712   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3713   // X.
3714   case X86::SHR64ri:
3715   case X86::SHR32ri:
3716   case X86::SHL64ri:
3717   case X86::SHL32ri:
3718     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3719            "expected for shift opcode!");
3720     return MI->getOperand(0).getReg() == NullValueReg &&
3721            MI->getOperand(1).getReg() == NullValueReg;
3722   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3723   // null value.
3724   case X86::MOV32rr:
3725     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3726       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3727     });
3728   default:
3729     return false;
3730   }
3731   llvm_unreachable("Should be handled above!");
3732 }
3733 
3734 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3735     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3736     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3737     const TargetRegisterInfo *TRI) const {
3738   const MCInstrDesc &Desc = MemOp.getDesc();
3739   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3740   if (MemRefBegin < 0)
3741     return false;
3742 
3743   MemRefBegin += X86II::getOperandBias(Desc);
3744 
3745   const MachineOperand *BaseOp =
3746       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3747   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3748     return false;
3749 
3750   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3751     return false;
3752 
3753   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3754       X86::NoRegister)
3755     return false;
3756 
3757   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3758 
3759   // Displacement can be symbolic
3760   if (!DispMO.isImm())
3761     return false;
3762 
3763   Offset = DispMO.getImm();
3764 
3765   if (!BaseOp->isReg())
3766     return false;
3767 
3768   OffsetIsScalable = false;
3769   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3770   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3771   // there is no use of `Width` for X86 back-end at the moment.
3772   Width =
3773       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3774   BaseOps.push_back(BaseOp);
3775   return true;
3776 }
3777 
3778 static unsigned getStoreRegOpcode(Register SrcReg,
3779                                   const TargetRegisterClass *RC,
3780                                   bool IsStackAligned,
3781                                   const X86Subtarget &STI) {
3782   return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3783 }
3784 
3785 static unsigned getLoadRegOpcode(Register DestReg,
3786                                  const TargetRegisterClass *RC,
3787                                  bool IsStackAligned, const X86Subtarget &STI) {
3788   return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3789 }
3790 
3791 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3792                                        MachineBasicBlock::iterator MI,
3793                                        Register SrcReg, bool isKill, int FrameIdx,
3794                                        const TargetRegisterClass *RC,
3795                                        const TargetRegisterInfo *TRI) const {
3796   const MachineFunction &MF = *MBB.getParent();
3797   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3798          "Stack slot too small for store");
3799   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3800   bool isAligned =
3801       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3802       RI.canRealignStack(MF);
3803   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3804   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3805     .addReg(SrcReg, getKillRegState(isKill));
3806 }
3807 
3808 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3809                                         MachineBasicBlock::iterator MI,
3810                                         Register DestReg, int FrameIdx,
3811                                         const TargetRegisterClass *RC,
3812                                         const TargetRegisterInfo *TRI) const {
3813   const MachineFunction &MF = *MBB.getParent();
3814   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3815   bool isAligned =
3816       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3817       RI.canRealignStack(MF);
3818   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3819   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3820 }
3821 
3822 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3823                                   Register &SrcReg2, int &CmpMask,
3824                                   int &CmpValue) const {
3825   switch (MI.getOpcode()) {
3826   default: break;
3827   case X86::CMP64ri32:
3828   case X86::CMP64ri8:
3829   case X86::CMP32ri:
3830   case X86::CMP32ri8:
3831   case X86::CMP16ri:
3832   case X86::CMP16ri8:
3833   case X86::CMP8ri:
3834     SrcReg = MI.getOperand(0).getReg();
3835     SrcReg2 = 0;
3836     if (MI.getOperand(1).isImm()) {
3837       CmpMask = ~0;
3838       CmpValue = MI.getOperand(1).getImm();
3839     } else {
3840       CmpMask = CmpValue = 0;
3841     }
3842     return true;
3843   // A SUB can be used to perform comparison.
3844   case X86::SUB64rm:
3845   case X86::SUB32rm:
3846   case X86::SUB16rm:
3847   case X86::SUB8rm:
3848     SrcReg = MI.getOperand(1).getReg();
3849     SrcReg2 = 0;
3850     CmpMask = 0;
3851     CmpValue = 0;
3852     return true;
3853   case X86::SUB64rr:
3854   case X86::SUB32rr:
3855   case X86::SUB16rr:
3856   case X86::SUB8rr:
3857     SrcReg = MI.getOperand(1).getReg();
3858     SrcReg2 = MI.getOperand(2).getReg();
3859     CmpMask = 0;
3860     CmpValue = 0;
3861     return true;
3862   case X86::SUB64ri32:
3863   case X86::SUB64ri8:
3864   case X86::SUB32ri:
3865   case X86::SUB32ri8:
3866   case X86::SUB16ri:
3867   case X86::SUB16ri8:
3868   case X86::SUB8ri:
3869     SrcReg = MI.getOperand(1).getReg();
3870     SrcReg2 = 0;
3871     if (MI.getOperand(2).isImm()) {
3872       CmpMask = ~0;
3873       CmpValue = MI.getOperand(2).getImm();
3874     } else {
3875       CmpMask = CmpValue = 0;
3876     }
3877     return true;
3878   case X86::CMP64rr:
3879   case X86::CMP32rr:
3880   case X86::CMP16rr:
3881   case X86::CMP8rr:
3882     SrcReg = MI.getOperand(0).getReg();
3883     SrcReg2 = MI.getOperand(1).getReg();
3884     CmpMask = 0;
3885     CmpValue = 0;
3886     return true;
3887   case X86::TEST8rr:
3888   case X86::TEST16rr:
3889   case X86::TEST32rr:
3890   case X86::TEST64rr:
3891     SrcReg = MI.getOperand(0).getReg();
3892     if (MI.getOperand(1).getReg() != SrcReg)
3893       return false;
3894     // Compare against zero.
3895     SrcReg2 = 0;
3896     CmpMask = ~0;
3897     CmpValue = 0;
3898     return true;
3899   }
3900   return false;
3901 }
3902 
3903 /// Check whether the first instruction, whose only
3904 /// purpose is to update flags, can be made redundant.
3905 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3906 /// This function can be extended later on.
3907 /// SrcReg, SrcRegs: register operands for FlagI.
3908 /// ImmValue: immediate for FlagI if it takes an immediate.
3909 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3910                                         Register SrcReg, Register SrcReg2,
3911                                         int ImmMask, int ImmValue,
3912                                         const MachineInstr &OI) {
3913   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3914        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3915        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3916        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3917       ((OI.getOperand(1).getReg() == SrcReg &&
3918         OI.getOperand(2).getReg() == SrcReg2) ||
3919        (OI.getOperand(1).getReg() == SrcReg2 &&
3920         OI.getOperand(2).getReg() == SrcReg)))
3921     return true;
3922 
3923   if (ImmMask != 0 &&
3924       ((FlagI.getOpcode() == X86::CMP64ri32 &&
3925         OI.getOpcode() == X86::SUB64ri32) ||
3926        (FlagI.getOpcode() == X86::CMP64ri8 &&
3927         OI.getOpcode() == X86::SUB64ri8) ||
3928        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3929        (FlagI.getOpcode() == X86::CMP32ri8 &&
3930         OI.getOpcode() == X86::SUB32ri8) ||
3931        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3932        (FlagI.getOpcode() == X86::CMP16ri8 &&
3933         OI.getOpcode() == X86::SUB16ri8) ||
3934        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3935       OI.getOperand(1).getReg() == SrcReg &&
3936       OI.getOperand(2).getImm() == ImmValue)
3937     return true;
3938   return false;
3939 }
3940 
3941 /// Check whether the definition can be converted
3942 /// to remove a comparison against zero.
3943 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3944   NoSignFlag = false;
3945 
3946   switch (MI.getOpcode()) {
3947   default: return false;
3948 
3949   // The shift instructions only modify ZF if their shift count is non-zero.
3950   // N.B.: The processor truncates the shift count depending on the encoding.
3951   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3952   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3953      return getTruncatedShiftCount(MI, 2) != 0;
3954 
3955   // Some left shift instructions can be turned into LEA instructions but only
3956   // if their flags aren't used. Avoid transforming such instructions.
3957   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3958     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3959     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3960     return ShAmt != 0;
3961   }
3962 
3963   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3964   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3965      return getTruncatedShiftCount(MI, 3) != 0;
3966 
3967   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3968   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3969   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3970   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3971   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3972   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3973   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3974   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3975   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3976   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3977   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3978   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3979   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3980   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3981   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3982   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3983   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3984   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3985   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3986   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3987   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3988   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3989   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3990   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3991   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3992   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3993   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3994   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3995   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3996   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3997   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3998   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
3999   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4000   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
4001   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
4002   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
4003   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
4004   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4005   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4006   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4007   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4008   case X86::ANDN32rr:  case X86::ANDN32rm:
4009   case X86::ANDN64rr:  case X86::ANDN64rm:
4010   case X86::BLSI32rr:  case X86::BLSI32rm:
4011   case X86::BLSI64rr:  case X86::BLSI64rm:
4012   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4013   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4014   case X86::BLSR32rr:  case X86::BLSR32rm:
4015   case X86::BLSR64rr:  case X86::BLSR64rm:
4016   case X86::BZHI32rr:  case X86::BZHI32rm:
4017   case X86::BZHI64rr:  case X86::BZHI64rm:
4018   case X86::LZCNT16rr: case X86::LZCNT16rm:
4019   case X86::LZCNT32rr: case X86::LZCNT32rm:
4020   case X86::LZCNT64rr: case X86::LZCNT64rm:
4021   case X86::POPCNT16rr:case X86::POPCNT16rm:
4022   case X86::POPCNT32rr:case X86::POPCNT32rm:
4023   case X86::POPCNT64rr:case X86::POPCNT64rm:
4024   case X86::TZCNT16rr: case X86::TZCNT16rm:
4025   case X86::TZCNT32rr: case X86::TZCNT32rm:
4026   case X86::TZCNT64rr: case X86::TZCNT64rm:
4027   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4028   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4029   case X86::BLCI32rr:    case X86::BLCI32rm:
4030   case X86::BLCI64rr:    case X86::BLCI64rm:
4031   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4032   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4033   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4034   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4035   case X86::BLCS32rr:    case X86::BLCS32rm:
4036   case X86::BLCS64rr:    case X86::BLCS64rm:
4037   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4038   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4039   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4040   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4041   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4042   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4043   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4044   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4045     return true;
4046   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4047   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4048   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4049   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4050     // BEXTR doesn't update the sign flag so we can't use it.
4051     NoSignFlag = true;
4052     return true;
4053   }
4054 }
4055 
4056 /// Check whether the use can be converted to remove a comparison against zero.
4057 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4058   switch (MI.getOpcode()) {
4059   default: return X86::COND_INVALID;
4060   case X86::NEG8r:
4061   case X86::NEG16r:
4062   case X86::NEG32r:
4063   case X86::NEG64r:
4064     return X86::COND_AE;
4065   case X86::LZCNT16rr:
4066   case X86::LZCNT32rr:
4067   case X86::LZCNT64rr:
4068     return X86::COND_B;
4069   case X86::POPCNT16rr:
4070   case X86::POPCNT32rr:
4071   case X86::POPCNT64rr:
4072     return X86::COND_E;
4073   case X86::TZCNT16rr:
4074   case X86::TZCNT32rr:
4075   case X86::TZCNT64rr:
4076     return X86::COND_B;
4077   case X86::BSF16rr:
4078   case X86::BSF32rr:
4079   case X86::BSF64rr:
4080   case X86::BSR16rr:
4081   case X86::BSR32rr:
4082   case X86::BSR64rr:
4083     return X86::COND_E;
4084   case X86::BLSI32rr:
4085   case X86::BLSI64rr:
4086     return X86::COND_AE;
4087   case X86::BLSR32rr:
4088   case X86::BLSR64rr:
4089   case X86::BLSMSK32rr:
4090   case X86::BLSMSK64rr:
4091     return X86::COND_B;
4092   // TODO: TBM instructions.
4093   }
4094 }
4095 
4096 /// Check if there exists an earlier instruction that
4097 /// operates on the same source operands and sets flags in the same way as
4098 /// Compare; remove Compare if possible.
4099 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4100                                         Register SrcReg2, int CmpMask,
4101                                         int CmpValue,
4102                                         const MachineRegisterInfo *MRI) const {
4103   // Check whether we can replace SUB with CMP.
4104   switch (CmpInstr.getOpcode()) {
4105   default: break;
4106   case X86::SUB64ri32:
4107   case X86::SUB64ri8:
4108   case X86::SUB32ri:
4109   case X86::SUB32ri8:
4110   case X86::SUB16ri:
4111   case X86::SUB16ri8:
4112   case X86::SUB8ri:
4113   case X86::SUB64rm:
4114   case X86::SUB32rm:
4115   case X86::SUB16rm:
4116   case X86::SUB8rm:
4117   case X86::SUB64rr:
4118   case X86::SUB32rr:
4119   case X86::SUB16rr:
4120   case X86::SUB8rr: {
4121     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4122       return false;
4123     // There is no use of the destination register, we can replace SUB with CMP.
4124     unsigned NewOpcode = 0;
4125     switch (CmpInstr.getOpcode()) {
4126     default: llvm_unreachable("Unreachable!");
4127     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4128     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4129     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4130     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4131     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4132     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4133     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4134     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4135     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4136     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4137     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4138     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4139     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4140     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4141     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4142     }
4143     CmpInstr.setDesc(get(NewOpcode));
4144     CmpInstr.RemoveOperand(0);
4145     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4146     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4147         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4148       return false;
4149   }
4150   }
4151 
4152   // Get the unique definition of SrcReg.
4153   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4154   if (!MI) return false;
4155 
4156   // CmpInstr is the first instruction of the BB.
4157   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4158 
4159   // If we are comparing against zero, check whether we can use MI to update
4160   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4161   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4162   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4163     return false;
4164 
4165   // If we have a use of the source register between the def and our compare
4166   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4167   // right way.
4168   bool ShouldUpdateCC = false;
4169   bool NoSignFlag = false;
4170   X86::CondCode NewCC = X86::COND_INVALID;
4171   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
4172     // Scan forward from the use until we hit the use we're looking for or the
4173     // compare instruction.
4174     for (MachineBasicBlock::iterator J = MI;; ++J) {
4175       // Do we have a convertible instruction?
4176       NewCC = isUseDefConvertible(*J);
4177       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4178           J->getOperand(1).getReg() == SrcReg) {
4179         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4180         ShouldUpdateCC = true; // Update CC later on.
4181         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4182         // with the new def.
4183         Def = J;
4184         MI = &*Def;
4185         break;
4186       }
4187 
4188       if (J == I)
4189         return false;
4190     }
4191   }
4192 
4193   // We are searching for an earlier instruction that can make CmpInstr
4194   // redundant and that instruction will be saved in Sub.
4195   MachineInstr *Sub = nullptr;
4196   const TargetRegisterInfo *TRI = &getRegisterInfo();
4197 
4198   // We iterate backward, starting from the instruction before CmpInstr and
4199   // stop when reaching the definition of a source register or done with the BB.
4200   // RI points to the instruction before CmpInstr.
4201   // If the definition is in this basic block, RE points to the definition;
4202   // otherwise, RE is the rend of the basic block.
4203   MachineBasicBlock::reverse_iterator
4204       RI = ++I.getReverse(),
4205       RE = CmpInstr.getParent() == MI->getParent()
4206                ? Def.getReverse() /* points to MI */
4207                : CmpInstr.getParent()->rend();
4208   MachineInstr *Movr0Inst = nullptr;
4209   for (; RI != RE; ++RI) {
4210     MachineInstr &Instr = *RI;
4211     // Check whether CmpInstr can be made redundant by the current instruction.
4212     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4213                                            CmpValue, Instr)) {
4214       Sub = &Instr;
4215       break;
4216     }
4217 
4218     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4219         Instr.readsRegister(X86::EFLAGS, TRI)) {
4220       // This instruction modifies or uses EFLAGS.
4221 
4222       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4223       // They are safe to move up, if the definition to EFLAGS is dead and
4224       // earlier instructions do not read or write EFLAGS.
4225       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4226           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4227         Movr0Inst = &Instr;
4228         continue;
4229       }
4230 
4231       // We can't remove CmpInstr.
4232       return false;
4233     }
4234   }
4235 
4236   // Return false if no candidates exist.
4237   if (!IsCmpZero && !Sub)
4238     return false;
4239 
4240   bool IsSwapped =
4241       (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4242        Sub->getOperand(2).getReg() == SrcReg);
4243 
4244   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4245   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4246   // If we are done with the basic block, we need to check whether EFLAGS is
4247   // live-out.
4248   bool IsSafe = false;
4249   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4250   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4251   for (++I; I != E; ++I) {
4252     const MachineInstr &Instr = *I;
4253     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4254     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4255     // We should check the usage if this instruction uses and updates EFLAGS.
4256     if (!UseEFLAGS && ModifyEFLAGS) {
4257       // It is safe to remove CmpInstr if EFLAGS is updated again.
4258       IsSafe = true;
4259       break;
4260     }
4261     if (!UseEFLAGS && !ModifyEFLAGS)
4262       continue;
4263 
4264     // EFLAGS is used by this instruction.
4265     X86::CondCode OldCC = X86::COND_INVALID;
4266     if (IsCmpZero || IsSwapped) {
4267       // We decode the condition code from opcode.
4268       if (Instr.isBranch())
4269         OldCC = X86::getCondFromBranch(Instr);
4270       else {
4271         OldCC = X86::getCondFromSETCC(Instr);
4272         if (OldCC == X86::COND_INVALID)
4273           OldCC = X86::getCondFromCMov(Instr);
4274       }
4275       if (OldCC == X86::COND_INVALID) return false;
4276     }
4277     X86::CondCode ReplacementCC = X86::COND_INVALID;
4278     if (IsCmpZero) {
4279       switch (OldCC) {
4280       default: break;
4281       case X86::COND_A: case X86::COND_AE:
4282       case X86::COND_B: case X86::COND_BE:
4283       case X86::COND_G: case X86::COND_GE:
4284       case X86::COND_L: case X86::COND_LE:
4285       case X86::COND_O: case X86::COND_NO:
4286         // CF and OF are used, we can't perform this optimization.
4287         return false;
4288       case X86::COND_S: case X86::COND_NS:
4289         // If SF is used, but the instruction doesn't update the SF, then we
4290         // can't do the optimization.
4291         if (NoSignFlag)
4292           return false;
4293         break;
4294       }
4295 
4296       // If we're updating the condition code check if we have to reverse the
4297       // condition.
4298       if (ShouldUpdateCC)
4299         switch (OldCC) {
4300         default:
4301           return false;
4302         case X86::COND_E:
4303           ReplacementCC = NewCC;
4304           break;
4305         case X86::COND_NE:
4306           ReplacementCC = GetOppositeBranchCondition(NewCC);
4307           break;
4308         }
4309     } else if (IsSwapped) {
4310       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4311       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4312       // We swap the condition code and synthesize the new opcode.
4313       ReplacementCC = getSwappedCondition(OldCC);
4314       if (ReplacementCC == X86::COND_INVALID) return false;
4315     }
4316 
4317     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4318       // Push the MachineInstr to OpsToUpdate.
4319       // If it is safe to remove CmpInstr, the condition code of these
4320       // instructions will be modified.
4321       OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4322     }
4323     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4324       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4325       IsSafe = true;
4326       break;
4327     }
4328   }
4329 
4330   // If EFLAGS is not killed nor re-defined, we should check whether it is
4331   // live-out. If it is live-out, do not optimize.
4332   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4333     MachineBasicBlock *MBB = CmpInstr.getParent();
4334     for (MachineBasicBlock *Successor : MBB->successors())
4335       if (Successor->isLiveIn(X86::EFLAGS))
4336         return false;
4337   }
4338 
4339   // The instruction to be updated is either Sub or MI.
4340   Sub = IsCmpZero ? MI : Sub;
4341   // Move Movr0Inst to the appropriate place before Sub.
4342   if (Movr0Inst) {
4343     // Look backwards until we find a def that doesn't use the current EFLAGS.
4344     Def = Sub;
4345     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4346                                         InsertE = Sub->getParent()->rend();
4347     for (; InsertI != InsertE; ++InsertI) {
4348       MachineInstr *Instr = &*InsertI;
4349       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4350           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4351         Sub->getParent()->remove(Movr0Inst);
4352         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4353                                    Movr0Inst);
4354         break;
4355       }
4356     }
4357     if (InsertI == InsertE)
4358       return false;
4359   }
4360 
4361   // Make sure Sub instruction defines EFLAGS and mark the def live.
4362   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4363   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4364   FlagDef->setIsDead(false);
4365 
4366   CmpInstr.eraseFromParent();
4367 
4368   // Modify the condition code of instructions in OpsToUpdate.
4369   for (auto &Op : OpsToUpdate) {
4370     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4371         .setImm(Op.second);
4372   }
4373   return true;
4374 }
4375 
4376 /// Try to remove the load by folding it to a register
4377 /// operand at the use. We fold the load instructions if load defines a virtual
4378 /// register, the virtual register is used once in the same BB, and the
4379 /// instructions in-between do not load or store, and have no side effects.
4380 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4381                                               const MachineRegisterInfo *MRI,
4382                                               Register &FoldAsLoadDefReg,
4383                                               MachineInstr *&DefMI) const {
4384   // Check whether we can move DefMI here.
4385   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4386   assert(DefMI);
4387   bool SawStore = false;
4388   if (!DefMI->isSafeToMove(nullptr, SawStore))
4389     return nullptr;
4390 
4391   // Collect information about virtual register operands of MI.
4392   SmallVector<unsigned, 1> SrcOperandIds;
4393   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4394     MachineOperand &MO = MI.getOperand(i);
4395     if (!MO.isReg())
4396       continue;
4397     Register Reg = MO.getReg();
4398     if (Reg != FoldAsLoadDefReg)
4399       continue;
4400     // Do not fold if we have a subreg use or a def.
4401     if (MO.getSubReg() || MO.isDef())
4402       return nullptr;
4403     SrcOperandIds.push_back(i);
4404   }
4405   if (SrcOperandIds.empty())
4406     return nullptr;
4407 
4408   // Check whether we can fold the def into SrcOperandId.
4409   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4410     FoldAsLoadDefReg = 0;
4411     return FoldMI;
4412   }
4413 
4414   return nullptr;
4415 }
4416 
4417 /// Expand a single-def pseudo instruction to a two-addr
4418 /// instruction with two undef reads of the register being defined.
4419 /// This is used for mapping:
4420 ///   %xmm4 = V_SET0
4421 /// to:
4422 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4423 ///
4424 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4425                              const MCInstrDesc &Desc) {
4426   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4427   Register Reg = MIB.getReg(0);
4428   MIB->setDesc(Desc);
4429 
4430   // MachineInstr::addOperand() will insert explicit operands before any
4431   // implicit operands.
4432   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4433   // But we don't trust that.
4434   assert(MIB.getReg(1) == Reg &&
4435          MIB.getReg(2) == Reg && "Misplaced operand");
4436   return true;
4437 }
4438 
4439 /// Expand a single-def pseudo instruction to a two-addr
4440 /// instruction with two %k0 reads.
4441 /// This is used for mapping:
4442 ///   %k4 = K_SET1
4443 /// to:
4444 ///   %k4 = KXNORrr %k0, %k0
4445 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4446                             Register Reg) {
4447   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4448   MIB->setDesc(Desc);
4449   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4450   return true;
4451 }
4452 
4453 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4454                           bool MinusOne) {
4455   MachineBasicBlock &MBB = *MIB->getParent();
4456   DebugLoc DL = MIB->getDebugLoc();
4457   Register Reg = MIB.getReg(0);
4458 
4459   // Insert the XOR.
4460   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4461       .addReg(Reg, RegState::Undef)
4462       .addReg(Reg, RegState::Undef);
4463 
4464   // Turn the pseudo into an INC or DEC.
4465   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4466   MIB.addReg(Reg);
4467 
4468   return true;
4469 }
4470 
4471 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4472                                const TargetInstrInfo &TII,
4473                                const X86Subtarget &Subtarget) {
4474   MachineBasicBlock &MBB = *MIB->getParent();
4475   DebugLoc DL = MIB->getDebugLoc();
4476   int64_t Imm = MIB->getOperand(1).getImm();
4477   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4478   MachineBasicBlock::iterator I = MIB.getInstr();
4479 
4480   int StackAdjustment;
4481 
4482   if (Subtarget.is64Bit()) {
4483     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4484            MIB->getOpcode() == X86::MOV32ImmSExti8);
4485 
4486     // Can't use push/pop lowering if the function might write to the red zone.
4487     X86MachineFunctionInfo *X86FI =
4488         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4489     if (X86FI->getUsesRedZone()) {
4490       MIB->setDesc(TII.get(MIB->getOpcode() ==
4491                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4492       return true;
4493     }
4494 
4495     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4496     // widen the register if necessary.
4497     StackAdjustment = 8;
4498     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4499     MIB->setDesc(TII.get(X86::POP64r));
4500     MIB->getOperand(0)
4501         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4502   } else {
4503     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4504     StackAdjustment = 4;
4505     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4506     MIB->setDesc(TII.get(X86::POP32r));
4507   }
4508   MIB->RemoveOperand(1);
4509   MIB->addImplicitDefUseOperands(*MBB.getParent());
4510 
4511   // Build CFI if necessary.
4512   MachineFunction &MF = *MBB.getParent();
4513   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4514   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4515   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4516   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4517   if (EmitCFI) {
4518     TFL->BuildCFI(MBB, I, DL,
4519         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4520     TFL->BuildCFI(MBB, std::next(I), DL,
4521         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4522   }
4523 
4524   return true;
4525 }
4526 
4527 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4528 // code sequence is needed for other targets.
4529 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4530                                  const TargetInstrInfo &TII) {
4531   MachineBasicBlock &MBB = *MIB->getParent();
4532   DebugLoc DL = MIB->getDebugLoc();
4533   Register Reg = MIB.getReg(0);
4534   const GlobalValue *GV =
4535       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4536   auto Flags = MachineMemOperand::MOLoad |
4537                MachineMemOperand::MODereferenceable |
4538                MachineMemOperand::MOInvariant;
4539   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4540       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4541   MachineBasicBlock::iterator I = MIB.getInstr();
4542 
4543   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4544       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4545       .addMemOperand(MMO);
4546   MIB->setDebugLoc(DL);
4547   MIB->setDesc(TII.get(X86::MOV64rm));
4548   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4549 }
4550 
4551 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4552   MachineBasicBlock &MBB = *MIB->getParent();
4553   MachineFunction &MF = *MBB.getParent();
4554   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4555   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4556   unsigned XorOp =
4557       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4558   MIB->setDesc(TII.get(XorOp));
4559   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4560   return true;
4561 }
4562 
4563 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4564 // but not VLX. If it uses an extended register we need to use an instruction
4565 // that loads the lower 128/256-bit, but is available with only AVX512F.
4566 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4567                             const TargetRegisterInfo *TRI,
4568                             const MCInstrDesc &LoadDesc,
4569                             const MCInstrDesc &BroadcastDesc,
4570                             unsigned SubIdx) {
4571   Register DestReg = MIB.getReg(0);
4572   // Check if DestReg is XMM16-31 or YMM16-31.
4573   if (TRI->getEncodingValue(DestReg) < 16) {
4574     // We can use a normal VEX encoded load.
4575     MIB->setDesc(LoadDesc);
4576   } else {
4577     // Use a 128/256-bit VBROADCAST instruction.
4578     MIB->setDesc(BroadcastDesc);
4579     // Change the destination to a 512-bit register.
4580     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4581     MIB->getOperand(0).setReg(DestReg);
4582   }
4583   return true;
4584 }
4585 
4586 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4587 // but not VLX. If it uses an extended register we need to use an instruction
4588 // that stores the lower 128/256-bit, but is available with only AVX512F.
4589 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4590                              const TargetRegisterInfo *TRI,
4591                              const MCInstrDesc &StoreDesc,
4592                              const MCInstrDesc &ExtractDesc,
4593                              unsigned SubIdx) {
4594   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4595   // Check if DestReg is XMM16-31 or YMM16-31.
4596   if (TRI->getEncodingValue(SrcReg) < 16) {
4597     // We can use a normal VEX encoded store.
4598     MIB->setDesc(StoreDesc);
4599   } else {
4600     // Use a VEXTRACTF instruction.
4601     MIB->setDesc(ExtractDesc);
4602     // Change the destination to a 512-bit register.
4603     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4604     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4605     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4606   }
4607 
4608   return true;
4609 }
4610 
4611 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4612   MIB->setDesc(Desc);
4613   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4614   // Temporarily remove the immediate so we can add another source register.
4615   MIB->RemoveOperand(2);
4616   // Add the register. Don't copy the kill flag if there is one.
4617   MIB.addReg(MIB.getReg(1),
4618              getUndefRegState(MIB->getOperand(1).isUndef()));
4619   // Add back the immediate.
4620   MIB.addImm(ShiftAmt);
4621   return true;
4622 }
4623 
4624 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4625   bool HasAVX = Subtarget.hasAVX();
4626   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4627   switch (MI.getOpcode()) {
4628   case X86::MOV32r0:
4629     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4630   case X86::MOV32r1:
4631     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4632   case X86::MOV32r_1:
4633     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4634   case X86::MOV32ImmSExti8:
4635   case X86::MOV64ImmSExti8:
4636     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4637   case X86::SETB_C32r:
4638     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4639   case X86::SETB_C64r:
4640     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4641   case X86::MMX_SET0:
4642     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4643   case X86::V_SET0:
4644   case X86::FsFLD0SS:
4645   case X86::FsFLD0SD:
4646   case X86::FsFLD0F128:
4647     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4648   case X86::AVX_SET0: {
4649     assert(HasAVX && "AVX not supported");
4650     const TargetRegisterInfo *TRI = &getRegisterInfo();
4651     Register SrcReg = MIB.getReg(0);
4652     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4653     MIB->getOperand(0).setReg(XReg);
4654     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4655     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4656     return true;
4657   }
4658   case X86::AVX512_128_SET0:
4659   case X86::AVX512_FsFLD0SS:
4660   case X86::AVX512_FsFLD0SD:
4661   case X86::AVX512_FsFLD0F128: {
4662     bool HasVLX = Subtarget.hasVLX();
4663     Register SrcReg = MIB.getReg(0);
4664     const TargetRegisterInfo *TRI = &getRegisterInfo();
4665     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4666       return Expand2AddrUndef(MIB,
4667                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4668     // Extended register without VLX. Use a larger XOR.
4669     SrcReg =
4670         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4671     MIB->getOperand(0).setReg(SrcReg);
4672     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4673   }
4674   case X86::AVX512_256_SET0:
4675   case X86::AVX512_512_SET0: {
4676     bool HasVLX = Subtarget.hasVLX();
4677     Register SrcReg = MIB.getReg(0);
4678     const TargetRegisterInfo *TRI = &getRegisterInfo();
4679     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4680       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4681       MIB->getOperand(0).setReg(XReg);
4682       Expand2AddrUndef(MIB,
4683                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4684       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4685       return true;
4686     }
4687     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4688       // No VLX so we must reference a zmm.
4689       unsigned ZReg =
4690         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4691       MIB->getOperand(0).setReg(ZReg);
4692     }
4693     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4694   }
4695   case X86::V_SETALLONES:
4696     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4697   case X86::AVX2_SETALLONES:
4698     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4699   case X86::AVX1_SETALLONES: {
4700     Register Reg = MIB.getReg(0);
4701     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4702     MIB->setDesc(get(X86::VCMPPSYrri));
4703     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4704     return true;
4705   }
4706   case X86::AVX512_512_SETALLONES: {
4707     Register Reg = MIB.getReg(0);
4708     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4709     // VPTERNLOGD needs 3 register inputs and an immediate.
4710     // 0xff will return 1s for any input.
4711     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4712        .addReg(Reg, RegState::Undef).addImm(0xff);
4713     return true;
4714   }
4715   case X86::AVX512_512_SEXT_MASK_32:
4716   case X86::AVX512_512_SEXT_MASK_64: {
4717     Register Reg = MIB.getReg(0);
4718     Register MaskReg = MIB.getReg(1);
4719     unsigned MaskState = getRegState(MIB->getOperand(1));
4720     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4721                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4722     MI.RemoveOperand(1);
4723     MIB->setDesc(get(Opc));
4724     // VPTERNLOG needs 3 register inputs and an immediate.
4725     // 0xff will return 1s for any input.
4726     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4727        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4728     return true;
4729   }
4730   case X86::VMOVAPSZ128rm_NOVLX:
4731     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4732                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4733   case X86::VMOVUPSZ128rm_NOVLX:
4734     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4735                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4736   case X86::VMOVAPSZ256rm_NOVLX:
4737     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4738                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4739   case X86::VMOVUPSZ256rm_NOVLX:
4740     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4741                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4742   case X86::VMOVAPSZ128mr_NOVLX:
4743     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4744                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4745   case X86::VMOVUPSZ128mr_NOVLX:
4746     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4747                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4748   case X86::VMOVAPSZ256mr_NOVLX:
4749     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4750                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4751   case X86::VMOVUPSZ256mr_NOVLX:
4752     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4753                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4754   case X86::MOV32ri64: {
4755     Register Reg = MIB.getReg(0);
4756     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4757     MI.setDesc(get(X86::MOV32ri));
4758     MIB->getOperand(0).setReg(Reg32);
4759     MIB.addReg(Reg, RegState::ImplicitDefine);
4760     return true;
4761   }
4762 
4763   // KNL does not recognize dependency-breaking idioms for mask registers,
4764   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4765   // Using %k0 as the undef input register is a performance heuristic based
4766   // on the assumption that %k0 is used less frequently than the other mask
4767   // registers, since it is not usable as a write mask.
4768   // FIXME: A more advanced approach would be to choose the best input mask
4769   // register based on context.
4770   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4771   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4772   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4773   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4774   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4775   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4776   case TargetOpcode::LOAD_STACK_GUARD:
4777     expandLoadStackGuard(MIB, *this);
4778     return true;
4779   case X86::XOR64_FP:
4780   case X86::XOR32_FP:
4781     return expandXorFP(MIB, *this);
4782   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4783   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4784   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4785   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4786   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4787   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4788   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4789   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4790   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4791   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4792   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4793   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4794   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4795   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4796   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4797   }
4798   return false;
4799 }
4800 
4801 /// Return true for all instructions that only update
4802 /// the first 32 or 64-bits of the destination register and leave the rest
4803 /// unmodified. This can be used to avoid folding loads if the instructions
4804 /// only update part of the destination register, and the non-updated part is
4805 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4806 /// instructions breaks the partial register dependency and it can improve
4807 /// performance. e.g.:
4808 ///
4809 ///   movss (%rdi), %xmm0
4810 ///   cvtss2sd %xmm0, %xmm0
4811 ///
4812 /// Instead of
4813 ///   cvtss2sd (%rdi), %xmm0
4814 ///
4815 /// FIXME: This should be turned into a TSFlags.
4816 ///
4817 static bool hasPartialRegUpdate(unsigned Opcode,
4818                                 const X86Subtarget &Subtarget,
4819                                 bool ForLoadFold = false) {
4820   switch (Opcode) {
4821   case X86::CVTSI2SSrr:
4822   case X86::CVTSI2SSrm:
4823   case X86::CVTSI642SSrr:
4824   case X86::CVTSI642SSrm:
4825   case X86::CVTSI2SDrr:
4826   case X86::CVTSI2SDrm:
4827   case X86::CVTSI642SDrr:
4828   case X86::CVTSI642SDrm:
4829     // Load folding won't effect the undef register update since the input is
4830     // a GPR.
4831     return !ForLoadFold;
4832   case X86::CVTSD2SSrr:
4833   case X86::CVTSD2SSrm:
4834   case X86::CVTSS2SDrr:
4835   case X86::CVTSS2SDrm:
4836   case X86::MOVHPDrm:
4837   case X86::MOVHPSrm:
4838   case X86::MOVLPDrm:
4839   case X86::MOVLPSrm:
4840   case X86::RCPSSr:
4841   case X86::RCPSSm:
4842   case X86::RCPSSr_Int:
4843   case X86::RCPSSm_Int:
4844   case X86::ROUNDSDr:
4845   case X86::ROUNDSDm:
4846   case X86::ROUNDSSr:
4847   case X86::ROUNDSSm:
4848   case X86::RSQRTSSr:
4849   case X86::RSQRTSSm:
4850   case X86::RSQRTSSr_Int:
4851   case X86::RSQRTSSm_Int:
4852   case X86::SQRTSSr:
4853   case X86::SQRTSSm:
4854   case X86::SQRTSSr_Int:
4855   case X86::SQRTSSm_Int:
4856   case X86::SQRTSDr:
4857   case X86::SQRTSDm:
4858   case X86::SQRTSDr_Int:
4859   case X86::SQRTSDm_Int:
4860     return true;
4861   // GPR
4862   case X86::POPCNT32rm:
4863   case X86::POPCNT32rr:
4864   case X86::POPCNT64rm:
4865   case X86::POPCNT64rr:
4866     return Subtarget.hasPOPCNTFalseDeps();
4867   case X86::LZCNT32rm:
4868   case X86::LZCNT32rr:
4869   case X86::LZCNT64rm:
4870   case X86::LZCNT64rr:
4871   case X86::TZCNT32rm:
4872   case X86::TZCNT32rr:
4873   case X86::TZCNT64rm:
4874   case X86::TZCNT64rr:
4875     return Subtarget.hasLZCNTFalseDeps();
4876   }
4877 
4878   return false;
4879 }
4880 
4881 /// Inform the BreakFalseDeps pass how many idle
4882 /// instructions we would like before a partial register update.
4883 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4884     const MachineInstr &MI, unsigned OpNum,
4885     const TargetRegisterInfo *TRI) const {
4886   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4887     return 0;
4888 
4889   // If MI is marked as reading Reg, the partial register update is wanted.
4890   const MachineOperand &MO = MI.getOperand(0);
4891   Register Reg = MO.getReg();
4892   if (Reg.isVirtual()) {
4893     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4894       return 0;
4895   } else {
4896     if (MI.readsRegister(Reg, TRI))
4897       return 0;
4898   }
4899 
4900   // If any instructions in the clearance range are reading Reg, insert a
4901   // dependency breaking instruction, which is inexpensive and is likely to
4902   // be hidden in other instruction's cycles.
4903   return PartialRegUpdateClearance;
4904 }
4905 
4906 // Return true for any instruction the copies the high bits of the first source
4907 // operand into the unused high bits of the destination operand.
4908 // Also returns true for instructions that have two inputs where one may
4909 // be undef and we want it to use the same register as the other input.
4910 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
4911                               bool ForLoadFold = false) {
4912   // Set the OpNum parameter to the first source operand.
4913   switch (Opcode) {
4914   case X86::MMX_PUNPCKHBWirr:
4915   case X86::MMX_PUNPCKHWDirr:
4916   case X86::MMX_PUNPCKHDQirr:
4917   case X86::MMX_PUNPCKLBWirr:
4918   case X86::MMX_PUNPCKLWDirr:
4919   case X86::MMX_PUNPCKLDQirr:
4920   case X86::MOVHLPSrr:
4921   case X86::PACKSSWBrr:
4922   case X86::PACKUSWBrr:
4923   case X86::PACKSSDWrr:
4924   case X86::PACKUSDWrr:
4925   case X86::PUNPCKHBWrr:
4926   case X86::PUNPCKLBWrr:
4927   case X86::PUNPCKHWDrr:
4928   case X86::PUNPCKLWDrr:
4929   case X86::PUNPCKHDQrr:
4930   case X86::PUNPCKLDQrr:
4931   case X86::PUNPCKHQDQrr:
4932   case X86::PUNPCKLQDQrr:
4933   case X86::SHUFPDrri:
4934   case X86::SHUFPSrri:
4935     // These instructions are sometimes used with an undef first or second
4936     // source. Return true here so BreakFalseDeps will assign this source to the
4937     // same register as the first source to avoid a false dependency.
4938     // Operand 1 of these instructions is tied so they're separate from their
4939     // VEX counterparts.
4940     return OpNum == 2 && !ForLoadFold;
4941 
4942   case X86::VMOVLHPSrr:
4943   case X86::VMOVLHPSZrr:
4944   case X86::VPACKSSWBrr:
4945   case X86::VPACKUSWBrr:
4946   case X86::VPACKSSDWrr:
4947   case X86::VPACKUSDWrr:
4948   case X86::VPACKSSWBZ128rr:
4949   case X86::VPACKUSWBZ128rr:
4950   case X86::VPACKSSDWZ128rr:
4951   case X86::VPACKUSDWZ128rr:
4952   case X86::VPERM2F128rr:
4953   case X86::VPERM2I128rr:
4954   case X86::VSHUFF32X4Z256rri:
4955   case X86::VSHUFF32X4Zrri:
4956   case X86::VSHUFF64X2Z256rri:
4957   case X86::VSHUFF64X2Zrri:
4958   case X86::VSHUFI32X4Z256rri:
4959   case X86::VSHUFI32X4Zrri:
4960   case X86::VSHUFI64X2Z256rri:
4961   case X86::VSHUFI64X2Zrri:
4962   case X86::VPUNPCKHBWrr:
4963   case X86::VPUNPCKLBWrr:
4964   case X86::VPUNPCKHBWYrr:
4965   case X86::VPUNPCKLBWYrr:
4966   case X86::VPUNPCKHBWZ128rr:
4967   case X86::VPUNPCKLBWZ128rr:
4968   case X86::VPUNPCKHBWZ256rr:
4969   case X86::VPUNPCKLBWZ256rr:
4970   case X86::VPUNPCKHBWZrr:
4971   case X86::VPUNPCKLBWZrr:
4972   case X86::VPUNPCKHWDrr:
4973   case X86::VPUNPCKLWDrr:
4974   case X86::VPUNPCKHWDYrr:
4975   case X86::VPUNPCKLWDYrr:
4976   case X86::VPUNPCKHWDZ128rr:
4977   case X86::VPUNPCKLWDZ128rr:
4978   case X86::VPUNPCKHWDZ256rr:
4979   case X86::VPUNPCKLWDZ256rr:
4980   case X86::VPUNPCKHWDZrr:
4981   case X86::VPUNPCKLWDZrr:
4982   case X86::VPUNPCKHDQrr:
4983   case X86::VPUNPCKLDQrr:
4984   case X86::VPUNPCKHDQYrr:
4985   case X86::VPUNPCKLDQYrr:
4986   case X86::VPUNPCKHDQZ128rr:
4987   case X86::VPUNPCKLDQZ128rr:
4988   case X86::VPUNPCKHDQZ256rr:
4989   case X86::VPUNPCKLDQZ256rr:
4990   case X86::VPUNPCKHDQZrr:
4991   case X86::VPUNPCKLDQZrr:
4992   case X86::VPUNPCKHQDQrr:
4993   case X86::VPUNPCKLQDQrr:
4994   case X86::VPUNPCKHQDQYrr:
4995   case X86::VPUNPCKLQDQYrr:
4996   case X86::VPUNPCKHQDQZ128rr:
4997   case X86::VPUNPCKLQDQZ128rr:
4998   case X86::VPUNPCKHQDQZ256rr:
4999   case X86::VPUNPCKLQDQZ256rr:
5000   case X86::VPUNPCKHQDQZrr:
5001   case X86::VPUNPCKLQDQZrr:
5002     // These instructions are sometimes used with an undef first or second
5003     // source. Return true here so BreakFalseDeps will assign this source to the
5004     // same register as the first source to avoid a false dependency.
5005     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5006 
5007   case X86::VCVTSI2SSrr:
5008   case X86::VCVTSI2SSrm:
5009   case X86::VCVTSI2SSrr_Int:
5010   case X86::VCVTSI2SSrm_Int:
5011   case X86::VCVTSI642SSrr:
5012   case X86::VCVTSI642SSrm:
5013   case X86::VCVTSI642SSrr_Int:
5014   case X86::VCVTSI642SSrm_Int:
5015   case X86::VCVTSI2SDrr:
5016   case X86::VCVTSI2SDrm:
5017   case X86::VCVTSI2SDrr_Int:
5018   case X86::VCVTSI2SDrm_Int:
5019   case X86::VCVTSI642SDrr:
5020   case X86::VCVTSI642SDrm:
5021   case X86::VCVTSI642SDrr_Int:
5022   case X86::VCVTSI642SDrm_Int:
5023   // AVX-512
5024   case X86::VCVTSI2SSZrr:
5025   case X86::VCVTSI2SSZrm:
5026   case X86::VCVTSI2SSZrr_Int:
5027   case X86::VCVTSI2SSZrrb_Int:
5028   case X86::VCVTSI2SSZrm_Int:
5029   case X86::VCVTSI642SSZrr:
5030   case X86::VCVTSI642SSZrm:
5031   case X86::VCVTSI642SSZrr_Int:
5032   case X86::VCVTSI642SSZrrb_Int:
5033   case X86::VCVTSI642SSZrm_Int:
5034   case X86::VCVTSI2SDZrr:
5035   case X86::VCVTSI2SDZrm:
5036   case X86::VCVTSI2SDZrr_Int:
5037   case X86::VCVTSI2SDZrm_Int:
5038   case X86::VCVTSI642SDZrr:
5039   case X86::VCVTSI642SDZrm:
5040   case X86::VCVTSI642SDZrr_Int:
5041   case X86::VCVTSI642SDZrrb_Int:
5042   case X86::VCVTSI642SDZrm_Int:
5043   case X86::VCVTUSI2SSZrr:
5044   case X86::VCVTUSI2SSZrm:
5045   case X86::VCVTUSI2SSZrr_Int:
5046   case X86::VCVTUSI2SSZrrb_Int:
5047   case X86::VCVTUSI2SSZrm_Int:
5048   case X86::VCVTUSI642SSZrr:
5049   case X86::VCVTUSI642SSZrm:
5050   case X86::VCVTUSI642SSZrr_Int:
5051   case X86::VCVTUSI642SSZrrb_Int:
5052   case X86::VCVTUSI642SSZrm_Int:
5053   case X86::VCVTUSI2SDZrr:
5054   case X86::VCVTUSI2SDZrm:
5055   case X86::VCVTUSI2SDZrr_Int:
5056   case X86::VCVTUSI2SDZrm_Int:
5057   case X86::VCVTUSI642SDZrr:
5058   case X86::VCVTUSI642SDZrm:
5059   case X86::VCVTUSI642SDZrr_Int:
5060   case X86::VCVTUSI642SDZrrb_Int:
5061   case X86::VCVTUSI642SDZrm_Int:
5062     // Load folding won't effect the undef register update since the input is
5063     // a GPR.
5064     return OpNum == 1 && !ForLoadFold;
5065   case X86::VCVTSD2SSrr:
5066   case X86::VCVTSD2SSrm:
5067   case X86::VCVTSD2SSrr_Int:
5068   case X86::VCVTSD2SSrm_Int:
5069   case X86::VCVTSS2SDrr:
5070   case X86::VCVTSS2SDrm:
5071   case X86::VCVTSS2SDrr_Int:
5072   case X86::VCVTSS2SDrm_Int:
5073   case X86::VRCPSSr:
5074   case X86::VRCPSSr_Int:
5075   case X86::VRCPSSm:
5076   case X86::VRCPSSm_Int:
5077   case X86::VROUNDSDr:
5078   case X86::VROUNDSDm:
5079   case X86::VROUNDSDr_Int:
5080   case X86::VROUNDSDm_Int:
5081   case X86::VROUNDSSr:
5082   case X86::VROUNDSSm:
5083   case X86::VROUNDSSr_Int:
5084   case X86::VROUNDSSm_Int:
5085   case X86::VRSQRTSSr:
5086   case X86::VRSQRTSSr_Int:
5087   case X86::VRSQRTSSm:
5088   case X86::VRSQRTSSm_Int:
5089   case X86::VSQRTSSr:
5090   case X86::VSQRTSSr_Int:
5091   case X86::VSQRTSSm:
5092   case X86::VSQRTSSm_Int:
5093   case X86::VSQRTSDr:
5094   case X86::VSQRTSDr_Int:
5095   case X86::VSQRTSDm:
5096   case X86::VSQRTSDm_Int:
5097   // AVX-512
5098   case X86::VCVTSD2SSZrr:
5099   case X86::VCVTSD2SSZrr_Int:
5100   case X86::VCVTSD2SSZrrb_Int:
5101   case X86::VCVTSD2SSZrm:
5102   case X86::VCVTSD2SSZrm_Int:
5103   case X86::VCVTSS2SDZrr:
5104   case X86::VCVTSS2SDZrr_Int:
5105   case X86::VCVTSS2SDZrrb_Int:
5106   case X86::VCVTSS2SDZrm:
5107   case X86::VCVTSS2SDZrm_Int:
5108   case X86::VGETEXPSDZr:
5109   case X86::VGETEXPSDZrb:
5110   case X86::VGETEXPSDZm:
5111   case X86::VGETEXPSSZr:
5112   case X86::VGETEXPSSZrb:
5113   case X86::VGETEXPSSZm:
5114   case X86::VGETMANTSDZrri:
5115   case X86::VGETMANTSDZrrib:
5116   case X86::VGETMANTSDZrmi:
5117   case X86::VGETMANTSSZrri:
5118   case X86::VGETMANTSSZrrib:
5119   case X86::VGETMANTSSZrmi:
5120   case X86::VRNDSCALESDZr:
5121   case X86::VRNDSCALESDZr_Int:
5122   case X86::VRNDSCALESDZrb_Int:
5123   case X86::VRNDSCALESDZm:
5124   case X86::VRNDSCALESDZm_Int:
5125   case X86::VRNDSCALESSZr:
5126   case X86::VRNDSCALESSZr_Int:
5127   case X86::VRNDSCALESSZrb_Int:
5128   case X86::VRNDSCALESSZm:
5129   case X86::VRNDSCALESSZm_Int:
5130   case X86::VRCP14SDZrr:
5131   case X86::VRCP14SDZrm:
5132   case X86::VRCP14SSZrr:
5133   case X86::VRCP14SSZrm:
5134   case X86::VRCP28SDZr:
5135   case X86::VRCP28SDZrb:
5136   case X86::VRCP28SDZm:
5137   case X86::VRCP28SSZr:
5138   case X86::VRCP28SSZrb:
5139   case X86::VRCP28SSZm:
5140   case X86::VREDUCESSZrmi:
5141   case X86::VREDUCESSZrri:
5142   case X86::VREDUCESSZrrib:
5143   case X86::VRSQRT14SDZrr:
5144   case X86::VRSQRT14SDZrm:
5145   case X86::VRSQRT14SSZrr:
5146   case X86::VRSQRT14SSZrm:
5147   case X86::VRSQRT28SDZr:
5148   case X86::VRSQRT28SDZrb:
5149   case X86::VRSQRT28SDZm:
5150   case X86::VRSQRT28SSZr:
5151   case X86::VRSQRT28SSZrb:
5152   case X86::VRSQRT28SSZm:
5153   case X86::VSQRTSSZr:
5154   case X86::VSQRTSSZr_Int:
5155   case X86::VSQRTSSZrb_Int:
5156   case X86::VSQRTSSZm:
5157   case X86::VSQRTSSZm_Int:
5158   case X86::VSQRTSDZr:
5159   case X86::VSQRTSDZr_Int:
5160   case X86::VSQRTSDZrb_Int:
5161   case X86::VSQRTSDZm:
5162   case X86::VSQRTSDZm_Int:
5163     return OpNum == 1;
5164   case X86::VMOVSSZrrk:
5165   case X86::VMOVSDZrrk:
5166     return OpNum == 3 && !ForLoadFold;
5167   case X86::VMOVSSZrrkz:
5168   case X86::VMOVSDZrrkz:
5169     return OpNum == 2 && !ForLoadFold;
5170   }
5171 
5172   return false;
5173 }
5174 
5175 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5176 /// before certain undef register reads.
5177 ///
5178 /// This catches the VCVTSI2SD family of instructions:
5179 ///
5180 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5181 ///
5182 /// We should to be careful *not* to catch VXOR idioms which are presumably
5183 /// handled specially in the pipeline:
5184 ///
5185 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5186 ///
5187 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5188 /// high bits that are passed-through are not live.
5189 unsigned
5190 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5191                                    const TargetRegisterInfo *TRI) const {
5192   const MachineOperand &MO = MI.getOperand(OpNum);
5193   if (Register::isPhysicalRegister(MO.getReg()) &&
5194       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5195     return UndefRegClearance;
5196 
5197   return 0;
5198 }
5199 
5200 void X86InstrInfo::breakPartialRegDependency(
5201     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5202   Register Reg = MI.getOperand(OpNum).getReg();
5203   // If MI kills this register, the false dependence is already broken.
5204   if (MI.killsRegister(Reg, TRI))
5205     return;
5206 
5207   if (X86::VR128RegClass.contains(Reg)) {
5208     // These instructions are all floating point domain, so xorps is the best
5209     // choice.
5210     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5211     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5212         .addReg(Reg, RegState::Undef)
5213         .addReg(Reg, RegState::Undef);
5214     MI.addRegisterKilled(Reg, TRI, true);
5215   } else if (X86::VR256RegClass.contains(Reg)) {
5216     // Use vxorps to clear the full ymm register.
5217     // It wants to read and write the xmm sub-register.
5218     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5219     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5220         .addReg(XReg, RegState::Undef)
5221         .addReg(XReg, RegState::Undef)
5222         .addReg(Reg, RegState::ImplicitDefine);
5223     MI.addRegisterKilled(Reg, TRI, true);
5224   } else if (X86::GR64RegClass.contains(Reg)) {
5225     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5226     // as well.
5227     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5228     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5229         .addReg(XReg, RegState::Undef)
5230         .addReg(XReg, RegState::Undef)
5231         .addReg(Reg, RegState::ImplicitDefine);
5232     MI.addRegisterKilled(Reg, TRI, true);
5233   } else if (X86::GR32RegClass.contains(Reg)) {
5234     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5235         .addReg(Reg, RegState::Undef)
5236         .addReg(Reg, RegState::Undef);
5237     MI.addRegisterKilled(Reg, TRI, true);
5238   }
5239 }
5240 
5241 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5242                         int PtrOffset = 0) {
5243   unsigned NumAddrOps = MOs.size();
5244 
5245   if (NumAddrOps < 4) {
5246     // FrameIndex only - add an immediate offset (whether its zero or not).
5247     for (unsigned i = 0; i != NumAddrOps; ++i)
5248       MIB.add(MOs[i]);
5249     addOffset(MIB, PtrOffset);
5250   } else {
5251     // General Memory Addressing - we need to add any offset to an existing
5252     // offset.
5253     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5254     for (unsigned i = 0; i != NumAddrOps; ++i) {
5255       const MachineOperand &MO = MOs[i];
5256       if (i == 3 && PtrOffset != 0) {
5257         MIB.addDisp(MO, PtrOffset);
5258       } else {
5259         MIB.add(MO);
5260       }
5261     }
5262   }
5263 }
5264 
5265 static void updateOperandRegConstraints(MachineFunction &MF,
5266                                         MachineInstr &NewMI,
5267                                         const TargetInstrInfo &TII) {
5268   MachineRegisterInfo &MRI = MF.getRegInfo();
5269   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5270 
5271   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5272     MachineOperand &MO = NewMI.getOperand(Idx);
5273     // We only need to update constraints on virtual register operands.
5274     if (!MO.isReg())
5275       continue;
5276     Register Reg = MO.getReg();
5277     if (!Reg.isVirtual())
5278       continue;
5279 
5280     auto *NewRC = MRI.constrainRegClass(
5281         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5282     if (!NewRC) {
5283       LLVM_DEBUG(
5284           dbgs() << "WARNING: Unable to update register constraint for operand "
5285                  << Idx << " of instruction:\n";
5286           NewMI.dump(); dbgs() << "\n");
5287     }
5288   }
5289 }
5290 
5291 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5292                                      ArrayRef<MachineOperand> MOs,
5293                                      MachineBasicBlock::iterator InsertPt,
5294                                      MachineInstr &MI,
5295                                      const TargetInstrInfo &TII) {
5296   // Create the base instruction with the memory operand as the first part.
5297   // Omit the implicit operands, something BuildMI can't do.
5298   MachineInstr *NewMI =
5299       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5300   MachineInstrBuilder MIB(MF, NewMI);
5301   addOperands(MIB, MOs);
5302 
5303   // Loop over the rest of the ri operands, converting them over.
5304   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5305   for (unsigned i = 0; i != NumOps; ++i) {
5306     MachineOperand &MO = MI.getOperand(i + 2);
5307     MIB.add(MO);
5308   }
5309   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5310     MachineOperand &MO = MI.getOperand(i);
5311     MIB.add(MO);
5312   }
5313 
5314   updateOperandRegConstraints(MF, *NewMI, TII);
5315 
5316   MachineBasicBlock *MBB = InsertPt->getParent();
5317   MBB->insert(InsertPt, NewMI);
5318 
5319   return MIB;
5320 }
5321 
5322 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5323                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5324                               MachineBasicBlock::iterator InsertPt,
5325                               MachineInstr &MI, const TargetInstrInfo &TII,
5326                               int PtrOffset = 0) {
5327   // Omit the implicit operands, something BuildMI can't do.
5328   MachineInstr *NewMI =
5329       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5330   MachineInstrBuilder MIB(MF, NewMI);
5331 
5332   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5333     MachineOperand &MO = MI.getOperand(i);
5334     if (i == OpNo) {
5335       assert(MO.isReg() && "Expected to fold into reg operand!");
5336       addOperands(MIB, MOs, PtrOffset);
5337     } else {
5338       MIB.add(MO);
5339     }
5340   }
5341 
5342   updateOperandRegConstraints(MF, *NewMI, TII);
5343 
5344   // Copy the NoFPExcept flag from the instruction we're fusing.
5345   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5346     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5347 
5348   MachineBasicBlock *MBB = InsertPt->getParent();
5349   MBB->insert(InsertPt, NewMI);
5350 
5351   return MIB;
5352 }
5353 
5354 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5355                                 ArrayRef<MachineOperand> MOs,
5356                                 MachineBasicBlock::iterator InsertPt,
5357                                 MachineInstr &MI) {
5358   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5359                                     MI.getDebugLoc(), TII.get(Opcode));
5360   addOperands(MIB, MOs);
5361   return MIB.addImm(0);
5362 }
5363 
5364 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5365     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5366     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5367     unsigned Size, Align Alignment) const {
5368   switch (MI.getOpcode()) {
5369   case X86::INSERTPSrr:
5370   case X86::VINSERTPSrr:
5371   case X86::VINSERTPSZrr:
5372     // Attempt to convert the load of inserted vector into a fold load
5373     // of a single float.
5374     if (OpNum == 2) {
5375       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5376       unsigned ZMask = Imm & 15;
5377       unsigned DstIdx = (Imm >> 4) & 3;
5378       unsigned SrcIdx = (Imm >> 6) & 3;
5379 
5380       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5381       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5382       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5383       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5384         int PtrOffset = SrcIdx * 4;
5385         unsigned NewImm = (DstIdx << 4) | ZMask;
5386         unsigned NewOpCode =
5387             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5388             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5389                                                     X86::INSERTPSrm;
5390         MachineInstr *NewMI =
5391             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5392         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5393         return NewMI;
5394       }
5395     }
5396     break;
5397   case X86::MOVHLPSrr:
5398   case X86::VMOVHLPSrr:
5399   case X86::VMOVHLPSZrr:
5400     // Move the upper 64-bits of the second operand to the lower 64-bits.
5401     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5402     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5403     if (OpNum == 2) {
5404       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5405       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5406       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5407       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5408         unsigned NewOpCode =
5409             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5410             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5411                                                    X86::MOVLPSrm;
5412         MachineInstr *NewMI =
5413             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5414         return NewMI;
5415       }
5416     }
5417     break;
5418   case X86::UNPCKLPDrr:
5419     // If we won't be able to fold this to the memory form of UNPCKL, use
5420     // MOVHPD instead. Done as custom because we can't have this in the load
5421     // table twice.
5422     if (OpNum == 2) {
5423       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5424       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5425       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5426       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5427         MachineInstr *NewMI =
5428             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5429         return NewMI;
5430       }
5431     }
5432     break;
5433   }
5434 
5435   return nullptr;
5436 }
5437 
5438 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5439                                                MachineInstr &MI) {
5440   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5441       !MI.getOperand(1).isReg())
5442     return false;
5443 
5444   // The are two cases we need to handle depending on where in the pipeline
5445   // the folding attempt is being made.
5446   // -Register has the undef flag set.
5447   // -Register is produced by the IMPLICIT_DEF instruction.
5448 
5449   if (MI.getOperand(1).isUndef())
5450     return true;
5451 
5452   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5453   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5454   return VRegDef && VRegDef->isImplicitDef();
5455 }
5456 
5457 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5458     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5459     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5460     unsigned Size, Align Alignment, bool AllowCommute) const {
5461   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5462   bool isTwoAddrFold = false;
5463 
5464   // For CPUs that favor the register form of a call or push,
5465   // do not fold loads into calls or pushes, unless optimizing for size
5466   // aggressively.
5467   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5468       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5469        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5470        MI.getOpcode() == X86::PUSH64r))
5471     return nullptr;
5472 
5473   // Avoid partial and undef register update stalls unless optimizing for size.
5474   if (!MF.getFunction().hasOptSize() &&
5475       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5476        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5477     return nullptr;
5478 
5479   unsigned NumOps = MI.getDesc().getNumOperands();
5480   bool isTwoAddr =
5481       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5482 
5483   // FIXME: AsmPrinter doesn't know how to handle
5484   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5485   if (MI.getOpcode() == X86::ADD32ri &&
5486       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5487     return nullptr;
5488 
5489   // GOTTPOFF relocation loads can only be folded into add instructions.
5490   // FIXME: Need to exclude other relocations that only support specific
5491   // instructions.
5492   if (MOs.size() == X86::AddrNumOperands &&
5493       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5494       MI.getOpcode() != X86::ADD64rr)
5495     return nullptr;
5496 
5497   MachineInstr *NewMI = nullptr;
5498 
5499   // Attempt to fold any custom cases we have.
5500   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5501           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5502     return CustomMI;
5503 
5504   const X86MemoryFoldTableEntry *I = nullptr;
5505 
5506   // Folding a memory location into the two-address part of a two-address
5507   // instruction is different than folding it other places.  It requires
5508   // replacing the *two* registers with the memory location.
5509   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5510       MI.getOperand(1).isReg() &&
5511       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5512     I = lookupTwoAddrFoldTable(MI.getOpcode());
5513     isTwoAddrFold = true;
5514   } else {
5515     if (OpNum == 0) {
5516       if (MI.getOpcode() == X86::MOV32r0) {
5517         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5518         if (NewMI)
5519           return NewMI;
5520       }
5521     }
5522 
5523     I = lookupFoldTable(MI.getOpcode(), OpNum);
5524   }
5525 
5526   if (I != nullptr) {
5527     unsigned Opcode = I->DstOp;
5528     bool FoldedLoad =
5529         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5530     bool FoldedStore =
5531         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5532     MaybeAlign MinAlign =
5533         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5534     if (MinAlign && Alignment < *MinAlign)
5535       return nullptr;
5536     bool NarrowToMOV32rm = false;
5537     if (Size) {
5538       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5539       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5540                                                   &RI, MF);
5541       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5542       // Check if it's safe to fold the load. If the size of the object is
5543       // narrower than the load width, then it's not.
5544       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5545       if (FoldedLoad && Size < RCSize) {
5546         // If this is a 64-bit load, but the spill slot is 32, then we can do
5547         // a 32-bit load which is implicitly zero-extended. This likely is
5548         // due to live interval analysis remat'ing a load from stack slot.
5549         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5550           return nullptr;
5551         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5552           return nullptr;
5553         Opcode = X86::MOV32rm;
5554         NarrowToMOV32rm = true;
5555       }
5556       // For stores, make sure the size of the object is equal to the size of
5557       // the store. If the object is larger, the extra bits would be garbage. If
5558       // the object is smaller we might overwrite another object or fault.
5559       if (FoldedStore && Size != RCSize)
5560         return nullptr;
5561     }
5562 
5563     if (isTwoAddrFold)
5564       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5565     else
5566       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5567 
5568     if (NarrowToMOV32rm) {
5569       // If this is the special case where we use a MOV32rm to load a 32-bit
5570       // value and zero-extend the top bits. Change the destination register
5571       // to a 32-bit one.
5572       Register DstReg = NewMI->getOperand(0).getReg();
5573       if (DstReg.isPhysical())
5574         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5575       else
5576         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5577     }
5578     return NewMI;
5579   }
5580 
5581   // If the instruction and target operand are commutable, commute the
5582   // instruction and try again.
5583   if (AllowCommute) {
5584     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5585     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5586       bool HasDef = MI.getDesc().getNumDefs();
5587       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5588       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5589       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5590       bool Tied1 =
5591           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5592       bool Tied2 =
5593           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5594 
5595       // If either of the commutable operands are tied to the destination
5596       // then we can not commute + fold.
5597       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5598           (HasDef && Reg0 == Reg2 && Tied2))
5599         return nullptr;
5600 
5601       MachineInstr *CommutedMI =
5602           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5603       if (!CommutedMI) {
5604         // Unable to commute.
5605         return nullptr;
5606       }
5607       if (CommutedMI != &MI) {
5608         // New instruction. We can't fold from this.
5609         CommutedMI->eraseFromParent();
5610         return nullptr;
5611       }
5612 
5613       // Attempt to fold with the commuted version of the instruction.
5614       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5615                                     Alignment, /*AllowCommute=*/false);
5616       if (NewMI)
5617         return NewMI;
5618 
5619       // Folding failed again - undo the commute before returning.
5620       MachineInstr *UncommutedMI =
5621           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5622       if (!UncommutedMI) {
5623         // Unable to commute.
5624         return nullptr;
5625       }
5626       if (UncommutedMI != &MI) {
5627         // New instruction. It doesn't need to be kept.
5628         UncommutedMI->eraseFromParent();
5629         return nullptr;
5630       }
5631 
5632       // Return here to prevent duplicate fuse failure report.
5633       return nullptr;
5634     }
5635   }
5636 
5637   // No fusion
5638   if (PrintFailedFusing && !MI.isCopy())
5639     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5640   return nullptr;
5641 }
5642 
5643 MachineInstr *
5644 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5645                                     ArrayRef<unsigned> Ops,
5646                                     MachineBasicBlock::iterator InsertPt,
5647                                     int FrameIndex, LiveIntervals *LIS,
5648                                     VirtRegMap *VRM) const {
5649   // Check switch flag
5650   if (NoFusing)
5651     return nullptr;
5652 
5653   // Avoid partial and undef register update stalls unless optimizing for size.
5654   if (!MF.getFunction().hasOptSize() &&
5655       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5656        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5657     return nullptr;
5658 
5659   // Don't fold subreg spills, or reloads that use a high subreg.
5660   for (auto Op : Ops) {
5661     MachineOperand &MO = MI.getOperand(Op);
5662     auto SubReg = MO.getSubReg();
5663     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5664       return nullptr;
5665   }
5666 
5667   const MachineFrameInfo &MFI = MF.getFrameInfo();
5668   unsigned Size = MFI.getObjectSize(FrameIndex);
5669   Align Alignment = MFI.getObjectAlign(FrameIndex);
5670   // If the function stack isn't realigned we don't want to fold instructions
5671   // that need increased alignment.
5672   if (!RI.needsStackRealignment(MF))
5673     Alignment =
5674         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5675   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5676     unsigned NewOpc = 0;
5677     unsigned RCSize = 0;
5678     switch (MI.getOpcode()) {
5679     default: return nullptr;
5680     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5681     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5682     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5683     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5684     }
5685     // Check if it's safe to fold the load. If the size of the object is
5686     // narrower than the load width, then it's not.
5687     if (Size < RCSize)
5688       return nullptr;
5689     // Change to CMPXXri r, 0 first.
5690     MI.setDesc(get(NewOpc));
5691     MI.getOperand(1).ChangeToImmediate(0);
5692   } else if (Ops.size() != 1)
5693     return nullptr;
5694 
5695   return foldMemoryOperandImpl(MF, MI, Ops[0],
5696                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5697                                Size, Alignment, /*AllowCommute=*/true);
5698 }
5699 
5700 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5701 /// because the latter uses contents that wouldn't be defined in the folded
5702 /// version.  For instance, this transformation isn't legal:
5703 ///   movss (%rdi), %xmm0
5704 ///   addps %xmm0, %xmm0
5705 /// ->
5706 ///   addps (%rdi), %xmm0
5707 ///
5708 /// But this one is:
5709 ///   movss (%rdi), %xmm0
5710 ///   addss %xmm0, %xmm0
5711 /// ->
5712 ///   addss (%rdi), %xmm0
5713 ///
5714 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5715                                              const MachineInstr &UserMI,
5716                                              const MachineFunction &MF) {
5717   unsigned Opc = LoadMI.getOpcode();
5718   unsigned UserOpc = UserMI.getOpcode();
5719   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5720   const TargetRegisterClass *RC =
5721       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5722   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5723 
5724   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5725        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5726        Opc == X86::VMOVSSZrm_alt) &&
5727       RegSize > 32) {
5728     // These instructions only load 32 bits, we can't fold them if the
5729     // destination register is wider than 32 bits (4 bytes), and its user
5730     // instruction isn't scalar (SS).
5731     switch (UserOpc) {
5732     case X86::CVTSS2SDrr_Int:
5733     case X86::VCVTSS2SDrr_Int:
5734     case X86::VCVTSS2SDZrr_Int:
5735     case X86::VCVTSS2SDZrr_Intk:
5736     case X86::VCVTSS2SDZrr_Intkz:
5737     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5738     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5739     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5740     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5741     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5742     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5743     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5744     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5745     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5746     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5747     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5748     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5749     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5750     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5751     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5752     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5753     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5754     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5755     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5756     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5757     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5758     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5759     case X86::VCMPSSZrr_Intk:
5760     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5761     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5762     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5763     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5764     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5765     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5766     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5767     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5768     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5769     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5770     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5771     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5772     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5773     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5774     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5775     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5776     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5777     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5778     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5779     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5780     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5781     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5782     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5783     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5784     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5785     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5786     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5787     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5788     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5789     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5790     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5791     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5792     case X86::VFIXUPIMMSSZrri:
5793     case X86::VFIXUPIMMSSZrrik:
5794     case X86::VFIXUPIMMSSZrrikz:
5795     case X86::VFPCLASSSSZrr:
5796     case X86::VFPCLASSSSZrrk:
5797     case X86::VGETEXPSSZr:
5798     case X86::VGETEXPSSZrk:
5799     case X86::VGETEXPSSZrkz:
5800     case X86::VGETMANTSSZrri:
5801     case X86::VGETMANTSSZrrik:
5802     case X86::VGETMANTSSZrrikz:
5803     case X86::VRANGESSZrri:
5804     case X86::VRANGESSZrrik:
5805     case X86::VRANGESSZrrikz:
5806     case X86::VRCP14SSZrr:
5807     case X86::VRCP14SSZrrk:
5808     case X86::VRCP14SSZrrkz:
5809     case X86::VRCP28SSZr:
5810     case X86::VRCP28SSZrk:
5811     case X86::VRCP28SSZrkz:
5812     case X86::VREDUCESSZrri:
5813     case X86::VREDUCESSZrrik:
5814     case X86::VREDUCESSZrrikz:
5815     case X86::VRNDSCALESSZr_Int:
5816     case X86::VRNDSCALESSZr_Intk:
5817     case X86::VRNDSCALESSZr_Intkz:
5818     case X86::VRSQRT14SSZrr:
5819     case X86::VRSQRT14SSZrrk:
5820     case X86::VRSQRT14SSZrrkz:
5821     case X86::VRSQRT28SSZr:
5822     case X86::VRSQRT28SSZrk:
5823     case X86::VRSQRT28SSZrkz:
5824     case X86::VSCALEFSSZrr:
5825     case X86::VSCALEFSSZrrk:
5826     case X86::VSCALEFSSZrrkz:
5827       return false;
5828     default:
5829       return true;
5830     }
5831   }
5832 
5833   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5834        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5835        Opc == X86::VMOVSDZrm_alt) &&
5836       RegSize > 64) {
5837     // These instructions only load 64 bits, we can't fold them if the
5838     // destination register is wider than 64 bits (8 bytes), and its user
5839     // instruction isn't scalar (SD).
5840     switch (UserOpc) {
5841     case X86::CVTSD2SSrr_Int:
5842     case X86::VCVTSD2SSrr_Int:
5843     case X86::VCVTSD2SSZrr_Int:
5844     case X86::VCVTSD2SSZrr_Intk:
5845     case X86::VCVTSD2SSZrr_Intkz:
5846     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
5847     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
5848     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
5849     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
5850     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
5851     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
5852     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
5853     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
5854     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
5855     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
5856     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
5857     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5858     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5859     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5860     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5861     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5862     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5863     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
5864     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5865     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5866     case X86::VCMPSDZrr_Intk:
5867     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5868     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5869     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5870     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5871     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
5872     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5873     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
5874     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
5875     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
5876     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
5877     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
5878     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
5879     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
5880     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
5881     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5882     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5883     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5884     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5885     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5886     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5887     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5888     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5889     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5890     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5891     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5892     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5893     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5894     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5895     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5896     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5897     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5898     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5899     case X86::VFIXUPIMMSDZrri:
5900     case X86::VFIXUPIMMSDZrrik:
5901     case X86::VFIXUPIMMSDZrrikz:
5902     case X86::VFPCLASSSDZrr:
5903     case X86::VFPCLASSSDZrrk:
5904     case X86::VGETEXPSDZr:
5905     case X86::VGETEXPSDZrk:
5906     case X86::VGETEXPSDZrkz:
5907     case X86::VGETMANTSDZrri:
5908     case X86::VGETMANTSDZrrik:
5909     case X86::VGETMANTSDZrrikz:
5910     case X86::VRANGESDZrri:
5911     case X86::VRANGESDZrrik:
5912     case X86::VRANGESDZrrikz:
5913     case X86::VRCP14SDZrr:
5914     case X86::VRCP14SDZrrk:
5915     case X86::VRCP14SDZrrkz:
5916     case X86::VRCP28SDZr:
5917     case X86::VRCP28SDZrk:
5918     case X86::VRCP28SDZrkz:
5919     case X86::VREDUCESDZrri:
5920     case X86::VREDUCESDZrrik:
5921     case X86::VREDUCESDZrrikz:
5922     case X86::VRNDSCALESDZr_Int:
5923     case X86::VRNDSCALESDZr_Intk:
5924     case X86::VRNDSCALESDZr_Intkz:
5925     case X86::VRSQRT14SDZrr:
5926     case X86::VRSQRT14SDZrrk:
5927     case X86::VRSQRT14SDZrrkz:
5928     case X86::VRSQRT28SDZr:
5929     case X86::VRSQRT28SDZrk:
5930     case X86::VRSQRT28SDZrkz:
5931     case X86::VSCALEFSDZrr:
5932     case X86::VSCALEFSDZrrk:
5933     case X86::VSCALEFSDZrrkz:
5934       return false;
5935     default:
5936       return true;
5937     }
5938   }
5939 
5940   return false;
5941 }
5942 
5943 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5944     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5945     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5946     LiveIntervals *LIS) const {
5947 
5948   // TODO: Support the case where LoadMI loads a wide register, but MI
5949   // only uses a subreg.
5950   for (auto Op : Ops) {
5951     if (MI.getOperand(Op).getSubReg())
5952       return nullptr;
5953   }
5954 
5955   // If loading from a FrameIndex, fold directly from the FrameIndex.
5956   unsigned NumOps = LoadMI.getDesc().getNumOperands();
5957   int FrameIndex;
5958   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5959     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5960       return nullptr;
5961     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5962   }
5963 
5964   // Check switch flag
5965   if (NoFusing) return nullptr;
5966 
5967   // Avoid partial and undef register update stalls unless optimizing for size.
5968   if (!MF.getFunction().hasOptSize() &&
5969       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5970        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5971     return nullptr;
5972 
5973   // Determine the alignment of the load.
5974   Align Alignment;
5975   if (LoadMI.hasOneMemOperand())
5976     Alignment = (*LoadMI.memoperands_begin())->getAlign();
5977   else
5978     switch (LoadMI.getOpcode()) {
5979     case X86::AVX512_512_SET0:
5980     case X86::AVX512_512_SETALLONES:
5981       Alignment = Align(64);
5982       break;
5983     case X86::AVX2_SETALLONES:
5984     case X86::AVX1_SETALLONES:
5985     case X86::AVX_SET0:
5986     case X86::AVX512_256_SET0:
5987       Alignment = Align(32);
5988       break;
5989     case X86::V_SET0:
5990     case X86::V_SETALLONES:
5991     case X86::AVX512_128_SET0:
5992     case X86::FsFLD0F128:
5993     case X86::AVX512_FsFLD0F128:
5994       Alignment = Align(16);
5995       break;
5996     case X86::MMX_SET0:
5997     case X86::FsFLD0SD:
5998     case X86::AVX512_FsFLD0SD:
5999       Alignment = Align(8);
6000       break;
6001     case X86::FsFLD0SS:
6002     case X86::AVX512_FsFLD0SS:
6003       Alignment = Align(4);
6004       break;
6005     default:
6006       return nullptr;
6007     }
6008   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6009     unsigned NewOpc = 0;
6010     switch (MI.getOpcode()) {
6011     default: return nullptr;
6012     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6013     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6014     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6015     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6016     }
6017     // Change to CMPXXri r, 0 first.
6018     MI.setDesc(get(NewOpc));
6019     MI.getOperand(1).ChangeToImmediate(0);
6020   } else if (Ops.size() != 1)
6021     return nullptr;
6022 
6023   // Make sure the subregisters match.
6024   // Otherwise we risk changing the size of the load.
6025   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6026     return nullptr;
6027 
6028   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6029   switch (LoadMI.getOpcode()) {
6030   case X86::MMX_SET0:
6031   case X86::V_SET0:
6032   case X86::V_SETALLONES:
6033   case X86::AVX2_SETALLONES:
6034   case X86::AVX1_SETALLONES:
6035   case X86::AVX_SET0:
6036   case X86::AVX512_128_SET0:
6037   case X86::AVX512_256_SET0:
6038   case X86::AVX512_512_SET0:
6039   case X86::AVX512_512_SETALLONES:
6040   case X86::FsFLD0SD:
6041   case X86::AVX512_FsFLD0SD:
6042   case X86::FsFLD0SS:
6043   case X86::AVX512_FsFLD0SS:
6044   case X86::FsFLD0F128:
6045   case X86::AVX512_FsFLD0F128: {
6046     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6047     // Create a constant-pool entry and operands to load from it.
6048 
6049     // Medium and large mode can't fold loads this way.
6050     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6051         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6052       return nullptr;
6053 
6054     // x86-32 PIC requires a PIC base register for constant pools.
6055     unsigned PICBase = 0;
6056     if (MF.getTarget().isPositionIndependent()) {
6057       if (Subtarget.is64Bit())
6058         PICBase = X86::RIP;
6059       else
6060         // FIXME: PICBase = getGlobalBaseReg(&MF);
6061         // This doesn't work for several reasons.
6062         // 1. GlobalBaseReg may have been spilled.
6063         // 2. It may not be live at MI.
6064         return nullptr;
6065     }
6066 
6067     // Create a constant-pool entry.
6068     MachineConstantPool &MCP = *MF.getConstantPool();
6069     Type *Ty;
6070     unsigned Opc = LoadMI.getOpcode();
6071     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6072       Ty = Type::getFloatTy(MF.getFunction().getContext());
6073     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6074       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6075     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6076       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6077     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6078       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6079                                 16);
6080     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6081              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6082       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6083                                 8);
6084     else if (Opc == X86::MMX_SET0)
6085       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6086                                 2);
6087     else
6088       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6089                                 4);
6090 
6091     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6092                       Opc == X86::AVX512_512_SETALLONES ||
6093                       Opc == X86::AVX1_SETALLONES);
6094     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6095                                     Constant::getNullValue(Ty);
6096     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6097 
6098     // Create operands to load from the constant pool entry.
6099     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6100     MOs.push_back(MachineOperand::CreateImm(1));
6101     MOs.push_back(MachineOperand::CreateReg(0, false));
6102     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6103     MOs.push_back(MachineOperand::CreateReg(0, false));
6104     break;
6105   }
6106   default: {
6107     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6108       return nullptr;
6109 
6110     // Folding a normal load. Just copy the load's address operands.
6111     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6112                LoadMI.operands_begin() + NumOps);
6113     break;
6114   }
6115   }
6116   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6117                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6118 }
6119 
6120 static SmallVector<MachineMemOperand *, 2>
6121 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6122   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6123 
6124   for (MachineMemOperand *MMO : MMOs) {
6125     if (!MMO->isLoad())
6126       continue;
6127 
6128     if (!MMO->isStore()) {
6129       // Reuse the MMO.
6130       LoadMMOs.push_back(MMO);
6131     } else {
6132       // Clone the MMO and unset the store flag.
6133       LoadMMOs.push_back(MF.getMachineMemOperand(
6134           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6135     }
6136   }
6137 
6138   return LoadMMOs;
6139 }
6140 
6141 static SmallVector<MachineMemOperand *, 2>
6142 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6143   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6144 
6145   for (MachineMemOperand *MMO : MMOs) {
6146     if (!MMO->isStore())
6147       continue;
6148 
6149     if (!MMO->isLoad()) {
6150       // Reuse the MMO.
6151       StoreMMOs.push_back(MMO);
6152     } else {
6153       // Clone the MMO and unset the load flag.
6154       StoreMMOs.push_back(MF.getMachineMemOperand(
6155           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6156     }
6157   }
6158 
6159   return StoreMMOs;
6160 }
6161 
6162 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6163                                    const TargetRegisterClass *RC,
6164                                    const X86Subtarget &STI) {
6165   assert(STI.hasAVX512() && "Expected at least AVX512!");
6166   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6167   assert((SpillSize == 64 || STI.hasVLX()) &&
6168          "Can't broadcast less than 64 bytes without AVX512VL!");
6169 
6170   switch (I->Flags & TB_BCAST_MASK) {
6171   default: llvm_unreachable("Unexpected broadcast type!");
6172   case TB_BCAST_D:
6173     switch (SpillSize) {
6174     default: llvm_unreachable("Unknown spill size");
6175     case 16: return X86::VPBROADCASTDZ128rm;
6176     case 32: return X86::VPBROADCASTDZ256rm;
6177     case 64: return X86::VPBROADCASTDZrm;
6178     }
6179     break;
6180   case TB_BCAST_Q:
6181     switch (SpillSize) {
6182     default: llvm_unreachable("Unknown spill size");
6183     case 16: return X86::VPBROADCASTQZ128rm;
6184     case 32: return X86::VPBROADCASTQZ256rm;
6185     case 64: return X86::VPBROADCASTQZrm;
6186     }
6187     break;
6188   case TB_BCAST_SS:
6189     switch (SpillSize) {
6190     default: llvm_unreachable("Unknown spill size");
6191     case 16: return X86::VBROADCASTSSZ128rm;
6192     case 32: return X86::VBROADCASTSSZ256rm;
6193     case 64: return X86::VBROADCASTSSZrm;
6194     }
6195     break;
6196   case TB_BCAST_SD:
6197     switch (SpillSize) {
6198     default: llvm_unreachable("Unknown spill size");
6199     case 16: return X86::VMOVDDUPZ128rm;
6200     case 32: return X86::VBROADCASTSDZ256rm;
6201     case 64: return X86::VBROADCASTSDZrm;
6202     }
6203     break;
6204   }
6205 }
6206 
6207 bool X86InstrInfo::unfoldMemoryOperand(
6208     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6209     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6210   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6211   if (I == nullptr)
6212     return false;
6213   unsigned Opc = I->DstOp;
6214   unsigned Index = I->Flags & TB_INDEX_MASK;
6215   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6216   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6217   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6218   if (UnfoldLoad && !FoldedLoad)
6219     return false;
6220   UnfoldLoad &= FoldedLoad;
6221   if (UnfoldStore && !FoldedStore)
6222     return false;
6223   UnfoldStore &= FoldedStore;
6224 
6225   const MCInstrDesc &MCID = get(Opc);
6226 
6227   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6228   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6229   // TODO: Check if 32-byte or greater accesses are slow too?
6230   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6231       Subtarget.isUnalignedMem16Slow())
6232     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6233     // conservatively assume the address is unaligned. That's bad for
6234     // performance.
6235     return false;
6236   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6237   SmallVector<MachineOperand,2> BeforeOps;
6238   SmallVector<MachineOperand,2> AfterOps;
6239   SmallVector<MachineOperand,4> ImpOps;
6240   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6241     MachineOperand &Op = MI.getOperand(i);
6242     if (i >= Index && i < Index + X86::AddrNumOperands)
6243       AddrOps.push_back(Op);
6244     else if (Op.isReg() && Op.isImplicit())
6245       ImpOps.push_back(Op);
6246     else if (i < Index)
6247       BeforeOps.push_back(Op);
6248     else if (i > Index)
6249       AfterOps.push_back(Op);
6250   }
6251 
6252   // Emit the load or broadcast instruction.
6253   if (UnfoldLoad) {
6254     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6255 
6256     unsigned Opc;
6257     if (FoldedBCast) {
6258       Opc = getBroadcastOpcode(I, RC, Subtarget);
6259     } else {
6260       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6261       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6262       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6263     }
6264 
6265     DebugLoc DL;
6266     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6267     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6268       MIB.add(AddrOps[i]);
6269     MIB.setMemRefs(MMOs);
6270     NewMIs.push_back(MIB);
6271 
6272     if (UnfoldStore) {
6273       // Address operands cannot be marked isKill.
6274       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6275         MachineOperand &MO = NewMIs[0]->getOperand(i);
6276         if (MO.isReg())
6277           MO.setIsKill(false);
6278       }
6279     }
6280   }
6281 
6282   // Emit the data processing instruction.
6283   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6284   MachineInstrBuilder MIB(MF, DataMI);
6285 
6286   if (FoldedStore)
6287     MIB.addReg(Reg, RegState::Define);
6288   for (MachineOperand &BeforeOp : BeforeOps)
6289     MIB.add(BeforeOp);
6290   if (FoldedLoad)
6291     MIB.addReg(Reg);
6292   for (MachineOperand &AfterOp : AfterOps)
6293     MIB.add(AfterOp);
6294   for (MachineOperand &ImpOp : ImpOps) {
6295     MIB.addReg(ImpOp.getReg(),
6296                getDefRegState(ImpOp.isDef()) |
6297                RegState::Implicit |
6298                getKillRegState(ImpOp.isKill()) |
6299                getDeadRegState(ImpOp.isDead()) |
6300                getUndefRegState(ImpOp.isUndef()));
6301   }
6302   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6303   switch (DataMI->getOpcode()) {
6304   default: break;
6305   case X86::CMP64ri32:
6306   case X86::CMP64ri8:
6307   case X86::CMP32ri:
6308   case X86::CMP32ri8:
6309   case X86::CMP16ri:
6310   case X86::CMP16ri8:
6311   case X86::CMP8ri: {
6312     MachineOperand &MO0 = DataMI->getOperand(0);
6313     MachineOperand &MO1 = DataMI->getOperand(1);
6314     if (MO1.getImm() == 0) {
6315       unsigned NewOpc;
6316       switch (DataMI->getOpcode()) {
6317       default: llvm_unreachable("Unreachable!");
6318       case X86::CMP64ri8:
6319       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6320       case X86::CMP32ri8:
6321       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6322       case X86::CMP16ri8:
6323       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6324       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6325       }
6326       DataMI->setDesc(get(NewOpc));
6327       MO1.ChangeToRegister(MO0.getReg(), false);
6328     }
6329   }
6330   }
6331   NewMIs.push_back(DataMI);
6332 
6333   // Emit the store instruction.
6334   if (UnfoldStore) {
6335     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6336     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6337     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6338     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6339     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6340     DebugLoc DL;
6341     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6342     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6343       MIB.add(AddrOps[i]);
6344     MIB.addReg(Reg, RegState::Kill);
6345     MIB.setMemRefs(MMOs);
6346     NewMIs.push_back(MIB);
6347   }
6348 
6349   return true;
6350 }
6351 
6352 bool
6353 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6354                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6355   if (!N->isMachineOpcode())
6356     return false;
6357 
6358   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6359   if (I == nullptr)
6360     return false;
6361   unsigned Opc = I->DstOp;
6362   unsigned Index = I->Flags & TB_INDEX_MASK;
6363   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6364   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6365   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6366   const MCInstrDesc &MCID = get(Opc);
6367   MachineFunction &MF = DAG.getMachineFunction();
6368   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6369   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6370   unsigned NumDefs = MCID.NumDefs;
6371   std::vector<SDValue> AddrOps;
6372   std::vector<SDValue> BeforeOps;
6373   std::vector<SDValue> AfterOps;
6374   SDLoc dl(N);
6375   unsigned NumOps = N->getNumOperands();
6376   for (unsigned i = 0; i != NumOps-1; ++i) {
6377     SDValue Op = N->getOperand(i);
6378     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6379       AddrOps.push_back(Op);
6380     else if (i < Index-NumDefs)
6381       BeforeOps.push_back(Op);
6382     else if (i > Index-NumDefs)
6383       AfterOps.push_back(Op);
6384   }
6385   SDValue Chain = N->getOperand(NumOps-1);
6386   AddrOps.push_back(Chain);
6387 
6388   // Emit the load instruction.
6389   SDNode *Load = nullptr;
6390   if (FoldedLoad) {
6391     EVT VT = *TRI.legalclasstypes_begin(*RC);
6392     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6393     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6394         Subtarget.isUnalignedMem16Slow())
6395       // Do not introduce a slow unaligned load.
6396       return false;
6397     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6398     // memory access is slow above.
6399 
6400     unsigned Opc;
6401     if (FoldedBCast) {
6402       Opc = getBroadcastOpcode(I, RC, Subtarget);
6403     } else {
6404       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6405       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6406       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6407     }
6408 
6409     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6410     NewNodes.push_back(Load);
6411 
6412     // Preserve memory reference information.
6413     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6414   }
6415 
6416   // Emit the data processing instruction.
6417   std::vector<EVT> VTs;
6418   const TargetRegisterClass *DstRC = nullptr;
6419   if (MCID.getNumDefs() > 0) {
6420     DstRC = getRegClass(MCID, 0, &RI, MF);
6421     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6422   }
6423   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6424     EVT VT = N->getValueType(i);
6425     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6426       VTs.push_back(VT);
6427   }
6428   if (Load)
6429     BeforeOps.push_back(SDValue(Load, 0));
6430   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6431   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6432   switch (Opc) {
6433     default: break;
6434     case X86::CMP64ri32:
6435     case X86::CMP64ri8:
6436     case X86::CMP32ri:
6437     case X86::CMP32ri8:
6438     case X86::CMP16ri:
6439     case X86::CMP16ri8:
6440     case X86::CMP8ri:
6441       if (isNullConstant(BeforeOps[1])) {
6442         switch (Opc) {
6443           default: llvm_unreachable("Unreachable!");
6444           case X86::CMP64ri8:
6445           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6446           case X86::CMP32ri8:
6447           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6448           case X86::CMP16ri8:
6449           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6450           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6451         }
6452         BeforeOps[1] = BeforeOps[0];
6453       }
6454   }
6455   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6456   NewNodes.push_back(NewNode);
6457 
6458   // Emit the store instruction.
6459   if (FoldedStore) {
6460     AddrOps.pop_back();
6461     AddrOps.push_back(SDValue(NewNode, 0));
6462     AddrOps.push_back(Chain);
6463     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6464     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6465         Subtarget.isUnalignedMem16Slow())
6466       // Do not introduce a slow unaligned store.
6467       return false;
6468     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6469     // memory access is slow above.
6470     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6471     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6472     SDNode *Store =
6473         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6474                            dl, MVT::Other, AddrOps);
6475     NewNodes.push_back(Store);
6476 
6477     // Preserve memory reference information.
6478     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6479   }
6480 
6481   return true;
6482 }
6483 
6484 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6485                                       bool UnfoldLoad, bool UnfoldStore,
6486                                       unsigned *LoadRegIndex) const {
6487   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6488   if (I == nullptr)
6489     return 0;
6490   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6491   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6492   if (UnfoldLoad && !FoldedLoad)
6493     return 0;
6494   if (UnfoldStore && !FoldedStore)
6495     return 0;
6496   if (LoadRegIndex)
6497     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6498   return I->DstOp;
6499 }
6500 
6501 bool
6502 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6503                                      int64_t &Offset1, int64_t &Offset2) const {
6504   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6505     return false;
6506   unsigned Opc1 = Load1->getMachineOpcode();
6507   unsigned Opc2 = Load2->getMachineOpcode();
6508   switch (Opc1) {
6509   default: return false;
6510   case X86::MOV8rm:
6511   case X86::MOV16rm:
6512   case X86::MOV32rm:
6513   case X86::MOV64rm:
6514   case X86::LD_Fp32m:
6515   case X86::LD_Fp64m:
6516   case X86::LD_Fp80m:
6517   case X86::MOVSSrm:
6518   case X86::MOVSSrm_alt:
6519   case X86::MOVSDrm:
6520   case X86::MOVSDrm_alt:
6521   case X86::MMX_MOVD64rm:
6522   case X86::MMX_MOVQ64rm:
6523   case X86::MOVAPSrm:
6524   case X86::MOVUPSrm:
6525   case X86::MOVAPDrm:
6526   case X86::MOVUPDrm:
6527   case X86::MOVDQArm:
6528   case X86::MOVDQUrm:
6529   // AVX load instructions
6530   case X86::VMOVSSrm:
6531   case X86::VMOVSSrm_alt:
6532   case X86::VMOVSDrm:
6533   case X86::VMOVSDrm_alt:
6534   case X86::VMOVAPSrm:
6535   case X86::VMOVUPSrm:
6536   case X86::VMOVAPDrm:
6537   case X86::VMOVUPDrm:
6538   case X86::VMOVDQArm:
6539   case X86::VMOVDQUrm:
6540   case X86::VMOVAPSYrm:
6541   case X86::VMOVUPSYrm:
6542   case X86::VMOVAPDYrm:
6543   case X86::VMOVUPDYrm:
6544   case X86::VMOVDQAYrm:
6545   case X86::VMOVDQUYrm:
6546   // AVX512 load instructions
6547   case X86::VMOVSSZrm:
6548   case X86::VMOVSSZrm_alt:
6549   case X86::VMOVSDZrm:
6550   case X86::VMOVSDZrm_alt:
6551   case X86::VMOVAPSZ128rm:
6552   case X86::VMOVUPSZ128rm:
6553   case X86::VMOVAPSZ128rm_NOVLX:
6554   case X86::VMOVUPSZ128rm_NOVLX:
6555   case X86::VMOVAPDZ128rm:
6556   case X86::VMOVUPDZ128rm:
6557   case X86::VMOVDQU8Z128rm:
6558   case X86::VMOVDQU16Z128rm:
6559   case X86::VMOVDQA32Z128rm:
6560   case X86::VMOVDQU32Z128rm:
6561   case X86::VMOVDQA64Z128rm:
6562   case X86::VMOVDQU64Z128rm:
6563   case X86::VMOVAPSZ256rm:
6564   case X86::VMOVUPSZ256rm:
6565   case X86::VMOVAPSZ256rm_NOVLX:
6566   case X86::VMOVUPSZ256rm_NOVLX:
6567   case X86::VMOVAPDZ256rm:
6568   case X86::VMOVUPDZ256rm:
6569   case X86::VMOVDQU8Z256rm:
6570   case X86::VMOVDQU16Z256rm:
6571   case X86::VMOVDQA32Z256rm:
6572   case X86::VMOVDQU32Z256rm:
6573   case X86::VMOVDQA64Z256rm:
6574   case X86::VMOVDQU64Z256rm:
6575   case X86::VMOVAPSZrm:
6576   case X86::VMOVUPSZrm:
6577   case X86::VMOVAPDZrm:
6578   case X86::VMOVUPDZrm:
6579   case X86::VMOVDQU8Zrm:
6580   case X86::VMOVDQU16Zrm:
6581   case X86::VMOVDQA32Zrm:
6582   case X86::VMOVDQU32Zrm:
6583   case X86::VMOVDQA64Zrm:
6584   case X86::VMOVDQU64Zrm:
6585   case X86::KMOVBkm:
6586   case X86::KMOVWkm:
6587   case X86::KMOVDkm:
6588   case X86::KMOVQkm:
6589     break;
6590   }
6591   switch (Opc2) {
6592   default: return false;
6593   case X86::MOV8rm:
6594   case X86::MOV16rm:
6595   case X86::MOV32rm:
6596   case X86::MOV64rm:
6597   case X86::LD_Fp32m:
6598   case X86::LD_Fp64m:
6599   case X86::LD_Fp80m:
6600   case X86::MOVSSrm:
6601   case X86::MOVSSrm_alt:
6602   case X86::MOVSDrm:
6603   case X86::MOVSDrm_alt:
6604   case X86::MMX_MOVD64rm:
6605   case X86::MMX_MOVQ64rm:
6606   case X86::MOVAPSrm:
6607   case X86::MOVUPSrm:
6608   case X86::MOVAPDrm:
6609   case X86::MOVUPDrm:
6610   case X86::MOVDQArm:
6611   case X86::MOVDQUrm:
6612   // AVX load instructions
6613   case X86::VMOVSSrm:
6614   case X86::VMOVSSrm_alt:
6615   case X86::VMOVSDrm:
6616   case X86::VMOVSDrm_alt:
6617   case X86::VMOVAPSrm:
6618   case X86::VMOVUPSrm:
6619   case X86::VMOVAPDrm:
6620   case X86::VMOVUPDrm:
6621   case X86::VMOVDQArm:
6622   case X86::VMOVDQUrm:
6623   case X86::VMOVAPSYrm:
6624   case X86::VMOVUPSYrm:
6625   case X86::VMOVAPDYrm:
6626   case X86::VMOVUPDYrm:
6627   case X86::VMOVDQAYrm:
6628   case X86::VMOVDQUYrm:
6629   // AVX512 load instructions
6630   case X86::VMOVSSZrm:
6631   case X86::VMOVSSZrm_alt:
6632   case X86::VMOVSDZrm:
6633   case X86::VMOVSDZrm_alt:
6634   case X86::VMOVAPSZ128rm:
6635   case X86::VMOVUPSZ128rm:
6636   case X86::VMOVAPSZ128rm_NOVLX:
6637   case X86::VMOVUPSZ128rm_NOVLX:
6638   case X86::VMOVAPDZ128rm:
6639   case X86::VMOVUPDZ128rm:
6640   case X86::VMOVDQU8Z128rm:
6641   case X86::VMOVDQU16Z128rm:
6642   case X86::VMOVDQA32Z128rm:
6643   case X86::VMOVDQU32Z128rm:
6644   case X86::VMOVDQA64Z128rm:
6645   case X86::VMOVDQU64Z128rm:
6646   case X86::VMOVAPSZ256rm:
6647   case X86::VMOVUPSZ256rm:
6648   case X86::VMOVAPSZ256rm_NOVLX:
6649   case X86::VMOVUPSZ256rm_NOVLX:
6650   case X86::VMOVAPDZ256rm:
6651   case X86::VMOVUPDZ256rm:
6652   case X86::VMOVDQU8Z256rm:
6653   case X86::VMOVDQU16Z256rm:
6654   case X86::VMOVDQA32Z256rm:
6655   case X86::VMOVDQU32Z256rm:
6656   case X86::VMOVDQA64Z256rm:
6657   case X86::VMOVDQU64Z256rm:
6658   case X86::VMOVAPSZrm:
6659   case X86::VMOVUPSZrm:
6660   case X86::VMOVAPDZrm:
6661   case X86::VMOVUPDZrm:
6662   case X86::VMOVDQU8Zrm:
6663   case X86::VMOVDQU16Zrm:
6664   case X86::VMOVDQA32Zrm:
6665   case X86::VMOVDQU32Zrm:
6666   case X86::VMOVDQA64Zrm:
6667   case X86::VMOVDQU64Zrm:
6668   case X86::KMOVBkm:
6669   case X86::KMOVWkm:
6670   case X86::KMOVDkm:
6671   case X86::KMOVQkm:
6672     break;
6673   }
6674 
6675   // Lambda to check if both the loads have the same value for an operand index.
6676   auto HasSameOp = [&](int I) {
6677     return Load1->getOperand(I) == Load2->getOperand(I);
6678   };
6679 
6680   // All operands except the displacement should match.
6681   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6682       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6683     return false;
6684 
6685   // Chain Operand must be the same.
6686   if (!HasSameOp(5))
6687     return false;
6688 
6689   // Now let's examine if the displacements are constants.
6690   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6691   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6692   if (!Disp1 || !Disp2)
6693     return false;
6694 
6695   Offset1 = Disp1->getSExtValue();
6696   Offset2 = Disp2->getSExtValue();
6697   return true;
6698 }
6699 
6700 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6701                                            int64_t Offset1, int64_t Offset2,
6702                                            unsigned NumLoads) const {
6703   assert(Offset2 > Offset1);
6704   if ((Offset2 - Offset1) / 8 > 64)
6705     return false;
6706 
6707   unsigned Opc1 = Load1->getMachineOpcode();
6708   unsigned Opc2 = Load2->getMachineOpcode();
6709   if (Opc1 != Opc2)
6710     return false;  // FIXME: overly conservative?
6711 
6712   switch (Opc1) {
6713   default: break;
6714   case X86::LD_Fp32m:
6715   case X86::LD_Fp64m:
6716   case X86::LD_Fp80m:
6717   case X86::MMX_MOVD64rm:
6718   case X86::MMX_MOVQ64rm:
6719     return false;
6720   }
6721 
6722   EVT VT = Load1->getValueType(0);
6723   switch (VT.getSimpleVT().SimpleTy) {
6724   default:
6725     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6726     // have 16 of them to play with.
6727     if (Subtarget.is64Bit()) {
6728       if (NumLoads >= 3)
6729         return false;
6730     } else if (NumLoads) {
6731       return false;
6732     }
6733     break;
6734   case MVT::i8:
6735   case MVT::i16:
6736   case MVT::i32:
6737   case MVT::i64:
6738   case MVT::f32:
6739   case MVT::f64:
6740     if (NumLoads)
6741       return false;
6742     break;
6743   }
6744 
6745   return true;
6746 }
6747 
6748 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
6749                                         const MachineBasicBlock *MBB,
6750                                         const MachineFunction &MF) const {
6751 
6752   // ENDBR instructions should not be scheduled around.
6753   unsigned Opcode = MI.getOpcode();
6754   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32)
6755     return true;
6756 
6757   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
6758 }
6759 
6760 bool X86InstrInfo::
6761 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6762   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6763   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6764   Cond[0].setImm(GetOppositeBranchCondition(CC));
6765   return false;
6766 }
6767 
6768 bool X86InstrInfo::
6769 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6770   // FIXME: Return false for x87 stack register classes for now. We can't
6771   // allow any loads of these registers before FpGet_ST0_80.
6772   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6773            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6774            RC == &X86::RFP80RegClass);
6775 }
6776 
6777 /// Return a virtual register initialized with the
6778 /// the global base register value. Output instructions required to
6779 /// initialize the register in the function entry block, if necessary.
6780 ///
6781 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6782 ///
6783 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6784   assert((!Subtarget.is64Bit() ||
6785           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6786           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6787          "X86-64 PIC uses RIP relative addressing");
6788 
6789   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6790   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
6791   if (GlobalBaseReg != 0)
6792     return GlobalBaseReg;
6793 
6794   // Create the register. The code to initialize it is inserted
6795   // later, by the CGBR pass (below).
6796   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6797   GlobalBaseReg = RegInfo.createVirtualRegister(
6798       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6799   X86FI->setGlobalBaseReg(GlobalBaseReg);
6800   return GlobalBaseReg;
6801 }
6802 
6803 // These are the replaceable SSE instructions. Some of these have Int variants
6804 // that we don't include here. We don't want to replace instructions selected
6805 // by intrinsics.
6806 static const uint16_t ReplaceableInstrs[][3] = {
6807   //PackedSingle     PackedDouble    PackedInt
6808   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6809   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6810   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6811   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6812   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6813   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
6814   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
6815   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
6816   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
6817   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
6818   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
6819   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
6820   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6821   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6822   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6823   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6824   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6825   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6826   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6827   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6828   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6829   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
6830   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
6831   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
6832   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
6833   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
6834   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
6835   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
6836   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
6837   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
6838   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
6839   // AVX 128-bit support
6840   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6841   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6842   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6843   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6844   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6845   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
6846   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
6847   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
6848   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
6849   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
6850   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
6851   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
6852   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6853   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6854   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6855   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6856   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6857   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6858   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6859   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6860   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6861   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
6862   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
6863   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
6864   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
6865   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
6866   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
6867   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
6868   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
6869   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
6870   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
6871   // AVX 256-bit support
6872   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6873   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6874   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6875   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6876   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6877   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
6878   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
6879   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
6880   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
6881   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
6882   // AVX512 support
6883   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
6884   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6885   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6886   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
6887   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
6888   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
6889   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
6890   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
6891   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
6892   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
6893   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
6894   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
6895   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
6896   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
6897   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
6898   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
6899   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
6900   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
6901   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
6902   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
6903   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
6904   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
6905   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
6906   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
6907   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
6908   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
6909   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
6910   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
6911   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
6912   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
6913   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6914   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6915   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6916   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6917   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
6918   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
6919   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
6920   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
6921   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
6922   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
6923   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
6924   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
6925   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6926   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6927   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6928   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6929   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
6930   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
6931   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
6932   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
6933   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
6934   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
6935   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
6936   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
6937   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
6938   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
6939   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
6940   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
6941   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
6942   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
6943   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
6944   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
6945   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
6946   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
6947   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
6948   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
6949   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
6950   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
6951   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
6952   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
6953   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
6954   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
6955   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
6956   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
6957   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
6958   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
6959   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
6960   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
6961   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
6962   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
6963   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
6964   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
6965   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
6966   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
6967   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
6968   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
6969   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
6970   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
6971   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
6972   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
6973   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
6974   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
6975 };
6976 
6977 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6978   //PackedSingle       PackedDouble       PackedInt
6979   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6980   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6981   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6982   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6983   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6984   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6985   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6986   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6987   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6988   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6989   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6990   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6991   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
6992   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
6993   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6994   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6995   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6996   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6997   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
6998   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
6999   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7000   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7001   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7002   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7003   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7004   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7005   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7006   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7007   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7008   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7009   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7010 };
7011 
7012 static const uint16_t ReplaceableInstrsFP[][3] = {
7013   //PackedSingle         PackedDouble
7014   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7015   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7016   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7017   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7018   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7019   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7020   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7021   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7022   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7023 };
7024 
7025 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7026   //PackedSingle       PackedDouble       PackedInt
7027   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7028   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7029   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7030   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7031 };
7032 
7033 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7034   // Two integer columns for 64-bit and 32-bit elements.
7035   //PackedSingle        PackedDouble        PackedInt             PackedInt
7036   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7037   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7038   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7039   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7040   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7041   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7042   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7043   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7044   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7045   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7046   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7047   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7048   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7049   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7050   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7051 };
7052 
7053 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7054   // Two integer columns for 64-bit and 32-bit elements.
7055   //PackedSingle        PackedDouble        PackedInt           PackedInt
7056   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7057   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7058   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7059   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7060   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7061   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7062   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7063   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7064   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7065   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7066   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7067   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7068   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7069   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7070   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7071   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7072   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7073   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7074   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7075   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7076   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7077   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7078   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7079   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7080 };
7081 
7082 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7083   // Two integer columns for 64-bit and 32-bit elements.
7084   //PackedSingle          PackedDouble
7085   //PackedInt             PackedInt
7086   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7087     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7088   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7089     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7090   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7091     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7092   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7093     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7094   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7095     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7096   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7097     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7098   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7099     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7100   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7101     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7102   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7103     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7104   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7105     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7106   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7107     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7108   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7109     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7110   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7111     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7112   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7113     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7114   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7115     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7116   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7117     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7118   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7119     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7120   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7121     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7122   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7123     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7124   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7125     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7126   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7127     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7128   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7129     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7130   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7131     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7132   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7133     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7134   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7135     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7136   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7137     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7138   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7139     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7140   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7141     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7142   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7143     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7144   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7145     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7146   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7147     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7148   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7149     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7150   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7151     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7152   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7153     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7154   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7155     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7156   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7157     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7158   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7159     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7160   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7161     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7162   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7163     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7164   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7165     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7166   { X86::VORPSZrmk,       X86::VORPDZrmk,
7167     X86::VPORQZrmk,       X86::VPORDZrmk       },
7168   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7169     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7170   { X86::VORPSZrrk,       X86::VORPDZrrk,
7171     X86::VPORQZrrk,       X86::VPORDZrrk       },
7172   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7173     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7174   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7175     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7176   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7177     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7178   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7179     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7180   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7181     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7182   // Broadcast loads can be handled the same as masked operations to avoid
7183   // changing element size.
7184   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7185     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7186   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7187     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7188   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7189     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7190   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7191     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7192   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7193     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7194   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7195     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7196   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7197     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7198   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7199     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7200   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7201     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7202   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7203     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7204   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7205     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7206   { X86::VORPSZrmb,       X86::VORPDZrmb,
7207     X86::VPORQZrmb,       X86::VPORDZrmb       },
7208   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7209     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7210   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7211     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7212   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7213     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7214   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7215     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7216   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7217     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7218   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7219     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7220   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7221     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7222   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7223     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7224   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7225     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7226   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7227     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7228   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7229     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7230   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7231     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7232   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7233     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7234   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7235     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7236   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7237     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7238   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7239     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7240   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7241     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7242   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7243     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7244   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7245     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7246   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7247     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7248   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7249     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7250   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7251     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7252   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7253     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7254   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7255     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7256   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7257     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7258   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7259     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7260   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7261     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7262 };
7263 
7264 // NOTE: These should only be used by the custom domain methods.
7265 static const uint16_t ReplaceableBlendInstrs[][3] = {
7266   //PackedSingle             PackedDouble             PackedInt
7267   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7268   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7269   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7270   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7271   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7272   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7273 };
7274 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7275   //PackedSingle             PackedDouble             PackedInt
7276   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7277   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7278   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7279   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7280 };
7281 
7282 // Special table for changing EVEX logic instructions to VEX.
7283 // TODO: Should we run EVEX->VEX earlier?
7284 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7285   // Two integer columns for 64-bit and 32-bit elements.
7286   //PackedSingle     PackedDouble     PackedInt           PackedInt
7287   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7288   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7289   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7290   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7291   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7292   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7293   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7294   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7295   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7296   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7297   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7298   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7299   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7300   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7301   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7302   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7303 };
7304 
7305 // FIXME: Some shuffle and unpack instructions have equivalents in different
7306 // domains, but they require a bit more work than just switching opcodes.
7307 
7308 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7309                               ArrayRef<uint16_t[3]> Table) {
7310   for (const uint16_t (&Row)[3] : Table)
7311     if (Row[domain-1] == opcode)
7312       return Row;
7313   return nullptr;
7314 }
7315 
7316 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7317                                     ArrayRef<uint16_t[4]> Table) {
7318   // If this is the integer domain make sure to check both integer columns.
7319   for (const uint16_t (&Row)[4] : Table)
7320     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7321       return Row;
7322   return nullptr;
7323 }
7324 
7325 // Helper to attempt to widen/narrow blend masks.
7326 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7327                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7328   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7329          "Illegal blend mask scale");
7330   unsigned NewMask = 0;
7331 
7332   if ((OldWidth % NewWidth) == 0) {
7333     unsigned Scale = OldWidth / NewWidth;
7334     unsigned SubMask = (1u << Scale) - 1;
7335     for (unsigned i = 0; i != NewWidth; ++i) {
7336       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7337       if (Sub == SubMask)
7338         NewMask |= (1u << i);
7339       else if (Sub != 0x0)
7340         return false;
7341     }
7342   } else {
7343     unsigned Scale = NewWidth / OldWidth;
7344     unsigned SubMask = (1u << Scale) - 1;
7345     for (unsigned i = 0; i != OldWidth; ++i) {
7346       if (OldMask & (1 << i)) {
7347         NewMask |= (SubMask << (i * Scale));
7348       }
7349     }
7350   }
7351 
7352   if (pNewMask)
7353     *pNewMask = NewMask;
7354   return true;
7355 }
7356 
7357 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7358   unsigned Opcode = MI.getOpcode();
7359   unsigned NumOperands = MI.getDesc().getNumOperands();
7360 
7361   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7362     uint16_t validDomains = 0;
7363     if (MI.getOperand(NumOperands - 1).isImm()) {
7364       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7365       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7366         validDomains |= 0x2; // PackedSingle
7367       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7368         validDomains |= 0x4; // PackedDouble
7369       if (!Is256 || Subtarget.hasAVX2())
7370         validDomains |= 0x8; // PackedInt
7371     }
7372     return validDomains;
7373   };
7374 
7375   switch (Opcode) {
7376   case X86::BLENDPDrmi:
7377   case X86::BLENDPDrri:
7378   case X86::VBLENDPDrmi:
7379   case X86::VBLENDPDrri:
7380     return GetBlendDomains(2, false);
7381   case X86::VBLENDPDYrmi:
7382   case X86::VBLENDPDYrri:
7383     return GetBlendDomains(4, true);
7384   case X86::BLENDPSrmi:
7385   case X86::BLENDPSrri:
7386   case X86::VBLENDPSrmi:
7387   case X86::VBLENDPSrri:
7388   case X86::VPBLENDDrmi:
7389   case X86::VPBLENDDrri:
7390     return GetBlendDomains(4, false);
7391   case X86::VBLENDPSYrmi:
7392   case X86::VBLENDPSYrri:
7393   case X86::VPBLENDDYrmi:
7394   case X86::VPBLENDDYrri:
7395     return GetBlendDomains(8, true);
7396   case X86::PBLENDWrmi:
7397   case X86::PBLENDWrri:
7398   case X86::VPBLENDWrmi:
7399   case X86::VPBLENDWrri:
7400   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7401   case X86::VPBLENDWYrmi:
7402   case X86::VPBLENDWYrri:
7403     return GetBlendDomains(8, false);
7404   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7405   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7406   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7407   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7408   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7409   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7410   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7411   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7412   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7413   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7414   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7415   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7416   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7417   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7418   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7419   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7420     // If we don't have DQI see if we can still switch from an EVEX integer
7421     // instruction to a VEX floating point instruction.
7422     if (Subtarget.hasDQI())
7423       return 0;
7424 
7425     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7426       return 0;
7427     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7428       return 0;
7429     // Register forms will have 3 operands. Memory form will have more.
7430     if (NumOperands == 3 &&
7431         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7432       return 0;
7433 
7434     // All domains are valid.
7435     return 0xe;
7436   case X86::MOVHLPSrr:
7437     // We can swap domains when both inputs are the same register.
7438     // FIXME: This doesn't catch all the cases we would like. If the input
7439     // register isn't KILLed by the instruction, the two address instruction
7440     // pass puts a COPY on one input. The other input uses the original
7441     // register. This prevents the same physical register from being used by
7442     // both inputs.
7443     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7444         MI.getOperand(0).getSubReg() == 0 &&
7445         MI.getOperand(1).getSubReg() == 0 &&
7446         MI.getOperand(2).getSubReg() == 0)
7447       return 0x6;
7448     return 0;
7449   case X86::SHUFPDrri:
7450     return 0x6;
7451   }
7452   return 0;
7453 }
7454 
7455 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7456                                             unsigned Domain) const {
7457   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7458   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7459   assert(dom && "Not an SSE instruction");
7460 
7461   unsigned Opcode = MI.getOpcode();
7462   unsigned NumOperands = MI.getDesc().getNumOperands();
7463 
7464   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7465     if (MI.getOperand(NumOperands - 1).isImm()) {
7466       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7467       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7468       unsigned NewImm = Imm;
7469 
7470       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7471       if (!table)
7472         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7473 
7474       if (Domain == 1) { // PackedSingle
7475         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7476       } else if (Domain == 2) { // PackedDouble
7477         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7478       } else if (Domain == 3) { // PackedInt
7479         if (Subtarget.hasAVX2()) {
7480           // If we are already VPBLENDW use that, else use VPBLENDD.
7481           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7482             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7483             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7484           }
7485         } else {
7486           assert(!Is256 && "128-bit vector expected");
7487           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7488         }
7489       }
7490 
7491       assert(table && table[Domain - 1] && "Unknown domain op");
7492       MI.setDesc(get(table[Domain - 1]));
7493       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7494     }
7495     return true;
7496   };
7497 
7498   switch (Opcode) {
7499   case X86::BLENDPDrmi:
7500   case X86::BLENDPDrri:
7501   case X86::VBLENDPDrmi:
7502   case X86::VBLENDPDrri:
7503     return SetBlendDomain(2, false);
7504   case X86::VBLENDPDYrmi:
7505   case X86::VBLENDPDYrri:
7506     return SetBlendDomain(4, true);
7507   case X86::BLENDPSrmi:
7508   case X86::BLENDPSrri:
7509   case X86::VBLENDPSrmi:
7510   case X86::VBLENDPSrri:
7511   case X86::VPBLENDDrmi:
7512   case X86::VPBLENDDrri:
7513     return SetBlendDomain(4, false);
7514   case X86::VBLENDPSYrmi:
7515   case X86::VBLENDPSYrri:
7516   case X86::VPBLENDDYrmi:
7517   case X86::VPBLENDDYrri:
7518     return SetBlendDomain(8, true);
7519   case X86::PBLENDWrmi:
7520   case X86::PBLENDWrri:
7521   case X86::VPBLENDWrmi:
7522   case X86::VPBLENDWrri:
7523     return SetBlendDomain(8, false);
7524   case X86::VPBLENDWYrmi:
7525   case X86::VPBLENDWYrri:
7526     return SetBlendDomain(16, true);
7527   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7528   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7529   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7530   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7531   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7532   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7533   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7534   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7535   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7536   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7537   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7538   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7539   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7540   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7541   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7542   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7543     // Without DQI, convert EVEX instructions to VEX instructions.
7544     if (Subtarget.hasDQI())
7545       return false;
7546 
7547     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7548                                          ReplaceableCustomAVX512LogicInstrs);
7549     assert(table && "Instruction not found in table?");
7550     // Don't change integer Q instructions to D instructions and
7551     // use D intructions if we started with a PS instruction.
7552     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7553       Domain = 4;
7554     MI.setDesc(get(table[Domain - 1]));
7555     return true;
7556   }
7557   case X86::UNPCKHPDrr:
7558   case X86::MOVHLPSrr:
7559     // We just need to commute the instruction which will switch the domains.
7560     if (Domain != dom && Domain != 3 &&
7561         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7562         MI.getOperand(0).getSubReg() == 0 &&
7563         MI.getOperand(1).getSubReg() == 0 &&
7564         MI.getOperand(2).getSubReg() == 0) {
7565       commuteInstruction(MI, false);
7566       return true;
7567     }
7568     // We must always return true for MOVHLPSrr.
7569     if (Opcode == X86::MOVHLPSrr)
7570       return true;
7571     break;
7572   case X86::SHUFPDrri: {
7573     if (Domain == 1) {
7574       unsigned Imm = MI.getOperand(3).getImm();
7575       unsigned NewImm = 0x44;
7576       if (Imm & 1) NewImm |= 0x0a;
7577       if (Imm & 2) NewImm |= 0xa0;
7578       MI.getOperand(3).setImm(NewImm);
7579       MI.setDesc(get(X86::SHUFPSrri));
7580     }
7581     return true;
7582   }
7583   }
7584   return false;
7585 }
7586 
7587 std::pair<uint16_t, uint16_t>
7588 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7589   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7590   unsigned opcode = MI.getOpcode();
7591   uint16_t validDomains = 0;
7592   if (domain) {
7593     // Attempt to match for custom instructions.
7594     validDomains = getExecutionDomainCustom(MI);
7595     if (validDomains)
7596       return std::make_pair(domain, validDomains);
7597 
7598     if (lookup(opcode, domain, ReplaceableInstrs)) {
7599       validDomains = 0xe;
7600     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7601       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7602     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7603       validDomains = 0x6;
7604     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7605       // Insert/extract instructions should only effect domain if AVX2
7606       // is enabled.
7607       if (!Subtarget.hasAVX2())
7608         return std::make_pair(0, 0);
7609       validDomains = 0xe;
7610     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7611       validDomains = 0xe;
7612     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7613                                                   ReplaceableInstrsAVX512DQ)) {
7614       validDomains = 0xe;
7615     } else if (Subtarget.hasDQI()) {
7616       if (const uint16_t *table = lookupAVX512(opcode, domain,
7617                                              ReplaceableInstrsAVX512DQMasked)) {
7618         if (domain == 1 || (domain == 3 && table[3] == opcode))
7619           validDomains = 0xa;
7620         else
7621           validDomains = 0xc;
7622       }
7623     }
7624   }
7625   return std::make_pair(domain, validDomains);
7626 }
7627 
7628 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7629   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7630   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7631   assert(dom && "Not an SSE instruction");
7632 
7633   // Attempt to match for custom instructions.
7634   if (setExecutionDomainCustom(MI, Domain))
7635     return;
7636 
7637   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7638   if (!table) { // try the other table
7639     assert((Subtarget.hasAVX2() || Domain < 3) &&
7640            "256-bit vector operations only available in AVX2");
7641     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7642   }
7643   if (!table) { // try the FP table
7644     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7645     assert((!table || Domain < 3) &&
7646            "Can only select PackedSingle or PackedDouble");
7647   }
7648   if (!table) { // try the other table
7649     assert(Subtarget.hasAVX2() &&
7650            "256-bit insert/extract only available in AVX2");
7651     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7652   }
7653   if (!table) { // try the AVX512 table
7654     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7655     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7656     // Don't change integer Q instructions to D instructions.
7657     if (table && Domain == 3 && table[3] == MI.getOpcode())
7658       Domain = 4;
7659   }
7660   if (!table) { // try the AVX512DQ table
7661     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7662     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7663     // Don't change integer Q instructions to D instructions and
7664     // use D instructions if we started with a PS instruction.
7665     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7666       Domain = 4;
7667   }
7668   if (!table) { // try the AVX512DQMasked table
7669     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7670     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7671     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7672       Domain = 4;
7673   }
7674   assert(table && "Cannot change domain");
7675   MI.setDesc(get(table[Domain - 1]));
7676 }
7677 
7678 /// Return the noop instruction to use for a noop.
7679 void X86InstrInfo::getNoop(MCInst &NopInst) const {
7680   NopInst.setOpcode(X86::NOOP);
7681 }
7682 
7683 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7684   switch (opc) {
7685   default: return false;
7686   case X86::DIVPDrm:
7687   case X86::DIVPDrr:
7688   case X86::DIVPSrm:
7689   case X86::DIVPSrr:
7690   case X86::DIVSDrm:
7691   case X86::DIVSDrm_Int:
7692   case X86::DIVSDrr:
7693   case X86::DIVSDrr_Int:
7694   case X86::DIVSSrm:
7695   case X86::DIVSSrm_Int:
7696   case X86::DIVSSrr:
7697   case X86::DIVSSrr_Int:
7698   case X86::SQRTPDm:
7699   case X86::SQRTPDr:
7700   case X86::SQRTPSm:
7701   case X86::SQRTPSr:
7702   case X86::SQRTSDm:
7703   case X86::SQRTSDm_Int:
7704   case X86::SQRTSDr:
7705   case X86::SQRTSDr_Int:
7706   case X86::SQRTSSm:
7707   case X86::SQRTSSm_Int:
7708   case X86::SQRTSSr:
7709   case X86::SQRTSSr_Int:
7710   // AVX instructions with high latency
7711   case X86::VDIVPDrm:
7712   case X86::VDIVPDrr:
7713   case X86::VDIVPDYrm:
7714   case X86::VDIVPDYrr:
7715   case X86::VDIVPSrm:
7716   case X86::VDIVPSrr:
7717   case X86::VDIVPSYrm:
7718   case X86::VDIVPSYrr:
7719   case X86::VDIVSDrm:
7720   case X86::VDIVSDrm_Int:
7721   case X86::VDIVSDrr:
7722   case X86::VDIVSDrr_Int:
7723   case X86::VDIVSSrm:
7724   case X86::VDIVSSrm_Int:
7725   case X86::VDIVSSrr:
7726   case X86::VDIVSSrr_Int:
7727   case X86::VSQRTPDm:
7728   case X86::VSQRTPDr:
7729   case X86::VSQRTPDYm:
7730   case X86::VSQRTPDYr:
7731   case X86::VSQRTPSm:
7732   case X86::VSQRTPSr:
7733   case X86::VSQRTPSYm:
7734   case X86::VSQRTPSYr:
7735   case X86::VSQRTSDm:
7736   case X86::VSQRTSDm_Int:
7737   case X86::VSQRTSDr:
7738   case X86::VSQRTSDr_Int:
7739   case X86::VSQRTSSm:
7740   case X86::VSQRTSSm_Int:
7741   case X86::VSQRTSSr:
7742   case X86::VSQRTSSr_Int:
7743   // AVX512 instructions with high latency
7744   case X86::VDIVPDZ128rm:
7745   case X86::VDIVPDZ128rmb:
7746   case X86::VDIVPDZ128rmbk:
7747   case X86::VDIVPDZ128rmbkz:
7748   case X86::VDIVPDZ128rmk:
7749   case X86::VDIVPDZ128rmkz:
7750   case X86::VDIVPDZ128rr:
7751   case X86::VDIVPDZ128rrk:
7752   case X86::VDIVPDZ128rrkz:
7753   case X86::VDIVPDZ256rm:
7754   case X86::VDIVPDZ256rmb:
7755   case X86::VDIVPDZ256rmbk:
7756   case X86::VDIVPDZ256rmbkz:
7757   case X86::VDIVPDZ256rmk:
7758   case X86::VDIVPDZ256rmkz:
7759   case X86::VDIVPDZ256rr:
7760   case X86::VDIVPDZ256rrk:
7761   case X86::VDIVPDZ256rrkz:
7762   case X86::VDIVPDZrrb:
7763   case X86::VDIVPDZrrbk:
7764   case X86::VDIVPDZrrbkz:
7765   case X86::VDIVPDZrm:
7766   case X86::VDIVPDZrmb:
7767   case X86::VDIVPDZrmbk:
7768   case X86::VDIVPDZrmbkz:
7769   case X86::VDIVPDZrmk:
7770   case X86::VDIVPDZrmkz:
7771   case X86::VDIVPDZrr:
7772   case X86::VDIVPDZrrk:
7773   case X86::VDIVPDZrrkz:
7774   case X86::VDIVPSZ128rm:
7775   case X86::VDIVPSZ128rmb:
7776   case X86::VDIVPSZ128rmbk:
7777   case X86::VDIVPSZ128rmbkz:
7778   case X86::VDIVPSZ128rmk:
7779   case X86::VDIVPSZ128rmkz:
7780   case X86::VDIVPSZ128rr:
7781   case X86::VDIVPSZ128rrk:
7782   case X86::VDIVPSZ128rrkz:
7783   case X86::VDIVPSZ256rm:
7784   case X86::VDIVPSZ256rmb:
7785   case X86::VDIVPSZ256rmbk:
7786   case X86::VDIVPSZ256rmbkz:
7787   case X86::VDIVPSZ256rmk:
7788   case X86::VDIVPSZ256rmkz:
7789   case X86::VDIVPSZ256rr:
7790   case X86::VDIVPSZ256rrk:
7791   case X86::VDIVPSZ256rrkz:
7792   case X86::VDIVPSZrrb:
7793   case X86::VDIVPSZrrbk:
7794   case X86::VDIVPSZrrbkz:
7795   case X86::VDIVPSZrm:
7796   case X86::VDIVPSZrmb:
7797   case X86::VDIVPSZrmbk:
7798   case X86::VDIVPSZrmbkz:
7799   case X86::VDIVPSZrmk:
7800   case X86::VDIVPSZrmkz:
7801   case X86::VDIVPSZrr:
7802   case X86::VDIVPSZrrk:
7803   case X86::VDIVPSZrrkz:
7804   case X86::VDIVSDZrm:
7805   case X86::VDIVSDZrr:
7806   case X86::VDIVSDZrm_Int:
7807   case X86::VDIVSDZrm_Intk:
7808   case X86::VDIVSDZrm_Intkz:
7809   case X86::VDIVSDZrr_Int:
7810   case X86::VDIVSDZrr_Intk:
7811   case X86::VDIVSDZrr_Intkz:
7812   case X86::VDIVSDZrrb_Int:
7813   case X86::VDIVSDZrrb_Intk:
7814   case X86::VDIVSDZrrb_Intkz:
7815   case X86::VDIVSSZrm:
7816   case X86::VDIVSSZrr:
7817   case X86::VDIVSSZrm_Int:
7818   case X86::VDIVSSZrm_Intk:
7819   case X86::VDIVSSZrm_Intkz:
7820   case X86::VDIVSSZrr_Int:
7821   case X86::VDIVSSZrr_Intk:
7822   case X86::VDIVSSZrr_Intkz:
7823   case X86::VDIVSSZrrb_Int:
7824   case X86::VDIVSSZrrb_Intk:
7825   case X86::VDIVSSZrrb_Intkz:
7826   case X86::VSQRTPDZ128m:
7827   case X86::VSQRTPDZ128mb:
7828   case X86::VSQRTPDZ128mbk:
7829   case X86::VSQRTPDZ128mbkz:
7830   case X86::VSQRTPDZ128mk:
7831   case X86::VSQRTPDZ128mkz:
7832   case X86::VSQRTPDZ128r:
7833   case X86::VSQRTPDZ128rk:
7834   case X86::VSQRTPDZ128rkz:
7835   case X86::VSQRTPDZ256m:
7836   case X86::VSQRTPDZ256mb:
7837   case X86::VSQRTPDZ256mbk:
7838   case X86::VSQRTPDZ256mbkz:
7839   case X86::VSQRTPDZ256mk:
7840   case X86::VSQRTPDZ256mkz:
7841   case X86::VSQRTPDZ256r:
7842   case X86::VSQRTPDZ256rk:
7843   case X86::VSQRTPDZ256rkz:
7844   case X86::VSQRTPDZm:
7845   case X86::VSQRTPDZmb:
7846   case X86::VSQRTPDZmbk:
7847   case X86::VSQRTPDZmbkz:
7848   case X86::VSQRTPDZmk:
7849   case X86::VSQRTPDZmkz:
7850   case X86::VSQRTPDZr:
7851   case X86::VSQRTPDZrb:
7852   case X86::VSQRTPDZrbk:
7853   case X86::VSQRTPDZrbkz:
7854   case X86::VSQRTPDZrk:
7855   case X86::VSQRTPDZrkz:
7856   case X86::VSQRTPSZ128m:
7857   case X86::VSQRTPSZ128mb:
7858   case X86::VSQRTPSZ128mbk:
7859   case X86::VSQRTPSZ128mbkz:
7860   case X86::VSQRTPSZ128mk:
7861   case X86::VSQRTPSZ128mkz:
7862   case X86::VSQRTPSZ128r:
7863   case X86::VSQRTPSZ128rk:
7864   case X86::VSQRTPSZ128rkz:
7865   case X86::VSQRTPSZ256m:
7866   case X86::VSQRTPSZ256mb:
7867   case X86::VSQRTPSZ256mbk:
7868   case X86::VSQRTPSZ256mbkz:
7869   case X86::VSQRTPSZ256mk:
7870   case X86::VSQRTPSZ256mkz:
7871   case X86::VSQRTPSZ256r:
7872   case X86::VSQRTPSZ256rk:
7873   case X86::VSQRTPSZ256rkz:
7874   case X86::VSQRTPSZm:
7875   case X86::VSQRTPSZmb:
7876   case X86::VSQRTPSZmbk:
7877   case X86::VSQRTPSZmbkz:
7878   case X86::VSQRTPSZmk:
7879   case X86::VSQRTPSZmkz:
7880   case X86::VSQRTPSZr:
7881   case X86::VSQRTPSZrb:
7882   case X86::VSQRTPSZrbk:
7883   case X86::VSQRTPSZrbkz:
7884   case X86::VSQRTPSZrk:
7885   case X86::VSQRTPSZrkz:
7886   case X86::VSQRTSDZm:
7887   case X86::VSQRTSDZm_Int:
7888   case X86::VSQRTSDZm_Intk:
7889   case X86::VSQRTSDZm_Intkz:
7890   case X86::VSQRTSDZr:
7891   case X86::VSQRTSDZr_Int:
7892   case X86::VSQRTSDZr_Intk:
7893   case X86::VSQRTSDZr_Intkz:
7894   case X86::VSQRTSDZrb_Int:
7895   case X86::VSQRTSDZrb_Intk:
7896   case X86::VSQRTSDZrb_Intkz:
7897   case X86::VSQRTSSZm:
7898   case X86::VSQRTSSZm_Int:
7899   case X86::VSQRTSSZm_Intk:
7900   case X86::VSQRTSSZm_Intkz:
7901   case X86::VSQRTSSZr:
7902   case X86::VSQRTSSZr_Int:
7903   case X86::VSQRTSSZr_Intk:
7904   case X86::VSQRTSSZr_Intkz:
7905   case X86::VSQRTSSZrb_Int:
7906   case X86::VSQRTSSZrb_Intk:
7907   case X86::VSQRTSSZrb_Intkz:
7908 
7909   case X86::VGATHERDPDYrm:
7910   case X86::VGATHERDPDZ128rm:
7911   case X86::VGATHERDPDZ256rm:
7912   case X86::VGATHERDPDZrm:
7913   case X86::VGATHERDPDrm:
7914   case X86::VGATHERDPSYrm:
7915   case X86::VGATHERDPSZ128rm:
7916   case X86::VGATHERDPSZ256rm:
7917   case X86::VGATHERDPSZrm:
7918   case X86::VGATHERDPSrm:
7919   case X86::VGATHERPF0DPDm:
7920   case X86::VGATHERPF0DPSm:
7921   case X86::VGATHERPF0QPDm:
7922   case X86::VGATHERPF0QPSm:
7923   case X86::VGATHERPF1DPDm:
7924   case X86::VGATHERPF1DPSm:
7925   case X86::VGATHERPF1QPDm:
7926   case X86::VGATHERPF1QPSm:
7927   case X86::VGATHERQPDYrm:
7928   case X86::VGATHERQPDZ128rm:
7929   case X86::VGATHERQPDZ256rm:
7930   case X86::VGATHERQPDZrm:
7931   case X86::VGATHERQPDrm:
7932   case X86::VGATHERQPSYrm:
7933   case X86::VGATHERQPSZ128rm:
7934   case X86::VGATHERQPSZ256rm:
7935   case X86::VGATHERQPSZrm:
7936   case X86::VGATHERQPSrm:
7937   case X86::VPGATHERDDYrm:
7938   case X86::VPGATHERDDZ128rm:
7939   case X86::VPGATHERDDZ256rm:
7940   case X86::VPGATHERDDZrm:
7941   case X86::VPGATHERDDrm:
7942   case X86::VPGATHERDQYrm:
7943   case X86::VPGATHERDQZ128rm:
7944   case X86::VPGATHERDQZ256rm:
7945   case X86::VPGATHERDQZrm:
7946   case X86::VPGATHERDQrm:
7947   case X86::VPGATHERQDYrm:
7948   case X86::VPGATHERQDZ128rm:
7949   case X86::VPGATHERQDZ256rm:
7950   case X86::VPGATHERQDZrm:
7951   case X86::VPGATHERQDrm:
7952   case X86::VPGATHERQQYrm:
7953   case X86::VPGATHERQQZ128rm:
7954   case X86::VPGATHERQQZ256rm:
7955   case X86::VPGATHERQQZrm:
7956   case X86::VPGATHERQQrm:
7957   case X86::VSCATTERDPDZ128mr:
7958   case X86::VSCATTERDPDZ256mr:
7959   case X86::VSCATTERDPDZmr:
7960   case X86::VSCATTERDPSZ128mr:
7961   case X86::VSCATTERDPSZ256mr:
7962   case X86::VSCATTERDPSZmr:
7963   case X86::VSCATTERPF0DPDm:
7964   case X86::VSCATTERPF0DPSm:
7965   case X86::VSCATTERPF0QPDm:
7966   case X86::VSCATTERPF0QPSm:
7967   case X86::VSCATTERPF1DPDm:
7968   case X86::VSCATTERPF1DPSm:
7969   case X86::VSCATTERPF1QPDm:
7970   case X86::VSCATTERPF1QPSm:
7971   case X86::VSCATTERQPDZ128mr:
7972   case X86::VSCATTERQPDZ256mr:
7973   case X86::VSCATTERQPDZmr:
7974   case X86::VSCATTERQPSZ128mr:
7975   case X86::VSCATTERQPSZ256mr:
7976   case X86::VSCATTERQPSZmr:
7977   case X86::VPSCATTERDDZ128mr:
7978   case X86::VPSCATTERDDZ256mr:
7979   case X86::VPSCATTERDDZmr:
7980   case X86::VPSCATTERDQZ128mr:
7981   case X86::VPSCATTERDQZ256mr:
7982   case X86::VPSCATTERDQZmr:
7983   case X86::VPSCATTERQDZ128mr:
7984   case X86::VPSCATTERQDZ256mr:
7985   case X86::VPSCATTERQDZmr:
7986   case X86::VPSCATTERQQZ128mr:
7987   case X86::VPSCATTERQQZ256mr:
7988   case X86::VPSCATTERQQZmr:
7989     return true;
7990   }
7991 }
7992 
7993 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7994                                          const MachineRegisterInfo *MRI,
7995                                          const MachineInstr &DefMI,
7996                                          unsigned DefIdx,
7997                                          const MachineInstr &UseMI,
7998                                          unsigned UseIdx) const {
7999   return isHighLatencyDef(DefMI.getOpcode());
8000 }
8001 
8002 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8003                                            const MachineBasicBlock *MBB) const {
8004   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8005          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8006 
8007   // Integer binary math/logic instructions have a third source operand:
8008   // the EFLAGS register. That operand must be both defined here and never
8009   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8010   // not change anything because rearranging the operands could affect other
8011   // instructions that depend on the exact status flags (zero, sign, etc.)
8012   // that are set by using these particular operands with this operation.
8013   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8014   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8015          "Implicit def isn't flags?");
8016   if (FlagDef && !FlagDef->isDead())
8017     return false;
8018 
8019   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8020 }
8021 
8022 // TODO: There are many more machine instruction opcodes to match:
8023 //       1. Other data types (integer, vectors)
8024 //       2. Other math / logic operations (xor, or)
8025 //       3. Other forms of the same operation (intrinsics and other variants)
8026 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8027   switch (Inst.getOpcode()) {
8028   case X86::AND8rr:
8029   case X86::AND16rr:
8030   case X86::AND32rr:
8031   case X86::AND64rr:
8032   case X86::OR8rr:
8033   case X86::OR16rr:
8034   case X86::OR32rr:
8035   case X86::OR64rr:
8036   case X86::XOR8rr:
8037   case X86::XOR16rr:
8038   case X86::XOR32rr:
8039   case X86::XOR64rr:
8040   case X86::IMUL16rr:
8041   case X86::IMUL32rr:
8042   case X86::IMUL64rr:
8043   case X86::PANDrr:
8044   case X86::PORrr:
8045   case X86::PXORrr:
8046   case X86::ANDPDrr:
8047   case X86::ANDPSrr:
8048   case X86::ORPDrr:
8049   case X86::ORPSrr:
8050   case X86::XORPDrr:
8051   case X86::XORPSrr:
8052   case X86::PADDBrr:
8053   case X86::PADDWrr:
8054   case X86::PADDDrr:
8055   case X86::PADDQrr:
8056   case X86::PMULLWrr:
8057   case X86::PMULLDrr:
8058   case X86::PMAXSBrr:
8059   case X86::PMAXSDrr:
8060   case X86::PMAXSWrr:
8061   case X86::PMAXUBrr:
8062   case X86::PMAXUDrr:
8063   case X86::PMAXUWrr:
8064   case X86::PMINSBrr:
8065   case X86::PMINSDrr:
8066   case X86::PMINSWrr:
8067   case X86::PMINUBrr:
8068   case X86::PMINUDrr:
8069   case X86::PMINUWrr:
8070   case X86::VPANDrr:
8071   case X86::VPANDYrr:
8072   case X86::VPANDDZ128rr:
8073   case X86::VPANDDZ256rr:
8074   case X86::VPANDDZrr:
8075   case X86::VPANDQZ128rr:
8076   case X86::VPANDQZ256rr:
8077   case X86::VPANDQZrr:
8078   case X86::VPORrr:
8079   case X86::VPORYrr:
8080   case X86::VPORDZ128rr:
8081   case X86::VPORDZ256rr:
8082   case X86::VPORDZrr:
8083   case X86::VPORQZ128rr:
8084   case X86::VPORQZ256rr:
8085   case X86::VPORQZrr:
8086   case X86::VPXORrr:
8087   case X86::VPXORYrr:
8088   case X86::VPXORDZ128rr:
8089   case X86::VPXORDZ256rr:
8090   case X86::VPXORDZrr:
8091   case X86::VPXORQZ128rr:
8092   case X86::VPXORQZ256rr:
8093   case X86::VPXORQZrr:
8094   case X86::VANDPDrr:
8095   case X86::VANDPSrr:
8096   case X86::VANDPDYrr:
8097   case X86::VANDPSYrr:
8098   case X86::VANDPDZ128rr:
8099   case X86::VANDPSZ128rr:
8100   case X86::VANDPDZ256rr:
8101   case X86::VANDPSZ256rr:
8102   case X86::VANDPDZrr:
8103   case X86::VANDPSZrr:
8104   case X86::VORPDrr:
8105   case X86::VORPSrr:
8106   case X86::VORPDYrr:
8107   case X86::VORPSYrr:
8108   case X86::VORPDZ128rr:
8109   case X86::VORPSZ128rr:
8110   case X86::VORPDZ256rr:
8111   case X86::VORPSZ256rr:
8112   case X86::VORPDZrr:
8113   case X86::VORPSZrr:
8114   case X86::VXORPDrr:
8115   case X86::VXORPSrr:
8116   case X86::VXORPDYrr:
8117   case X86::VXORPSYrr:
8118   case X86::VXORPDZ128rr:
8119   case X86::VXORPSZ128rr:
8120   case X86::VXORPDZ256rr:
8121   case X86::VXORPSZ256rr:
8122   case X86::VXORPDZrr:
8123   case X86::VXORPSZrr:
8124   case X86::KADDBrr:
8125   case X86::KADDWrr:
8126   case X86::KADDDrr:
8127   case X86::KADDQrr:
8128   case X86::KANDBrr:
8129   case X86::KANDWrr:
8130   case X86::KANDDrr:
8131   case X86::KANDQrr:
8132   case X86::KORBrr:
8133   case X86::KORWrr:
8134   case X86::KORDrr:
8135   case X86::KORQrr:
8136   case X86::KXORBrr:
8137   case X86::KXORWrr:
8138   case X86::KXORDrr:
8139   case X86::KXORQrr:
8140   case X86::VPADDBrr:
8141   case X86::VPADDWrr:
8142   case X86::VPADDDrr:
8143   case X86::VPADDQrr:
8144   case X86::VPADDBYrr:
8145   case X86::VPADDWYrr:
8146   case X86::VPADDDYrr:
8147   case X86::VPADDQYrr:
8148   case X86::VPADDBZ128rr:
8149   case X86::VPADDWZ128rr:
8150   case X86::VPADDDZ128rr:
8151   case X86::VPADDQZ128rr:
8152   case X86::VPADDBZ256rr:
8153   case X86::VPADDWZ256rr:
8154   case X86::VPADDDZ256rr:
8155   case X86::VPADDQZ256rr:
8156   case X86::VPADDBZrr:
8157   case X86::VPADDWZrr:
8158   case X86::VPADDDZrr:
8159   case X86::VPADDQZrr:
8160   case X86::VPMULLWrr:
8161   case X86::VPMULLWYrr:
8162   case X86::VPMULLWZ128rr:
8163   case X86::VPMULLWZ256rr:
8164   case X86::VPMULLWZrr:
8165   case X86::VPMULLDrr:
8166   case X86::VPMULLDYrr:
8167   case X86::VPMULLDZ128rr:
8168   case X86::VPMULLDZ256rr:
8169   case X86::VPMULLDZrr:
8170   case X86::VPMULLQZ128rr:
8171   case X86::VPMULLQZ256rr:
8172   case X86::VPMULLQZrr:
8173   case X86::VPMAXSBrr:
8174   case X86::VPMAXSBYrr:
8175   case X86::VPMAXSBZ128rr:
8176   case X86::VPMAXSBZ256rr:
8177   case X86::VPMAXSBZrr:
8178   case X86::VPMAXSDrr:
8179   case X86::VPMAXSDYrr:
8180   case X86::VPMAXSDZ128rr:
8181   case X86::VPMAXSDZ256rr:
8182   case X86::VPMAXSDZrr:
8183   case X86::VPMAXSQZ128rr:
8184   case X86::VPMAXSQZ256rr:
8185   case X86::VPMAXSQZrr:
8186   case X86::VPMAXSWrr:
8187   case X86::VPMAXSWYrr:
8188   case X86::VPMAXSWZ128rr:
8189   case X86::VPMAXSWZ256rr:
8190   case X86::VPMAXSWZrr:
8191   case X86::VPMAXUBrr:
8192   case X86::VPMAXUBYrr:
8193   case X86::VPMAXUBZ128rr:
8194   case X86::VPMAXUBZ256rr:
8195   case X86::VPMAXUBZrr:
8196   case X86::VPMAXUDrr:
8197   case X86::VPMAXUDYrr:
8198   case X86::VPMAXUDZ128rr:
8199   case X86::VPMAXUDZ256rr:
8200   case X86::VPMAXUDZrr:
8201   case X86::VPMAXUQZ128rr:
8202   case X86::VPMAXUQZ256rr:
8203   case X86::VPMAXUQZrr:
8204   case X86::VPMAXUWrr:
8205   case X86::VPMAXUWYrr:
8206   case X86::VPMAXUWZ128rr:
8207   case X86::VPMAXUWZ256rr:
8208   case X86::VPMAXUWZrr:
8209   case X86::VPMINSBrr:
8210   case X86::VPMINSBYrr:
8211   case X86::VPMINSBZ128rr:
8212   case X86::VPMINSBZ256rr:
8213   case X86::VPMINSBZrr:
8214   case X86::VPMINSDrr:
8215   case X86::VPMINSDYrr:
8216   case X86::VPMINSDZ128rr:
8217   case X86::VPMINSDZ256rr:
8218   case X86::VPMINSDZrr:
8219   case X86::VPMINSQZ128rr:
8220   case X86::VPMINSQZ256rr:
8221   case X86::VPMINSQZrr:
8222   case X86::VPMINSWrr:
8223   case X86::VPMINSWYrr:
8224   case X86::VPMINSWZ128rr:
8225   case X86::VPMINSWZ256rr:
8226   case X86::VPMINSWZrr:
8227   case X86::VPMINUBrr:
8228   case X86::VPMINUBYrr:
8229   case X86::VPMINUBZ128rr:
8230   case X86::VPMINUBZ256rr:
8231   case X86::VPMINUBZrr:
8232   case X86::VPMINUDrr:
8233   case X86::VPMINUDYrr:
8234   case X86::VPMINUDZ128rr:
8235   case X86::VPMINUDZ256rr:
8236   case X86::VPMINUDZrr:
8237   case X86::VPMINUQZ128rr:
8238   case X86::VPMINUQZ256rr:
8239   case X86::VPMINUQZrr:
8240   case X86::VPMINUWrr:
8241   case X86::VPMINUWYrr:
8242   case X86::VPMINUWZ128rr:
8243   case X86::VPMINUWZ256rr:
8244   case X86::VPMINUWZrr:
8245   // Normal min/max instructions are not commutative because of NaN and signed
8246   // zero semantics, but these are. Thus, there's no need to check for global
8247   // relaxed math; the instructions themselves have the properties we need.
8248   case X86::MAXCPDrr:
8249   case X86::MAXCPSrr:
8250   case X86::MAXCSDrr:
8251   case X86::MAXCSSrr:
8252   case X86::MINCPDrr:
8253   case X86::MINCPSrr:
8254   case X86::MINCSDrr:
8255   case X86::MINCSSrr:
8256   case X86::VMAXCPDrr:
8257   case X86::VMAXCPSrr:
8258   case X86::VMAXCPDYrr:
8259   case X86::VMAXCPSYrr:
8260   case X86::VMAXCPDZ128rr:
8261   case X86::VMAXCPSZ128rr:
8262   case X86::VMAXCPDZ256rr:
8263   case X86::VMAXCPSZ256rr:
8264   case X86::VMAXCPDZrr:
8265   case X86::VMAXCPSZrr:
8266   case X86::VMAXCSDrr:
8267   case X86::VMAXCSSrr:
8268   case X86::VMAXCSDZrr:
8269   case X86::VMAXCSSZrr:
8270   case X86::VMINCPDrr:
8271   case X86::VMINCPSrr:
8272   case X86::VMINCPDYrr:
8273   case X86::VMINCPSYrr:
8274   case X86::VMINCPDZ128rr:
8275   case X86::VMINCPSZ128rr:
8276   case X86::VMINCPDZ256rr:
8277   case X86::VMINCPSZ256rr:
8278   case X86::VMINCPDZrr:
8279   case X86::VMINCPSZrr:
8280   case X86::VMINCSDrr:
8281   case X86::VMINCSSrr:
8282   case X86::VMINCSDZrr:
8283   case X86::VMINCSSZrr:
8284     return true;
8285   case X86::ADDPDrr:
8286   case X86::ADDPSrr:
8287   case X86::ADDSDrr:
8288   case X86::ADDSSrr:
8289   case X86::MULPDrr:
8290   case X86::MULPSrr:
8291   case X86::MULSDrr:
8292   case X86::MULSSrr:
8293   case X86::VADDPDrr:
8294   case X86::VADDPSrr:
8295   case X86::VADDPDYrr:
8296   case X86::VADDPSYrr:
8297   case X86::VADDPDZ128rr:
8298   case X86::VADDPSZ128rr:
8299   case X86::VADDPDZ256rr:
8300   case X86::VADDPSZ256rr:
8301   case X86::VADDPDZrr:
8302   case X86::VADDPSZrr:
8303   case X86::VADDSDrr:
8304   case X86::VADDSSrr:
8305   case X86::VADDSDZrr:
8306   case X86::VADDSSZrr:
8307   case X86::VMULPDrr:
8308   case X86::VMULPSrr:
8309   case X86::VMULPDYrr:
8310   case X86::VMULPSYrr:
8311   case X86::VMULPDZ128rr:
8312   case X86::VMULPSZ128rr:
8313   case X86::VMULPDZ256rr:
8314   case X86::VMULPSZ256rr:
8315   case X86::VMULPDZrr:
8316   case X86::VMULPSZrr:
8317   case X86::VMULSDrr:
8318   case X86::VMULSSrr:
8319   case X86::VMULSDZrr:
8320   case X86::VMULSSZrr:
8321     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8322            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8323   default:
8324     return false;
8325   }
8326 }
8327 
8328 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8329 /// register then, if possible, describe the value in terms of the source
8330 /// register.
8331 static Optional<ParamLoadedValue>
8332 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8333                          const TargetRegisterInfo *TRI) {
8334   Register DestReg = MI.getOperand(0).getReg();
8335   Register SrcReg = MI.getOperand(1).getReg();
8336 
8337   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8338 
8339   // If the described register is the destination, just return the source.
8340   if (DestReg == DescribedReg)
8341     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8342 
8343   // If the described register is a sub-register of the destination register,
8344   // then pick out the source register's corresponding sub-register.
8345   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8346     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8347     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8348   }
8349 
8350   // The remaining case to consider is when the described register is a
8351   // super-register of the destination register. MOV8rr and MOV16rr does not
8352   // write to any of the other bytes in the register, meaning that we'd have to
8353   // describe the value using a combination of the source register and the
8354   // non-overlapping bits in the described register, which is not currently
8355   // possible.
8356   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8357       !TRI->isSuperRegister(DestReg, DescribedReg))
8358     return None;
8359 
8360   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8361   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8362 }
8363 
8364 Optional<ParamLoadedValue>
8365 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8366   const MachineOperand *Op = nullptr;
8367   DIExpression *Expr = nullptr;
8368 
8369   const TargetRegisterInfo *TRI = &getRegisterInfo();
8370 
8371   switch (MI.getOpcode()) {
8372   case X86::LEA32r:
8373   case X86::LEA64r:
8374   case X86::LEA64_32r: {
8375     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8376     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8377       return None;
8378 
8379     // Operand 4 could be global address. For now we do not support
8380     // such situation.
8381     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8382       return None;
8383 
8384     const MachineOperand &Op1 = MI.getOperand(1);
8385     const MachineOperand &Op2 = MI.getOperand(3);
8386     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8387                            Register::isPhysicalRegister(Op2.getReg())));
8388 
8389     // Omit situations like:
8390     // %rsi = lea %rsi, 4, ...
8391     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8392         Op2.getReg() == MI.getOperand(0).getReg())
8393       return None;
8394     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8395               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8396              (Op2.getReg() != X86::NoRegister &&
8397               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8398       return None;
8399 
8400     int64_t Coef = MI.getOperand(2).getImm();
8401     int64_t Offset = MI.getOperand(4).getImm();
8402     SmallVector<uint64_t, 8> Ops;
8403 
8404     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8405       Op = &Op1;
8406     } else if (Op1.isFI())
8407       Op = &Op1;
8408 
8409     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8410       Ops.push_back(dwarf::DW_OP_constu);
8411       Ops.push_back(Coef + 1);
8412       Ops.push_back(dwarf::DW_OP_mul);
8413     } else {
8414       if (Op && Op2.getReg() != X86::NoRegister) {
8415         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8416         if (dwarfReg < 0)
8417           return None;
8418         else if (dwarfReg < 32) {
8419           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8420           Ops.push_back(0);
8421         } else {
8422           Ops.push_back(dwarf::DW_OP_bregx);
8423           Ops.push_back(dwarfReg);
8424           Ops.push_back(0);
8425         }
8426       } else if (!Op) {
8427         assert(Op2.getReg() != X86::NoRegister);
8428         Op = &Op2;
8429       }
8430 
8431       if (Coef > 1) {
8432         assert(Op2.getReg() != X86::NoRegister);
8433         Ops.push_back(dwarf::DW_OP_constu);
8434         Ops.push_back(Coef);
8435         Ops.push_back(dwarf::DW_OP_mul);
8436       }
8437 
8438       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8439           Op2.getReg() != X86::NoRegister) {
8440         Ops.push_back(dwarf::DW_OP_plus);
8441       }
8442     }
8443 
8444     DIExpression::appendOffset(Ops, Offset);
8445     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8446 
8447     return ParamLoadedValue(*Op, Expr);;
8448   }
8449   case X86::MOV8ri:
8450   case X86::MOV16ri:
8451     // TODO: Handle MOV8ri and MOV16ri.
8452     return None;
8453   case X86::MOV32ri:
8454   case X86::MOV64ri:
8455   case X86::MOV64ri32:
8456     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8457     // 64-bit parameters, so we need to consider super-registers.
8458     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8459       return None;
8460     return ParamLoadedValue(MI.getOperand(1), Expr);
8461   case X86::MOV8rr:
8462   case X86::MOV16rr:
8463   case X86::MOV32rr:
8464   case X86::MOV64rr:
8465     return describeMOVrrLoadedValue(MI, Reg, TRI);
8466   case X86::XOR32rr: {
8467     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8468     // super-registers.
8469     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8470       return None;
8471     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8472       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8473     return None;
8474   }
8475   case X86::MOVSX64rr32: {
8476     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8477     // cases like this:
8478     //
8479     //  $ebx = [...]
8480     //  $rdi = MOVSX64rr32 $ebx
8481     //  $esi = MOV32rr $edi
8482     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8483       return None;
8484 
8485     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8486 
8487     // If the described register is the destination register we need to
8488     // sign-extend the source register from 32 bits. The other case we handle
8489     // is when the described register is the 32-bit sub-register of the
8490     // destination register, in case we just need to return the source
8491     // register.
8492     if (Reg == MI.getOperand(0).getReg())
8493       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8494     else
8495       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8496              "Unhandled sub-register case for MOVSX64rr32");
8497 
8498     return ParamLoadedValue(MI.getOperand(1), Expr);
8499   }
8500   default:
8501     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8502     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8503   }
8504 }
8505 
8506 /// This is an architecture-specific helper function of reassociateOps.
8507 /// Set special operand attributes for new instructions after reassociation.
8508 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8509                                          MachineInstr &OldMI2,
8510                                          MachineInstr &NewMI1,
8511                                          MachineInstr &NewMI2) const {
8512   // Propagate FP flags from the original instructions.
8513   // But clear poison-generating flags because those may not be valid now.
8514   // TODO: There should be a helper function for copying only fast-math-flags.
8515   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8516   NewMI1.setFlags(IntersectedFlags);
8517   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8518   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8519   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8520 
8521   NewMI2.setFlags(IntersectedFlags);
8522   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8523   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8524   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8525 
8526   // Integer instructions may define an implicit EFLAGS dest register operand.
8527   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8528   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8529 
8530   assert(!OldFlagDef1 == !OldFlagDef2 &&
8531          "Unexpected instruction type for reassociation");
8532 
8533   if (!OldFlagDef1 || !OldFlagDef2)
8534     return;
8535 
8536   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8537          "Must have dead EFLAGS operand in reassociable instruction");
8538 
8539   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8540   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8541 
8542   assert(NewFlagDef1 && NewFlagDef2 &&
8543          "Unexpected operand in reassociable instruction");
8544 
8545   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8546   // of this pass or other passes. The EFLAGS operands must be dead in these new
8547   // instructions because the EFLAGS operands in the original instructions must
8548   // be dead in order for reassociation to occur.
8549   NewFlagDef1->setIsDead();
8550   NewFlagDef2->setIsDead();
8551 }
8552 
8553 std::pair<unsigned, unsigned>
8554 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8555   return std::make_pair(TF, 0u);
8556 }
8557 
8558 ArrayRef<std::pair<unsigned, const char *>>
8559 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8560   using namespace X86II;
8561   static const std::pair<unsigned, const char *> TargetFlags[] = {
8562       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8563       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8564       {MO_GOT, "x86-got"},
8565       {MO_GOTOFF, "x86-gotoff"},
8566       {MO_GOTPCREL, "x86-gotpcrel"},
8567       {MO_PLT, "x86-plt"},
8568       {MO_TLSGD, "x86-tlsgd"},
8569       {MO_TLSLD, "x86-tlsld"},
8570       {MO_TLSLDM, "x86-tlsldm"},
8571       {MO_GOTTPOFF, "x86-gottpoff"},
8572       {MO_INDNTPOFF, "x86-indntpoff"},
8573       {MO_TPOFF, "x86-tpoff"},
8574       {MO_DTPOFF, "x86-dtpoff"},
8575       {MO_NTPOFF, "x86-ntpoff"},
8576       {MO_GOTNTPOFF, "x86-gotntpoff"},
8577       {MO_DLLIMPORT, "x86-dllimport"},
8578       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8579       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8580       {MO_TLVP, "x86-tlvp"},
8581       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8582       {MO_SECREL, "x86-secrel"},
8583       {MO_COFFSTUB, "x86-coffstub"}};
8584   return makeArrayRef(TargetFlags);
8585 }
8586 
8587 namespace {
8588   /// Create Global Base Reg pass. This initializes the PIC
8589   /// global base register for x86-32.
8590   struct CGBR : public MachineFunctionPass {
8591     static char ID;
8592     CGBR() : MachineFunctionPass(ID) {}
8593 
8594     bool runOnMachineFunction(MachineFunction &MF) override {
8595       const X86TargetMachine *TM =
8596         static_cast<const X86TargetMachine *>(&MF.getTarget());
8597       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8598 
8599       // Don't do anything in the 64-bit small and kernel code models. They use
8600       // RIP-relative addressing for everything.
8601       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8602                             TM->getCodeModel() == CodeModel::Kernel))
8603         return false;
8604 
8605       // Only emit a global base reg in PIC mode.
8606       if (!TM->isPositionIndependent())
8607         return false;
8608 
8609       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8610       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
8611 
8612       // If we didn't need a GlobalBaseReg, don't insert code.
8613       if (GlobalBaseReg == 0)
8614         return false;
8615 
8616       // Insert the set of GlobalBaseReg into the first MBB of the function
8617       MachineBasicBlock &FirstMBB = MF.front();
8618       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8619       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8620       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8621       const X86InstrInfo *TII = STI.getInstrInfo();
8622 
8623       Register PC;
8624       if (STI.isPICStyleGOT())
8625         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8626       else
8627         PC = GlobalBaseReg;
8628 
8629       if (STI.is64Bit()) {
8630         if (TM->getCodeModel() == CodeModel::Medium) {
8631           // In the medium code model, use a RIP-relative LEA to materialize the
8632           // GOT.
8633           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8634               .addReg(X86::RIP)
8635               .addImm(0)
8636               .addReg(0)
8637               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8638               .addReg(0);
8639         } else if (TM->getCodeModel() == CodeModel::Large) {
8640           // In the large code model, we are aiming for this code, though the
8641           // register allocation may vary:
8642           //   leaq .LN$pb(%rip), %rax
8643           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8644           //   addq %rcx, %rax
8645           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8646           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8647           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8648           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8649               .addReg(X86::RIP)
8650               .addImm(0)
8651               .addReg(0)
8652               .addSym(MF.getPICBaseSymbol())
8653               .addReg(0);
8654           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8655           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8656               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8657                                  X86II::MO_PIC_BASE_OFFSET);
8658           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8659               .addReg(PBReg, RegState::Kill)
8660               .addReg(GOTReg, RegState::Kill);
8661         } else {
8662           llvm_unreachable("unexpected code model");
8663         }
8664       } else {
8665         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8666         // only used in JIT code emission as displacement to pc.
8667         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8668 
8669         // If we're using vanilla 'GOT' PIC style, we should use relative
8670         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8671         if (STI.isPICStyleGOT()) {
8672           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8673           // %some_register
8674           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8675               .addReg(PC)
8676               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8677                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8678         }
8679       }
8680 
8681       return true;
8682     }
8683 
8684     StringRef getPassName() const override {
8685       return "X86 PIC Global Base Reg Initialization";
8686     }
8687 
8688     void getAnalysisUsage(AnalysisUsage &AU) const override {
8689       AU.setPreservesCFG();
8690       MachineFunctionPass::getAnalysisUsage(AU);
8691     }
8692   };
8693 } // namespace
8694 
8695 char CGBR::ID = 0;
8696 FunctionPass*
8697 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8698 
8699 namespace {
8700   struct LDTLSCleanup : public MachineFunctionPass {
8701     static char ID;
8702     LDTLSCleanup() : MachineFunctionPass(ID) {}
8703 
8704     bool runOnMachineFunction(MachineFunction &MF) override {
8705       if (skipFunction(MF.getFunction()))
8706         return false;
8707 
8708       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8709       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8710         // No point folding accesses if there isn't at least two.
8711         return false;
8712       }
8713 
8714       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8715       return VisitNode(DT->getRootNode(), 0);
8716     }
8717 
8718     // Visit the dominator subtree rooted at Node in pre-order.
8719     // If TLSBaseAddrReg is non-null, then use that to replace any
8720     // TLS_base_addr instructions. Otherwise, create the register
8721     // when the first such instruction is seen, and then use it
8722     // as we encounter more instructions.
8723     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8724       MachineBasicBlock *BB = Node->getBlock();
8725       bool Changed = false;
8726 
8727       // Traverse the current block.
8728       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8729            ++I) {
8730         switch (I->getOpcode()) {
8731           case X86::TLS_base_addr32:
8732           case X86::TLS_base_addr64:
8733             if (TLSBaseAddrReg)
8734               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8735             else
8736               I = SetRegister(*I, &TLSBaseAddrReg);
8737             Changed = true;
8738             break;
8739           default:
8740             break;
8741         }
8742       }
8743 
8744       // Visit the children of this block in the dominator tree.
8745       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
8746         Changed |= VisitNode(*I, TLSBaseAddrReg);
8747       }
8748 
8749       return Changed;
8750     }
8751 
8752     // Replace the TLS_base_addr instruction I with a copy from
8753     // TLSBaseAddrReg, returning the new instruction.
8754     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8755                                          unsigned TLSBaseAddrReg) {
8756       MachineFunction *MF = I.getParent()->getParent();
8757       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8758       const bool is64Bit = STI.is64Bit();
8759       const X86InstrInfo *TII = STI.getInstrInfo();
8760 
8761       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8762       MachineInstr *Copy =
8763           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8764                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8765               .addReg(TLSBaseAddrReg);
8766 
8767       // Erase the TLS_base_addr instruction.
8768       I.eraseFromParent();
8769 
8770       return Copy;
8771     }
8772 
8773     // Create a virtual register in *TLSBaseAddrReg, and populate it by
8774     // inserting a copy instruction after I. Returns the new instruction.
8775     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8776       MachineFunction *MF = I.getParent()->getParent();
8777       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8778       const bool is64Bit = STI.is64Bit();
8779       const X86InstrInfo *TII = STI.getInstrInfo();
8780 
8781       // Create a virtual register for the TLS base address.
8782       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8783       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8784                                                       ? &X86::GR64RegClass
8785                                                       : &X86::GR32RegClass);
8786 
8787       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8788       MachineInstr *Next = I.getNextNode();
8789       MachineInstr *Copy =
8790           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8791                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8792               .addReg(is64Bit ? X86::RAX : X86::EAX);
8793 
8794       return Copy;
8795     }
8796 
8797     StringRef getPassName() const override {
8798       return "Local Dynamic TLS Access Clean-up";
8799     }
8800 
8801     void getAnalysisUsage(AnalysisUsage &AU) const override {
8802       AU.setPreservesCFG();
8803       AU.addRequired<MachineDominatorTree>();
8804       MachineFunctionPass::getAnalysisUsage(AU);
8805     }
8806   };
8807 }
8808 
8809 char LDTLSCleanup::ID = 0;
8810 FunctionPass*
8811 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8812 
8813 /// Constants defining how certain sequences should be outlined.
8814 ///
8815 /// \p MachineOutlinerDefault implies that the function is called with a call
8816 /// instruction, and a return must be emitted for the outlined function frame.
8817 ///
8818 /// That is,
8819 ///
8820 /// I1                                 OUTLINED_FUNCTION:
8821 /// I2 --> call OUTLINED_FUNCTION       I1
8822 /// I3                                  I2
8823 ///                                     I3
8824 ///                                     ret
8825 ///
8826 /// * Call construction overhead: 1 (call instruction)
8827 /// * Frame construction overhead: 1 (return instruction)
8828 ///
8829 /// \p MachineOutlinerTailCall implies that the function is being tail called.
8830 /// A jump is emitted instead of a call, and the return is already present in
8831 /// the outlined sequence. That is,
8832 ///
8833 /// I1                                 OUTLINED_FUNCTION:
8834 /// I2 --> jmp OUTLINED_FUNCTION       I1
8835 /// ret                                I2
8836 ///                                    ret
8837 ///
8838 /// * Call construction overhead: 1 (jump instruction)
8839 /// * Frame construction overhead: 0 (don't need to return)
8840 ///
8841 enum MachineOutlinerClass {
8842   MachineOutlinerDefault,
8843   MachineOutlinerTailCall
8844 };
8845 
8846 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
8847     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
8848   unsigned SequenceSize =
8849       std::accumulate(RepeatedSequenceLocs[0].front(),
8850                       std::next(RepeatedSequenceLocs[0].back()), 0,
8851                       [](unsigned Sum, const MachineInstr &MI) {
8852                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
8853                         // we can't tell the cost.  Just assume each instruction
8854                         // is one byte.
8855                         if (MI.isDebugInstr() || MI.isKill())
8856                           return Sum;
8857                         return Sum + 1;
8858                       });
8859 
8860   // We check to see if CFI Instructions are present, and if they are
8861   // we find the number of CFI Instructions in the candidates.
8862   unsigned CFICount = 0;
8863   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
8864   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
8865        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
8866     const std::vector<MCCFIInstruction> &CFIInstructions =
8867         RepeatedSequenceLocs[0].getMF()->getFrameInstructions();
8868     if (MBBI->isCFIInstruction()) {
8869       unsigned CFIIndex = MBBI->getOperand(0).getCFIIndex();
8870       MCCFIInstruction CFI = CFIInstructions[CFIIndex];
8871       CFICount++;
8872     }
8873     MBBI++;
8874   }
8875 
8876   // We compare the number of found CFI Instructions to  the number of CFI
8877   // instructions in the parent function for each candidate.  We must check this
8878   // since if we outline one of the CFI instructions in a function, we have to
8879   // outline them all for correctness. If we do not, the address offsets will be
8880   // incorrect between the two sections of the program.
8881   for (outliner::Candidate &C : RepeatedSequenceLocs) {
8882     std::vector<MCCFIInstruction> CFIInstructions =
8883         C.getMF()->getFrameInstructions();
8884 
8885     if (CFICount > 0 && CFICount != CFIInstructions.size())
8886       return outliner::OutlinedFunction();
8887   }
8888 
8889   // FIXME: Use real size in bytes for call and ret instructions.
8890   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
8891     for (outliner::Candidate &C : RepeatedSequenceLocs)
8892       C.setCallInfo(MachineOutlinerTailCall, 1);
8893 
8894     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
8895                                       0, // Number of bytes to emit frame.
8896                                       MachineOutlinerTailCall // Type of frame.
8897     );
8898   }
8899 
8900   if (CFICount > 0)
8901     return outliner::OutlinedFunction();
8902 
8903   for (outliner::Candidate &C : RepeatedSequenceLocs)
8904     C.setCallInfo(MachineOutlinerDefault, 1);
8905 
8906   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
8907                                     MachineOutlinerDefault);
8908 }
8909 
8910 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
8911                                            bool OutlineFromLinkOnceODRs) const {
8912   const Function &F = MF.getFunction();
8913 
8914   // Does the function use a red zone? If it does, then we can't risk messing
8915   // with the stack.
8916   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
8917     // It could have a red zone. If it does, then we don't want to touch it.
8918     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8919     if (!X86FI || X86FI->getUsesRedZone())
8920       return false;
8921   }
8922 
8923   // If we *don't* want to outline from things that could potentially be deduped
8924   // then return false.
8925   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
8926       return false;
8927 
8928   // This function is viable for outlining, so return true.
8929   return true;
8930 }
8931 
8932 outliner::InstrType
8933 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
8934   MachineInstr &MI = *MIT;
8935   // Don't allow debug values to impact outlining type.
8936   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
8937     return outliner::InstrType::Invisible;
8938 
8939   // At this point, KILL instructions don't really tell us much so we can go
8940   // ahead and skip over them.
8941   if (MI.isKill())
8942     return outliner::InstrType::Invisible;
8943 
8944   // Is this a tail call? If yes, we can outline as a tail call.
8945   if (isTailCall(MI))
8946     return outliner::InstrType::Legal;
8947 
8948   // Is this the terminator of a basic block?
8949   if (MI.isTerminator() || MI.isReturn()) {
8950 
8951     // Does its parent have any successors in its MachineFunction?
8952     if (MI.getParent()->succ_empty())
8953       return outliner::InstrType::Legal;
8954 
8955     // It does, so we can't tail call it.
8956     return outliner::InstrType::Illegal;
8957   }
8958 
8959   // Don't outline anything that modifies or reads from the stack pointer.
8960   //
8961   // FIXME: There are instructions which are being manually built without
8962   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
8963   // able to remove the extra checks once those are fixed up. For example,
8964   // sometimes we might get something like %rax = POP64r 1. This won't be
8965   // caught by modifiesRegister or readsRegister even though the instruction
8966   // really ought to be formed so that modifiesRegister/readsRegister would
8967   // catch it.
8968   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8969       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8970       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
8971     return outliner::InstrType::Illegal;
8972 
8973   // Outlined calls change the instruction pointer, so don't read from it.
8974   if (MI.readsRegister(X86::RIP, &RI) ||
8975       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8976       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
8977     return outliner::InstrType::Illegal;
8978 
8979   // Positions can't safely be outlined.
8980   if (MI.isPosition())
8981     return outliner::InstrType::Illegal;
8982 
8983   // Make sure none of the operands of this instruction do anything tricky.
8984   for (const MachineOperand &MOP : MI.operands())
8985     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
8986         MOP.isTargetIndex())
8987       return outliner::InstrType::Illegal;
8988 
8989   return outliner::InstrType::Legal;
8990 }
8991 
8992 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
8993                                           MachineFunction &MF,
8994                                           const outliner::OutlinedFunction &OF)
8995                                           const {
8996   // If we're a tail call, we already have a return, so don't do anything.
8997   if (OF.FrameConstructionID == MachineOutlinerTailCall)
8998     return;
8999 
9000   // We're a normal call, so our sequence doesn't have a return instruction.
9001   // Add it in.
9002   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
9003   MBB.insert(MBB.end(), retq);
9004 }
9005 
9006 MachineBasicBlock::iterator
9007 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9008                                  MachineBasicBlock::iterator &It,
9009                                  MachineFunction &MF,
9010                                  const outliner::Candidate &C) const {
9011   // Is it a tail call?
9012   if (C.CallConstructionID == MachineOutlinerTailCall) {
9013     // Yes, just insert a JMP.
9014     It = MBB.insert(It,
9015                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9016                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9017   } else {
9018     // No, insert a call.
9019     It = MBB.insert(It,
9020                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9021                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9022   }
9023 
9024   return It;
9025 }
9026 
9027 #define GET_INSTRINFO_HELPERS
9028 #include "X86GenInstrInfo.inc"
9029