1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86.h" 16 #include "X86InstrBuilder.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/LiveVariables.h" 22 #include "llvm/CodeGen/MachineConstantPool.h" 23 #include "llvm/CodeGen/MachineDominators.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/StackMaps.h" 28 #include "llvm/IR/DerivedTypes.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/LLVMContext.h" 31 #include "llvm/MC/MCAsmInfo.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCInst.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetOptions.h" 39 #include <limits> 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "x86-instr-info" 44 45 #define GET_INSTRINFO_CTOR_DTOR 46 #include "X86GenInstrInfo.inc" 47 48 static cl::opt<bool> 49 NoFusing("disable-spill-fusing", 50 cl::desc("Disable fusing of spill code into instructions")); 51 static cl::opt<bool> 52 PrintFailedFusing("print-failed-fuse-candidates", 53 cl::desc("Print instructions that the allocator wants to" 54 " fuse, but the X86 backend currently can't"), 55 cl::Hidden); 56 static cl::opt<bool> 57 ReMatPICStubLoad("remat-pic-stub-load", 58 cl::desc("Re-materialize load from stub in PIC mode"), 59 cl::init(false), cl::Hidden); 60 61 enum { 62 // Select which memory operand is being unfolded. 63 // (stored in bits 0 - 3) 64 TB_INDEX_0 = 0, 65 TB_INDEX_1 = 1, 66 TB_INDEX_2 = 2, 67 TB_INDEX_3 = 3, 68 TB_INDEX_4 = 4, 69 TB_INDEX_MASK = 0xf, 70 71 // Do not insert the reverse map (MemOp -> RegOp) into the table. 72 // This may be needed because there is a many -> one mapping. 73 TB_NO_REVERSE = 1 << 4, 74 75 // Do not insert the forward map (RegOp -> MemOp) into the table. 76 // This is needed for Native Client, which prohibits branch 77 // instructions from using a memory operand. 78 TB_NO_FORWARD = 1 << 5, 79 80 TB_FOLDED_LOAD = 1 << 6, 81 TB_FOLDED_STORE = 1 << 7, 82 83 // Minimum alignment required for load/store. 84 // Used for RegOp->MemOp conversion. 85 // (stored in bits 8 - 15) 86 TB_ALIGN_SHIFT = 8, 87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, 91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 92 }; 93 94 struct X86MemoryFoldTableEntry { 95 uint16_t RegOp; 96 uint16_t MemOp; 97 uint16_t Flags; 98 }; 99 100 // Pin the vtable to this file. 101 void X86InstrInfo::anchor() {} 102 103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI) 104 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 105 : X86::ADJCALLSTACKDOWN32), 106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 107 : X86::ADJCALLSTACKUP32), 108 X86::CATCHRET), 109 Subtarget(STI), RI(STI.getTargetTriple()) { 110 111 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = { 112 { X86::ADC32ri, X86::ADC32mi, 0 }, 113 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 114 { X86::ADC32rr, X86::ADC32mr, 0 }, 115 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 116 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 117 { X86::ADC64rr, X86::ADC64mr, 0 }, 118 { X86::ADD16ri, X86::ADD16mi, 0 }, 119 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 120 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 121 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 122 { X86::ADD16rr, X86::ADD16mr, 0 }, 123 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 124 { X86::ADD32ri, X86::ADD32mi, 0 }, 125 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 126 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 127 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 128 { X86::ADD32rr, X86::ADD32mr, 0 }, 129 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 130 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 131 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 132 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 133 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 134 { X86::ADD64rr, X86::ADD64mr, 0 }, 135 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 136 { X86::ADD8ri, X86::ADD8mi, 0 }, 137 { X86::ADD8rr, X86::ADD8mr, 0 }, 138 { X86::AND16ri, X86::AND16mi, 0 }, 139 { X86::AND16ri8, X86::AND16mi8, 0 }, 140 { X86::AND16rr, X86::AND16mr, 0 }, 141 { X86::AND32ri, X86::AND32mi, 0 }, 142 { X86::AND32ri8, X86::AND32mi8, 0 }, 143 { X86::AND32rr, X86::AND32mr, 0 }, 144 { X86::AND64ri32, X86::AND64mi32, 0 }, 145 { X86::AND64ri8, X86::AND64mi8, 0 }, 146 { X86::AND64rr, X86::AND64mr, 0 }, 147 { X86::AND8ri, X86::AND8mi, 0 }, 148 { X86::AND8rr, X86::AND8mr, 0 }, 149 { X86::DEC16r, X86::DEC16m, 0 }, 150 { X86::DEC32r, X86::DEC32m, 0 }, 151 { X86::DEC64r, X86::DEC64m, 0 }, 152 { X86::DEC8r, X86::DEC8m, 0 }, 153 { X86::INC16r, X86::INC16m, 0 }, 154 { X86::INC32r, X86::INC32m, 0 }, 155 { X86::INC64r, X86::INC64m, 0 }, 156 { X86::INC8r, X86::INC8m, 0 }, 157 { X86::NEG16r, X86::NEG16m, 0 }, 158 { X86::NEG32r, X86::NEG32m, 0 }, 159 { X86::NEG64r, X86::NEG64m, 0 }, 160 { X86::NEG8r, X86::NEG8m, 0 }, 161 { X86::NOT16r, X86::NOT16m, 0 }, 162 { X86::NOT32r, X86::NOT32m, 0 }, 163 { X86::NOT64r, X86::NOT64m, 0 }, 164 { X86::NOT8r, X86::NOT8m, 0 }, 165 { X86::OR16ri, X86::OR16mi, 0 }, 166 { X86::OR16ri8, X86::OR16mi8, 0 }, 167 { X86::OR16rr, X86::OR16mr, 0 }, 168 { X86::OR32ri, X86::OR32mi, 0 }, 169 { X86::OR32ri8, X86::OR32mi8, 0 }, 170 { X86::OR32rr, X86::OR32mr, 0 }, 171 { X86::OR64ri32, X86::OR64mi32, 0 }, 172 { X86::OR64ri8, X86::OR64mi8, 0 }, 173 { X86::OR64rr, X86::OR64mr, 0 }, 174 { X86::OR8ri, X86::OR8mi, 0 }, 175 { X86::OR8rr, X86::OR8mr, 0 }, 176 { X86::ROL16r1, X86::ROL16m1, 0 }, 177 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 178 { X86::ROL16ri, X86::ROL16mi, 0 }, 179 { X86::ROL32r1, X86::ROL32m1, 0 }, 180 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 181 { X86::ROL32ri, X86::ROL32mi, 0 }, 182 { X86::ROL64r1, X86::ROL64m1, 0 }, 183 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 184 { X86::ROL64ri, X86::ROL64mi, 0 }, 185 { X86::ROL8r1, X86::ROL8m1, 0 }, 186 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 187 { X86::ROL8ri, X86::ROL8mi, 0 }, 188 { X86::ROR16r1, X86::ROR16m1, 0 }, 189 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 190 { X86::ROR16ri, X86::ROR16mi, 0 }, 191 { X86::ROR32r1, X86::ROR32m1, 0 }, 192 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 193 { X86::ROR32ri, X86::ROR32mi, 0 }, 194 { X86::ROR64r1, X86::ROR64m1, 0 }, 195 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 196 { X86::ROR64ri, X86::ROR64mi, 0 }, 197 { X86::ROR8r1, X86::ROR8m1, 0 }, 198 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 199 { X86::ROR8ri, X86::ROR8mi, 0 }, 200 { X86::SAR16r1, X86::SAR16m1, 0 }, 201 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 202 { X86::SAR16ri, X86::SAR16mi, 0 }, 203 { X86::SAR32r1, X86::SAR32m1, 0 }, 204 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 205 { X86::SAR32ri, X86::SAR32mi, 0 }, 206 { X86::SAR64r1, X86::SAR64m1, 0 }, 207 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 208 { X86::SAR64ri, X86::SAR64mi, 0 }, 209 { X86::SAR8r1, X86::SAR8m1, 0 }, 210 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 211 { X86::SAR8ri, X86::SAR8mi, 0 }, 212 { X86::SBB32ri, X86::SBB32mi, 0 }, 213 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 214 { X86::SBB32rr, X86::SBB32mr, 0 }, 215 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 216 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 217 { X86::SBB64rr, X86::SBB64mr, 0 }, 218 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 219 { X86::SHL16ri, X86::SHL16mi, 0 }, 220 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 221 { X86::SHL32ri, X86::SHL32mi, 0 }, 222 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 223 { X86::SHL64ri, X86::SHL64mi, 0 }, 224 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 225 { X86::SHL8ri, X86::SHL8mi, 0 }, 226 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 227 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 228 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 229 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 230 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 231 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 232 { X86::SHR16r1, X86::SHR16m1, 0 }, 233 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 234 { X86::SHR16ri, X86::SHR16mi, 0 }, 235 { X86::SHR32r1, X86::SHR32m1, 0 }, 236 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 237 { X86::SHR32ri, X86::SHR32mi, 0 }, 238 { X86::SHR64r1, X86::SHR64m1, 0 }, 239 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 240 { X86::SHR64ri, X86::SHR64mi, 0 }, 241 { X86::SHR8r1, X86::SHR8m1, 0 }, 242 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 243 { X86::SHR8ri, X86::SHR8mi, 0 }, 244 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 245 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 246 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 247 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 248 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 249 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 250 { X86::SUB16ri, X86::SUB16mi, 0 }, 251 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 252 { X86::SUB16rr, X86::SUB16mr, 0 }, 253 { X86::SUB32ri, X86::SUB32mi, 0 }, 254 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 255 { X86::SUB32rr, X86::SUB32mr, 0 }, 256 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 257 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 258 { X86::SUB64rr, X86::SUB64mr, 0 }, 259 { X86::SUB8ri, X86::SUB8mi, 0 }, 260 { X86::SUB8rr, X86::SUB8mr, 0 }, 261 { X86::XOR16ri, X86::XOR16mi, 0 }, 262 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 263 { X86::XOR16rr, X86::XOR16mr, 0 }, 264 { X86::XOR32ri, X86::XOR32mi, 0 }, 265 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 266 { X86::XOR32rr, X86::XOR32mr, 0 }, 267 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 268 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 269 { X86::XOR64rr, X86::XOR64mr, 0 }, 270 { X86::XOR8ri, X86::XOR8mi, 0 }, 271 { X86::XOR8rr, X86::XOR8mr, 0 } 272 }; 273 274 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) { 275 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 276 Entry.RegOp, Entry.MemOp, 277 // Index 0, folded load and store, no alignment requirement. 278 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 279 } 280 281 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = { 282 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 283 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 284 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 285 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 286 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 287 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 288 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 289 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 290 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 291 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 292 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 293 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 294 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 295 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 296 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 297 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 298 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 299 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 300 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 301 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 302 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE }, 336 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE }, 337 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD }, 338 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD }, 339 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD }, 340 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 341 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 342 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 343 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 344 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 345 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 346 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 347 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 348 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 349 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 350 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 351 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 352 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 353 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 354 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 355 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 356 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 357 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 358 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD }, 359 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 360 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 361 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 362 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 363 364 // AVX 128-bit versions of foldable instructions 365 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 366 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 367 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 368 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 369 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 370 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 371 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 372 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 373 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 374 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 375 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 376 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE }, 377 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE }, 378 379 // AVX 256-bit foldable instructions 380 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 381 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 382 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 383 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 384 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 385 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }, 386 387 // AVX-512 foldable instructions 388 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }, 389 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 390 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 391 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 392 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 393 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE }, 394 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE }, 395 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE }, 396 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE }, 397 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE }, 398 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE }, 399 400 // AVX-512 foldable instructions (256-bit versions) 401 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 402 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 403 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 404 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 405 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE }, 406 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE }, 407 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE }, 408 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE }, 409 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE }, 410 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE }, 411 412 // AVX-512 foldable instructions (128-bit versions) 413 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 414 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 415 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 416 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 417 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE }, 418 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE }, 419 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE }, 420 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE }, 421 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE }, 422 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE }, 423 424 // F16C foldable instructions 425 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE }, 426 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE } 427 }; 428 429 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) { 430 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 431 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags); 432 } 433 434 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = { 435 { X86::BSF16rr, X86::BSF16rm, 0 }, 436 { X86::BSF32rr, X86::BSF32rm, 0 }, 437 { X86::BSF64rr, X86::BSF64rm, 0 }, 438 { X86::BSR16rr, X86::BSR16rm, 0 }, 439 { X86::BSR32rr, X86::BSR32rm, 0 }, 440 { X86::BSR64rr, X86::BSR64rm, 0 }, 441 { X86::CMP16rr, X86::CMP16rm, 0 }, 442 { X86::CMP32rr, X86::CMP32rm, 0 }, 443 { X86::CMP64rr, X86::CMP64rm, 0 }, 444 { X86::CMP8rr, X86::CMP8rm, 0 }, 445 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 446 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 447 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 448 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 449 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 450 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 451 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 452 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 453 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 454 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 455 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 456 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 457 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 458 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 459 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 460 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 461 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 462 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 463 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 464 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 465 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 466 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 467 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 }, 468 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 }, 469 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 }, 470 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 }, 471 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 }, 472 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 }, 473 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 474 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 475 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 476 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 477 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 478 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 479 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 480 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 481 { X86::MOV16rr, X86::MOV16rm, 0 }, 482 { X86::MOV32rr, X86::MOV32rm, 0 }, 483 { X86::MOV64rr, X86::MOV64rm, 0 }, 484 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 485 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 486 { X86::MOV8rr, X86::MOV8rm, 0 }, 487 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 488 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 489 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 490 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 491 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 492 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 493 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 494 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 495 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 496 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 497 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 498 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 499 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 500 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 501 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 502 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 503 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 504 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 505 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 506 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 507 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 508 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 509 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 510 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 511 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 }, 512 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 }, 513 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 }, 514 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 }, 515 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 }, 516 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 }, 517 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 }, 518 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 }, 519 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 }, 520 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 }, 521 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 }, 522 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 }, 523 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 }, 524 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 }, 525 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 }, 526 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 }, 527 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 }, 528 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 529 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 530 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 531 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 }, 532 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 533 { X86::RCPSSr, X86::RCPSSm, 0 }, 534 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 }, 535 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 }, 536 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 }, 537 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 538 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 539 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 540 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 541 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 542 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 543 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 544 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 545 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 546 { X86::TEST16rr, X86::TEST16rm, 0 }, 547 { X86::TEST32rr, X86::TEST32rm, 0 }, 548 { X86::TEST64rr, X86::TEST64rm, 0 }, 549 { X86::TEST8rr, X86::TEST8rm, 0 }, 550 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 551 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 552 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 553 554 // MMX version of foldable instructions 555 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 }, 556 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 }, 557 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 }, 558 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 }, 559 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 }, 560 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 }, 561 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 }, 562 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 }, 563 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 }, 564 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 }, 565 566 // 3DNow! version of foldable instructions 567 { X86::PF2IDrr, X86::PF2IDrm, 0 }, 568 { X86::PF2IWrr, X86::PF2IWrm, 0 }, 569 { X86::PFRCPrr, X86::PFRCPrm, 0 }, 570 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 }, 571 { X86::PI2FDrr, X86::PI2FDrm, 0 }, 572 { X86::PI2FWrr, X86::PI2FWrm, 0 }, 573 { X86::PSWAPDrr, X86::PSWAPDrm, 0 }, 574 575 // AVX 128-bit versions of foldable instructions 576 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 577 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 578 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 579 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 580 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 581 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 582 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 583 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 584 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 585 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 586 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 587 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 588 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 589 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 590 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 591 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 592 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 }, 593 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 }, 594 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 }, 595 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 }, 596 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 }, 597 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 }, 598 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, 599 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 600 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 601 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 602 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 603 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 604 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 605 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 606 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 607 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 608 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 }, 609 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 }, 610 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 611 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 612 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 613 { X86::VPABSBrr128, X86::VPABSBrm128, 0 }, 614 { X86::VPABSDrr128, X86::VPABSDrm128, 0 }, 615 { X86::VPABSWrr128, X86::VPABSWrm128, 0 }, 616 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 }, 617 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 }, 618 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 }, 619 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 }, 620 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 }, 621 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 622 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 623 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 }, 624 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 }, 625 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 }, 626 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 }, 627 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 }, 628 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 }, 629 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 }, 630 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 }, 631 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 }, 632 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 }, 633 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 }, 634 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 }, 635 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 636 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 637 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 638 { X86::VPTESTrr, X86::VPTESTrm, 0 }, 639 { X86::VRCPPSr, X86::VRCPPSm, 0 }, 640 { X86::VROUNDPDr, X86::VROUNDPDm, 0 }, 641 { X86::VROUNDPSr, X86::VROUNDPSm, 0 }, 642 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 643 { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 644 { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 645 { X86::VTESTPDrr, X86::VTESTPDrm, 0 }, 646 { X86::VTESTPSrr, X86::VTESTPSrm, 0 }, 647 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 648 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 649 650 // AVX 256-bit foldable instructions 651 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 }, 652 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 }, 653 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 }, 654 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 }, 655 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 }, 656 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 }, 657 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 }, 658 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 }, 659 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 660 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 661 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 }, 662 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 663 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 }, 664 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 }, 665 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 666 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 667 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 668 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 669 { X86::VPTESTYrr, X86::VPTESTYrm, 0 }, 670 { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 671 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 }, 672 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 }, 673 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 674 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 675 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 676 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 }, 677 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 }, 678 679 // AVX2 foldable instructions 680 681 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the 682 // VBROADCASTS{SD}rm memory instructions were available from AVX1. 683 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction 684 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions 685 // so they don't need an equivalent limitation. 686 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 687 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 688 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 689 { X86::VPABSBrr256, X86::VPABSBrm256, 0 }, 690 { X86::VPABSDrr256, X86::VPABSDrm256, 0 }, 691 { X86::VPABSWrr256, X86::VPABSWrm256, 0 }, 692 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 }, 693 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 }, 694 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 }, 695 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 }, 696 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 }, 697 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 }, 698 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 }, 699 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 }, 700 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 701 { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 702 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 }, 703 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 }, 704 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 }, 705 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 }, 706 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 }, 707 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 }, 708 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 }, 709 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 }, 710 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 }, 711 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 }, 712 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 }, 713 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 }, 714 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 715 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 716 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 717 718 // XOP foldable instructions 719 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 }, 720 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 }, 721 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 }, 722 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 }, 723 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 }, 724 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 }, 725 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 }, 726 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 }, 727 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 }, 728 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 }, 729 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 }, 730 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 }, 731 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 }, 732 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 }, 733 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 }, 734 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 }, 735 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 }, 736 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 }, 737 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 }, 738 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 }, 739 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 }, 740 { X86::VPROTBri, X86::VPROTBmi, 0 }, 741 { X86::VPROTBrr, X86::VPROTBmr, 0 }, 742 { X86::VPROTDri, X86::VPROTDmi, 0 }, 743 { X86::VPROTDrr, X86::VPROTDmr, 0 }, 744 { X86::VPROTQri, X86::VPROTQmi, 0 }, 745 { X86::VPROTQrr, X86::VPROTQmr, 0 }, 746 { X86::VPROTWri, X86::VPROTWmi, 0 }, 747 { X86::VPROTWrr, X86::VPROTWmr, 0 }, 748 { X86::VPSHABrr, X86::VPSHABmr, 0 }, 749 { X86::VPSHADrr, X86::VPSHADmr, 0 }, 750 { X86::VPSHAQrr, X86::VPSHAQmr, 0 }, 751 { X86::VPSHAWrr, X86::VPSHAWmr, 0 }, 752 { X86::VPSHLBrr, X86::VPSHLBmr, 0 }, 753 { X86::VPSHLDrr, X86::VPSHLDmr, 0 }, 754 { X86::VPSHLQrr, X86::VPSHLQmr, 0 }, 755 { X86::VPSHLWrr, X86::VPSHLWmr, 0 }, 756 757 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions 758 { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 759 { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 760 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 }, 761 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 }, 762 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 }, 763 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 }, 764 { X86::BLCI32rr, X86::BLCI32rm, 0 }, 765 { X86::BLCI64rr, X86::BLCI64rm, 0 }, 766 { X86::BLCIC32rr, X86::BLCIC32rm, 0 }, 767 { X86::BLCIC64rr, X86::BLCIC64rm, 0 }, 768 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 }, 769 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 }, 770 { X86::BLCS32rr, X86::BLCS32rm, 0 }, 771 { X86::BLCS64rr, X86::BLCS64rm, 0 }, 772 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 }, 773 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 }, 774 { X86::BLSI32rr, X86::BLSI32rm, 0 }, 775 { X86::BLSI64rr, X86::BLSI64rm, 0 }, 776 { X86::BLSIC32rr, X86::BLSIC32rm, 0 }, 777 { X86::BLSIC64rr, X86::BLSIC64rm, 0 }, 778 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 779 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 780 { X86::BLSR32rr, X86::BLSR32rm, 0 }, 781 { X86::BLSR64rr, X86::BLSR64rm, 0 }, 782 { X86::BZHI32rr, X86::BZHI32rm, 0 }, 783 { X86::BZHI64rr, X86::BZHI64rm, 0 }, 784 { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 785 { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 786 { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 787 { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 788 { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 789 { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 790 { X86::RORX32ri, X86::RORX32mi, 0 }, 791 { X86::RORX64ri, X86::RORX64mi, 0 }, 792 { X86::SARX32rr, X86::SARX32rm, 0 }, 793 { X86::SARX64rr, X86::SARX64rm, 0 }, 794 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 795 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 796 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 797 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 798 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 }, 799 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 }, 800 { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 801 { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 802 { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 803 { X86::TZMSK32rr, X86::TZMSK32rm, 0 }, 804 { X86::TZMSK64rr, X86::TZMSK64rm, 0 }, 805 806 // AVX-512 foldable instructions 807 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 }, 808 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 }, 809 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 }, 810 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 }, 811 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 }, 812 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 }, 813 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 }, 814 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 }, 815 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 }, 816 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 }, 817 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 }, 818 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 }, 819 { X86::VPABSDZrr, X86::VPABSDZrm, 0 }, 820 { X86::VPABSQZrr, X86::VPABSQZrm, 0 }, 821 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE }, 822 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE }, 823 824 // AVX-512 foldable instructions (256-bit versions) 825 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 }, 826 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 }, 827 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 }, 828 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 }, 829 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 }, 830 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 }, 831 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 }, 832 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 }, 833 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 }, 834 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 }, 835 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE }, 836 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE }, 837 838 // AVX-512 foldable instructions (256-bit versions) 839 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 }, 840 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 }, 841 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 }, 842 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 }, 843 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 }, 844 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 }, 845 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 }, 846 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 }, 847 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 }, 848 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 }, 849 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE }, 850 851 // F16C foldable instructions 852 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 }, 853 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 }, 854 855 // AES foldable instructions 856 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 }, 857 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 }, 858 { X86::VAESIMCrr, X86::VAESIMCrm, 0 }, 859 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 } 860 }; 861 862 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) { 863 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 864 Entry.RegOp, Entry.MemOp, 865 // Index 1, folded load 866 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 867 } 868 869 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = { 870 { X86::ADC32rr, X86::ADC32rm, 0 }, 871 { X86::ADC64rr, X86::ADC64rm, 0 }, 872 { X86::ADD16rr, X86::ADD16rm, 0 }, 873 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 874 { X86::ADD32rr, X86::ADD32rm, 0 }, 875 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 876 { X86::ADD64rr, X86::ADD64rm, 0 }, 877 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 878 { X86::ADD8rr, X86::ADD8rm, 0 }, 879 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 880 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 881 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 882 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 }, 883 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 884 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 }, 885 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 886 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 887 { X86::AND16rr, X86::AND16rm, 0 }, 888 { X86::AND32rr, X86::AND32rm, 0 }, 889 { X86::AND64rr, X86::AND64rm, 0 }, 890 { X86::AND8rr, X86::AND8rm, 0 }, 891 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 892 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 893 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 894 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 895 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 896 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 897 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 898 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 899 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 900 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 901 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 902 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 903 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 904 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 905 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 906 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 907 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 908 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 909 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 910 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 911 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 912 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 913 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 914 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 915 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 916 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 917 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 918 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 919 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 920 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 921 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 922 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 923 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 924 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 925 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 926 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 927 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 928 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 929 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 930 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 931 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 932 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 933 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 934 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 935 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 936 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 937 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 938 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 939 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 940 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 941 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 942 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 943 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 944 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 945 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 946 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 947 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 948 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 949 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 950 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 951 { X86::CRC32r32r32, X86::CRC32r32m32, 0 }, 952 { X86::CRC32r64r64, X86::CRC32r64m64, 0 }, 953 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 954 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 955 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 956 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 }, 957 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 958 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 }, 959 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 }, 960 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 }, 961 962 // Do not fold Fs* scalar logical op loads because there are no scalar 963 // load variants for these instructions. When folded, the load is required 964 // to be 128-bits, so the load size would not match. 965 966 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 }, 967 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 }, 968 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 }, 969 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 }, 970 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 }, 971 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 }, 972 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 }, 973 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 }, 974 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 975 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 976 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 977 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 978 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 979 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 980 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 981 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 982 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 983 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 984 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 985 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 986 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 987 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 988 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 989 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 990 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 991 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 992 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 993 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 994 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 995 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 996 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 997 { X86::MINSDrr, X86::MINSDrm, 0 }, 998 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 999 { X86::MINSSrr, X86::MINSSrm, 0 }, 1000 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 1001 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 1002 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 1003 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 1004 { X86::MULSDrr, X86::MULSDrm, 0 }, 1005 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 }, 1006 { X86::MULSSrr, X86::MULSSrm, 0 }, 1007 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 }, 1008 { X86::OR16rr, X86::OR16rm, 0 }, 1009 { X86::OR32rr, X86::OR32rm, 0 }, 1010 { X86::OR64rr, X86::OR64rm, 0 }, 1011 { X86::OR8rr, X86::OR8rm, 0 }, 1012 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 1013 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 1014 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 1015 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 1016 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 1017 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 1018 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 1019 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 1020 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 1021 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 1022 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 1023 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 1024 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 1025 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 1026 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 1027 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 1028 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 1029 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 1030 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 1031 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 }, 1032 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 1033 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 }, 1034 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 1035 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 1036 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 1037 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 1038 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 1039 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 1040 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 1041 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 1042 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 1043 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 1044 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 1045 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 1046 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 1047 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 1048 { X86::PINSRBrr, X86::PINSRBrm, 0 }, 1049 { X86::PINSRDrr, X86::PINSRDrm, 0 }, 1050 { X86::PINSRQrr, X86::PINSRQrm, 0 }, 1051 { X86::PINSRWrri, X86::PINSRWrmi, 0 }, 1052 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 1053 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 1054 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 1055 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 1056 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 1057 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 1058 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 1059 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 1060 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 1061 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 1062 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 1063 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 1064 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 1065 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 1066 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 1067 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 1068 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 1069 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 1070 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 1071 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 1072 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 1073 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 1074 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 1075 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 1076 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 1077 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 1078 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 1079 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 1080 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 1081 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 1082 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 1083 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 1084 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 1085 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 1086 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 1087 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 1088 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 1089 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 }, 1090 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 1091 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 1092 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 }, 1093 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 }, 1094 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 1095 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 1096 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 1097 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 1098 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 1099 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 1100 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 1101 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 1102 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 1103 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 1104 { X86::ROUNDSDr, X86::ROUNDSDm, 0 }, 1105 { X86::ROUNDSSr, X86::ROUNDSSm, 0 }, 1106 { X86::SBB32rr, X86::SBB32rm, 0 }, 1107 { X86::SBB64rr, X86::SBB64rm, 0 }, 1108 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 1109 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 1110 { X86::SUB16rr, X86::SUB16rm, 0 }, 1111 { X86::SUB32rr, X86::SUB32rm, 0 }, 1112 { X86::SUB64rr, X86::SUB64rm, 0 }, 1113 { X86::SUB8rr, X86::SUB8rm, 0 }, 1114 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 1115 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 1116 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 1117 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 }, 1118 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 1119 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 }, 1120 // FIXME: TEST*rr -> swapped operand of TEST*mr. 1121 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 1122 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 1123 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 1124 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 1125 { X86::XOR16rr, X86::XOR16rm, 0 }, 1126 { X86::XOR32rr, X86::XOR32rm, 0 }, 1127 { X86::XOR64rr, X86::XOR64rm, 0 }, 1128 { X86::XOR8rr, X86::XOR8rm, 0 }, 1129 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 1130 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 1131 1132 // MMX version of foldable instructions 1133 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 }, 1134 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 }, 1135 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 }, 1136 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 }, 1137 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 }, 1138 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 }, 1139 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 }, 1140 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 }, 1141 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 }, 1142 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 }, 1143 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 }, 1144 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 }, 1145 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 }, 1146 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 }, 1147 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 }, 1148 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 }, 1149 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 }, 1150 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 }, 1151 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 }, 1152 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 }, 1153 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 }, 1154 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 }, 1155 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 }, 1156 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 }, 1157 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 }, 1158 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 }, 1159 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 }, 1160 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 }, 1161 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 }, 1162 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 }, 1163 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 }, 1164 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 }, 1165 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 }, 1166 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 }, 1167 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 }, 1168 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 }, 1169 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 }, 1170 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 }, 1171 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 }, 1172 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 }, 1173 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 }, 1174 { X86::MMX_PORirr, X86::MMX_PORirm, 0 }, 1175 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 }, 1176 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 }, 1177 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 }, 1178 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 }, 1179 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 }, 1180 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 }, 1181 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 }, 1182 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 }, 1183 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 }, 1184 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 }, 1185 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 }, 1186 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 }, 1187 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 }, 1188 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 }, 1189 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 }, 1190 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 }, 1191 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 }, 1192 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 }, 1193 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 }, 1194 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 }, 1195 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 }, 1196 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 }, 1197 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 }, 1198 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 }, 1199 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 }, 1200 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 }, 1201 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 }, 1202 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 }, 1203 1204 // 3DNow! version of foldable instructions 1205 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 }, 1206 { X86::PFACCrr, X86::PFACCrm, 0 }, 1207 { X86::PFADDrr, X86::PFADDrm, 0 }, 1208 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 }, 1209 { X86::PFCMPGErr, X86::PFCMPGErm, 0 }, 1210 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 }, 1211 { X86::PFMAXrr, X86::PFMAXrm, 0 }, 1212 { X86::PFMINrr, X86::PFMINrm, 0 }, 1213 { X86::PFMULrr, X86::PFMULrm, 0 }, 1214 { X86::PFNACCrr, X86::PFNACCrm, 0 }, 1215 { X86::PFPNACCrr, X86::PFPNACCrm, 0 }, 1216 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 }, 1217 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 }, 1218 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 }, 1219 { X86::PFSUBrr, X86::PFSUBrm, 0 }, 1220 { X86::PFSUBRrr, X86::PFSUBRrm, 0 }, 1221 { X86::PMULHRWrr, X86::PMULHRWrm, 0 }, 1222 1223 // AVX 128-bit versions of foldable instructions 1224 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 1225 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 1226 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 1227 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 1228 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 1229 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 1230 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 1231 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 1232 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 1233 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 1234 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 1235 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 1236 { X86::VRCPSSr, X86::VRCPSSm, 0 }, 1237 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 }, 1238 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 1239 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 }, 1240 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 1241 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 }, 1242 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 1243 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 }, 1244 { X86::VADDPDrr, X86::VADDPDrm, 0 }, 1245 { X86::VADDPSrr, X86::VADDPSrm, 0 }, 1246 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 1247 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 }, 1248 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 1249 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 }, 1250 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 1251 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 1252 { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 1253 { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 1254 { X86::VANDPDrr, X86::VANDPDrm, 0 }, 1255 { X86::VANDPSrr, X86::VANDPSrm, 0 }, 1256 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 1257 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 1258 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 1259 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 1260 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 1261 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 1262 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 1263 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 1264 { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 1265 { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 1266 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 1267 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 }, 1268 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 1269 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 }, 1270 { X86::VDPPDrri, X86::VDPPDrmi, 0 }, 1271 { X86::VDPPSrri, X86::VDPPSrmi, 0 }, 1272 // Do not fold VFs* loads because there are no scalar load variants for 1273 // these instructions. When folded, the load is required to be 128-bits, so 1274 // the load size would not match. 1275 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 }, 1276 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 }, 1277 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 }, 1278 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 }, 1279 { X86::VFvORPDrr, X86::VFvORPDrm, 0 }, 1280 { X86::VFvORPSrr, X86::VFvORPSrm, 0 }, 1281 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 }, 1282 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 }, 1283 { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 1284 { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 1285 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 1286 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 1287 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 1288 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 1289 { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 1290 { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 1291 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 1292 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 }, 1293 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 1294 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 }, 1295 { X86::VMINPDrr, X86::VMINPDrm, 0 }, 1296 { X86::VMINPSrr, X86::VMINPSrm, 0 }, 1297 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 1298 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 }, 1299 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 1300 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 }, 1301 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 1302 { X86::VMULPDrr, X86::VMULPDrm, 0 }, 1303 { X86::VMULPSrr, X86::VMULPSrm, 0 }, 1304 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 1305 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 }, 1306 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 1307 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 }, 1308 { X86::VORPDrr, X86::VORPDrm, 0 }, 1309 { X86::VORPSrr, X86::VORPSrm, 0 }, 1310 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 1311 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 1312 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 1313 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 1314 { X86::VPADDBrr, X86::VPADDBrm, 0 }, 1315 { X86::VPADDDrr, X86::VPADDDrm, 0 }, 1316 { X86::VPADDQrr, X86::VPADDQrm, 0 }, 1317 { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 1318 { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 1319 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 1320 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 1321 { X86::VPADDWrr, X86::VPADDWrm, 0 }, 1322 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 }, 1323 { X86::VPANDNrr, X86::VPANDNrm, 0 }, 1324 { X86::VPANDrr, X86::VPANDrm, 0 }, 1325 { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 1326 { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 1327 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 }, 1328 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 1329 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 }, 1330 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 1331 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 1332 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 1333 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 1334 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 1335 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 1336 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 1337 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 1338 { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 1339 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 1340 { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 1341 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 1342 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 1343 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 1344 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 1345 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 1346 { X86::VPINSRBrr, X86::VPINSRBrm, 0 }, 1347 { X86::VPINSRDrr, X86::VPINSRDrm, 0 }, 1348 { X86::VPINSRQrr, X86::VPINSRQrm, 0 }, 1349 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 1350 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 }, 1351 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 1352 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 1353 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 1354 { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 1355 { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 1356 { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 1357 { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 1358 { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 1359 { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 1360 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 1361 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 1362 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 1363 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 1364 { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 1365 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 }, 1366 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 1367 { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 1368 { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 1369 { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 1370 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 1371 { X86::VPORrr, X86::VPORrm, 0 }, 1372 { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 1373 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 1374 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 }, 1375 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 }, 1376 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 }, 1377 { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 1378 { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 1379 { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 1380 { X86::VPSRADrr, X86::VPSRADrm, 0 }, 1381 { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 1382 { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 1383 { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 1384 { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 1385 { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 1386 { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 1387 { X86::VPSUBQrr, X86::VPSUBQrm, 0 }, 1388 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 1389 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 1390 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 }, 1391 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 }, 1392 { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 1393 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 1394 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 1395 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 1396 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 1397 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 1398 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 1399 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 1400 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 1401 { X86::VPXORrr, X86::VPXORrm, 0 }, 1402 { X86::VROUNDSDr, X86::VROUNDSDm, 0 }, 1403 { X86::VROUNDSSr, X86::VROUNDSSm, 0 }, 1404 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 1405 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 1406 { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 1407 { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 1408 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 1409 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 }, 1410 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 1411 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 }, 1412 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 1413 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 1414 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 1415 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 1416 { X86::VXORPDrr, X86::VXORPDrm, 0 }, 1417 { X86::VXORPSrr, X86::VXORPSrm, 0 }, 1418 1419 // AVX 256-bit foldable instructions 1420 { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 1421 { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 1422 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 1423 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 1424 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 1425 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 1426 { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 1427 { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1428 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1429 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1430 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1431 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1432 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1433 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1434 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1435 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1436 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 }, 1437 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1438 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1439 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1440 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1441 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1442 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1443 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1444 { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1445 { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1446 { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1447 { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1448 { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1449 { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1450 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1451 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1452 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1453 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1454 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1455 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1456 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1457 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1458 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1459 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1460 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1461 { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1462 { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1463 1464 // AVX2 foldable instructions 1465 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1466 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1467 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1468 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1469 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1470 { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1471 { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1472 { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1473 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1474 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1475 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1476 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1477 { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1478 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 }, 1479 { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1480 { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1481 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1482 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1483 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1484 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1485 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 }, 1486 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1487 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1488 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1489 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1490 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1491 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1492 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1493 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1494 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1495 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1496 { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1497 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1498 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1499 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1500 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1501 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1502 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1503 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1504 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 }, 1505 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1506 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1507 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1508 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1509 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1510 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1511 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1512 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1513 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1514 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1515 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1516 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1517 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1518 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1519 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1520 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 }, 1521 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1522 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1523 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1524 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1525 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1526 { X86::VPORYrr, X86::VPORYrm, 0 }, 1527 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1528 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1529 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 }, 1530 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 }, 1531 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 }, 1532 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1533 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1534 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1535 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1536 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1537 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1538 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1539 { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1540 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1541 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1542 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1543 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1544 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1545 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1546 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1547 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1548 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1549 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1550 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1551 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1552 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 }, 1553 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1554 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1555 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 }, 1556 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 }, 1557 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1558 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1559 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1560 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1561 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1562 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1563 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1564 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1565 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1566 { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1567 1568 // FMA4 foldable patterns 1569 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE }, 1570 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE }, 1571 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE }, 1572 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE }, 1573 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE }, 1574 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE }, 1575 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE }, 1576 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE }, 1577 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE }, 1578 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE }, 1579 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE }, 1580 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE }, 1581 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE }, 1582 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE }, 1583 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE }, 1584 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE }, 1585 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE }, 1586 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE }, 1587 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE }, 1588 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE }, 1589 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE }, 1590 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE }, 1591 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE }, 1592 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE }, 1593 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE }, 1594 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE }, 1595 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE }, 1596 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE }, 1597 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE }, 1598 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE }, 1599 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE }, 1600 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE }, 1601 1602 // XOP foldable instructions 1603 { X86::VPCMOVrr, X86::VPCMOVmr, 0 }, 1604 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 }, 1605 { X86::VPCOMBri, X86::VPCOMBmi, 0 }, 1606 { X86::VPCOMDri, X86::VPCOMDmi, 0 }, 1607 { X86::VPCOMQri, X86::VPCOMQmi, 0 }, 1608 { X86::VPCOMWri, X86::VPCOMWmi, 0 }, 1609 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 }, 1610 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 }, 1611 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 }, 1612 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 }, 1613 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 }, 1614 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 }, 1615 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 }, 1616 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 }, 1617 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 }, 1618 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 }, 1619 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 }, 1620 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 }, 1621 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 }, 1622 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 }, 1623 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 }, 1624 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 }, 1625 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 }, 1626 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 }, 1627 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 }, 1628 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 }, 1629 { X86::VPPERMrr, X86::VPPERMmr, 0 }, 1630 { X86::VPROTBrr, X86::VPROTBrm, 0 }, 1631 { X86::VPROTDrr, X86::VPROTDrm, 0 }, 1632 { X86::VPROTQrr, X86::VPROTQrm, 0 }, 1633 { X86::VPROTWrr, X86::VPROTWrm, 0 }, 1634 { X86::VPSHABrr, X86::VPSHABrm, 0 }, 1635 { X86::VPSHADrr, X86::VPSHADrm, 0 }, 1636 { X86::VPSHAQrr, X86::VPSHAQrm, 0 }, 1637 { X86::VPSHAWrr, X86::VPSHAWrm, 0 }, 1638 { X86::VPSHLBrr, X86::VPSHLBrm, 0 }, 1639 { X86::VPSHLDrr, X86::VPSHLDrm, 0 }, 1640 { X86::VPSHLQrr, X86::VPSHLQrm, 0 }, 1641 { X86::VPSHLWrr, X86::VPSHLWrm, 0 }, 1642 1643 // BMI/BMI2 foldable instructions 1644 { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1645 { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1646 { X86::MULX32rr, X86::MULX32rm, 0 }, 1647 { X86::MULX64rr, X86::MULX64rm, 0 }, 1648 { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1649 { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1650 { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1651 { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1652 1653 // AVX-512 foldable instructions 1654 { X86::VADDPSZrr, X86::VADDPSZrm, 0 }, 1655 { X86::VADDPDZrr, X86::VADDPDZrm, 0 }, 1656 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 }, 1657 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 }, 1658 { X86::VMULPSZrr, X86::VMULPSZrm, 0 }, 1659 { X86::VMULPDZrr, X86::VMULPDZrm, 0 }, 1660 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 }, 1661 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 }, 1662 { X86::VMINPSZrr, X86::VMINPSZrm, 0 }, 1663 { X86::VMINPDZrr, X86::VMINPDZrm, 0 }, 1664 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 }, 1665 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 }, 1666 { X86::VPADDDZrr, X86::VPADDDZrm, 0 }, 1667 { X86::VPADDQZrr, X86::VPADDQZrm, 0 }, 1668 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 }, 1669 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 }, 1670 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 }, 1671 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 }, 1672 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 }, 1673 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 }, 1674 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 }, 1675 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 }, 1676 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 }, 1677 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 }, 1678 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 }, 1679 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 }, 1680 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 }, 1681 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 }, 1682 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 }, 1683 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 }, 1684 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 }, 1685 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 }, 1686 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 }, 1687 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 }, 1688 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 }, 1689 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 }, 1690 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 }, 1691 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE }, 1692 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE }, 1693 1694 // AVX-512{F,VL} foldable instructions 1695 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE }, 1696 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE }, 1697 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE }, 1698 1699 // AVX-512{F,VL} foldable instructions 1700 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 }, 1701 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 }, 1702 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 }, 1703 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 }, 1704 1705 // AES foldable instructions 1706 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 }, 1707 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 }, 1708 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 }, 1709 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 }, 1710 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 }, 1711 { X86::VAESDECrr, X86::VAESDECrm, 0 }, 1712 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 }, 1713 { X86::VAESENCrr, X86::VAESENCrm, 0 }, 1714 1715 // SHA foldable instructions 1716 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 }, 1717 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 }, 1718 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 }, 1719 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 }, 1720 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 }, 1721 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 }, 1722 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 } 1723 }; 1724 1725 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) { 1726 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1727 Entry.RegOp, Entry.MemOp, 1728 // Index 2, folded load 1729 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1730 } 1731 1732 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = { 1733 // FMA foldable instructions 1734 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE }, 1735 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE }, 1736 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE }, 1737 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE }, 1738 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE }, 1739 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE }, 1740 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE }, 1741 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE }, 1742 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE }, 1743 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE }, 1744 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE }, 1745 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE }, 1746 1747 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE }, 1748 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE }, 1749 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE }, 1750 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE }, 1751 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE }, 1752 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE }, 1753 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE }, 1754 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE }, 1755 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE }, 1756 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE }, 1757 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE }, 1758 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE }, 1759 1760 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE }, 1761 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE }, 1762 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE }, 1763 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE }, 1764 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE }, 1765 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE }, 1766 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE }, 1767 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE }, 1768 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE }, 1769 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE }, 1770 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE }, 1771 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE }, 1772 1773 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE }, 1774 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE }, 1775 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE }, 1776 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE }, 1777 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE }, 1778 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE }, 1779 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE }, 1780 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE }, 1781 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE }, 1782 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE }, 1783 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE }, 1784 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE }, 1785 1786 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE }, 1787 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE }, 1788 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE }, 1789 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE }, 1790 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE }, 1791 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE }, 1792 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE }, 1793 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE }, 1794 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE }, 1795 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE }, 1796 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE }, 1797 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE }, 1798 1799 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE }, 1800 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE }, 1801 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE }, 1802 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE }, 1803 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE }, 1804 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE }, 1805 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE }, 1806 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE }, 1807 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE }, 1808 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE }, 1809 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE }, 1810 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE }, 1811 1812 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE }, 1813 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE }, 1814 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE }, 1815 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE }, 1816 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE }, 1817 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE }, 1818 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE }, 1819 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE }, 1820 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE }, 1821 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE }, 1822 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE }, 1823 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE }, 1824 1825 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE }, 1826 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE }, 1827 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE }, 1828 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE }, 1829 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE }, 1830 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE }, 1831 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE }, 1832 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE }, 1833 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE }, 1834 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE }, 1835 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE }, 1836 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE }, 1837 1838 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE }, 1839 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE }, 1840 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE }, 1841 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE }, 1842 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE }, 1843 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE }, 1844 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE }, 1845 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE }, 1846 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE }, 1847 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE }, 1848 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE }, 1849 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE }, 1850 1851 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE }, 1852 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE }, 1853 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE }, 1854 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE }, 1855 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE }, 1856 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE }, 1857 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE }, 1858 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE }, 1859 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE }, 1860 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE }, 1861 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE }, 1862 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE }, 1863 1864 // FMA4 foldable patterns 1865 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE }, 1866 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE }, 1867 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE }, 1868 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE }, 1869 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE }, 1870 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE }, 1871 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE }, 1872 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE }, 1873 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE }, 1874 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE }, 1875 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE }, 1876 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE }, 1877 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE }, 1878 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE }, 1879 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE }, 1880 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE }, 1881 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE }, 1882 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE }, 1883 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE }, 1884 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE }, 1885 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE }, 1886 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE }, 1887 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE }, 1888 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE }, 1889 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE }, 1890 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE }, 1891 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE }, 1892 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE }, 1893 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE }, 1894 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE }, 1895 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE }, 1896 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE }, 1897 1898 // XOP foldable instructions 1899 { X86::VPCMOVrr, X86::VPCMOVrm, 0 }, 1900 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 }, 1901 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 }, 1902 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 }, 1903 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 }, 1904 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 }, 1905 { X86::VPPERMrr, X86::VPPERMrm, 0 }, 1906 1907 // AVX-512 VPERMI instructions with 3 source operands. 1908 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 }, 1909 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 }, 1910 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 }, 1911 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 }, 1912 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 }, 1913 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 }, 1914 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 }, 1915 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }, 1916 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE }, 1917 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE }, 1918 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE }, 1919 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE }, 1920 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE }, 1921 // AVX-512 arithmetic instructions 1922 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 }, 1923 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 }, 1924 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 }, 1925 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 }, 1926 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 }, 1927 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 }, 1928 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 }, 1929 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 }, 1930 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 }, 1931 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 }, 1932 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 }, 1933 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 }, 1934 // AVX-512{F,VL} arithmetic instructions 256-bit 1935 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 }, 1936 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 }, 1937 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 }, 1938 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 }, 1939 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 }, 1940 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 }, 1941 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 }, 1942 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 }, 1943 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 }, 1944 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 }, 1945 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 }, 1946 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 }, 1947 // AVX-512{F,VL} arithmetic instructions 128-bit 1948 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 }, 1949 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 }, 1950 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 }, 1951 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 }, 1952 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 }, 1953 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 }, 1954 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 }, 1955 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 }, 1956 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 }, 1957 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 }, 1958 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 }, 1959 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 } 1960 }; 1961 1962 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) { 1963 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1964 Entry.RegOp, Entry.MemOp, 1965 // Index 3, folded load 1966 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1967 } 1968 1969 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = { 1970 // AVX-512 foldable instructions 1971 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 }, 1972 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 }, 1973 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 }, 1974 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 }, 1975 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 }, 1976 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 }, 1977 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 }, 1978 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 }, 1979 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 }, 1980 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 }, 1981 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 }, 1982 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 }, 1983 // AVX-512{F,VL} foldable instructions 256-bit 1984 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 }, 1985 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 }, 1986 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 }, 1987 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 }, 1988 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 }, 1989 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 }, 1990 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 }, 1991 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 }, 1992 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 }, 1993 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 }, 1994 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 }, 1995 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 }, 1996 // AVX-512{F,VL} foldable instructions 128-bit 1997 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 }, 1998 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 }, 1999 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 }, 2000 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 }, 2001 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 }, 2002 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 }, 2003 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 }, 2004 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 }, 2005 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 }, 2006 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 }, 2007 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 }, 2008 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 } 2009 }; 2010 2011 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) { 2012 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable, 2013 Entry.RegOp, Entry.MemOp, 2014 // Index 4, folded load 2015 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD); 2016 } 2017 } 2018 2019 void 2020 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 2021 MemOp2RegOpTableType &M2RTable, 2022 unsigned RegOp, unsigned MemOp, unsigned Flags) { 2023 if ((Flags & TB_NO_FORWARD) == 0) { 2024 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 2025 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 2026 } 2027 if ((Flags & TB_NO_REVERSE) == 0) { 2028 assert(!M2RTable.count(MemOp) && 2029 "Duplicated entries in unfolding maps?"); 2030 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 2031 } 2032 } 2033 2034 bool 2035 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 2036 unsigned &SrcReg, unsigned &DstReg, 2037 unsigned &SubIdx) const { 2038 switch (MI.getOpcode()) { 2039 default: break; 2040 case X86::MOVSX16rr8: 2041 case X86::MOVZX16rr8: 2042 case X86::MOVSX32rr8: 2043 case X86::MOVZX32rr8: 2044 case X86::MOVSX64rr8: 2045 if (!Subtarget.is64Bit()) 2046 // It's not always legal to reference the low 8-bit of the larger 2047 // register in 32-bit mode. 2048 return false; 2049 case X86::MOVSX32rr16: 2050 case X86::MOVZX32rr16: 2051 case X86::MOVSX64rr16: 2052 case X86::MOVSX64rr32: { 2053 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 2054 // Be conservative. 2055 return false; 2056 SrcReg = MI.getOperand(1).getReg(); 2057 DstReg = MI.getOperand(0).getReg(); 2058 switch (MI.getOpcode()) { 2059 default: llvm_unreachable("Unreachable!"); 2060 case X86::MOVSX16rr8: 2061 case X86::MOVZX16rr8: 2062 case X86::MOVSX32rr8: 2063 case X86::MOVZX32rr8: 2064 case X86::MOVSX64rr8: 2065 SubIdx = X86::sub_8bit; 2066 break; 2067 case X86::MOVSX32rr16: 2068 case X86::MOVZX32rr16: 2069 case X86::MOVSX64rr16: 2070 SubIdx = X86::sub_16bit; 2071 break; 2072 case X86::MOVSX64rr32: 2073 SubIdx = X86::sub_32bit; 2074 break; 2075 } 2076 return true; 2077 } 2078 } 2079 return false; 2080 } 2081 2082 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const { 2083 const MachineFunction *MF = MI->getParent()->getParent(); 2084 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); 2085 2086 if (MI->getOpcode() == getCallFrameSetupOpcode() || 2087 MI->getOpcode() == getCallFrameDestroyOpcode()) { 2088 unsigned StackAlign = TFI->getStackAlignment(); 2089 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign * 2090 StackAlign; 2091 2092 SPAdj -= MI->getOperand(1).getImm(); 2093 2094 if (MI->getOpcode() == getCallFrameSetupOpcode()) 2095 return SPAdj; 2096 else 2097 return -SPAdj; 2098 } 2099 2100 // To know whether a call adjusts the stack, we need information 2101 // that is bound to the following ADJCALLSTACKUP pseudo. 2102 // Look for the next ADJCALLSTACKUP that follows the call. 2103 if (MI->isCall()) { 2104 const MachineBasicBlock* MBB = MI->getParent(); 2105 auto I = ++MachineBasicBlock::const_iterator(MI); 2106 for (auto E = MBB->end(); I != E; ++I) { 2107 if (I->getOpcode() == getCallFrameDestroyOpcode() || 2108 I->isCall()) 2109 break; 2110 } 2111 2112 // If we could not find a frame destroy opcode, then it has already 2113 // been simplified, so we don't care. 2114 if (I->getOpcode() != getCallFrameDestroyOpcode()) 2115 return 0; 2116 2117 return -(I->getOperand(1).getImm()); 2118 } 2119 2120 // Currently handle only PUSHes we can reasonably expect to see 2121 // in call sequences 2122 switch (MI->getOpcode()) { 2123 default: 2124 return 0; 2125 case X86::PUSH32i8: 2126 case X86::PUSH32r: 2127 case X86::PUSH32rmm: 2128 case X86::PUSH32rmr: 2129 case X86::PUSHi32: 2130 return 4; 2131 } 2132 } 2133 2134 /// Return true and the FrameIndex if the specified 2135 /// operand and follow operands form a reference to the stack frame. 2136 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 2137 int &FrameIndex) const { 2138 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() && 2139 MI->getOperand(Op+X86::AddrScaleAmt).isImm() && 2140 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 2141 MI->getOperand(Op+X86::AddrDisp).isImm() && 2142 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 && 2143 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 && 2144 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) { 2145 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex(); 2146 return true; 2147 } 2148 return false; 2149 } 2150 2151 static bool isFrameLoadOpcode(int Opcode) { 2152 switch (Opcode) { 2153 default: 2154 return false; 2155 case X86::MOV8rm: 2156 case X86::MOV16rm: 2157 case X86::MOV32rm: 2158 case X86::MOV64rm: 2159 case X86::LD_Fp64m: 2160 case X86::MOVSSrm: 2161 case X86::MOVSDrm: 2162 case X86::MOVAPSrm: 2163 case X86::MOVAPDrm: 2164 case X86::MOVDQArm: 2165 case X86::VMOVSSrm: 2166 case X86::VMOVSDrm: 2167 case X86::VMOVAPSrm: 2168 case X86::VMOVAPDrm: 2169 case X86::VMOVDQArm: 2170 case X86::VMOVUPSYrm: 2171 case X86::VMOVAPSYrm: 2172 case X86::VMOVUPDYrm: 2173 case X86::VMOVAPDYrm: 2174 case X86::VMOVDQUYrm: 2175 case X86::VMOVDQAYrm: 2176 case X86::MMX_MOVD64rm: 2177 case X86::MMX_MOVQ64rm: 2178 case X86::VMOVAPSZrm: 2179 case X86::VMOVUPSZrm: 2180 return true; 2181 } 2182 } 2183 2184 static bool isFrameStoreOpcode(int Opcode) { 2185 switch (Opcode) { 2186 default: break; 2187 case X86::MOV8mr: 2188 case X86::MOV16mr: 2189 case X86::MOV32mr: 2190 case X86::MOV64mr: 2191 case X86::ST_FpP64m: 2192 case X86::MOVSSmr: 2193 case X86::MOVSDmr: 2194 case X86::MOVAPSmr: 2195 case X86::MOVAPDmr: 2196 case X86::MOVDQAmr: 2197 case X86::VMOVSSmr: 2198 case X86::VMOVSDmr: 2199 case X86::VMOVAPSmr: 2200 case X86::VMOVAPDmr: 2201 case X86::VMOVDQAmr: 2202 case X86::VMOVUPSYmr: 2203 case X86::VMOVAPSYmr: 2204 case X86::VMOVUPDYmr: 2205 case X86::VMOVAPDYmr: 2206 case X86::VMOVDQUYmr: 2207 case X86::VMOVDQAYmr: 2208 case X86::VMOVUPSZmr: 2209 case X86::VMOVAPSZmr: 2210 case X86::MMX_MOVD64mr: 2211 case X86::MMX_MOVQ64mr: 2212 case X86::MMX_MOVNTQmr: 2213 return true; 2214 } 2215 return false; 2216 } 2217 2218 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 2219 int &FrameIndex) const { 2220 if (isFrameLoadOpcode(MI->getOpcode())) 2221 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 2222 return MI->getOperand(0).getReg(); 2223 return 0; 2224 } 2225 2226 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 2227 int &FrameIndex) const { 2228 if (isFrameLoadOpcode(MI->getOpcode())) { 2229 unsigned Reg; 2230 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 2231 return Reg; 2232 // Check for post-frame index elimination operations 2233 const MachineMemOperand *Dummy; 2234 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 2235 } 2236 return 0; 2237 } 2238 2239 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 2240 int &FrameIndex) const { 2241 if (isFrameStoreOpcode(MI->getOpcode())) 2242 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 2243 isFrameOperand(MI, 0, FrameIndex)) 2244 return MI->getOperand(X86::AddrNumOperands).getReg(); 2245 return 0; 2246 } 2247 2248 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 2249 int &FrameIndex) const { 2250 if (isFrameStoreOpcode(MI->getOpcode())) { 2251 unsigned Reg; 2252 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 2253 return Reg; 2254 // Check for post-frame index elimination operations 2255 const MachineMemOperand *Dummy; 2256 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 2257 } 2258 return 0; 2259 } 2260 2261 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. 2262 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 2263 // Don't waste compile time scanning use-def chains of physregs. 2264 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 2265 return false; 2266 bool isPICBase = false; 2267 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), 2268 E = MRI.def_instr_end(); I != E; ++I) { 2269 MachineInstr *DefMI = &*I; 2270 if (DefMI->getOpcode() != X86::MOVPC32r) 2271 return false; 2272 assert(!isPICBase && "More than one PIC base?"); 2273 isPICBase = true; 2274 } 2275 return isPICBase; 2276 } 2277 2278 bool 2279 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 2280 AliasAnalysis *AA) const { 2281 switch (MI->getOpcode()) { 2282 default: break; 2283 case X86::MOV8rm: 2284 case X86::MOV16rm: 2285 case X86::MOV32rm: 2286 case X86::MOV64rm: 2287 case X86::LD_Fp64m: 2288 case X86::MOVSSrm: 2289 case X86::MOVSDrm: 2290 case X86::MOVAPSrm: 2291 case X86::MOVUPSrm: 2292 case X86::MOVAPDrm: 2293 case X86::MOVDQArm: 2294 case X86::MOVDQUrm: 2295 case X86::VMOVSSrm: 2296 case X86::VMOVSDrm: 2297 case X86::VMOVAPSrm: 2298 case X86::VMOVUPSrm: 2299 case X86::VMOVAPDrm: 2300 case X86::VMOVDQArm: 2301 case X86::VMOVDQUrm: 2302 case X86::VMOVAPSYrm: 2303 case X86::VMOVUPSYrm: 2304 case X86::VMOVAPDYrm: 2305 case X86::VMOVDQAYrm: 2306 case X86::VMOVDQUYrm: 2307 case X86::MMX_MOVD64rm: 2308 case X86::MMX_MOVQ64rm: 2309 case X86::FsVMOVAPSrm: 2310 case X86::FsVMOVAPDrm: 2311 case X86::FsMOVAPSrm: 2312 case X86::FsMOVAPDrm: 2313 // AVX-512 2314 case X86::VMOVAPDZ128rm: 2315 case X86::VMOVAPDZ256rm: 2316 case X86::VMOVAPDZrm: 2317 case X86::VMOVAPSZ128rm: 2318 case X86::VMOVAPSZ256rm: 2319 case X86::VMOVAPSZrm: 2320 case X86::VMOVDQA32Z128rm: 2321 case X86::VMOVDQA32Z256rm: 2322 case X86::VMOVDQA32Zrm: 2323 case X86::VMOVDQA64Z128rm: 2324 case X86::VMOVDQA64Z256rm: 2325 case X86::VMOVDQA64Zrm: 2326 case X86::VMOVDQU16Z128rm: 2327 case X86::VMOVDQU16Z256rm: 2328 case X86::VMOVDQU16Zrm: 2329 case X86::VMOVDQU32Z128rm: 2330 case X86::VMOVDQU32Z256rm: 2331 case X86::VMOVDQU32Zrm: 2332 case X86::VMOVDQU64Z128rm: 2333 case X86::VMOVDQU64Z256rm: 2334 case X86::VMOVDQU64Zrm: 2335 case X86::VMOVDQU8Z128rm: 2336 case X86::VMOVDQU8Z256rm: 2337 case X86::VMOVDQU8Zrm: 2338 case X86::VMOVUPSZ128rm: 2339 case X86::VMOVUPSZ256rm: 2340 case X86::VMOVUPSZrm: { 2341 // Loads from constant pools are trivially rematerializable. 2342 if (MI->getOperand(1+X86::AddrBaseReg).isReg() && 2343 MI->getOperand(1+X86::AddrScaleAmt).isImm() && 2344 MI->getOperand(1+X86::AddrIndexReg).isReg() && 2345 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 && 2346 MI->isInvariantLoad(AA)) { 2347 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); 2348 if (BaseReg == 0 || BaseReg == X86::RIP) 2349 return true; 2350 // Allow re-materialization of PIC load. 2351 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal()) 2352 return false; 2353 const MachineFunction &MF = *MI->getParent()->getParent(); 2354 const MachineRegisterInfo &MRI = MF.getRegInfo(); 2355 return regIsPICBase(BaseReg, MRI); 2356 } 2357 return false; 2358 } 2359 2360 case X86::LEA32r: 2361 case X86::LEA64r: { 2362 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() && 2363 MI->getOperand(1+X86::AddrIndexReg).isReg() && 2364 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 && 2365 !MI->getOperand(1+X86::AddrDisp).isReg()) { 2366 // lea fi#, lea GV, etc. are all rematerializable. 2367 if (!MI->getOperand(1+X86::AddrBaseReg).isReg()) 2368 return true; 2369 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); 2370 if (BaseReg == 0) 2371 return true; 2372 // Allow re-materialization of lea PICBase + x. 2373 const MachineFunction &MF = *MI->getParent()->getParent(); 2374 const MachineRegisterInfo &MRI = MF.getRegInfo(); 2375 return regIsPICBase(BaseReg, MRI); 2376 } 2377 return false; 2378 } 2379 } 2380 2381 // All other instructions marked M_REMATERIALIZABLE are always trivially 2382 // rematerializable. 2383 return true; 2384 } 2385 2386 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 2387 MachineBasicBlock::iterator I) const { 2388 MachineBasicBlock::iterator E = MBB.end(); 2389 2390 // For compile time consideration, if we are not able to determine the 2391 // safety after visiting 4 instructions in each direction, we will assume 2392 // it's not safe. 2393 MachineBasicBlock::iterator Iter = I; 2394 for (unsigned i = 0; Iter != E && i < 4; ++i) { 2395 bool SeenDef = false; 2396 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 2397 MachineOperand &MO = Iter->getOperand(j); 2398 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 2399 SeenDef = true; 2400 if (!MO.isReg()) 2401 continue; 2402 if (MO.getReg() == X86::EFLAGS) { 2403 if (MO.isUse()) 2404 return false; 2405 SeenDef = true; 2406 } 2407 } 2408 2409 if (SeenDef) 2410 // This instruction defines EFLAGS, no need to look any further. 2411 return true; 2412 ++Iter; 2413 // Skip over DBG_VALUE. 2414 while (Iter != E && Iter->isDebugValue()) 2415 ++Iter; 2416 } 2417 2418 // It is safe to clobber EFLAGS at the end of a block of no successor has it 2419 // live in. 2420 if (Iter == E) { 2421 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 2422 SE = MBB.succ_end(); SI != SE; ++SI) 2423 if ((*SI)->isLiveIn(X86::EFLAGS)) 2424 return false; 2425 return true; 2426 } 2427 2428 MachineBasicBlock::iterator B = MBB.begin(); 2429 Iter = I; 2430 for (unsigned i = 0; i < 4; ++i) { 2431 // If we make it to the beginning of the block, it's safe to clobber 2432 // EFLAGS iff EFLAGS is not live-in. 2433 if (Iter == B) 2434 return !MBB.isLiveIn(X86::EFLAGS); 2435 2436 --Iter; 2437 // Skip over DBG_VALUE. 2438 while (Iter != B && Iter->isDebugValue()) 2439 --Iter; 2440 2441 bool SawKill = false; 2442 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 2443 MachineOperand &MO = Iter->getOperand(j); 2444 // A register mask may clobber EFLAGS, but we should still look for a 2445 // live EFLAGS def. 2446 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 2447 SawKill = true; 2448 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 2449 if (MO.isDef()) return MO.isDead(); 2450 if (MO.isKill()) SawKill = true; 2451 } 2452 } 2453 2454 if (SawKill) 2455 // This instruction kills EFLAGS and doesn't redefine it, so 2456 // there's no need to look further. 2457 return true; 2458 } 2459 2460 // Conservative answer. 2461 return false; 2462 } 2463 2464 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 2465 MachineBasicBlock::iterator I, 2466 unsigned DestReg, unsigned SubIdx, 2467 const MachineInstr *Orig, 2468 const TargetRegisterInfo &TRI) const { 2469 // MOV32r0 is implemented with a xor which clobbers condition code. 2470 // Re-materialize it as movri instructions to avoid side effects. 2471 unsigned Opc = Orig->getOpcode(); 2472 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) { 2473 DebugLoc DL = Orig->getDebugLoc(); 2474 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0)) 2475 .addImm(0); 2476 } else { 2477 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 2478 MBB.insert(I, MI); 2479 } 2480 2481 MachineInstr *NewMI = std::prev(I); 2482 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 2483 } 2484 2485 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead. 2486 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const { 2487 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2488 MachineOperand &MO = MI->getOperand(i); 2489 if (MO.isReg() && MO.isDef() && 2490 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 2491 return true; 2492 } 2493 } 2494 return false; 2495 } 2496 2497 /// Check whether the shift count for a machine operand is non-zero. 2498 inline static unsigned getTruncatedShiftCount(MachineInstr *MI, 2499 unsigned ShiftAmtOperandIdx) { 2500 // The shift count is six bits with the REX.W prefix and five bits without. 2501 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31; 2502 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm(); 2503 return Imm & ShiftCountMask; 2504 } 2505 2506 /// Check whether the given shift count is appropriate 2507 /// can be represented by a LEA instruction. 2508 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) { 2509 // Left shift instructions can be transformed into load-effective-address 2510 // instructions if we can encode them appropriately. 2511 // A LEA instruction utilizes a SIB byte to encode its scale factor. 2512 // The SIB.scale field is two bits wide which means that we can encode any 2513 // shift amount less than 4. 2514 return ShAmt < 4 && ShAmt > 0; 2515 } 2516 2517 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, 2518 unsigned Opc, bool AllowSP, 2519 unsigned &NewSrc, bool &isKill, bool &isUndef, 2520 MachineOperand &ImplicitOp) const { 2521 MachineFunction &MF = *MI->getParent()->getParent(); 2522 const TargetRegisterClass *RC; 2523 if (AllowSP) { 2524 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 2525 } else { 2526 RC = Opc != X86::LEA32r ? 2527 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; 2528 } 2529 unsigned SrcReg = Src.getReg(); 2530 2531 // For both LEA64 and LEA32 the register already has essentially the right 2532 // type (32-bit or 64-bit) we may just need to forbid SP. 2533 if (Opc != X86::LEA64_32r) { 2534 NewSrc = SrcReg; 2535 isKill = Src.isKill(); 2536 isUndef = Src.isUndef(); 2537 2538 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && 2539 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 2540 return false; 2541 2542 return true; 2543 } 2544 2545 // This is for an LEA64_32r and incoming registers are 32-bit. One way or 2546 // another we need to add 64-bit registers to the final MI. 2547 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 2548 ImplicitOp = Src; 2549 ImplicitOp.setImplicit(); 2550 2551 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64); 2552 MachineBasicBlock::LivenessQueryResult LQR = 2553 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI); 2554 2555 switch (LQR) { 2556 case MachineBasicBlock::LQR_Unknown: 2557 // We can't give sane liveness flags to the instruction, abandon LEA 2558 // formation. 2559 return false; 2560 case MachineBasicBlock::LQR_Live: 2561 isKill = MI->killsRegister(SrcReg); 2562 isUndef = false; 2563 break; 2564 default: 2565 // The physreg itself is dead, so we have to use it as an <undef>. 2566 isKill = false; 2567 isUndef = true; 2568 break; 2569 } 2570 } else { 2571 // Virtual register of the wrong class, we have to create a temporary 64-bit 2572 // vreg to feed into the LEA. 2573 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 2574 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 2575 get(TargetOpcode::COPY)) 2576 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) 2577 .addOperand(Src); 2578 2579 // Which is obviously going to be dead after we're done with it. 2580 isKill = true; 2581 isUndef = false; 2582 } 2583 2584 // We've set all the parameters without issue. 2585 return true; 2586 } 2587 2588 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit 2589 /// LEA to form 3-address code by promoting to a 32-bit superregister and then 2590 /// truncating back down to a 16-bit subregister. 2591 MachineInstr * 2592 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 2593 MachineFunction::iterator &MFI, 2594 MachineBasicBlock::iterator &MBBI, 2595 LiveVariables *LV) const { 2596 MachineInstr *MI = MBBI; 2597 unsigned Dest = MI->getOperand(0).getReg(); 2598 unsigned Src = MI->getOperand(1).getReg(); 2599 bool isDead = MI->getOperand(0).isDead(); 2600 bool isKill = MI->getOperand(1).isKill(); 2601 2602 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 2603 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 2604 unsigned Opc, leaInReg; 2605 if (Subtarget.is64Bit()) { 2606 Opc = X86::LEA64_32r; 2607 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 2608 } else { 2609 Opc = X86::LEA32r; 2610 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 2611 } 2612 2613 // Build and insert into an implicit UNDEF value. This is OK because 2614 // well be shifting and then extracting the lower 16-bits. 2615 // This has the potential to cause partial register stall. e.g. 2616 // movw (%rbp,%rcx,2), %dx 2617 // leal -65(%rdx), %esi 2618 // But testing has shown this *does* help performance in 64-bit mode (at 2619 // least on modern x86 machines). 2620 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 2621 MachineInstr *InsMI = 2622 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2623 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 2624 .addReg(Src, getKillRegState(isKill)); 2625 2626 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 2627 get(Opc), leaOutReg); 2628 switch (MIOpc) { 2629 default: llvm_unreachable("Unreachable!"); 2630 case X86::SHL16ri: { 2631 unsigned ShAmt = MI->getOperand(2).getImm(); 2632 MIB.addReg(0).addImm(1 << ShAmt) 2633 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 2634 break; 2635 } 2636 case X86::INC16r: 2637 addRegOffset(MIB, leaInReg, true, 1); 2638 break; 2639 case X86::DEC16r: 2640 addRegOffset(MIB, leaInReg, true, -1); 2641 break; 2642 case X86::ADD16ri: 2643 case X86::ADD16ri8: 2644 case X86::ADD16ri_DB: 2645 case X86::ADD16ri8_DB: 2646 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 2647 break; 2648 case X86::ADD16rr: 2649 case X86::ADD16rr_DB: { 2650 unsigned Src2 = MI->getOperand(2).getReg(); 2651 bool isKill2 = MI->getOperand(2).isKill(); 2652 unsigned leaInReg2 = 0; 2653 MachineInstr *InsMI2 = nullptr; 2654 if (Src == Src2) { 2655 // ADD16rr %reg1028<kill>, %reg1028 2656 // just a single insert_subreg. 2657 addRegReg(MIB, leaInReg, true, leaInReg, false); 2658 } else { 2659 if (Subtarget.is64Bit()) 2660 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 2661 else 2662 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 2663 // Build and insert into an implicit UNDEF value. This is OK because 2664 // well be shifting and then extracting the lower 16-bits. 2665 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 2666 InsMI2 = 2667 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2668 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 2669 .addReg(Src2, getKillRegState(isKill2)); 2670 addRegReg(MIB, leaInReg, true, leaInReg2, true); 2671 } 2672 if (LV && isKill2 && InsMI2) 2673 LV->replaceKillInstruction(Src2, MI, InsMI2); 2674 break; 2675 } 2676 } 2677 2678 MachineInstr *NewMI = MIB; 2679 MachineInstr *ExtMI = 2680 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2681 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 2682 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 2683 2684 if (LV) { 2685 // Update live variables 2686 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 2687 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 2688 if (isKill) 2689 LV->replaceKillInstruction(Src, MI, InsMI); 2690 if (isDead) 2691 LV->replaceKillInstruction(Dest, MI, ExtMI); 2692 } 2693 2694 return ExtMI; 2695 } 2696 2697 /// This method must be implemented by targets that 2698 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2699 /// may be able to convert a two-address instruction into a true 2700 /// three-address instruction on demand. This allows the X86 target (for 2701 /// example) to convert ADD and SHL instructions into LEA instructions if they 2702 /// would require register copies due to two-addressness. 2703 /// 2704 /// This method returns a null pointer if the transformation cannot be 2705 /// performed, otherwise it returns the new instruction. 2706 /// 2707 MachineInstr * 2708 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 2709 MachineBasicBlock::iterator &MBBI, 2710 LiveVariables *LV) const { 2711 MachineInstr *MI = MBBI; 2712 2713 // The following opcodes also sets the condition code register(s). Only 2714 // convert them to equivalent lea if the condition code register def's 2715 // are dead! 2716 if (hasLiveCondCodeDef(MI)) 2717 return nullptr; 2718 2719 MachineFunction &MF = *MI->getParent()->getParent(); 2720 // All instructions input are two-addr instructions. Get the known operands. 2721 const MachineOperand &Dest = MI->getOperand(0); 2722 const MachineOperand &Src = MI->getOperand(1); 2723 2724 MachineInstr *NewMI = nullptr; 2725 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 2726 // we have better subtarget support, enable the 16-bit LEA generation here. 2727 // 16-bit LEA is also slow on Core2. 2728 bool DisableLEA16 = true; 2729 bool is64Bit = Subtarget.is64Bit(); 2730 2731 unsigned MIOpc = MI->getOpcode(); 2732 switch (MIOpc) { 2733 default: return nullptr; 2734 case X86::SHL64ri: { 2735 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2736 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2737 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2738 2739 // LEA can't handle RSP. 2740 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2741 !MF.getRegInfo().constrainRegClass(Src.getReg(), 2742 &X86::GR64_NOSPRegClass)) 2743 return nullptr; 2744 2745 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2746 .addOperand(Dest) 2747 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2748 break; 2749 } 2750 case X86::SHL32ri: { 2751 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2752 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2753 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2754 2755 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2756 2757 // LEA can't handle ESP. 2758 bool isKill, isUndef; 2759 unsigned SrcReg; 2760 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2761 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2762 SrcReg, isKill, isUndef, ImplicitOp)) 2763 return nullptr; 2764 2765 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2766 .addOperand(Dest) 2767 .addReg(0).addImm(1 << ShAmt) 2768 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 2769 .addImm(0).addReg(0); 2770 if (ImplicitOp.getReg() != 0) 2771 MIB.addOperand(ImplicitOp); 2772 NewMI = MIB; 2773 2774 break; 2775 } 2776 case X86::SHL16ri: { 2777 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2778 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2779 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2780 2781 if (DisableLEA16) 2782 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr; 2783 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2784 .addOperand(Dest) 2785 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2786 break; 2787 } 2788 case X86::INC64r: 2789 case X86::INC32r: { 2790 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2791 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 2792 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2793 bool isKill, isUndef; 2794 unsigned SrcReg; 2795 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2796 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2797 SrcReg, isKill, isUndef, ImplicitOp)) 2798 return nullptr; 2799 2800 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2801 .addOperand(Dest) 2802 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)); 2803 if (ImplicitOp.getReg() != 0) 2804 MIB.addOperand(ImplicitOp); 2805 2806 NewMI = addOffset(MIB, 1); 2807 break; 2808 } 2809 case X86::INC16r: 2810 if (DisableLEA16) 2811 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2812 : nullptr; 2813 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2814 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2815 .addOperand(Dest).addOperand(Src), 1); 2816 break; 2817 case X86::DEC64r: 2818 case X86::DEC32r: { 2819 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2820 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2821 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2822 2823 bool isKill, isUndef; 2824 unsigned SrcReg; 2825 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2826 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2827 SrcReg, isKill, isUndef, ImplicitOp)) 2828 return nullptr; 2829 2830 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2831 .addOperand(Dest) 2832 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2833 if (ImplicitOp.getReg() != 0) 2834 MIB.addOperand(ImplicitOp); 2835 2836 NewMI = addOffset(MIB, -1); 2837 2838 break; 2839 } 2840 case X86::DEC16r: 2841 if (DisableLEA16) 2842 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2843 : nullptr; 2844 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2845 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2846 .addOperand(Dest).addOperand(Src), -1); 2847 break; 2848 case X86::ADD64rr: 2849 case X86::ADD64rr_DB: 2850 case X86::ADD32rr: 2851 case X86::ADD32rr_DB: { 2852 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2853 unsigned Opc; 2854 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) 2855 Opc = X86::LEA64r; 2856 else 2857 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2858 2859 bool isKill, isUndef; 2860 unsigned SrcReg; 2861 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2862 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2863 SrcReg, isKill, isUndef, ImplicitOp)) 2864 return nullptr; 2865 2866 const MachineOperand &Src2 = MI->getOperand(2); 2867 bool isKill2, isUndef2; 2868 unsigned SrcReg2; 2869 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false); 2870 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2871 SrcReg2, isKill2, isUndef2, ImplicitOp2)) 2872 return nullptr; 2873 2874 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2875 .addOperand(Dest); 2876 if (ImplicitOp.getReg() != 0) 2877 MIB.addOperand(ImplicitOp); 2878 if (ImplicitOp2.getReg() != 0) 2879 MIB.addOperand(ImplicitOp2); 2880 2881 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); 2882 2883 // Preserve undefness of the operands. 2884 NewMI->getOperand(1).setIsUndef(isUndef); 2885 NewMI->getOperand(3).setIsUndef(isUndef2); 2886 2887 if (LV && Src2.isKill()) 2888 LV->replaceKillInstruction(SrcReg2, MI, NewMI); 2889 break; 2890 } 2891 case X86::ADD16rr: 2892 case X86::ADD16rr_DB: { 2893 if (DisableLEA16) 2894 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2895 : nullptr; 2896 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2897 unsigned Src2 = MI->getOperand(2).getReg(); 2898 bool isKill2 = MI->getOperand(2).isKill(); 2899 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2900 .addOperand(Dest), 2901 Src.getReg(), Src.isKill(), Src2, isKill2); 2902 2903 // Preserve undefness of the operands. 2904 bool isUndef = MI->getOperand(1).isUndef(); 2905 bool isUndef2 = MI->getOperand(2).isUndef(); 2906 NewMI->getOperand(1).setIsUndef(isUndef); 2907 NewMI->getOperand(3).setIsUndef(isUndef2); 2908 2909 if (LV && isKill2) 2910 LV->replaceKillInstruction(Src2, MI, NewMI); 2911 break; 2912 } 2913 case X86::ADD64ri32: 2914 case X86::ADD64ri8: 2915 case X86::ADD64ri32_DB: 2916 case X86::ADD64ri8_DB: 2917 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2918 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2919 .addOperand(Dest).addOperand(Src), 2920 MI->getOperand(2).getImm()); 2921 break; 2922 case X86::ADD32ri: 2923 case X86::ADD32ri8: 2924 case X86::ADD32ri_DB: 2925 case X86::ADD32ri8_DB: { 2926 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2927 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2928 2929 bool isKill, isUndef; 2930 unsigned SrcReg; 2931 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2932 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2933 SrcReg, isKill, isUndef, ImplicitOp)) 2934 return nullptr; 2935 2936 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2937 .addOperand(Dest) 2938 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2939 if (ImplicitOp.getReg() != 0) 2940 MIB.addOperand(ImplicitOp); 2941 2942 NewMI = addOffset(MIB, MI->getOperand(2).getImm()); 2943 break; 2944 } 2945 case X86::ADD16ri: 2946 case X86::ADD16ri8: 2947 case X86::ADD16ri_DB: 2948 case X86::ADD16ri8_DB: 2949 if (DisableLEA16) 2950 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2951 : nullptr; 2952 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2953 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2954 .addOperand(Dest).addOperand(Src), 2955 MI->getOperand(2).getImm()); 2956 break; 2957 } 2958 2959 if (!NewMI) return nullptr; 2960 2961 if (LV) { // Update live variables 2962 if (Src.isKill()) 2963 LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2964 if (Dest.isDead()) 2965 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2966 } 2967 2968 MFI->insert(MBBI, NewMI); // Insert the new inst 2969 return NewMI; 2970 } 2971 2972 /// Returns true if the given instruction opcode is FMA3. 2973 /// Otherwise, returns false. 2974 /// The second parameter is optional and is used as the second return from 2975 /// the function. It is set to true if the given instruction has FMA3 opcode 2976 /// that is used for lowering of scalar FMA intrinsics, and it is set to false 2977 /// otherwise. 2978 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) { 2979 if (IsIntrinsic) 2980 *IsIntrinsic = false; 2981 2982 switch (Opcode) { 2983 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m: 2984 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m: 2985 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m: 2986 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m: 2987 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m: 2988 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m: 2989 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m: 2990 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m: 2991 2992 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m: 2993 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m: 2994 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m: 2995 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m: 2996 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m: 2997 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m: 2998 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m: 2999 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m: 3000 3001 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m: 3002 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m: 3003 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m: 3004 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m: 3005 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m: 3006 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m: 3007 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m: 3008 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m: 3009 3010 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m: 3011 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m: 3012 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m: 3013 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m: 3014 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY: 3015 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY: 3016 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY: 3017 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY: 3018 3019 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m: 3020 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m: 3021 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m: 3022 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m: 3023 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m: 3024 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m: 3025 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m: 3026 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m: 3027 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY: 3028 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY: 3029 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY: 3030 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY: 3031 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY: 3032 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY: 3033 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY: 3034 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY: 3035 3036 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m: 3037 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m: 3038 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m: 3039 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m: 3040 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY: 3041 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY: 3042 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY: 3043 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY: 3044 3045 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m: 3046 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m: 3047 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m: 3048 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m: 3049 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m: 3050 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m: 3051 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m: 3052 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m: 3053 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY: 3054 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY: 3055 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY: 3056 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY: 3057 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY: 3058 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY: 3059 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY: 3060 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY: 3061 3062 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m: 3063 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m: 3064 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m: 3065 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m: 3066 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY: 3067 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY: 3068 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY: 3069 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY: 3070 3071 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m: 3072 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m: 3073 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m: 3074 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m: 3075 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m: 3076 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m: 3077 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m: 3078 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m: 3079 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY: 3080 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY: 3081 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY: 3082 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY: 3083 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY: 3084 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY: 3085 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY: 3086 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY: 3087 return true; 3088 3089 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int: 3090 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int: 3091 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int: 3092 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int: 3093 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int: 3094 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int: 3095 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int: 3096 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int: 3097 3098 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int: 3099 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int: 3100 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int: 3101 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int: 3102 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int: 3103 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int: 3104 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int: 3105 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int: 3106 3107 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int: 3108 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int: 3109 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int: 3110 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int: 3111 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int: 3112 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int: 3113 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int: 3114 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int: 3115 if (IsIntrinsic) 3116 *IsIntrinsic = true; 3117 return true; 3118 default: 3119 return false; 3120 } 3121 llvm_unreachable("Opcode not handled by the switch"); 3122 } 3123 3124 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI, 3125 bool NewMI, 3126 unsigned OpIdx1, 3127 unsigned OpIdx2) const { 3128 switch (MI->getOpcode()) { 3129 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 3130 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 3131 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 3132 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 3133 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 3134 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 3135 unsigned Opc; 3136 unsigned Size; 3137 switch (MI->getOpcode()) { 3138 default: llvm_unreachable("Unreachable!"); 3139 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 3140 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 3141 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 3142 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 3143 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 3144 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 3145 } 3146 unsigned Amt = MI->getOperand(3).getImm(); 3147 if (NewMI) { 3148 MachineFunction &MF = *MI->getParent()->getParent(); 3149 MI = MF.CloneMachineInstr(MI); 3150 NewMI = false; 3151 } 3152 MI->setDesc(get(Opc)); 3153 MI->getOperand(3).setImm(Size-Amt); 3154 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 3155 } 3156 case X86::BLENDPDrri: 3157 case X86::BLENDPSrri: 3158 case X86::PBLENDWrri: 3159 case X86::VBLENDPDrri: 3160 case X86::VBLENDPSrri: 3161 case X86::VBLENDPDYrri: 3162 case X86::VBLENDPSYrri: 3163 case X86::VPBLENDDrri: 3164 case X86::VPBLENDWrri: 3165 case X86::VPBLENDDYrri: 3166 case X86::VPBLENDWYrri:{ 3167 unsigned Mask; 3168 switch (MI->getOpcode()) { 3169 default: llvm_unreachable("Unreachable!"); 3170 case X86::BLENDPDrri: Mask = 0x03; break; 3171 case X86::BLENDPSrri: Mask = 0x0F; break; 3172 case X86::PBLENDWrri: Mask = 0xFF; break; 3173 case X86::VBLENDPDrri: Mask = 0x03; break; 3174 case X86::VBLENDPSrri: Mask = 0x0F; break; 3175 case X86::VBLENDPDYrri: Mask = 0x0F; break; 3176 case X86::VBLENDPSYrri: Mask = 0xFF; break; 3177 case X86::VPBLENDDrri: Mask = 0x0F; break; 3178 case X86::VPBLENDWrri: Mask = 0xFF; break; 3179 case X86::VPBLENDDYrri: Mask = 0xFF; break; 3180 case X86::VPBLENDWYrri: Mask = 0xFF; break; 3181 } 3182 // Only the least significant bits of Imm are used. 3183 unsigned Imm = MI->getOperand(3).getImm() & Mask; 3184 if (NewMI) { 3185 MachineFunction &MF = *MI->getParent()->getParent(); 3186 MI = MF.CloneMachineInstr(MI); 3187 NewMI = false; 3188 } 3189 MI->getOperand(3).setImm(Mask ^ Imm); 3190 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 3191 } 3192 case X86::PCLMULQDQrr: 3193 case X86::VPCLMULQDQrr:{ 3194 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0] 3195 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0] 3196 unsigned Imm = MI->getOperand(3).getImm(); 3197 unsigned Src1Hi = Imm & 0x01; 3198 unsigned Src2Hi = Imm & 0x10; 3199 if (NewMI) { 3200 MachineFunction &MF = *MI->getParent()->getParent(); 3201 MI = MF.CloneMachineInstr(MI); 3202 NewMI = false; 3203 } 3204 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4)); 3205 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 3206 } 3207 case X86::CMPPDrri: 3208 case X86::CMPPSrri: 3209 case X86::VCMPPDrri: 3210 case X86::VCMPPSrri: 3211 case X86::VCMPPDYrri: 3212 case X86::VCMPPSYrri: { 3213 // Float comparison can be safely commuted for 3214 // Ordered/Unordered/Equal/NotEqual tests 3215 unsigned Imm = MI->getOperand(3).getImm() & 0x7; 3216 switch (Imm) { 3217 case 0x00: // EQUAL 3218 case 0x03: // UNORDERED 3219 case 0x04: // NOT EQUAL 3220 case 0x07: // ORDERED 3221 if (NewMI) { 3222 MachineFunction &MF = *MI->getParent()->getParent(); 3223 MI = MF.CloneMachineInstr(MI); 3224 NewMI = false; 3225 } 3226 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 3227 default: 3228 return nullptr; 3229 } 3230 } 3231 case X86::VPCOMBri: case X86::VPCOMUBri: 3232 case X86::VPCOMDri: case X86::VPCOMUDri: 3233 case X86::VPCOMQri: case X86::VPCOMUQri: 3234 case X86::VPCOMWri: case X86::VPCOMUWri: { 3235 // Flip comparison mode immediate (if necessary). 3236 unsigned Imm = MI->getOperand(3).getImm() & 0x7; 3237 switch (Imm) { 3238 case 0x00: Imm = 0x02; break; // LT -> GT 3239 case 0x01: Imm = 0x03; break; // LE -> GE 3240 case 0x02: Imm = 0x00; break; // GT -> LT 3241 case 0x03: Imm = 0x01; break; // GE -> LE 3242 case 0x04: // EQ 3243 case 0x05: // NE 3244 case 0x06: // FALSE 3245 case 0x07: // TRUE 3246 default: 3247 break; 3248 } 3249 if (NewMI) { 3250 MachineFunction &MF = *MI->getParent()->getParent(); 3251 MI = MF.CloneMachineInstr(MI); 3252 NewMI = false; 3253 } 3254 MI->getOperand(3).setImm(Imm); 3255 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 3256 } 3257 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 3258 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 3259 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 3260 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 3261 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 3262 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 3263 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 3264 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 3265 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 3266 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 3267 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 3268 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 3269 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 3270 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 3271 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 3272 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 3273 unsigned Opc; 3274 switch (MI->getOpcode()) { 3275 default: llvm_unreachable("Unreachable!"); 3276 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 3277 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 3278 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 3279 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 3280 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 3281 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 3282 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 3283 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 3284 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 3285 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 3286 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 3287 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 3288 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 3289 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 3290 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 3291 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 3292 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 3293 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 3294 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 3295 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 3296 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 3297 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 3298 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 3299 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 3300 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 3301 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 3302 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 3303 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 3304 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 3305 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 3306 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 3307 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 3308 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 3309 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 3310 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 3311 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 3312 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 3313 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 3314 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 3315 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 3316 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 3317 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 3318 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 3319 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 3320 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 3321 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 3322 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 3323 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 3324 } 3325 if (NewMI) { 3326 MachineFunction &MF = *MI->getParent()->getParent(); 3327 MI = MF.CloneMachineInstr(MI); 3328 NewMI = false; 3329 } 3330 MI->setDesc(get(Opc)); 3331 // Fallthrough intended. 3332 } 3333 default: 3334 if (isFMA3(MI->getOpcode())) { 3335 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2); 3336 if (Opc == 0) 3337 return nullptr; 3338 if (NewMI) { 3339 MachineFunction &MF = *MI->getParent()->getParent(); 3340 MI = MF.CloneMachineInstr(MI); 3341 NewMI = false; 3342 } 3343 MI->setDesc(get(Opc)); 3344 } 3345 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 3346 } 3347 } 3348 3349 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI, 3350 unsigned &SrcOpIdx1, 3351 unsigned &SrcOpIdx2) const { 3352 3353 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3; 3354 3355 // Only the first RegOpsNum operands are commutable. 3356 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means 3357 // that the operand is not specified/fixed. 3358 if (SrcOpIdx1 != CommuteAnyOperandIndex && 3359 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum)) 3360 return false; 3361 if (SrcOpIdx2 != CommuteAnyOperandIndex && 3362 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum)) 3363 return false; 3364 3365 // Look for two different register operands assumed to be commutable 3366 // regardless of the FMA opcode. The FMA opcode is adjusted later. 3367 if (SrcOpIdx1 == CommuteAnyOperandIndex || 3368 SrcOpIdx2 == CommuteAnyOperandIndex) { 3369 unsigned CommutableOpIdx1 = SrcOpIdx1; 3370 unsigned CommutableOpIdx2 = SrcOpIdx2; 3371 3372 // At least one of operands to be commuted is not specified and 3373 // this method is free to choose appropriate commutable operands. 3374 if (SrcOpIdx1 == SrcOpIdx2) 3375 // Both of operands are not fixed. By default set one of commutable 3376 // operands to the last register operand of the instruction. 3377 CommutableOpIdx2 = RegOpsNum; 3378 else if (SrcOpIdx2 == CommuteAnyOperandIndex) 3379 // Only one of operands is not fixed. 3380 CommutableOpIdx2 = SrcOpIdx1; 3381 3382 // CommutableOpIdx2 is well defined now. Let's choose another commutable 3383 // operand and assign its index to CommutableOpIdx1. 3384 unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg(); 3385 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) { 3386 // The commuted operands must have different registers. 3387 // Otherwise, the commute transformation does not change anything and 3388 // is useless then. 3389 if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg()) 3390 break; 3391 } 3392 3393 // No appropriate commutable operands were found. 3394 if (CommutableOpIdx1 == 0) 3395 return false; 3396 3397 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2 3398 // to return those values. 3399 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 3400 CommutableOpIdx1, CommutableOpIdx2)) 3401 return false; 3402 } 3403 3404 // Check if we can adjust the opcode to preserve the semantics when 3405 // commute the register operands. 3406 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0; 3407 } 3408 3409 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI, 3410 unsigned SrcOpIdx1, 3411 unsigned SrcOpIdx2) const { 3412 unsigned Opc = MI->getOpcode(); 3413 3414 // Define the array that holds FMA opcodes in groups 3415 // of 3 opcodes(132, 213, 231) in each group. 3416 static const unsigned RegularOpcodeGroups[][3] = { 3417 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r }, 3418 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r }, 3419 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r }, 3420 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r }, 3421 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY }, 3422 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY }, 3423 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m }, 3424 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m }, 3425 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m }, 3426 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m }, 3427 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY }, 3428 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY }, 3429 3430 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r }, 3431 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r }, 3432 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r }, 3433 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r }, 3434 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY }, 3435 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY }, 3436 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m }, 3437 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m }, 3438 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m }, 3439 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m }, 3440 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY }, 3441 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY }, 3442 3443 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r }, 3444 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r }, 3445 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r }, 3446 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r }, 3447 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY }, 3448 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY }, 3449 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m }, 3450 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m }, 3451 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m }, 3452 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m }, 3453 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY }, 3454 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY }, 3455 3456 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r }, 3457 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r }, 3458 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r }, 3459 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r }, 3460 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY }, 3461 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY }, 3462 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m }, 3463 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m }, 3464 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m }, 3465 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m }, 3466 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY }, 3467 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY }, 3468 3469 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r }, 3470 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r }, 3471 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY }, 3472 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY }, 3473 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m }, 3474 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m }, 3475 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY }, 3476 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY }, 3477 3478 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r }, 3479 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r }, 3480 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY }, 3481 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY }, 3482 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m }, 3483 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m }, 3484 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY }, 3485 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY } 3486 }; 3487 3488 // Define the array that holds FMA*_Int opcodes in groups 3489 // of 3 opcodes(132, 213, 231) in each group. 3490 static const unsigned IntrinOpcodeGroups[][3] = { 3491 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int }, 3492 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int }, 3493 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int }, 3494 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int }, 3495 3496 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int }, 3497 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int }, 3498 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int }, 3499 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int }, 3500 3501 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int }, 3502 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int }, 3503 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int }, 3504 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int }, 3505 3506 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int }, 3507 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int }, 3508 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int }, 3509 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int }, 3510 }; 3511 3512 const unsigned Form132Index = 0; 3513 const unsigned Form213Index = 1; 3514 const unsigned Form231Index = 2; 3515 const unsigned FormsNum = 3; 3516 3517 bool IsIntrinOpcode; 3518 isFMA3(Opc, &IsIntrinOpcode); 3519 3520 size_t GroupsNum; 3521 const unsigned (*OpcodeGroups)[3]; 3522 if (IsIntrinOpcode) { 3523 GroupsNum = array_lengthof(IntrinOpcodeGroups); 3524 OpcodeGroups = IntrinOpcodeGroups; 3525 } else { 3526 GroupsNum = array_lengthof(RegularOpcodeGroups); 3527 OpcodeGroups = RegularOpcodeGroups; 3528 } 3529 3530 const unsigned *FoundOpcodesGroup = nullptr; 3531 size_t FormIndex; 3532 3533 // Look for the input opcode in the corresponding opcodes table. 3534 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup; 3535 ++GroupIndex) { 3536 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) { 3537 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) { 3538 FoundOpcodesGroup = OpcodeGroups[GroupIndex]; 3539 break; 3540 } 3541 } 3542 } 3543 3544 // The input opcode does not match with any of the opcodes from the tables. 3545 // The unsupported FMA opcode must be added to one of the two opcode groups 3546 // defined above. 3547 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode"); 3548 3549 // Put the lowest index to SrcOpIdx1 to simplify the checks below. 3550 if (SrcOpIdx1 > SrcOpIdx2) 3551 std::swap(SrcOpIdx1, SrcOpIdx2); 3552 3553 // TODO: Commuting the 1st operand of FMA*_Int requires some additional 3554 // analysis. The commute optimization is legal only if all users of FMA*_Int 3555 // use only the lowest element of the FMA*_Int instruction. Such analysis are 3556 // not implemented yet. So, just return 0 in that case. 3557 // When such analysis are available this place will be the right place for 3558 // calling it. 3559 if (IsIntrinOpcode && SrcOpIdx1 == 1) 3560 return 0; 3561 3562 unsigned Case; 3563 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2) 3564 Case = 0; 3565 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3) 3566 Case = 1; 3567 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3) 3568 Case = 2; 3569 else 3570 return 0; 3571 3572 // Define the FMA forms mapping array that helps to map input FMA form 3573 // to output FMA form to preserve the operation semantics after 3574 // commuting the operands. 3575 static const unsigned FormMapping[][3] = { 3576 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2; 3577 // FMA132 A, C, b; ==> FMA231 C, A, b; 3578 // FMA213 B, A, c; ==> FMA213 A, B, c; 3579 // FMA231 C, A, b; ==> FMA132 A, C, b; 3580 { Form231Index, Form213Index, Form132Index }, 3581 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3; 3582 // FMA132 A, c, B; ==> FMA132 B, c, A; 3583 // FMA213 B, a, C; ==> FMA231 C, a, B; 3584 // FMA231 C, a, B; ==> FMA213 B, a, C; 3585 { Form132Index, Form231Index, Form213Index }, 3586 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3; 3587 // FMA132 a, C, B; ==> FMA213 a, B, C; 3588 // FMA213 b, A, C; ==> FMA132 b, C, A; 3589 // FMA231 c, A, B; ==> FMA231 c, B, A; 3590 { Form213Index, Form132Index, Form231Index } 3591 }; 3592 3593 // Everything is ready, just adjust the FMA opcode and return it. 3594 FormIndex = FormMapping[Case][FormIndex]; 3595 return FoundOpcodesGroup[FormIndex]; 3596 } 3597 3598 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, 3599 unsigned &SrcOpIdx1, 3600 unsigned &SrcOpIdx2) const { 3601 switch (MI->getOpcode()) { 3602 case X86::CMPPDrri: 3603 case X86::CMPPSrri: 3604 case X86::VCMPPDrri: 3605 case X86::VCMPPSrri: 3606 case X86::VCMPPDYrri: 3607 case X86::VCMPPSYrri: { 3608 // Float comparison can be safely commuted for 3609 // Ordered/Unordered/Equal/NotEqual tests 3610 unsigned Imm = MI->getOperand(3).getImm() & 0x7; 3611 switch (Imm) { 3612 case 0x00: // EQUAL 3613 case 0x03: // UNORDERED 3614 case 0x04: // NOT EQUAL 3615 case 0x07: // ORDERED 3616 // The indices of the commutable operands are 1 and 2. 3617 // Assign them to the returned operand indices here. 3618 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2); 3619 } 3620 return false; 3621 } 3622 default: 3623 if (isFMA3(MI->getOpcode())) 3624 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 3625 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 3626 } 3627 return false; 3628 } 3629 3630 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 3631 switch (BrOpc) { 3632 default: return X86::COND_INVALID; 3633 case X86::JE_1: return X86::COND_E; 3634 case X86::JNE_1: return X86::COND_NE; 3635 case X86::JL_1: return X86::COND_L; 3636 case X86::JLE_1: return X86::COND_LE; 3637 case X86::JG_1: return X86::COND_G; 3638 case X86::JGE_1: return X86::COND_GE; 3639 case X86::JB_1: return X86::COND_B; 3640 case X86::JBE_1: return X86::COND_BE; 3641 case X86::JA_1: return X86::COND_A; 3642 case X86::JAE_1: return X86::COND_AE; 3643 case X86::JS_1: return X86::COND_S; 3644 case X86::JNS_1: return X86::COND_NS; 3645 case X86::JP_1: return X86::COND_P; 3646 case X86::JNP_1: return X86::COND_NP; 3647 case X86::JO_1: return X86::COND_O; 3648 case X86::JNO_1: return X86::COND_NO; 3649 } 3650 } 3651 3652 /// Return condition code of a SET opcode. 3653 static X86::CondCode getCondFromSETOpc(unsigned Opc) { 3654 switch (Opc) { 3655 default: return X86::COND_INVALID; 3656 case X86::SETAr: case X86::SETAm: return X86::COND_A; 3657 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 3658 case X86::SETBr: case X86::SETBm: return X86::COND_B; 3659 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 3660 case X86::SETEr: case X86::SETEm: return X86::COND_E; 3661 case X86::SETGr: case X86::SETGm: return X86::COND_G; 3662 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 3663 case X86::SETLr: case X86::SETLm: return X86::COND_L; 3664 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 3665 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 3666 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 3667 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 3668 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 3669 case X86::SETOr: case X86::SETOm: return X86::COND_O; 3670 case X86::SETPr: case X86::SETPm: return X86::COND_P; 3671 case X86::SETSr: case X86::SETSm: return X86::COND_S; 3672 } 3673 } 3674 3675 /// Return condition code of a CMov opcode. 3676 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 3677 switch (Opc) { 3678 default: return X86::COND_INVALID; 3679 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 3680 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 3681 return X86::COND_A; 3682 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 3683 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 3684 return X86::COND_AE; 3685 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 3686 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 3687 return X86::COND_B; 3688 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 3689 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 3690 return X86::COND_BE; 3691 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 3692 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 3693 return X86::COND_E; 3694 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 3695 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 3696 return X86::COND_G; 3697 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 3698 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 3699 return X86::COND_GE; 3700 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 3701 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 3702 return X86::COND_L; 3703 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 3704 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 3705 return X86::COND_LE; 3706 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 3707 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 3708 return X86::COND_NE; 3709 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 3710 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 3711 return X86::COND_NO; 3712 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 3713 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 3714 return X86::COND_NP; 3715 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 3716 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 3717 return X86::COND_NS; 3718 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 3719 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 3720 return X86::COND_O; 3721 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 3722 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 3723 return X86::COND_P; 3724 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 3725 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 3726 return X86::COND_S; 3727 } 3728 } 3729 3730 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 3731 switch (CC) { 3732 default: llvm_unreachable("Illegal condition code!"); 3733 case X86::COND_E: return X86::JE_1; 3734 case X86::COND_NE: return X86::JNE_1; 3735 case X86::COND_L: return X86::JL_1; 3736 case X86::COND_LE: return X86::JLE_1; 3737 case X86::COND_G: return X86::JG_1; 3738 case X86::COND_GE: return X86::JGE_1; 3739 case X86::COND_B: return X86::JB_1; 3740 case X86::COND_BE: return X86::JBE_1; 3741 case X86::COND_A: return X86::JA_1; 3742 case X86::COND_AE: return X86::JAE_1; 3743 case X86::COND_S: return X86::JS_1; 3744 case X86::COND_NS: return X86::JNS_1; 3745 case X86::COND_P: return X86::JP_1; 3746 case X86::COND_NP: return X86::JNP_1; 3747 case X86::COND_O: return X86::JO_1; 3748 case X86::COND_NO: return X86::JNO_1; 3749 } 3750 } 3751 3752 /// Return the inverse of the specified condition, 3753 /// e.g. turning COND_E to COND_NE. 3754 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 3755 switch (CC) { 3756 default: llvm_unreachable("Illegal condition code!"); 3757 case X86::COND_E: return X86::COND_NE; 3758 case X86::COND_NE: return X86::COND_E; 3759 case X86::COND_L: return X86::COND_GE; 3760 case X86::COND_LE: return X86::COND_G; 3761 case X86::COND_G: return X86::COND_LE; 3762 case X86::COND_GE: return X86::COND_L; 3763 case X86::COND_B: return X86::COND_AE; 3764 case X86::COND_BE: return X86::COND_A; 3765 case X86::COND_A: return X86::COND_BE; 3766 case X86::COND_AE: return X86::COND_B; 3767 case X86::COND_S: return X86::COND_NS; 3768 case X86::COND_NS: return X86::COND_S; 3769 case X86::COND_P: return X86::COND_NP; 3770 case X86::COND_NP: return X86::COND_P; 3771 case X86::COND_O: return X86::COND_NO; 3772 case X86::COND_NO: return X86::COND_O; 3773 } 3774 } 3775 3776 /// Assuming the flags are set by MI(a,b), return the condition code if we 3777 /// modify the instructions such that flags are set by MI(b,a). 3778 static X86::CondCode getSwappedCondition(X86::CondCode CC) { 3779 switch (CC) { 3780 default: return X86::COND_INVALID; 3781 case X86::COND_E: return X86::COND_E; 3782 case X86::COND_NE: return X86::COND_NE; 3783 case X86::COND_L: return X86::COND_G; 3784 case X86::COND_LE: return X86::COND_GE; 3785 case X86::COND_G: return X86::COND_L; 3786 case X86::COND_GE: return X86::COND_LE; 3787 case X86::COND_B: return X86::COND_A; 3788 case X86::COND_BE: return X86::COND_AE; 3789 case X86::COND_A: return X86::COND_B; 3790 case X86::COND_AE: return X86::COND_BE; 3791 } 3792 } 3793 3794 /// Return a set opcode for the given condition and 3795 /// whether it has memory operand. 3796 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) { 3797 static const uint16_t Opc[16][2] = { 3798 { X86::SETAr, X86::SETAm }, 3799 { X86::SETAEr, X86::SETAEm }, 3800 { X86::SETBr, X86::SETBm }, 3801 { X86::SETBEr, X86::SETBEm }, 3802 { X86::SETEr, X86::SETEm }, 3803 { X86::SETGr, X86::SETGm }, 3804 { X86::SETGEr, X86::SETGEm }, 3805 { X86::SETLr, X86::SETLm }, 3806 { X86::SETLEr, X86::SETLEm }, 3807 { X86::SETNEr, X86::SETNEm }, 3808 { X86::SETNOr, X86::SETNOm }, 3809 { X86::SETNPr, X86::SETNPm }, 3810 { X86::SETNSr, X86::SETNSm }, 3811 { X86::SETOr, X86::SETOm }, 3812 { X86::SETPr, X86::SETPm }, 3813 { X86::SETSr, X86::SETSm } 3814 }; 3815 3816 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes"); 3817 return Opc[CC][HasMemoryOperand ? 1 : 0]; 3818 } 3819 3820 /// Return a cmov opcode for the given condition, 3821 /// register size in bytes, and operand type. 3822 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, 3823 bool HasMemoryOperand) { 3824 static const uint16_t Opc[32][3] = { 3825 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 3826 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 3827 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 3828 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 3829 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 3830 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 3831 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 3832 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 3833 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 3834 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 3835 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 3836 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 3837 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 3838 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 3839 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 3840 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 3841 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 3842 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 3843 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 3844 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 3845 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 3846 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 3847 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 3848 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 3849 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 3850 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 3851 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 3852 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 3853 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 3854 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 3855 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 3856 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 3857 }; 3858 3859 assert(CC < 16 && "Can only handle standard cond codes"); 3860 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 3861 switch(RegBytes) { 3862 default: llvm_unreachable("Illegal register size!"); 3863 case 2: return Opc[Idx][0]; 3864 case 4: return Opc[Idx][1]; 3865 case 8: return Opc[Idx][2]; 3866 } 3867 } 3868 3869 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 3870 if (!MI->isTerminator()) return false; 3871 3872 // Conditional branch is a special case. 3873 if (MI->isBranch() && !MI->isBarrier()) 3874 return true; 3875 if (!MI->isPredicable()) 3876 return true; 3877 return !isPredicated(MI); 3878 } 3879 3880 bool X86InstrInfo::AnalyzeBranchImpl( 3881 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 3882 SmallVectorImpl<MachineOperand> &Cond, 3883 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const { 3884 3885 // Start from the bottom of the block and work up, examining the 3886 // terminator instructions. 3887 MachineBasicBlock::iterator I = MBB.end(); 3888 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 3889 while (I != MBB.begin()) { 3890 --I; 3891 if (I->isDebugValue()) 3892 continue; 3893 3894 // Working from the bottom, when we see a non-terminator instruction, we're 3895 // done. 3896 if (!isUnpredicatedTerminator(I)) 3897 break; 3898 3899 // A terminator that isn't a branch can't easily be handled by this 3900 // analysis. 3901 if (!I->isBranch()) 3902 return true; 3903 3904 // Handle unconditional branches. 3905 if (I->getOpcode() == X86::JMP_1) { 3906 UnCondBrIter = I; 3907 3908 if (!AllowModify) { 3909 TBB = I->getOperand(0).getMBB(); 3910 continue; 3911 } 3912 3913 // If the block has any instructions after a JMP, delete them. 3914 while (std::next(I) != MBB.end()) 3915 std::next(I)->eraseFromParent(); 3916 3917 Cond.clear(); 3918 FBB = nullptr; 3919 3920 // Delete the JMP if it's equivalent to a fall-through. 3921 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 3922 TBB = nullptr; 3923 I->eraseFromParent(); 3924 I = MBB.end(); 3925 UnCondBrIter = MBB.end(); 3926 continue; 3927 } 3928 3929 // TBB is used to indicate the unconditional destination. 3930 TBB = I->getOperand(0).getMBB(); 3931 continue; 3932 } 3933 3934 // Handle conditional branches. 3935 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 3936 if (BranchCode == X86::COND_INVALID) 3937 return true; // Can't handle indirect branch. 3938 3939 // Working from the bottom, handle the first conditional branch. 3940 if (Cond.empty()) { 3941 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 3942 if (AllowModify && UnCondBrIter != MBB.end() && 3943 MBB.isLayoutSuccessor(TargetBB)) { 3944 // If we can modify the code and it ends in something like: 3945 // 3946 // jCC L1 3947 // jmp L2 3948 // L1: 3949 // ... 3950 // L2: 3951 // 3952 // Then we can change this to: 3953 // 3954 // jnCC L2 3955 // L1: 3956 // ... 3957 // L2: 3958 // 3959 // Which is a bit more efficient. 3960 // We conditionally jump to the fall-through block. 3961 BranchCode = GetOppositeBranchCondition(BranchCode); 3962 unsigned JNCC = GetCondBranchFromCond(BranchCode); 3963 MachineBasicBlock::iterator OldInst = I; 3964 3965 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 3966 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 3967 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1)) 3968 .addMBB(TargetBB); 3969 3970 OldInst->eraseFromParent(); 3971 UnCondBrIter->eraseFromParent(); 3972 3973 // Restart the analysis. 3974 UnCondBrIter = MBB.end(); 3975 I = MBB.end(); 3976 continue; 3977 } 3978 3979 FBB = TBB; 3980 TBB = I->getOperand(0).getMBB(); 3981 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 3982 CondBranches.push_back(I); 3983 continue; 3984 } 3985 3986 // Handle subsequent conditional branches. Only handle the case where all 3987 // conditional branches branch to the same destination and their condition 3988 // opcodes fit one of the special multi-branch idioms. 3989 assert(Cond.size() == 1); 3990 assert(TBB); 3991 3992 // Only handle the case where all conditional branches branch to the same 3993 // destination. 3994 if (TBB != I->getOperand(0).getMBB()) 3995 return true; 3996 3997 // If the conditions are the same, we can leave them alone. 3998 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 3999 if (OldBranchCode == BranchCode) 4000 continue; 4001 4002 // If they differ, see if they fit one of the known patterns. Theoretically, 4003 // we could handle more patterns here, but we shouldn't expect to see them 4004 // if instruction selection has done a reasonable job. 4005 if ((OldBranchCode == X86::COND_NP && 4006 BranchCode == X86::COND_E) || 4007 (OldBranchCode == X86::COND_E && 4008 BranchCode == X86::COND_NP)) 4009 BranchCode = X86::COND_NP_OR_E; 4010 else if ((OldBranchCode == X86::COND_P && 4011 BranchCode == X86::COND_NE) || 4012 (OldBranchCode == X86::COND_NE && 4013 BranchCode == X86::COND_P)) 4014 BranchCode = X86::COND_NE_OR_P; 4015 else 4016 return true; 4017 4018 // Update the MachineOperand. 4019 Cond[0].setImm(BranchCode); 4020 CondBranches.push_back(I); 4021 } 4022 4023 return false; 4024 } 4025 4026 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 4027 MachineBasicBlock *&TBB, 4028 MachineBasicBlock *&FBB, 4029 SmallVectorImpl<MachineOperand> &Cond, 4030 bool AllowModify) const { 4031 SmallVector<MachineInstr *, 4> CondBranches; 4032 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify); 4033 } 4034 4035 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB, 4036 MachineBranchPredicate &MBP, 4037 bool AllowModify) const { 4038 using namespace std::placeholders; 4039 4040 SmallVector<MachineOperand, 4> Cond; 4041 SmallVector<MachineInstr *, 4> CondBranches; 4042 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches, 4043 AllowModify)) 4044 return true; 4045 4046 if (Cond.size() != 1) 4047 return true; 4048 4049 assert(MBP.TrueDest && "expected!"); 4050 4051 if (!MBP.FalseDest) 4052 MBP.FalseDest = MBB.getNextNode(); 4053 4054 const TargetRegisterInfo *TRI = &getRegisterInfo(); 4055 4056 MachineInstr *ConditionDef = nullptr; 4057 bool SingleUseCondition = true; 4058 4059 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) { 4060 if (I->modifiesRegister(X86::EFLAGS, TRI)) { 4061 ConditionDef = &*I; 4062 break; 4063 } 4064 4065 if (I->readsRegister(X86::EFLAGS, TRI)) 4066 SingleUseCondition = false; 4067 } 4068 4069 if (!ConditionDef) 4070 return true; 4071 4072 if (SingleUseCondition) { 4073 for (auto *Succ : MBB.successors()) 4074 if (Succ->isLiveIn(X86::EFLAGS)) 4075 SingleUseCondition = false; 4076 } 4077 4078 MBP.ConditionDef = ConditionDef; 4079 MBP.SingleUseCondition = SingleUseCondition; 4080 4081 // Currently we only recognize the simple pattern: 4082 // 4083 // test %reg, %reg 4084 // je %label 4085 // 4086 const unsigned TestOpcode = 4087 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr; 4088 4089 if (ConditionDef->getOpcode() == TestOpcode && 4090 ConditionDef->getNumOperands() == 3 && 4091 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) && 4092 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) { 4093 MBP.LHS = ConditionDef->getOperand(0); 4094 MBP.RHS = MachineOperand::CreateImm(0); 4095 MBP.Predicate = Cond[0].getImm() == X86::COND_NE 4096 ? MachineBranchPredicate::PRED_NE 4097 : MachineBranchPredicate::PRED_EQ; 4098 return false; 4099 } 4100 4101 return true; 4102 } 4103 4104 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 4105 MachineBasicBlock::iterator I = MBB.end(); 4106 unsigned Count = 0; 4107 4108 while (I != MBB.begin()) { 4109 --I; 4110 if (I->isDebugValue()) 4111 continue; 4112 if (I->getOpcode() != X86::JMP_1 && 4113 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 4114 break; 4115 // Remove the branch. 4116 I->eraseFromParent(); 4117 I = MBB.end(); 4118 ++Count; 4119 } 4120 4121 return Count; 4122 } 4123 4124 unsigned 4125 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 4126 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 4127 DebugLoc DL) const { 4128 // Shouldn't be a fall through. 4129 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 4130 assert((Cond.size() == 1 || Cond.size() == 0) && 4131 "X86 branch conditions have one component!"); 4132 4133 if (Cond.empty()) { 4134 // Unconditional branch? 4135 assert(!FBB && "Unconditional branch with multiple successors!"); 4136 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB); 4137 return 1; 4138 } 4139 4140 // Conditional branch. 4141 unsigned Count = 0; 4142 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 4143 switch (CC) { 4144 case X86::COND_NP_OR_E: 4145 // Synthesize NP_OR_E with two branches. 4146 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB); 4147 ++Count; 4148 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB); 4149 ++Count; 4150 break; 4151 case X86::COND_NE_OR_P: 4152 // Synthesize NE_OR_P with two branches. 4153 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB); 4154 ++Count; 4155 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB); 4156 ++Count; 4157 break; 4158 default: { 4159 unsigned Opc = GetCondBranchFromCond(CC); 4160 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 4161 ++Count; 4162 } 4163 } 4164 if (FBB) { 4165 // Two-way Conditional branch. Insert the second branch. 4166 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB); 4167 ++Count; 4168 } 4169 return Count; 4170 } 4171 4172 bool X86InstrInfo:: 4173 canInsertSelect(const MachineBasicBlock &MBB, 4174 ArrayRef<MachineOperand> Cond, 4175 unsigned TrueReg, unsigned FalseReg, 4176 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 4177 // Not all subtargets have cmov instructions. 4178 if (!Subtarget.hasCMov()) 4179 return false; 4180 if (Cond.size() != 1) 4181 return false; 4182 // We cannot do the composite conditions, at least not in SSA form. 4183 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 4184 return false; 4185 4186 // Check register classes. 4187 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 4188 const TargetRegisterClass *RC = 4189 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 4190 if (!RC) 4191 return false; 4192 4193 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 4194 if (X86::GR16RegClass.hasSubClassEq(RC) || 4195 X86::GR32RegClass.hasSubClassEq(RC) || 4196 X86::GR64RegClass.hasSubClassEq(RC)) { 4197 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 4198 // Bridge. Probably Ivy Bridge as well. 4199 CondCycles = 2; 4200 TrueCycles = 2; 4201 FalseCycles = 2; 4202 return true; 4203 } 4204 4205 // Can't do vectors. 4206 return false; 4207 } 4208 4209 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 4210 MachineBasicBlock::iterator I, DebugLoc DL, 4211 unsigned DstReg, ArrayRef<MachineOperand> Cond, 4212 unsigned TrueReg, unsigned FalseReg) const { 4213 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 4214 assert(Cond.size() == 1 && "Invalid Cond array"); 4215 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 4216 MRI.getRegClass(DstReg)->getSize(), 4217 false/*HasMemoryOperand*/); 4218 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 4219 } 4220 4221 /// Test if the given register is a physical h register. 4222 static bool isHReg(unsigned Reg) { 4223 return X86::GR8_ABCD_HRegClass.contains(Reg); 4224 } 4225 4226 // Try and copy between VR128/VR64 and GR64 registers. 4227 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 4228 const X86Subtarget &Subtarget) { 4229 4230 // SrcReg(VR128) -> DestReg(GR64) 4231 // SrcReg(VR64) -> DestReg(GR64) 4232 // SrcReg(GR64) -> DestReg(VR128) 4233 // SrcReg(GR64) -> DestReg(VR64) 4234 4235 bool HasAVX = Subtarget.hasAVX(); 4236 bool HasAVX512 = Subtarget.hasAVX512(); 4237 if (X86::GR64RegClass.contains(DestReg)) { 4238 if (X86::VR128XRegClass.contains(SrcReg)) 4239 // Copy from a VR128 register to a GR64 register. 4240 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr : 4241 X86::MOVPQIto64rr); 4242 if (X86::VR64RegClass.contains(SrcReg)) 4243 // Copy from a VR64 register to a GR64 register. 4244 return X86::MMX_MOVD64from64rr; 4245 } else if (X86::GR64RegClass.contains(SrcReg)) { 4246 // Copy from a GR64 register to a VR128 register. 4247 if (X86::VR128XRegClass.contains(DestReg)) 4248 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr : 4249 X86::MOV64toPQIrr); 4250 // Copy from a GR64 register to a VR64 register. 4251 if (X86::VR64RegClass.contains(DestReg)) 4252 return X86::MMX_MOVD64to64rr; 4253 } 4254 4255 // SrcReg(FR32) -> DestReg(GR32) 4256 // SrcReg(GR32) -> DestReg(FR32) 4257 4258 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg)) 4259 // Copy from a FR32 register to a GR32 register. 4260 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr); 4261 4262 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 4263 // Copy from a GR32 register to a FR32 register. 4264 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr); 4265 return 0; 4266 } 4267 4268 static bool MaskRegClassContains(unsigned Reg) { 4269 return X86::VK8RegClass.contains(Reg) || 4270 X86::VK16RegClass.contains(Reg) || 4271 X86::VK32RegClass.contains(Reg) || 4272 X86::VK64RegClass.contains(Reg) || 4273 X86::VK1RegClass.contains(Reg); 4274 } 4275 4276 static bool GRRegClassContains(unsigned Reg) { 4277 return X86::GR64RegClass.contains(Reg) || 4278 X86::GR32RegClass.contains(Reg) || 4279 X86::GR16RegClass.contains(Reg) || 4280 X86::GR8RegClass.contains(Reg); 4281 } 4282 static 4283 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) { 4284 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) { 4285 DestReg = getX86SubSuperRegister(DestReg, MVT::i32); 4286 return X86::KMOVBrk; 4287 } 4288 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) { 4289 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32); 4290 return X86::KMOVBkr; 4291 } 4292 return 0; 4293 } 4294 4295 static 4296 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) { 4297 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg)) 4298 return X86::KMOVQkk; 4299 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg)) 4300 return X86::KMOVDrk; 4301 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg)) 4302 return X86::KMOVQrk; 4303 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 4304 return X86::KMOVDkr; 4305 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg)) 4306 return X86::KMOVQkr; 4307 return 0; 4308 } 4309 4310 static 4311 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg, 4312 const X86Subtarget &Subtarget) 4313 { 4314 if (Subtarget.hasDQI()) 4315 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg)) 4316 return Opc; 4317 if (Subtarget.hasBWI()) 4318 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg)) 4319 return Opc; 4320 if (X86::VR128XRegClass.contains(DestReg, SrcReg) || 4321 X86::VR256XRegClass.contains(DestReg, SrcReg) || 4322 X86::VR512RegClass.contains(DestReg, SrcReg)) { 4323 DestReg = get512BitSuperRegister(DestReg); 4324 SrcReg = get512BitSuperRegister(SrcReg); 4325 return X86::VMOVAPSZrr; 4326 } 4327 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) 4328 return X86::KMOVWkk; 4329 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) { 4330 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32); 4331 return X86::KMOVWkr; 4332 } 4333 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) { 4334 DestReg = getX86SubSuperRegister(DestReg, MVT::i32); 4335 return X86::KMOVWrk; 4336 } 4337 return 0; 4338 } 4339 4340 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 4341 MachineBasicBlock::iterator MI, DebugLoc DL, 4342 unsigned DestReg, unsigned SrcReg, 4343 bool KillSrc) const { 4344 // First deal with the normal symmetric copies. 4345 bool HasAVX = Subtarget.hasAVX(); 4346 bool HasAVX512 = Subtarget.hasAVX512(); 4347 unsigned Opc = 0; 4348 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 4349 Opc = X86::MOV64rr; 4350 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 4351 Opc = X86::MOV32rr; 4352 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 4353 Opc = X86::MOV16rr; 4354 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 4355 // Copying to or from a physical H register on x86-64 requires a NOREX 4356 // move. Otherwise use a normal move. 4357 if ((isHReg(DestReg) || isHReg(SrcReg)) && 4358 Subtarget.is64Bit()) { 4359 Opc = X86::MOV8rr_NOREX; 4360 // Both operands must be encodable without an REX prefix. 4361 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 4362 "8-bit H register can not be copied outside GR8_NOREX"); 4363 } else 4364 Opc = X86::MOV8rr; 4365 } 4366 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 4367 Opc = X86::MMX_MOVQ64rr; 4368 else if (HasAVX512) 4369 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget); 4370 else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 4371 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 4372 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 4373 Opc = X86::VMOVAPSYrr; 4374 if (!Opc) 4375 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget); 4376 4377 if (Opc) { 4378 BuildMI(MBB, MI, DL, get(Opc), DestReg) 4379 .addReg(SrcReg, getKillRegState(KillSrc)); 4380 return; 4381 } 4382 4383 bool FromEFLAGS = SrcReg == X86::EFLAGS; 4384 bool ToEFLAGS = DestReg == X86::EFLAGS; 4385 int Reg = FromEFLAGS ? DestReg : SrcReg; 4386 bool is32 = X86::GR32RegClass.contains(Reg); 4387 bool is64 = X86::GR64RegClass.contains(Reg); 4388 4389 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) { 4390 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr; 4391 int Push = is64 ? X86::PUSH64r : X86::PUSH32r; 4392 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32; 4393 int Pop = is64 ? X86::POP64r : X86::POP32r; 4394 int PopF = is64 ? X86::POPF64 : X86::POPF32; 4395 int AX = is64 ? X86::RAX : X86::EAX; 4396 4397 if (!Subtarget.hasLAHFSAHF()) { 4398 assert(is64 && "Not having LAHF/SAHF only happens on 64-bit."); 4399 // Moving EFLAGS to / from another register requires a push and a pop. 4400 // Notice that we have to adjust the stack if we don't want to clobber the 4401 // first frame index. See X86FrameLowering.cpp - clobbersTheStack. 4402 if (FromEFLAGS) { 4403 BuildMI(MBB, MI, DL, get(PushF)); 4404 BuildMI(MBB, MI, DL, get(Pop), DestReg); 4405 } 4406 if (ToEFLAGS) { 4407 BuildMI(MBB, MI, DL, get(Push)) 4408 .addReg(SrcReg, getKillRegState(KillSrc)); 4409 BuildMI(MBB, MI, DL, get(PopF)); 4410 } 4411 return; 4412 } 4413 4414 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is 4415 // inefficient. Instead: 4416 // - Save the overflow flag OF into AL using SETO, and restore it using a 4417 // signed 8-bit addition of AL and INT8_MAX. 4418 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH 4419 // using LAHF/SAHF. 4420 // - When RAX/EAX is live and isn't the destination register, make sure it 4421 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring 4422 // the flags. 4423 // This approach is ~2.25x faster than using PUSHF/POPF. 4424 // 4425 // This is still somewhat inefficient because we don't know which flags are 4426 // actually live inside EFLAGS. Were we able to do a single SETcc instead of 4427 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster. 4428 // 4429 // PUSHF/POPF is also potentially incorrect because it affects other flags 4430 // such as TF/IF/DF, which LLVM doesn't model. 4431 // 4432 // Notice that we have to adjust the stack if we don't want to clobber the 4433 // first frame index. See X86FrameLowering.cpp - clobbersTheStack. 4434 4435 4436 bool AXDead = (Reg == AX); 4437 // FIXME: The above could figure out that AX is dead in more cases with: 4438 // || (MachineBasicBlock::LQR_Dead == 4439 // MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI)); 4440 // 4441 // Unfortunately this is slightly broken, see PR24535 and the likely 4442 // related PR25033 PR24991 PR24992 PR25201. These issues seem to 4443 // showcase sub-register / super-register confusion: a previous kill 4444 // of AH but no kill of AL leads computeRegisterLiveness to 4445 // erroneously conclude that AX is dead. 4446 // 4447 // Once fixed, also update cmpxchg-clobber-flags.ll and 4448 // peephole-na-phys-copy-folding.ll. 4449 4450 if (!AXDead) 4451 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true)); 4452 if (FromEFLAGS) { 4453 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL); 4454 BuildMI(MBB, MI, DL, get(X86::LAHF)); 4455 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX); 4456 } 4457 if (ToEFLAGS) { 4458 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc)); 4459 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL) 4460 .addReg(X86::AL) 4461 .addImm(INT8_MAX); 4462 BuildMI(MBB, MI, DL, get(X86::SAHF)); 4463 } 4464 if (!AXDead) 4465 BuildMI(MBB, MI, DL, get(Pop), AX); 4466 return; 4467 } 4468 4469 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 4470 << " to " << RI.getName(DestReg) << '\n'); 4471 llvm_unreachable("Cannot emit physreg copy instruction"); 4472 } 4473 4474 static unsigned getLoadStoreRegOpcode(unsigned Reg, 4475 const TargetRegisterClass *RC, 4476 bool isStackAligned, 4477 const X86Subtarget &STI, 4478 bool load) { 4479 if (STI.hasAVX512()) { 4480 if (X86::VK8RegClass.hasSubClassEq(RC) || 4481 X86::VK16RegClass.hasSubClassEq(RC)) 4482 return load ? X86::KMOVWkm : X86::KMOVWmk; 4483 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC)) 4484 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr; 4485 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC)) 4486 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr; 4487 if (X86::VR512RegClass.hasSubClassEq(RC)) 4488 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 4489 } 4490 4491 bool HasAVX = STI.hasAVX(); 4492 switch (RC->getSize()) { 4493 default: 4494 llvm_unreachable("Unknown spill size"); 4495 case 1: 4496 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 4497 if (STI.is64Bit()) 4498 // Copying to or from a physical H register on x86-64 requires a NOREX 4499 // move. Otherwise use a normal move. 4500 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 4501 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 4502 return load ? X86::MOV8rm : X86::MOV8mr; 4503 case 2: 4504 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 4505 return load ? X86::MOV16rm : X86::MOV16mr; 4506 case 4: 4507 if (X86::GR32RegClass.hasSubClassEq(RC)) 4508 return load ? X86::MOV32rm : X86::MOV32mr; 4509 if (X86::FR32RegClass.hasSubClassEq(RC)) 4510 return load ? 4511 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 4512 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 4513 if (X86::RFP32RegClass.hasSubClassEq(RC)) 4514 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 4515 llvm_unreachable("Unknown 4-byte regclass"); 4516 case 8: 4517 if (X86::GR64RegClass.hasSubClassEq(RC)) 4518 return load ? X86::MOV64rm : X86::MOV64mr; 4519 if (X86::FR64RegClass.hasSubClassEq(RC)) 4520 return load ? 4521 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 4522 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 4523 if (X86::VR64RegClass.hasSubClassEq(RC)) 4524 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 4525 if (X86::RFP64RegClass.hasSubClassEq(RC)) 4526 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 4527 llvm_unreachable("Unknown 8-byte regclass"); 4528 case 10: 4529 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 4530 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 4531 case 16: { 4532 assert((X86::VR128RegClass.hasSubClassEq(RC) || 4533 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass"); 4534 // If stack is realigned we can use aligned stores. 4535 if (isStackAligned) 4536 return load ? 4537 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 4538 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 4539 else 4540 return load ? 4541 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 4542 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 4543 } 4544 case 32: 4545 assert((X86::VR256RegClass.hasSubClassEq(RC) || 4546 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass"); 4547 // If stack is realigned we can use aligned stores. 4548 if (isStackAligned) 4549 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 4550 else 4551 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 4552 case 64: 4553 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); 4554 if (isStackAligned) 4555 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; 4556 else 4557 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 4558 } 4559 } 4560 4561 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg, 4562 unsigned &Offset, 4563 const TargetRegisterInfo *TRI) const { 4564 const MCInstrDesc &Desc = MemOp->getDesc(); 4565 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode()); 4566 if (MemRefBegin < 0) 4567 return false; 4568 4569 MemRefBegin += X86II::getOperandBias(Desc); 4570 4571 BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg(); 4572 if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1) 4573 return false; 4574 4575 if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != 4576 X86::NoRegister) 4577 return false; 4578 4579 const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp); 4580 4581 // Displacement can be symbolic 4582 if (!DispMO.isImm()) 4583 return false; 4584 4585 Offset = DispMO.getImm(); 4586 4587 return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() == 4588 X86::NoRegister); 4589 } 4590 4591 static unsigned getStoreRegOpcode(unsigned SrcReg, 4592 const TargetRegisterClass *RC, 4593 bool isStackAligned, 4594 const X86Subtarget &STI) { 4595 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false); 4596 } 4597 4598 4599 static unsigned getLoadRegOpcode(unsigned DestReg, 4600 const TargetRegisterClass *RC, 4601 bool isStackAligned, 4602 const X86Subtarget &STI) { 4603 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true); 4604 } 4605 4606 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 4607 MachineBasicBlock::iterator MI, 4608 unsigned SrcReg, bool isKill, int FrameIdx, 4609 const TargetRegisterClass *RC, 4610 const TargetRegisterInfo *TRI) const { 4611 const MachineFunction &MF = *MBB.getParent(); 4612 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 4613 "Stack slot too small for store"); 4614 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 4615 bool isAligned = 4616 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) || 4617 RI.canRealignStack(MF); 4618 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 4619 DebugLoc DL = MBB.findDebugLoc(MI); 4620 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 4621 .addReg(SrcReg, getKillRegState(isKill)); 4622 } 4623 4624 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 4625 bool isKill, 4626 SmallVectorImpl<MachineOperand> &Addr, 4627 const TargetRegisterClass *RC, 4628 MachineInstr::mmo_iterator MMOBegin, 4629 MachineInstr::mmo_iterator MMOEnd, 4630 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4631 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 4632 bool isAligned = MMOBegin != MMOEnd && 4633 (*MMOBegin)->getAlignment() >= Alignment; 4634 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 4635 DebugLoc DL; 4636 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 4637 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 4638 MIB.addOperand(Addr[i]); 4639 MIB.addReg(SrcReg, getKillRegState(isKill)); 4640 (*MIB).setMemRefs(MMOBegin, MMOEnd); 4641 NewMIs.push_back(MIB); 4642 } 4643 4644 4645 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 4646 MachineBasicBlock::iterator MI, 4647 unsigned DestReg, int FrameIdx, 4648 const TargetRegisterClass *RC, 4649 const TargetRegisterInfo *TRI) const { 4650 const MachineFunction &MF = *MBB.getParent(); 4651 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 4652 bool isAligned = 4653 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) || 4654 RI.canRealignStack(MF); 4655 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 4656 DebugLoc DL = MBB.findDebugLoc(MI); 4657 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 4658 } 4659 4660 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 4661 SmallVectorImpl<MachineOperand> &Addr, 4662 const TargetRegisterClass *RC, 4663 MachineInstr::mmo_iterator MMOBegin, 4664 MachineInstr::mmo_iterator MMOEnd, 4665 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4666 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 4667 bool isAligned = MMOBegin != MMOEnd && 4668 (*MMOBegin)->getAlignment() >= Alignment; 4669 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 4670 DebugLoc DL; 4671 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 4672 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 4673 MIB.addOperand(Addr[i]); 4674 (*MIB).setMemRefs(MMOBegin, MMOEnd); 4675 NewMIs.push_back(MIB); 4676 } 4677 4678 bool X86InstrInfo:: 4679 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 4680 int &CmpMask, int &CmpValue) const { 4681 switch (MI->getOpcode()) { 4682 default: break; 4683 case X86::CMP64ri32: 4684 case X86::CMP64ri8: 4685 case X86::CMP32ri: 4686 case X86::CMP32ri8: 4687 case X86::CMP16ri: 4688 case X86::CMP16ri8: 4689 case X86::CMP8ri: 4690 SrcReg = MI->getOperand(0).getReg(); 4691 SrcReg2 = 0; 4692 CmpMask = ~0; 4693 CmpValue = MI->getOperand(1).getImm(); 4694 return true; 4695 // A SUB can be used to perform comparison. 4696 case X86::SUB64rm: 4697 case X86::SUB32rm: 4698 case X86::SUB16rm: 4699 case X86::SUB8rm: 4700 SrcReg = MI->getOperand(1).getReg(); 4701 SrcReg2 = 0; 4702 CmpMask = ~0; 4703 CmpValue = 0; 4704 return true; 4705 case X86::SUB64rr: 4706 case X86::SUB32rr: 4707 case X86::SUB16rr: 4708 case X86::SUB8rr: 4709 SrcReg = MI->getOperand(1).getReg(); 4710 SrcReg2 = MI->getOperand(2).getReg(); 4711 CmpMask = ~0; 4712 CmpValue = 0; 4713 return true; 4714 case X86::SUB64ri32: 4715 case X86::SUB64ri8: 4716 case X86::SUB32ri: 4717 case X86::SUB32ri8: 4718 case X86::SUB16ri: 4719 case X86::SUB16ri8: 4720 case X86::SUB8ri: 4721 SrcReg = MI->getOperand(1).getReg(); 4722 SrcReg2 = 0; 4723 CmpMask = ~0; 4724 CmpValue = MI->getOperand(2).getImm(); 4725 return true; 4726 case X86::CMP64rr: 4727 case X86::CMP32rr: 4728 case X86::CMP16rr: 4729 case X86::CMP8rr: 4730 SrcReg = MI->getOperand(0).getReg(); 4731 SrcReg2 = MI->getOperand(1).getReg(); 4732 CmpMask = ~0; 4733 CmpValue = 0; 4734 return true; 4735 case X86::TEST8rr: 4736 case X86::TEST16rr: 4737 case X86::TEST32rr: 4738 case X86::TEST64rr: 4739 SrcReg = MI->getOperand(0).getReg(); 4740 if (MI->getOperand(1).getReg() != SrcReg) return false; 4741 // Compare against zero. 4742 SrcReg2 = 0; 4743 CmpMask = ~0; 4744 CmpValue = 0; 4745 return true; 4746 } 4747 return false; 4748 } 4749 4750 /// Check whether the first instruction, whose only 4751 /// purpose is to update flags, can be made redundant. 4752 /// CMPrr can be made redundant by SUBrr if the operands are the same. 4753 /// This function can be extended later on. 4754 /// SrcReg, SrcRegs: register operands for FlagI. 4755 /// ImmValue: immediate for FlagI if it takes an immediate. 4756 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 4757 unsigned SrcReg2, int ImmValue, 4758 MachineInstr *OI) { 4759 if (((FlagI->getOpcode() == X86::CMP64rr && 4760 OI->getOpcode() == X86::SUB64rr) || 4761 (FlagI->getOpcode() == X86::CMP32rr && 4762 OI->getOpcode() == X86::SUB32rr)|| 4763 (FlagI->getOpcode() == X86::CMP16rr && 4764 OI->getOpcode() == X86::SUB16rr)|| 4765 (FlagI->getOpcode() == X86::CMP8rr && 4766 OI->getOpcode() == X86::SUB8rr)) && 4767 ((OI->getOperand(1).getReg() == SrcReg && 4768 OI->getOperand(2).getReg() == SrcReg2) || 4769 (OI->getOperand(1).getReg() == SrcReg2 && 4770 OI->getOperand(2).getReg() == SrcReg))) 4771 return true; 4772 4773 if (((FlagI->getOpcode() == X86::CMP64ri32 && 4774 OI->getOpcode() == X86::SUB64ri32) || 4775 (FlagI->getOpcode() == X86::CMP64ri8 && 4776 OI->getOpcode() == X86::SUB64ri8) || 4777 (FlagI->getOpcode() == X86::CMP32ri && 4778 OI->getOpcode() == X86::SUB32ri) || 4779 (FlagI->getOpcode() == X86::CMP32ri8 && 4780 OI->getOpcode() == X86::SUB32ri8) || 4781 (FlagI->getOpcode() == X86::CMP16ri && 4782 OI->getOpcode() == X86::SUB16ri) || 4783 (FlagI->getOpcode() == X86::CMP16ri8 && 4784 OI->getOpcode() == X86::SUB16ri8) || 4785 (FlagI->getOpcode() == X86::CMP8ri && 4786 OI->getOpcode() == X86::SUB8ri)) && 4787 OI->getOperand(1).getReg() == SrcReg && 4788 OI->getOperand(2).getImm() == ImmValue) 4789 return true; 4790 return false; 4791 } 4792 4793 /// Check whether the definition can be converted 4794 /// to remove a comparison against zero. 4795 inline static bool isDefConvertible(MachineInstr *MI) { 4796 switch (MI->getOpcode()) { 4797 default: return false; 4798 4799 // The shift instructions only modify ZF if their shift count is non-zero. 4800 // N.B.: The processor truncates the shift count depending on the encoding. 4801 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri: 4802 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri: 4803 return getTruncatedShiftCount(MI, 2) != 0; 4804 4805 // Some left shift instructions can be turned into LEA instructions but only 4806 // if their flags aren't used. Avoid transforming such instructions. 4807 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{ 4808 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 4809 if (isTruncatedShiftCountForLEA(ShAmt)) return false; 4810 return ShAmt != 0; 4811 } 4812 4813 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8: 4814 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8: 4815 return getTruncatedShiftCount(MI, 3) != 0; 4816 4817 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 4818 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 4819 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 4820 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 4821 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 4822 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 4823 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 4824 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 4825 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 4826 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 4827 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 4828 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 4829 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 4830 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 4831 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 4832 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 4833 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 4834 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 4835 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 4836 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 4837 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 4838 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 4839 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 4840 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 4841 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 4842 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 4843 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 4844 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: 4845 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1: 4846 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1: 4847 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1: 4848 case X86::ADC32ri: case X86::ADC32ri8: 4849 case X86::ADC32rr: case X86::ADC64ri32: 4850 case X86::ADC64ri8: case X86::ADC64rr: 4851 case X86::SBB32ri: case X86::SBB32ri8: 4852 case X86::SBB32rr: case X86::SBB64ri32: 4853 case X86::SBB64ri8: case X86::SBB64rr: 4854 case X86::ANDN32rr: case X86::ANDN32rm: 4855 case X86::ANDN64rr: case X86::ANDN64rm: 4856 case X86::BEXTR32rr: case X86::BEXTR64rr: 4857 case X86::BEXTR32rm: case X86::BEXTR64rm: 4858 case X86::BLSI32rr: case X86::BLSI32rm: 4859 case X86::BLSI64rr: case X86::BLSI64rm: 4860 case X86::BLSMSK32rr:case X86::BLSMSK32rm: 4861 case X86::BLSMSK64rr:case X86::BLSMSK64rm: 4862 case X86::BLSR32rr: case X86::BLSR32rm: 4863 case X86::BLSR64rr: case X86::BLSR64rm: 4864 case X86::BZHI32rr: case X86::BZHI32rm: 4865 case X86::BZHI64rr: case X86::BZHI64rm: 4866 case X86::LZCNT16rr: case X86::LZCNT16rm: 4867 case X86::LZCNT32rr: case X86::LZCNT32rm: 4868 case X86::LZCNT64rr: case X86::LZCNT64rm: 4869 case X86::POPCNT16rr:case X86::POPCNT16rm: 4870 case X86::POPCNT32rr:case X86::POPCNT32rm: 4871 case X86::POPCNT64rr:case X86::POPCNT64rm: 4872 case X86::TZCNT16rr: case X86::TZCNT16rm: 4873 case X86::TZCNT32rr: case X86::TZCNT32rm: 4874 case X86::TZCNT64rr: case X86::TZCNT64rm: 4875 return true; 4876 } 4877 } 4878 4879 /// Check whether the use can be converted to remove a comparison against zero. 4880 static X86::CondCode isUseDefConvertible(MachineInstr *MI) { 4881 switch (MI->getOpcode()) { 4882 default: return X86::COND_INVALID; 4883 case X86::LZCNT16rr: case X86::LZCNT16rm: 4884 case X86::LZCNT32rr: case X86::LZCNT32rm: 4885 case X86::LZCNT64rr: case X86::LZCNT64rm: 4886 return X86::COND_B; 4887 case X86::POPCNT16rr:case X86::POPCNT16rm: 4888 case X86::POPCNT32rr:case X86::POPCNT32rm: 4889 case X86::POPCNT64rr:case X86::POPCNT64rm: 4890 return X86::COND_E; 4891 case X86::TZCNT16rr: case X86::TZCNT16rm: 4892 case X86::TZCNT32rr: case X86::TZCNT32rm: 4893 case X86::TZCNT64rr: case X86::TZCNT64rm: 4894 return X86::COND_B; 4895 } 4896 } 4897 4898 /// Check if there exists an earlier instruction that 4899 /// operates on the same source operands and sets flags in the same way as 4900 /// Compare; remove Compare if possible. 4901 bool X86InstrInfo:: 4902 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 4903 int CmpMask, int CmpValue, 4904 const MachineRegisterInfo *MRI) const { 4905 // Check whether we can replace SUB with CMP. 4906 unsigned NewOpcode = 0; 4907 switch (CmpInstr->getOpcode()) { 4908 default: break; 4909 case X86::SUB64ri32: 4910 case X86::SUB64ri8: 4911 case X86::SUB32ri: 4912 case X86::SUB32ri8: 4913 case X86::SUB16ri: 4914 case X86::SUB16ri8: 4915 case X86::SUB8ri: 4916 case X86::SUB64rm: 4917 case X86::SUB32rm: 4918 case X86::SUB16rm: 4919 case X86::SUB8rm: 4920 case X86::SUB64rr: 4921 case X86::SUB32rr: 4922 case X86::SUB16rr: 4923 case X86::SUB8rr: { 4924 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 4925 return false; 4926 // There is no use of the destination register, we can replace SUB with CMP. 4927 switch (CmpInstr->getOpcode()) { 4928 default: llvm_unreachable("Unreachable!"); 4929 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 4930 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 4931 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 4932 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 4933 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 4934 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 4935 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 4936 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 4937 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 4938 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 4939 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 4940 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 4941 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 4942 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 4943 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 4944 } 4945 CmpInstr->setDesc(get(NewOpcode)); 4946 CmpInstr->RemoveOperand(0); 4947 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 4948 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 4949 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 4950 return false; 4951 } 4952 } 4953 4954 // Get the unique definition of SrcReg. 4955 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 4956 if (!MI) return false; 4957 4958 // CmpInstr is the first instruction of the BB. 4959 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 4960 4961 // If we are comparing against zero, check whether we can use MI to update 4962 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 4963 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 4964 if (IsCmpZero && MI->getParent() != CmpInstr->getParent()) 4965 return false; 4966 4967 // If we have a use of the source register between the def and our compare 4968 // instruction we can eliminate the compare iff the use sets EFLAGS in the 4969 // right way. 4970 bool ShouldUpdateCC = false; 4971 X86::CondCode NewCC = X86::COND_INVALID; 4972 if (IsCmpZero && !isDefConvertible(MI)) { 4973 // Scan forward from the use until we hit the use we're looking for or the 4974 // compare instruction. 4975 for (MachineBasicBlock::iterator J = MI;; ++J) { 4976 // Do we have a convertible instruction? 4977 NewCC = isUseDefConvertible(J); 4978 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() && 4979 J->getOperand(1).getReg() == SrcReg) { 4980 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"); 4981 ShouldUpdateCC = true; // Update CC later on. 4982 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going 4983 // with the new def. 4984 MI = Def = J; 4985 break; 4986 } 4987 4988 if (J == I) 4989 return false; 4990 } 4991 } 4992 4993 // We are searching for an earlier instruction that can make CmpInstr 4994 // redundant and that instruction will be saved in Sub. 4995 MachineInstr *Sub = nullptr; 4996 const TargetRegisterInfo *TRI = &getRegisterInfo(); 4997 4998 // We iterate backward, starting from the instruction before CmpInstr and 4999 // stop when reaching the definition of a source register or done with the BB. 5000 // RI points to the instruction before CmpInstr. 5001 // If the definition is in this basic block, RE points to the definition; 5002 // otherwise, RE is the rend of the basic block. 5003 MachineBasicBlock::reverse_iterator 5004 RI = MachineBasicBlock::reverse_iterator(I), 5005 RE = CmpInstr->getParent() == MI->getParent() ? 5006 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 5007 CmpInstr->getParent()->rend(); 5008 MachineInstr *Movr0Inst = nullptr; 5009 for (; RI != RE; ++RI) { 5010 MachineInstr *Instr = &*RI; 5011 // Check whether CmpInstr can be made redundant by the current instruction. 5012 if (!IsCmpZero && 5013 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 5014 Sub = Instr; 5015 break; 5016 } 5017 5018 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 5019 Instr->readsRegister(X86::EFLAGS, TRI)) { 5020 // This instruction modifies or uses EFLAGS. 5021 5022 // MOV32r0 etc. are implemented with xor which clobbers condition code. 5023 // They are safe to move up, if the definition to EFLAGS is dead and 5024 // earlier instructions do not read or write EFLAGS. 5025 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 && 5026 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 5027 Movr0Inst = Instr; 5028 continue; 5029 } 5030 5031 // We can't remove CmpInstr. 5032 return false; 5033 } 5034 } 5035 5036 // Return false if no candidates exist. 5037 if (!IsCmpZero && !Sub) 5038 return false; 5039 5040 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 5041 Sub->getOperand(2).getReg() == SrcReg); 5042 5043 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 5044 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 5045 // If we are done with the basic block, we need to check whether EFLAGS is 5046 // live-out. 5047 bool IsSafe = false; 5048 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 5049 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 5050 for (++I; I != E; ++I) { 5051 const MachineInstr &Instr = *I; 5052 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 5053 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 5054 // We should check the usage if this instruction uses and updates EFLAGS. 5055 if (!UseEFLAGS && ModifyEFLAGS) { 5056 // It is safe to remove CmpInstr if EFLAGS is updated again. 5057 IsSafe = true; 5058 break; 5059 } 5060 if (!UseEFLAGS && !ModifyEFLAGS) 5061 continue; 5062 5063 // EFLAGS is used by this instruction. 5064 X86::CondCode OldCC = X86::COND_INVALID; 5065 bool OpcIsSET = false; 5066 if (IsCmpZero || IsSwapped) { 5067 // We decode the condition code from opcode. 5068 if (Instr.isBranch()) 5069 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 5070 else { 5071 OldCC = getCondFromSETOpc(Instr.getOpcode()); 5072 if (OldCC != X86::COND_INVALID) 5073 OpcIsSET = true; 5074 else 5075 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 5076 } 5077 if (OldCC == X86::COND_INVALID) return false; 5078 } 5079 if (IsCmpZero) { 5080 switch (OldCC) { 5081 default: break; 5082 case X86::COND_A: case X86::COND_AE: 5083 case X86::COND_B: case X86::COND_BE: 5084 case X86::COND_G: case X86::COND_GE: 5085 case X86::COND_L: case X86::COND_LE: 5086 case X86::COND_O: case X86::COND_NO: 5087 // CF and OF are used, we can't perform this optimization. 5088 return false; 5089 } 5090 5091 // If we're updating the condition code check if we have to reverse the 5092 // condition. 5093 if (ShouldUpdateCC) 5094 switch (OldCC) { 5095 default: 5096 return false; 5097 case X86::COND_E: 5098 break; 5099 case X86::COND_NE: 5100 NewCC = GetOppositeBranchCondition(NewCC); 5101 break; 5102 } 5103 } else if (IsSwapped) { 5104 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 5105 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 5106 // We swap the condition code and synthesize the new opcode. 5107 NewCC = getSwappedCondition(OldCC); 5108 if (NewCC == X86::COND_INVALID) return false; 5109 } 5110 5111 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) { 5112 // Synthesize the new opcode. 5113 bool HasMemoryOperand = Instr.hasOneMemOperand(); 5114 unsigned NewOpc; 5115 if (Instr.isBranch()) 5116 NewOpc = GetCondBranchFromCond(NewCC); 5117 else if(OpcIsSET) 5118 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 5119 else { 5120 unsigned DstReg = Instr.getOperand(0).getReg(); 5121 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 5122 HasMemoryOperand); 5123 } 5124 5125 // Push the MachineInstr to OpsToUpdate. 5126 // If it is safe to remove CmpInstr, the condition code of these 5127 // instructions will be modified. 5128 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 5129 } 5130 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 5131 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 5132 IsSafe = true; 5133 break; 5134 } 5135 } 5136 5137 // If EFLAGS is not killed nor re-defined, we should check whether it is 5138 // live-out. If it is live-out, do not optimize. 5139 if ((IsCmpZero || IsSwapped) && !IsSafe) { 5140 MachineBasicBlock *MBB = CmpInstr->getParent(); 5141 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 5142 SE = MBB->succ_end(); SI != SE; ++SI) 5143 if ((*SI)->isLiveIn(X86::EFLAGS)) 5144 return false; 5145 } 5146 5147 // The instruction to be updated is either Sub or MI. 5148 Sub = IsCmpZero ? MI : Sub; 5149 // Move Movr0Inst to the appropriate place before Sub. 5150 if (Movr0Inst) { 5151 // Look backwards until we find a def that doesn't use the current EFLAGS. 5152 Def = Sub; 5153 MachineBasicBlock::reverse_iterator 5154 InsertI = MachineBasicBlock::reverse_iterator(++Def), 5155 InsertE = Sub->getParent()->rend(); 5156 for (; InsertI != InsertE; ++InsertI) { 5157 MachineInstr *Instr = &*InsertI; 5158 if (!Instr->readsRegister(X86::EFLAGS, TRI) && 5159 Instr->modifiesRegister(X86::EFLAGS, TRI)) { 5160 Sub->getParent()->remove(Movr0Inst); 5161 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr), 5162 Movr0Inst); 5163 break; 5164 } 5165 } 5166 if (InsertI == InsertE) 5167 return false; 5168 } 5169 5170 // Make sure Sub instruction defines EFLAGS and mark the def live. 5171 unsigned i = 0, e = Sub->getNumOperands(); 5172 for (; i != e; ++i) { 5173 MachineOperand &MO = Sub->getOperand(i); 5174 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) { 5175 MO.setIsDead(false); 5176 break; 5177 } 5178 } 5179 assert(i != e && "Unable to locate a def EFLAGS operand"); 5180 5181 CmpInstr->eraseFromParent(); 5182 5183 // Modify the condition code of instructions in OpsToUpdate. 5184 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 5185 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 5186 return true; 5187 } 5188 5189 /// Try to remove the load by folding it to a register 5190 /// operand at the use. We fold the load instructions if load defines a virtual 5191 /// register, the virtual register is used once in the same BB, and the 5192 /// instructions in-between do not load or store, and have no side effects. 5193 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI, 5194 const MachineRegisterInfo *MRI, 5195 unsigned &FoldAsLoadDefReg, 5196 MachineInstr *&DefMI) const { 5197 if (FoldAsLoadDefReg == 0) 5198 return nullptr; 5199 // To be conservative, if there exists another load, clear the load candidate. 5200 if (MI->mayLoad()) { 5201 FoldAsLoadDefReg = 0; 5202 return nullptr; 5203 } 5204 5205 // Check whether we can move DefMI here. 5206 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 5207 assert(DefMI); 5208 bool SawStore = false; 5209 if (!DefMI->isSafeToMove(nullptr, SawStore)) 5210 return nullptr; 5211 5212 // Collect information about virtual register operands of MI. 5213 unsigned SrcOperandId = 0; 5214 bool FoundSrcOperand = false; 5215 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 5216 MachineOperand &MO = MI->getOperand(i); 5217 if (!MO.isReg()) 5218 continue; 5219 unsigned Reg = MO.getReg(); 5220 if (Reg != FoldAsLoadDefReg) 5221 continue; 5222 // Do not fold if we have a subreg use or a def or multiple uses. 5223 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 5224 return nullptr; 5225 5226 SrcOperandId = i; 5227 FoundSrcOperand = true; 5228 } 5229 if (!FoundSrcOperand) 5230 return nullptr; 5231 5232 // Check whether we can fold the def into SrcOperandId. 5233 MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI); 5234 if (FoldMI) { 5235 FoldAsLoadDefReg = 0; 5236 return FoldMI; 5237 } 5238 5239 return nullptr; 5240 } 5241 5242 /// Expand a single-def pseudo instruction to a two-addr 5243 /// instruction with two undef reads of the register being defined. 5244 /// This is used for mapping: 5245 /// %xmm4 = V_SET0 5246 /// to: 5247 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 5248 /// 5249 static bool Expand2AddrUndef(MachineInstrBuilder &MIB, 5250 const MCInstrDesc &Desc) { 5251 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 5252 unsigned Reg = MIB->getOperand(0).getReg(); 5253 MIB->setDesc(Desc); 5254 5255 // MachineInstr::addOperand() will insert explicit operands before any 5256 // implicit operands. 5257 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 5258 // But we don't trust that. 5259 assert(MIB->getOperand(1).getReg() == Reg && 5260 MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 5261 return true; 5262 } 5263 5264 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different 5265 // code sequence is needed for other targets. 5266 static void expandLoadStackGuard(MachineInstrBuilder &MIB, 5267 const TargetInstrInfo &TII) { 5268 MachineBasicBlock &MBB = *MIB->getParent(); 5269 DebugLoc DL = MIB->getDebugLoc(); 5270 unsigned Reg = MIB->getOperand(0).getReg(); 5271 const GlobalValue *GV = 5272 cast<GlobalValue>((*MIB->memoperands_begin())->getValue()); 5273 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant; 5274 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand( 5275 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8); 5276 MachineBasicBlock::iterator I = MIB.getInstr(); 5277 5278 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1) 5279 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0) 5280 .addMemOperand(MMO); 5281 MIB->setDebugLoc(DL); 5282 MIB->setDesc(TII.get(X86::MOV64rm)); 5283 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0); 5284 } 5285 5286 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 5287 bool HasAVX = Subtarget.hasAVX(); 5288 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 5289 switch (MI->getOpcode()) { 5290 case X86::MOV32r0: 5291 return Expand2AddrUndef(MIB, get(X86::XOR32rr)); 5292 case X86::SETB_C8r: 5293 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 5294 case X86::SETB_C16r: 5295 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 5296 case X86::SETB_C32r: 5297 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 5298 case X86::SETB_C64r: 5299 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 5300 case X86::V_SET0: 5301 case X86::FsFLD0SS: 5302 case X86::FsFLD0SD: 5303 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 5304 case X86::AVX_SET0: 5305 assert(HasAVX && "AVX not supported"); 5306 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); 5307 case X86::AVX512_512_SET0: 5308 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 5309 case X86::V_SETALLONES: 5310 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 5311 case X86::AVX2_SETALLONES: 5312 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 5313 case X86::TEST8ri_NOREX: 5314 MI->setDesc(get(X86::TEST8ri)); 5315 return true; 5316 case X86::KSET0B: 5317 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr)); 5318 case X86::KSET0D: return Expand2AddrUndef(MIB, get(X86::KXORDrr)); 5319 case X86::KSET0Q: return Expand2AddrUndef(MIB, get(X86::KXORQrr)); 5320 case X86::KSET1B: 5321 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr)); 5322 case X86::KSET1D: return Expand2AddrUndef(MIB, get(X86::KXNORDrr)); 5323 case X86::KSET1Q: return Expand2AddrUndef(MIB, get(X86::KXNORQrr)); 5324 case TargetOpcode::LOAD_STACK_GUARD: 5325 expandLoadStackGuard(MIB, *this); 5326 return true; 5327 } 5328 return false; 5329 } 5330 5331 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs, 5332 int PtrOffset = 0) { 5333 unsigned NumAddrOps = MOs.size(); 5334 5335 if (NumAddrOps < 4) { 5336 // FrameIndex only - add an immediate offset (whether its zero or not). 5337 for (unsigned i = 0; i != NumAddrOps; ++i) 5338 MIB.addOperand(MOs[i]); 5339 addOffset(MIB, PtrOffset); 5340 } else { 5341 // General Memory Addressing - we need to add any offset to an existing 5342 // offset. 5343 assert(MOs.size() == 5 && "Unexpected memory operand list length"); 5344 for (unsigned i = 0; i != NumAddrOps; ++i) { 5345 const MachineOperand &MO = MOs[i]; 5346 if (i == 3 && PtrOffset != 0) { 5347 MIB.addDisp(MO, PtrOffset); 5348 } else { 5349 MIB.addOperand(MO); 5350 } 5351 } 5352 } 5353 } 5354 5355 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 5356 ArrayRef<MachineOperand> MOs, 5357 MachineBasicBlock::iterator InsertPt, 5358 MachineInstr *MI, 5359 const TargetInstrInfo &TII) { 5360 // Create the base instruction with the memory operand as the first part. 5361 // Omit the implicit operands, something BuildMI can't do. 5362 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 5363 MI->getDebugLoc(), true); 5364 MachineInstrBuilder MIB(MF, NewMI); 5365 addOperands(MIB, MOs); 5366 5367 // Loop over the rest of the ri operands, converting them over. 5368 unsigned NumOps = MI->getDesc().getNumOperands()-2; 5369 for (unsigned i = 0; i != NumOps; ++i) { 5370 MachineOperand &MO = MI->getOperand(i+2); 5371 MIB.addOperand(MO); 5372 } 5373 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 5374 MachineOperand &MO = MI->getOperand(i); 5375 MIB.addOperand(MO); 5376 } 5377 5378 MachineBasicBlock *MBB = InsertPt->getParent(); 5379 MBB->insert(InsertPt, NewMI); 5380 5381 return MIB; 5382 } 5383 5384 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode, 5385 unsigned OpNo, ArrayRef<MachineOperand> MOs, 5386 MachineBasicBlock::iterator InsertPt, 5387 MachineInstr *MI, const TargetInstrInfo &TII, 5388 int PtrOffset = 0) { 5389 // Omit the implicit operands, something BuildMI can't do. 5390 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 5391 MI->getDebugLoc(), true); 5392 MachineInstrBuilder MIB(MF, NewMI); 5393 5394 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 5395 MachineOperand &MO = MI->getOperand(i); 5396 if (i == OpNo) { 5397 assert(MO.isReg() && "Expected to fold into reg operand!"); 5398 addOperands(MIB, MOs, PtrOffset); 5399 } else { 5400 MIB.addOperand(MO); 5401 } 5402 } 5403 5404 MachineBasicBlock *MBB = InsertPt->getParent(); 5405 MBB->insert(InsertPt, NewMI); 5406 5407 return MIB; 5408 } 5409 5410 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 5411 ArrayRef<MachineOperand> MOs, 5412 MachineBasicBlock::iterator InsertPt, 5413 MachineInstr *MI) { 5414 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt, 5415 MI->getDebugLoc(), TII.get(Opcode)); 5416 addOperands(MIB, MOs); 5417 return MIB.addImm(0); 5418 } 5419 5420 MachineInstr *X86InstrInfo::foldMemoryOperandCustom( 5421 MachineFunction &MF, MachineInstr *MI, unsigned OpNum, 5422 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt, 5423 unsigned Size, unsigned Align) const { 5424 switch (MI->getOpcode()) { 5425 case X86::INSERTPSrr: 5426 case X86::VINSERTPSrr: 5427 // Attempt to convert the load of inserted vector into a fold load 5428 // of a single float. 5429 if (OpNum == 2) { 5430 unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); 5431 unsigned ZMask = Imm & 15; 5432 unsigned DstIdx = (Imm >> 4) & 3; 5433 unsigned SrcIdx = (Imm >> 6) & 3; 5434 5435 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize(); 5436 if (Size <= RCSize && 4 <= Align) { 5437 int PtrOffset = SrcIdx * 4; 5438 unsigned NewImm = (DstIdx << 4) | ZMask; 5439 unsigned NewOpCode = 5440 (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm 5441 : X86::INSERTPSrm); 5442 MachineInstr *NewMI = 5443 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset); 5444 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm); 5445 return NewMI; 5446 } 5447 } 5448 break; 5449 }; 5450 5451 return nullptr; 5452 } 5453 5454 MachineInstr *X86InstrInfo::foldMemoryOperandImpl( 5455 MachineFunction &MF, MachineInstr *MI, unsigned OpNum, 5456 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt, 5457 unsigned Size, unsigned Align, bool AllowCommute) const { 5458 const DenseMap<unsigned, 5459 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr; 5460 bool isCallRegIndirect = Subtarget.callRegIndirect(); 5461 bool isTwoAddrFold = false; 5462 5463 // For CPUs that favor the register form of a call or push, 5464 // do not fold loads into calls or pushes, unless optimizing for size 5465 // aggressively. 5466 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() && 5467 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r || 5468 MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r || 5469 MI->getOpcode() == X86::PUSH64r)) 5470 return nullptr; 5471 5472 unsigned NumOps = MI->getDesc().getNumOperands(); 5473 bool isTwoAddr = NumOps > 1 && 5474 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 5475 5476 // FIXME: AsmPrinter doesn't know how to handle 5477 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 5478 if (MI->getOpcode() == X86::ADD32ri && 5479 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 5480 return nullptr; 5481 5482 MachineInstr *NewMI = nullptr; 5483 5484 // Attempt to fold any custom cases we have. 5485 if (MachineInstr *CustomMI = 5486 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align)) 5487 return CustomMI; 5488 5489 // Folding a memory location into the two-address part of a two-address 5490 // instruction is different than folding it other places. It requires 5491 // replacing the *two* registers with the memory location. 5492 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && 5493 MI->getOperand(0).isReg() && 5494 MI->getOperand(1).isReg() && 5495 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 5496 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 5497 isTwoAddrFold = true; 5498 } else if (OpNum == 0) { 5499 if (MI->getOpcode() == X86::MOV32r0) { 5500 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI); 5501 if (NewMI) 5502 return NewMI; 5503 } 5504 5505 OpcodeTablePtr = &RegOp2MemOpTable0; 5506 } else if (OpNum == 1) { 5507 OpcodeTablePtr = &RegOp2MemOpTable1; 5508 } else if (OpNum == 2) { 5509 OpcodeTablePtr = &RegOp2MemOpTable2; 5510 } else if (OpNum == 3) { 5511 OpcodeTablePtr = &RegOp2MemOpTable3; 5512 } else if (OpNum == 4) { 5513 OpcodeTablePtr = &RegOp2MemOpTable4; 5514 } 5515 5516 // If table selected... 5517 if (OpcodeTablePtr) { 5518 // Find the Opcode to fuse 5519 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 5520 OpcodeTablePtr->find(MI->getOpcode()); 5521 if (I != OpcodeTablePtr->end()) { 5522 unsigned Opcode = I->second.first; 5523 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 5524 if (Align < MinAlign) 5525 return nullptr; 5526 bool NarrowToMOV32rm = false; 5527 if (Size) { 5528 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize(); 5529 if (Size < RCSize) { 5530 // Check if it's safe to fold the load. If the size of the object is 5531 // narrower than the load width, then it's not. 5532 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 5533 return nullptr; 5534 // If this is a 64-bit load, but the spill slot is 32, then we can do 5535 // a 32-bit load which is implicitly zero-extended. This likely is 5536 // due to live interval analysis remat'ing a load from stack slot. 5537 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 5538 return nullptr; 5539 Opcode = X86::MOV32rm; 5540 NarrowToMOV32rm = true; 5541 } 5542 } 5543 5544 if (isTwoAddrFold) 5545 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this); 5546 else 5547 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this); 5548 5549 if (NarrowToMOV32rm) { 5550 // If this is the special case where we use a MOV32rm to load a 32-bit 5551 // value and zero-extend the top bits. Change the destination register 5552 // to a 32-bit one. 5553 unsigned DstReg = NewMI->getOperand(0).getReg(); 5554 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 5555 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit)); 5556 else 5557 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 5558 } 5559 return NewMI; 5560 } 5561 } 5562 5563 // If the instruction and target operand are commutable, commute the 5564 // instruction and try again. 5565 if (AllowCommute) { 5566 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex; 5567 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) { 5568 bool HasDef = MI->getDesc().getNumDefs(); 5569 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; 5570 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg(); 5571 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg(); 5572 bool Tied1 = 5573 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); 5574 bool Tied2 = 5575 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); 5576 5577 // If either of the commutable operands are tied to the destination 5578 // then we can not commute + fold. 5579 if ((HasDef && Reg0 == Reg1 && Tied1) || 5580 (HasDef && Reg0 == Reg2 && Tied2)) 5581 return nullptr; 5582 5583 MachineInstr *CommutedMI = 5584 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2); 5585 if (!CommutedMI) { 5586 // Unable to commute. 5587 return nullptr; 5588 } 5589 if (CommutedMI != MI) { 5590 // New instruction. We can't fold from this. 5591 CommutedMI->eraseFromParent(); 5592 return nullptr; 5593 } 5594 5595 // Attempt to fold with the commuted version of the instruction. 5596 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, 5597 Size, Align, /*AllowCommute=*/false); 5598 if (NewMI) 5599 return NewMI; 5600 5601 // Folding failed again - undo the commute before returning. 5602 MachineInstr *UncommutedMI = 5603 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2); 5604 if (!UncommutedMI) { 5605 // Unable to commute. 5606 return nullptr; 5607 } 5608 if (UncommutedMI != MI) { 5609 // New instruction. It doesn't need to be kept. 5610 UncommutedMI->eraseFromParent(); 5611 return nullptr; 5612 } 5613 5614 // Return here to prevent duplicate fuse failure report. 5615 return nullptr; 5616 } 5617 } 5618 5619 // No fusion 5620 if (PrintFailedFusing && !MI->isCopy()) 5621 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI; 5622 return nullptr; 5623 } 5624 5625 /// Return true for all instructions that only update 5626 /// the first 32 or 64-bits of the destination register and leave the rest 5627 /// unmodified. This can be used to avoid folding loads if the instructions 5628 /// only update part of the destination register, and the non-updated part is 5629 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 5630 /// instructions breaks the partial register dependency and it can improve 5631 /// performance. e.g.: 5632 /// 5633 /// movss (%rdi), %xmm0 5634 /// cvtss2sd %xmm0, %xmm0 5635 /// 5636 /// Instead of 5637 /// cvtss2sd (%rdi), %xmm0 5638 /// 5639 /// FIXME: This should be turned into a TSFlags. 5640 /// 5641 static bool hasPartialRegUpdate(unsigned Opcode) { 5642 switch (Opcode) { 5643 case X86::CVTSI2SSrr: 5644 case X86::CVTSI2SSrm: 5645 case X86::CVTSI2SS64rr: 5646 case X86::CVTSI2SS64rm: 5647 case X86::CVTSI2SDrr: 5648 case X86::CVTSI2SDrm: 5649 case X86::CVTSI2SD64rr: 5650 case X86::CVTSI2SD64rm: 5651 case X86::CVTSD2SSrr: 5652 case X86::CVTSD2SSrm: 5653 case X86::Int_CVTSD2SSrr: 5654 case X86::Int_CVTSD2SSrm: 5655 case X86::CVTSS2SDrr: 5656 case X86::CVTSS2SDrm: 5657 case X86::Int_CVTSS2SDrr: 5658 case X86::Int_CVTSS2SDrm: 5659 case X86::RCPSSr: 5660 case X86::RCPSSm: 5661 case X86::RCPSSr_Int: 5662 case X86::RCPSSm_Int: 5663 case X86::ROUNDSDr: 5664 case X86::ROUNDSDm: 5665 case X86::ROUNDSDr_Int: 5666 case X86::ROUNDSSr: 5667 case X86::ROUNDSSm: 5668 case X86::ROUNDSSr_Int: 5669 case X86::RSQRTSSr: 5670 case X86::RSQRTSSm: 5671 case X86::RSQRTSSr_Int: 5672 case X86::RSQRTSSm_Int: 5673 case X86::SQRTSSr: 5674 case X86::SQRTSSm: 5675 case X86::SQRTSSr_Int: 5676 case X86::SQRTSSm_Int: 5677 case X86::SQRTSDr: 5678 case X86::SQRTSDm: 5679 case X86::SQRTSDr_Int: 5680 case X86::SQRTSDm_Int: 5681 return true; 5682 } 5683 5684 return false; 5685 } 5686 5687 /// Inform the ExeDepsFix pass how many idle 5688 /// instructions we would like before a partial register update. 5689 unsigned X86InstrInfo:: 5690 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 5691 const TargetRegisterInfo *TRI) const { 5692 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 5693 return 0; 5694 5695 // If MI is marked as reading Reg, the partial register update is wanted. 5696 const MachineOperand &MO = MI->getOperand(0); 5697 unsigned Reg = MO.getReg(); 5698 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 5699 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 5700 return 0; 5701 } else { 5702 if (MI->readsRegister(Reg, TRI)) 5703 return 0; 5704 } 5705 5706 // If any of the preceding 16 instructions are reading Reg, insert a 5707 // dependency breaking instruction. The magic number is based on a few 5708 // Nehalem experiments. 5709 return 16; 5710 } 5711 5712 // Return true for any instruction the copies the high bits of the first source 5713 // operand into the unused high bits of the destination operand. 5714 static bool hasUndefRegUpdate(unsigned Opcode) { 5715 switch (Opcode) { 5716 case X86::VCVTSI2SSrr: 5717 case X86::VCVTSI2SSrm: 5718 case X86::Int_VCVTSI2SSrr: 5719 case X86::Int_VCVTSI2SSrm: 5720 case X86::VCVTSI2SS64rr: 5721 case X86::VCVTSI2SS64rm: 5722 case X86::Int_VCVTSI2SS64rr: 5723 case X86::Int_VCVTSI2SS64rm: 5724 case X86::VCVTSI2SDrr: 5725 case X86::VCVTSI2SDrm: 5726 case X86::Int_VCVTSI2SDrr: 5727 case X86::Int_VCVTSI2SDrm: 5728 case X86::VCVTSI2SD64rr: 5729 case X86::VCVTSI2SD64rm: 5730 case X86::Int_VCVTSI2SD64rr: 5731 case X86::Int_VCVTSI2SD64rm: 5732 case X86::VCVTSD2SSrr: 5733 case X86::VCVTSD2SSrm: 5734 case X86::Int_VCVTSD2SSrr: 5735 case X86::Int_VCVTSD2SSrm: 5736 case X86::VCVTSS2SDrr: 5737 case X86::VCVTSS2SDrm: 5738 case X86::Int_VCVTSS2SDrr: 5739 case X86::Int_VCVTSS2SDrm: 5740 case X86::VRCPSSr: 5741 case X86::VRCPSSm: 5742 case X86::VRCPSSm_Int: 5743 case X86::VROUNDSDr: 5744 case X86::VROUNDSDm: 5745 case X86::VROUNDSDr_Int: 5746 case X86::VROUNDSSr: 5747 case X86::VROUNDSSm: 5748 case X86::VROUNDSSr_Int: 5749 case X86::VRSQRTSSr: 5750 case X86::VRSQRTSSm: 5751 case X86::VRSQRTSSm_Int: 5752 case X86::VSQRTSSr: 5753 case X86::VSQRTSSm: 5754 case X86::VSQRTSSm_Int: 5755 case X86::VSQRTSDr: 5756 case X86::VSQRTSDm: 5757 case X86::VSQRTSDm_Int: 5758 // AVX-512 5759 case X86::VCVTSD2SSZrr: 5760 case X86::VCVTSD2SSZrm: 5761 case X86::VCVTSS2SDZrr: 5762 case X86::VCVTSS2SDZrm: 5763 return true; 5764 } 5765 5766 return false; 5767 } 5768 5769 /// Inform the ExeDepsFix pass how many idle instructions we would like before 5770 /// certain undef register reads. 5771 /// 5772 /// This catches the VCVTSI2SD family of instructions: 5773 /// 5774 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 5775 /// 5776 /// We should to be careful *not* to catch VXOR idioms which are presumably 5777 /// handled specially in the pipeline: 5778 /// 5779 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1 5780 /// 5781 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the 5782 /// high bits that are passed-through are not live. 5783 unsigned X86InstrInfo:: 5784 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 5785 const TargetRegisterInfo *TRI) const { 5786 if (!hasUndefRegUpdate(MI->getOpcode())) 5787 return 0; 5788 5789 // Set the OpNum parameter to the first source operand. 5790 OpNum = 1; 5791 5792 const MachineOperand &MO = MI->getOperand(OpNum); 5793 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { 5794 // Use the same magic number as getPartialRegUpdateClearance. 5795 return 16; 5796 } 5797 return 0; 5798 } 5799 5800 void X86InstrInfo:: 5801 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 5802 const TargetRegisterInfo *TRI) const { 5803 unsigned Reg = MI->getOperand(OpNum).getReg(); 5804 // If MI kills this register, the false dependence is already broken. 5805 if (MI->killsRegister(Reg, TRI)) 5806 return; 5807 if (X86::VR128RegClass.contains(Reg)) { 5808 // These instructions are all floating point domain, so xorps is the best 5809 // choice. 5810 bool HasAVX = Subtarget.hasAVX(); 5811 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 5812 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 5813 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 5814 } else if (X86::VR256RegClass.contains(Reg)) { 5815 // Use vxorps to clear the full ymm register. 5816 // It wants to read and write the xmm sub-register. 5817 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 5818 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 5819 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 5820 .addReg(Reg, RegState::ImplicitDefine); 5821 } else 5822 return; 5823 MI->addRegisterKilled(Reg, TRI, true); 5824 } 5825 5826 MachineInstr *X86InstrInfo::foldMemoryOperandImpl( 5827 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, 5828 MachineBasicBlock::iterator InsertPt, int FrameIndex) const { 5829 // Check switch flag 5830 if (NoFusing) return nullptr; 5831 5832 // Unless optimizing for size, don't fold to avoid partial 5833 // register update stalls 5834 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode())) 5835 return nullptr; 5836 5837 const MachineFrameInfo *MFI = MF.getFrameInfo(); 5838 unsigned Size = MFI->getObjectSize(FrameIndex); 5839 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 5840 // If the function stack isn't realigned we don't want to fold instructions 5841 // that need increased alignment. 5842 if (!RI.needsStackRealignment(MF)) 5843 Alignment = 5844 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment()); 5845 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 5846 unsigned NewOpc = 0; 5847 unsigned RCSize = 0; 5848 switch (MI->getOpcode()) { 5849 default: return nullptr; 5850 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 5851 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 5852 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 5853 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 5854 } 5855 // Check if it's safe to fold the load. If the size of the object is 5856 // narrower than the load width, then it's not. 5857 if (Size < RCSize) 5858 return nullptr; 5859 // Change to CMPXXri r, 0 first. 5860 MI->setDesc(get(NewOpc)); 5861 MI->getOperand(1).ChangeToImmediate(0); 5862 } else if (Ops.size() != 1) 5863 return nullptr; 5864 5865 return foldMemoryOperandImpl(MF, MI, Ops[0], 5866 MachineOperand::CreateFI(FrameIndex), InsertPt, 5867 Size, Alignment, /*AllowCommute=*/true); 5868 } 5869 5870 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI 5871 /// because the latter uses contents that wouldn't be defined in the folded 5872 /// version. For instance, this transformation isn't legal: 5873 /// movss (%rdi), %xmm0 5874 /// addps %xmm0, %xmm0 5875 /// -> 5876 /// addps (%rdi), %xmm0 5877 /// 5878 /// But this one is: 5879 /// movss (%rdi), %xmm0 5880 /// addss %xmm0, %xmm0 5881 /// -> 5882 /// addss (%rdi), %xmm0 5883 /// 5884 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, 5885 const MachineInstr &UserMI, 5886 const MachineFunction &MF) { 5887 unsigned Opc = LoadMI.getOpcode(); 5888 unsigned UserOpc = UserMI.getOpcode(); 5889 unsigned RegSize = 5890 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize(); 5891 5892 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) { 5893 // These instructions only load 32 bits, we can't fold them if the 5894 // destination register is wider than 32 bits (4 bytes), and its user 5895 // instruction isn't scalar (SS). 5896 switch (UserOpc) { 5897 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: 5898 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: 5899 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: 5900 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: 5901 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int: 5902 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int: 5903 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int: 5904 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int: 5905 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int: 5906 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int: 5907 return false; 5908 default: 5909 return true; 5910 } 5911 } 5912 5913 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) { 5914 // These instructions only load 64 bits, we can't fold them if the 5915 // destination register is wider than 64 bits (8 bytes), and its user 5916 // instruction isn't scalar (SD). 5917 switch (UserOpc) { 5918 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: 5919 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: 5920 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: 5921 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: 5922 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int: 5923 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int: 5924 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int: 5925 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int: 5926 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int: 5927 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int: 5928 return false; 5929 default: 5930 return true; 5931 } 5932 } 5933 5934 return false; 5935 } 5936 5937 MachineInstr *X86InstrInfo::foldMemoryOperandImpl( 5938 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops, 5939 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const { 5940 // If loading from a FrameIndex, fold directly from the FrameIndex. 5941 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 5942 int FrameIndex; 5943 if (isLoadFromStackSlot(LoadMI, FrameIndex)) { 5944 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF)) 5945 return nullptr; 5946 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex); 5947 } 5948 5949 // Check switch flag 5950 if (NoFusing) return nullptr; 5951 5952 // Avoid partial register update stalls unless optimizing for size. 5953 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode())) 5954 return nullptr; 5955 5956 // Determine the alignment of the load. 5957 unsigned Alignment = 0; 5958 if (LoadMI->hasOneMemOperand()) 5959 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 5960 else 5961 switch (LoadMI->getOpcode()) { 5962 case X86::AVX2_SETALLONES: 5963 case X86::AVX_SET0: 5964 Alignment = 32; 5965 break; 5966 case X86::V_SET0: 5967 case X86::V_SETALLONES: 5968 Alignment = 16; 5969 break; 5970 case X86::FsFLD0SD: 5971 Alignment = 8; 5972 break; 5973 case X86::FsFLD0SS: 5974 Alignment = 4; 5975 break; 5976 default: 5977 return nullptr; 5978 } 5979 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 5980 unsigned NewOpc = 0; 5981 switch (MI->getOpcode()) { 5982 default: return nullptr; 5983 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 5984 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 5985 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 5986 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 5987 } 5988 // Change to CMPXXri r, 0 first. 5989 MI->setDesc(get(NewOpc)); 5990 MI->getOperand(1).ChangeToImmediate(0); 5991 } else if (Ops.size() != 1) 5992 return nullptr; 5993 5994 // Make sure the subregisters match. 5995 // Otherwise we risk changing the size of the load. 5996 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 5997 return nullptr; 5998 5999 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 6000 switch (LoadMI->getOpcode()) { 6001 case X86::V_SET0: 6002 case X86::V_SETALLONES: 6003 case X86::AVX2_SETALLONES: 6004 case X86::AVX_SET0: 6005 case X86::FsFLD0SD: 6006 case X86::FsFLD0SS: { 6007 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 6008 // Create a constant-pool entry and operands to load from it. 6009 6010 // Medium and large mode can't fold loads this way. 6011 if (MF.getTarget().getCodeModel() != CodeModel::Small && 6012 MF.getTarget().getCodeModel() != CodeModel::Kernel) 6013 return nullptr; 6014 6015 // x86-32 PIC requires a PIC base register for constant pools. 6016 unsigned PICBase = 0; 6017 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) { 6018 if (Subtarget.is64Bit()) 6019 PICBase = X86::RIP; 6020 else 6021 // FIXME: PICBase = getGlobalBaseReg(&MF); 6022 // This doesn't work for several reasons. 6023 // 1. GlobalBaseReg may have been spilled. 6024 // 2. It may not be live at MI. 6025 return nullptr; 6026 } 6027 6028 // Create a constant-pool entry. 6029 MachineConstantPool &MCP = *MF.getConstantPool(); 6030 Type *Ty; 6031 unsigned Opc = LoadMI->getOpcode(); 6032 if (Opc == X86::FsFLD0SS) 6033 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 6034 else if (Opc == X86::FsFLD0SD) 6035 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 6036 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 6037 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 6038 else 6039 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 6040 6041 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 6042 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 6043 Constant::getNullValue(Ty); 6044 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 6045 6046 // Create operands to load from the constant pool entry. 6047 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 6048 MOs.push_back(MachineOperand::CreateImm(1)); 6049 MOs.push_back(MachineOperand::CreateReg(0, false)); 6050 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 6051 MOs.push_back(MachineOperand::CreateReg(0, false)); 6052 break; 6053 } 6054 default: { 6055 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF)) 6056 return nullptr; 6057 6058 // Folding a normal load. Just copy the load's address operands. 6059 MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands, 6060 LoadMI->operands_begin() + NumOps); 6061 break; 6062 } 6063 } 6064 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt, 6065 /*Size=*/0, Alignment, /*AllowCommute=*/true); 6066 } 6067 6068 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 6069 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 6070 SmallVectorImpl<MachineInstr*> &NewMIs) const { 6071 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 6072 MemOp2RegOpTable.find(MI->getOpcode()); 6073 if (I == MemOp2RegOpTable.end()) 6074 return false; 6075 unsigned Opc = I->second.first; 6076 unsigned Index = I->second.second & TB_INDEX_MASK; 6077 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 6078 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 6079 if (UnfoldLoad && !FoldedLoad) 6080 return false; 6081 UnfoldLoad &= FoldedLoad; 6082 if (UnfoldStore && !FoldedStore) 6083 return false; 6084 UnfoldStore &= FoldedStore; 6085 6086 const MCInstrDesc &MCID = get(Opc); 6087 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 6088 // TODO: Check if 32-byte or greater accesses are slow too? 6089 if (!MI->hasOneMemOperand() && 6090 RC == &X86::VR128RegClass && 6091 Subtarget.isUnalignedMem16Slow()) 6092 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 6093 // conservatively assume the address is unaligned. That's bad for 6094 // performance. 6095 return false; 6096 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 6097 SmallVector<MachineOperand,2> BeforeOps; 6098 SmallVector<MachineOperand,2> AfterOps; 6099 SmallVector<MachineOperand,4> ImpOps; 6100 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 6101 MachineOperand &Op = MI->getOperand(i); 6102 if (i >= Index && i < Index + X86::AddrNumOperands) 6103 AddrOps.push_back(Op); 6104 else if (Op.isReg() && Op.isImplicit()) 6105 ImpOps.push_back(Op); 6106 else if (i < Index) 6107 BeforeOps.push_back(Op); 6108 else if (i > Index) 6109 AfterOps.push_back(Op); 6110 } 6111 6112 // Emit the load instruction. 6113 if (UnfoldLoad) { 6114 std::pair<MachineInstr::mmo_iterator, 6115 MachineInstr::mmo_iterator> MMOs = 6116 MF.extractLoadMemRefs(MI->memoperands_begin(), 6117 MI->memoperands_end()); 6118 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 6119 if (UnfoldStore) { 6120 // Address operands cannot be marked isKill. 6121 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 6122 MachineOperand &MO = NewMIs[0]->getOperand(i); 6123 if (MO.isReg()) 6124 MO.setIsKill(false); 6125 } 6126 } 6127 } 6128 6129 // Emit the data processing instruction. 6130 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 6131 MachineInstrBuilder MIB(MF, DataMI); 6132 6133 if (FoldedStore) 6134 MIB.addReg(Reg, RegState::Define); 6135 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 6136 MIB.addOperand(BeforeOps[i]); 6137 if (FoldedLoad) 6138 MIB.addReg(Reg); 6139 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 6140 MIB.addOperand(AfterOps[i]); 6141 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 6142 MachineOperand &MO = ImpOps[i]; 6143 MIB.addReg(MO.getReg(), 6144 getDefRegState(MO.isDef()) | 6145 RegState::Implicit | 6146 getKillRegState(MO.isKill()) | 6147 getDeadRegState(MO.isDead()) | 6148 getUndefRegState(MO.isUndef())); 6149 } 6150 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 6151 switch (DataMI->getOpcode()) { 6152 default: break; 6153 case X86::CMP64ri32: 6154 case X86::CMP64ri8: 6155 case X86::CMP32ri: 6156 case X86::CMP32ri8: 6157 case X86::CMP16ri: 6158 case X86::CMP16ri8: 6159 case X86::CMP8ri: { 6160 MachineOperand &MO0 = DataMI->getOperand(0); 6161 MachineOperand &MO1 = DataMI->getOperand(1); 6162 if (MO1.getImm() == 0) { 6163 unsigned NewOpc; 6164 switch (DataMI->getOpcode()) { 6165 default: llvm_unreachable("Unreachable!"); 6166 case X86::CMP64ri8: 6167 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 6168 case X86::CMP32ri8: 6169 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 6170 case X86::CMP16ri8: 6171 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 6172 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 6173 } 6174 DataMI->setDesc(get(NewOpc)); 6175 MO1.ChangeToRegister(MO0.getReg(), false); 6176 } 6177 } 6178 } 6179 NewMIs.push_back(DataMI); 6180 6181 // Emit the store instruction. 6182 if (UnfoldStore) { 6183 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 6184 std::pair<MachineInstr::mmo_iterator, 6185 MachineInstr::mmo_iterator> MMOs = 6186 MF.extractStoreMemRefs(MI->memoperands_begin(), 6187 MI->memoperands_end()); 6188 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 6189 } 6190 6191 return true; 6192 } 6193 6194 bool 6195 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 6196 SmallVectorImpl<SDNode*> &NewNodes) const { 6197 if (!N->isMachineOpcode()) 6198 return false; 6199 6200 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 6201 MemOp2RegOpTable.find(N->getMachineOpcode()); 6202 if (I == MemOp2RegOpTable.end()) 6203 return false; 6204 unsigned Opc = I->second.first; 6205 unsigned Index = I->second.second & TB_INDEX_MASK; 6206 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 6207 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 6208 const MCInstrDesc &MCID = get(Opc); 6209 MachineFunction &MF = DAG.getMachineFunction(); 6210 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 6211 unsigned NumDefs = MCID.NumDefs; 6212 std::vector<SDValue> AddrOps; 6213 std::vector<SDValue> BeforeOps; 6214 std::vector<SDValue> AfterOps; 6215 SDLoc dl(N); 6216 unsigned NumOps = N->getNumOperands(); 6217 for (unsigned i = 0; i != NumOps-1; ++i) { 6218 SDValue Op = N->getOperand(i); 6219 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 6220 AddrOps.push_back(Op); 6221 else if (i < Index-NumDefs) 6222 BeforeOps.push_back(Op); 6223 else if (i > Index-NumDefs) 6224 AfterOps.push_back(Op); 6225 } 6226 SDValue Chain = N->getOperand(NumOps-1); 6227 AddrOps.push_back(Chain); 6228 6229 // Emit the load instruction. 6230 SDNode *Load = nullptr; 6231 if (FoldedLoad) { 6232 EVT VT = *RC->vt_begin(); 6233 std::pair<MachineInstr::mmo_iterator, 6234 MachineInstr::mmo_iterator> MMOs = 6235 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 6236 cast<MachineSDNode>(N)->memoperands_end()); 6237 if (!(*MMOs.first) && 6238 RC == &X86::VR128RegClass && 6239 Subtarget.isUnalignedMem16Slow()) 6240 // Do not introduce a slow unaligned load. 6241 return false; 6242 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte 6243 // memory access is slow above. 6244 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 6245 bool isAligned = (*MMOs.first) && 6246 (*MMOs.first)->getAlignment() >= Alignment; 6247 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl, 6248 VT, MVT::Other, AddrOps); 6249 NewNodes.push_back(Load); 6250 6251 // Preserve memory reference information. 6252 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 6253 } 6254 6255 // Emit the data processing instruction. 6256 std::vector<EVT> VTs; 6257 const TargetRegisterClass *DstRC = nullptr; 6258 if (MCID.getNumDefs() > 0) { 6259 DstRC = getRegClass(MCID, 0, &RI, MF); 6260 VTs.push_back(*DstRC->vt_begin()); 6261 } 6262 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 6263 EVT VT = N->getValueType(i); 6264 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 6265 VTs.push_back(VT); 6266 } 6267 if (Load) 6268 BeforeOps.push_back(SDValue(Load, 0)); 6269 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end()); 6270 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 6271 NewNodes.push_back(NewNode); 6272 6273 // Emit the store instruction. 6274 if (FoldedStore) { 6275 AddrOps.pop_back(); 6276 AddrOps.push_back(SDValue(NewNode, 0)); 6277 AddrOps.push_back(Chain); 6278 std::pair<MachineInstr::mmo_iterator, 6279 MachineInstr::mmo_iterator> MMOs = 6280 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 6281 cast<MachineSDNode>(N)->memoperands_end()); 6282 if (!(*MMOs.first) && 6283 RC == &X86::VR128RegClass && 6284 Subtarget.isUnalignedMem16Slow()) 6285 // Do not introduce a slow unaligned store. 6286 return false; 6287 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte 6288 // memory access is slow above. 6289 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 6290 bool isAligned = (*MMOs.first) && 6291 (*MMOs.first)->getAlignment() >= Alignment; 6292 SDNode *Store = 6293 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget), 6294 dl, MVT::Other, AddrOps); 6295 NewNodes.push_back(Store); 6296 6297 // Preserve memory reference information. 6298 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second); 6299 } 6300 6301 return true; 6302 } 6303 6304 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 6305 bool UnfoldLoad, bool UnfoldStore, 6306 unsigned *LoadRegIndex) const { 6307 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 6308 MemOp2RegOpTable.find(Opc); 6309 if (I == MemOp2RegOpTable.end()) 6310 return 0; 6311 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 6312 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 6313 if (UnfoldLoad && !FoldedLoad) 6314 return 0; 6315 if (UnfoldStore && !FoldedStore) 6316 return 0; 6317 if (LoadRegIndex) 6318 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 6319 return I->second.first; 6320 } 6321 6322 bool 6323 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 6324 int64_t &Offset1, int64_t &Offset2) const { 6325 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 6326 return false; 6327 unsigned Opc1 = Load1->getMachineOpcode(); 6328 unsigned Opc2 = Load2->getMachineOpcode(); 6329 switch (Opc1) { 6330 default: return false; 6331 case X86::MOV8rm: 6332 case X86::MOV16rm: 6333 case X86::MOV32rm: 6334 case X86::MOV64rm: 6335 case X86::LD_Fp32m: 6336 case X86::LD_Fp64m: 6337 case X86::LD_Fp80m: 6338 case X86::MOVSSrm: 6339 case X86::MOVSDrm: 6340 case X86::MMX_MOVD64rm: 6341 case X86::MMX_MOVQ64rm: 6342 case X86::FsMOVAPSrm: 6343 case X86::FsMOVAPDrm: 6344 case X86::MOVAPSrm: 6345 case X86::MOVUPSrm: 6346 case X86::MOVAPDrm: 6347 case X86::MOVDQArm: 6348 case X86::MOVDQUrm: 6349 // AVX load instructions 6350 case X86::VMOVSSrm: 6351 case X86::VMOVSDrm: 6352 case X86::FsVMOVAPSrm: 6353 case X86::FsVMOVAPDrm: 6354 case X86::VMOVAPSrm: 6355 case X86::VMOVUPSrm: 6356 case X86::VMOVAPDrm: 6357 case X86::VMOVDQArm: 6358 case X86::VMOVDQUrm: 6359 case X86::VMOVAPSYrm: 6360 case X86::VMOVUPSYrm: 6361 case X86::VMOVAPDYrm: 6362 case X86::VMOVDQAYrm: 6363 case X86::VMOVDQUYrm: 6364 break; 6365 } 6366 switch (Opc2) { 6367 default: return false; 6368 case X86::MOV8rm: 6369 case X86::MOV16rm: 6370 case X86::MOV32rm: 6371 case X86::MOV64rm: 6372 case X86::LD_Fp32m: 6373 case X86::LD_Fp64m: 6374 case X86::LD_Fp80m: 6375 case X86::MOVSSrm: 6376 case X86::MOVSDrm: 6377 case X86::MMX_MOVD64rm: 6378 case X86::MMX_MOVQ64rm: 6379 case X86::FsMOVAPSrm: 6380 case X86::FsMOVAPDrm: 6381 case X86::MOVAPSrm: 6382 case X86::MOVUPSrm: 6383 case X86::MOVAPDrm: 6384 case X86::MOVDQArm: 6385 case X86::MOVDQUrm: 6386 // AVX load instructions 6387 case X86::VMOVSSrm: 6388 case X86::VMOVSDrm: 6389 case X86::FsVMOVAPSrm: 6390 case X86::FsVMOVAPDrm: 6391 case X86::VMOVAPSrm: 6392 case X86::VMOVUPSrm: 6393 case X86::VMOVAPDrm: 6394 case X86::VMOVDQArm: 6395 case X86::VMOVDQUrm: 6396 case X86::VMOVAPSYrm: 6397 case X86::VMOVUPSYrm: 6398 case X86::VMOVAPDYrm: 6399 case X86::VMOVDQAYrm: 6400 case X86::VMOVDQUYrm: 6401 break; 6402 } 6403 6404 // Check if chain operands and base addresses match. 6405 if (Load1->getOperand(0) != Load2->getOperand(0) || 6406 Load1->getOperand(5) != Load2->getOperand(5)) 6407 return false; 6408 // Segment operands should match as well. 6409 if (Load1->getOperand(4) != Load2->getOperand(4)) 6410 return false; 6411 // Scale should be 1, Index should be Reg0. 6412 if (Load1->getOperand(1) == Load2->getOperand(1) && 6413 Load1->getOperand(2) == Load2->getOperand(2)) { 6414 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 6415 return false; 6416 6417 // Now let's examine the displacements. 6418 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 6419 isa<ConstantSDNode>(Load2->getOperand(3))) { 6420 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 6421 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 6422 return true; 6423 } 6424 } 6425 return false; 6426 } 6427 6428 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 6429 int64_t Offset1, int64_t Offset2, 6430 unsigned NumLoads) const { 6431 assert(Offset2 > Offset1); 6432 if ((Offset2 - Offset1) / 8 > 64) 6433 return false; 6434 6435 unsigned Opc1 = Load1->getMachineOpcode(); 6436 unsigned Opc2 = Load2->getMachineOpcode(); 6437 if (Opc1 != Opc2) 6438 return false; // FIXME: overly conservative? 6439 6440 switch (Opc1) { 6441 default: break; 6442 case X86::LD_Fp32m: 6443 case X86::LD_Fp64m: 6444 case X86::LD_Fp80m: 6445 case X86::MMX_MOVD64rm: 6446 case X86::MMX_MOVQ64rm: 6447 return false; 6448 } 6449 6450 EVT VT = Load1->getValueType(0); 6451 switch (VT.getSimpleVT().SimpleTy) { 6452 default: 6453 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 6454 // have 16 of them to play with. 6455 if (Subtarget.is64Bit()) { 6456 if (NumLoads >= 3) 6457 return false; 6458 } else if (NumLoads) { 6459 return false; 6460 } 6461 break; 6462 case MVT::i8: 6463 case MVT::i16: 6464 case MVT::i32: 6465 case MVT::i64: 6466 case MVT::f32: 6467 case MVT::f64: 6468 if (NumLoads) 6469 return false; 6470 break; 6471 } 6472 6473 return true; 6474 } 6475 6476 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First, 6477 MachineInstr *Second) const { 6478 // Check if this processor supports macro-fusion. Since this is a minor 6479 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent 6480 // proxy for SandyBridge+. 6481 if (!Subtarget.hasAVX()) 6482 return false; 6483 6484 enum { 6485 FuseTest, 6486 FuseCmp, 6487 FuseInc 6488 } FuseKind; 6489 6490 switch(Second->getOpcode()) { 6491 default: 6492 return false; 6493 case X86::JE_1: 6494 case X86::JNE_1: 6495 case X86::JL_1: 6496 case X86::JLE_1: 6497 case X86::JG_1: 6498 case X86::JGE_1: 6499 FuseKind = FuseInc; 6500 break; 6501 case X86::JB_1: 6502 case X86::JBE_1: 6503 case X86::JA_1: 6504 case X86::JAE_1: 6505 FuseKind = FuseCmp; 6506 break; 6507 case X86::JS_1: 6508 case X86::JNS_1: 6509 case X86::JP_1: 6510 case X86::JNP_1: 6511 case X86::JO_1: 6512 case X86::JNO_1: 6513 FuseKind = FuseTest; 6514 break; 6515 } 6516 switch (First->getOpcode()) { 6517 default: 6518 return false; 6519 case X86::TEST8rr: 6520 case X86::TEST16rr: 6521 case X86::TEST32rr: 6522 case X86::TEST64rr: 6523 case X86::TEST8ri: 6524 case X86::TEST16ri: 6525 case X86::TEST32ri: 6526 case X86::TEST32i32: 6527 case X86::TEST64i32: 6528 case X86::TEST64ri32: 6529 case X86::TEST8rm: 6530 case X86::TEST16rm: 6531 case X86::TEST32rm: 6532 case X86::TEST64rm: 6533 case X86::TEST8ri_NOREX: 6534 case X86::AND16i16: 6535 case X86::AND16ri: 6536 case X86::AND16ri8: 6537 case X86::AND16rm: 6538 case X86::AND16rr: 6539 case X86::AND32i32: 6540 case X86::AND32ri: 6541 case X86::AND32ri8: 6542 case X86::AND32rm: 6543 case X86::AND32rr: 6544 case X86::AND64i32: 6545 case X86::AND64ri32: 6546 case X86::AND64ri8: 6547 case X86::AND64rm: 6548 case X86::AND64rr: 6549 case X86::AND8i8: 6550 case X86::AND8ri: 6551 case X86::AND8rm: 6552 case X86::AND8rr: 6553 return true; 6554 case X86::CMP16i16: 6555 case X86::CMP16ri: 6556 case X86::CMP16ri8: 6557 case X86::CMP16rm: 6558 case X86::CMP16rr: 6559 case X86::CMP32i32: 6560 case X86::CMP32ri: 6561 case X86::CMP32ri8: 6562 case X86::CMP32rm: 6563 case X86::CMP32rr: 6564 case X86::CMP64i32: 6565 case X86::CMP64ri32: 6566 case X86::CMP64ri8: 6567 case X86::CMP64rm: 6568 case X86::CMP64rr: 6569 case X86::CMP8i8: 6570 case X86::CMP8ri: 6571 case X86::CMP8rm: 6572 case X86::CMP8rr: 6573 case X86::ADD16i16: 6574 case X86::ADD16ri: 6575 case X86::ADD16ri8: 6576 case X86::ADD16ri8_DB: 6577 case X86::ADD16ri_DB: 6578 case X86::ADD16rm: 6579 case X86::ADD16rr: 6580 case X86::ADD16rr_DB: 6581 case X86::ADD32i32: 6582 case X86::ADD32ri: 6583 case X86::ADD32ri8: 6584 case X86::ADD32ri8_DB: 6585 case X86::ADD32ri_DB: 6586 case X86::ADD32rm: 6587 case X86::ADD32rr: 6588 case X86::ADD32rr_DB: 6589 case X86::ADD64i32: 6590 case X86::ADD64ri32: 6591 case X86::ADD64ri32_DB: 6592 case X86::ADD64ri8: 6593 case X86::ADD64ri8_DB: 6594 case X86::ADD64rm: 6595 case X86::ADD64rr: 6596 case X86::ADD64rr_DB: 6597 case X86::ADD8i8: 6598 case X86::ADD8mi: 6599 case X86::ADD8mr: 6600 case X86::ADD8ri: 6601 case X86::ADD8rm: 6602 case X86::ADD8rr: 6603 case X86::SUB16i16: 6604 case X86::SUB16ri: 6605 case X86::SUB16ri8: 6606 case X86::SUB16rm: 6607 case X86::SUB16rr: 6608 case X86::SUB32i32: 6609 case X86::SUB32ri: 6610 case X86::SUB32ri8: 6611 case X86::SUB32rm: 6612 case X86::SUB32rr: 6613 case X86::SUB64i32: 6614 case X86::SUB64ri32: 6615 case X86::SUB64ri8: 6616 case X86::SUB64rm: 6617 case X86::SUB64rr: 6618 case X86::SUB8i8: 6619 case X86::SUB8ri: 6620 case X86::SUB8rm: 6621 case X86::SUB8rr: 6622 return FuseKind == FuseCmp || FuseKind == FuseInc; 6623 case X86::INC16r: 6624 case X86::INC32r: 6625 case X86::INC64r: 6626 case X86::INC8r: 6627 case X86::DEC16r: 6628 case X86::DEC32r: 6629 case X86::DEC64r: 6630 case X86::DEC8r: 6631 return FuseKind == FuseInc; 6632 } 6633 } 6634 6635 bool X86InstrInfo:: 6636 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 6637 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 6638 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 6639 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 6640 return true; 6641 Cond[0].setImm(GetOppositeBranchCondition(CC)); 6642 return false; 6643 } 6644 6645 bool X86InstrInfo:: 6646 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 6647 // FIXME: Return false for x87 stack register classes for now. We can't 6648 // allow any loads of these registers before FpGet_ST0_80. 6649 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 6650 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 6651 } 6652 6653 /// Return a virtual register initialized with the 6654 /// the global base register value. Output instructions required to 6655 /// initialize the register in the function entry block, if necessary. 6656 /// 6657 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 6658 /// 6659 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 6660 assert(!Subtarget.is64Bit() && 6661 "X86-64 PIC uses RIP relative addressing"); 6662 6663 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 6664 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 6665 if (GlobalBaseReg != 0) 6666 return GlobalBaseReg; 6667 6668 // Create the register. The code to initialize it is inserted 6669 // later, by the CGBR pass (below). 6670 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 6671 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 6672 X86FI->setGlobalBaseReg(GlobalBaseReg); 6673 return GlobalBaseReg; 6674 } 6675 6676 // These are the replaceable SSE instructions. Some of these have Int variants 6677 // that we don't include here. We don't want to replace instructions selected 6678 // by intrinsics. 6679 static const uint16_t ReplaceableInstrs[][3] = { 6680 //PackedSingle PackedDouble PackedInt 6681 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 6682 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 6683 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 6684 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 6685 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 6686 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr }, 6687 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 6688 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 6689 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 6690 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 6691 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 6692 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 6693 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 6694 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 6695 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 6696 // AVX 128-bit support 6697 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 6698 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 6699 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 6700 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 6701 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 6702 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr }, 6703 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 6704 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 6705 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 6706 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 6707 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 6708 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 6709 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 6710 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 6711 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 6712 // AVX 256-bit support 6713 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 6714 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 6715 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 6716 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 6717 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 6718 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 6719 }; 6720 6721 static const uint16_t ReplaceableInstrsAVX2[][3] = { 6722 //PackedSingle PackedDouble PackedInt 6723 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 6724 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 6725 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 6726 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 6727 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 6728 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 6729 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 6730 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 6731 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 6732 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 6733 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 6734 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 6735 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 6736 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }, 6737 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm}, 6738 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr}, 6739 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr}, 6740 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm}, 6741 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr}, 6742 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm} 6743 }; 6744 6745 // FIXME: Some shuffle and unpack instructions have equivalents in different 6746 // domains, but they require a bit more work than just switching opcodes. 6747 6748 static const uint16_t *lookup(unsigned opcode, unsigned domain) { 6749 for (const uint16_t (&Row)[3] : ReplaceableInstrs) 6750 if (Row[domain-1] == opcode) 6751 return Row; 6752 return nullptr; 6753 } 6754 6755 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 6756 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2) 6757 if (Row[domain-1] == opcode) 6758 return Row; 6759 return nullptr; 6760 } 6761 6762 std::pair<uint16_t, uint16_t> 6763 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 6764 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 6765 bool hasAVX2 = Subtarget.hasAVX2(); 6766 uint16_t validDomains = 0; 6767 if (domain && lookup(MI->getOpcode(), domain)) 6768 validDomains = 0xe; 6769 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 6770 validDomains = hasAVX2 ? 0xe : 0x6; 6771 return std::make_pair(domain, validDomains); 6772 } 6773 6774 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 6775 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 6776 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 6777 assert(dom && "Not an SSE instruction"); 6778 const uint16_t *table = lookup(MI->getOpcode(), dom); 6779 if (!table) { // try the other table 6780 assert((Subtarget.hasAVX2() || Domain < 3) && 6781 "256-bit vector operations only available in AVX2"); 6782 table = lookupAVX2(MI->getOpcode(), dom); 6783 } 6784 assert(table && "Cannot change domain"); 6785 MI->setDesc(get(table[Domain-1])); 6786 } 6787 6788 /// Return the noop instruction to use for a noop. 6789 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 6790 NopInst.setOpcode(X86::NOOP); 6791 } 6792 6793 // This code must remain in sync with getJumpInstrTableEntryBound in this class! 6794 // In particular, getJumpInstrTableEntryBound must always return an upper bound 6795 // on the encoding lengths of the instructions generated by 6796 // getUnconditionalBranch and getTrap. 6797 void X86InstrInfo::getUnconditionalBranch( 6798 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const { 6799 Branch.setOpcode(X86::JMP_1); 6800 Branch.addOperand(MCOperand::createExpr(BranchTarget)); 6801 } 6802 6803 // This code must remain in sync with getJumpInstrTableEntryBound in this class! 6804 // In particular, getJumpInstrTableEntryBound must always return an upper bound 6805 // on the encoding lengths of the instructions generated by 6806 // getUnconditionalBranch and getTrap. 6807 void X86InstrInfo::getTrap(MCInst &MI) const { 6808 MI.setOpcode(X86::TRAP); 6809 } 6810 6811 // See getTrap and getUnconditionalBranch for conditions on the value returned 6812 // by this function. 6813 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const { 6814 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4 6815 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B). 6816 return 5; 6817 } 6818 6819 bool X86InstrInfo::isHighLatencyDef(int opc) const { 6820 switch (opc) { 6821 default: return false; 6822 case X86::DIVSDrm: 6823 case X86::DIVSDrm_Int: 6824 case X86::DIVSDrr: 6825 case X86::DIVSDrr_Int: 6826 case X86::DIVSSrm: 6827 case X86::DIVSSrm_Int: 6828 case X86::DIVSSrr: 6829 case X86::DIVSSrr_Int: 6830 case X86::SQRTPDm: 6831 case X86::SQRTPDr: 6832 case X86::SQRTPSm: 6833 case X86::SQRTPSr: 6834 case X86::SQRTSDm: 6835 case X86::SQRTSDm_Int: 6836 case X86::SQRTSDr: 6837 case X86::SQRTSDr_Int: 6838 case X86::SQRTSSm: 6839 case X86::SQRTSSm_Int: 6840 case X86::SQRTSSr: 6841 case X86::SQRTSSr_Int: 6842 // AVX instructions with high latency 6843 case X86::VDIVSDrm: 6844 case X86::VDIVSDrm_Int: 6845 case X86::VDIVSDrr: 6846 case X86::VDIVSDrr_Int: 6847 case X86::VDIVSSrm: 6848 case X86::VDIVSSrm_Int: 6849 case X86::VDIVSSrr: 6850 case X86::VDIVSSrr_Int: 6851 case X86::VSQRTPDm: 6852 case X86::VSQRTPDr: 6853 case X86::VSQRTPSm: 6854 case X86::VSQRTPSr: 6855 case X86::VSQRTSDm: 6856 case X86::VSQRTSDm_Int: 6857 case X86::VSQRTSDr: 6858 case X86::VSQRTSSm: 6859 case X86::VSQRTSSm_Int: 6860 case X86::VSQRTSSr: 6861 case X86::VSQRTPDZm: 6862 case X86::VSQRTPDZr: 6863 case X86::VSQRTPSZm: 6864 case X86::VSQRTPSZr: 6865 case X86::VSQRTSDZm: 6866 case X86::VSQRTSDZm_Int: 6867 case X86::VSQRTSDZr: 6868 case X86::VSQRTSSZm_Int: 6869 case X86::VSQRTSSZr: 6870 case X86::VSQRTSSZm: 6871 case X86::VDIVSDZrm: 6872 case X86::VDIVSDZrr: 6873 case X86::VDIVSSZrm: 6874 case X86::VDIVSSZrr: 6875 6876 case X86::VGATHERQPSZrm: 6877 case X86::VGATHERQPDZrm: 6878 case X86::VGATHERDPDZrm: 6879 case X86::VGATHERDPSZrm: 6880 case X86::VPGATHERQDZrm: 6881 case X86::VPGATHERQQZrm: 6882 case X86::VPGATHERDDZrm: 6883 case X86::VPGATHERDQZrm: 6884 case X86::VSCATTERQPDZmr: 6885 case X86::VSCATTERQPSZmr: 6886 case X86::VSCATTERDPDZmr: 6887 case X86::VSCATTERDPSZmr: 6888 case X86::VPSCATTERQDZmr: 6889 case X86::VPSCATTERQQZmr: 6890 case X86::VPSCATTERDDZmr: 6891 case X86::VPSCATTERDQZmr: 6892 return true; 6893 } 6894 } 6895 6896 bool X86InstrInfo:: 6897 hasHighOperandLatency(const TargetSchedModel &SchedModel, 6898 const MachineRegisterInfo *MRI, 6899 const MachineInstr *DefMI, unsigned DefIdx, 6900 const MachineInstr *UseMI, unsigned UseIdx) const { 6901 return isHighLatencyDef(DefMI->getOpcode()); 6902 } 6903 6904 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst, 6905 const MachineBasicBlock *MBB) const { 6906 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) && 6907 "Reassociation needs binary operators"); 6908 6909 // Integer binary math/logic instructions have a third source operand: 6910 // the EFLAGS register. That operand must be both defined here and never 6911 // used; ie, it must be dead. If the EFLAGS operand is live, then we can 6912 // not change anything because rearranging the operands could affect other 6913 // instructions that depend on the exact status flags (zero, sign, etc.) 6914 // that are set by using these particular operands with this operation. 6915 if (Inst.getNumOperands() == 4) { 6916 assert(Inst.getOperand(3).isReg() && 6917 Inst.getOperand(3).getReg() == X86::EFLAGS && 6918 "Unexpected operand in reassociable instruction"); 6919 if (!Inst.getOperand(3).isDead()) 6920 return false; 6921 } 6922 6923 return TargetInstrInfo::hasReassociableOperands(Inst, MBB); 6924 } 6925 6926 // TODO: There are many more machine instruction opcodes to match: 6927 // 1. Other data types (integer, vectors) 6928 // 2. Other math / logic operations (xor, or) 6929 // 3. Other forms of the same operation (intrinsics and other variants) 6930 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const { 6931 switch (Inst.getOpcode()) { 6932 case X86::AND8rr: 6933 case X86::AND16rr: 6934 case X86::AND32rr: 6935 case X86::AND64rr: 6936 case X86::OR8rr: 6937 case X86::OR16rr: 6938 case X86::OR32rr: 6939 case X86::OR64rr: 6940 case X86::XOR8rr: 6941 case X86::XOR16rr: 6942 case X86::XOR32rr: 6943 case X86::XOR64rr: 6944 case X86::IMUL16rr: 6945 case X86::IMUL32rr: 6946 case X86::IMUL64rr: 6947 case X86::PANDrr: 6948 case X86::PORrr: 6949 case X86::PXORrr: 6950 case X86::VPANDrr: 6951 case X86::VPANDYrr: 6952 case X86::VPORrr: 6953 case X86::VPORYrr: 6954 case X86::VPXORrr: 6955 case X86::VPXORYrr: 6956 // Normal min/max instructions are not commutative because of NaN and signed 6957 // zero semantics, but these are. Thus, there's no need to check for global 6958 // relaxed math; the instructions themselves have the properties we need. 6959 case X86::MAXCPDrr: 6960 case X86::MAXCPSrr: 6961 case X86::MAXCSDrr: 6962 case X86::MAXCSSrr: 6963 case X86::MINCPDrr: 6964 case X86::MINCPSrr: 6965 case X86::MINCSDrr: 6966 case X86::MINCSSrr: 6967 case X86::VMAXCPDrr: 6968 case X86::VMAXCPSrr: 6969 case X86::VMAXCPDYrr: 6970 case X86::VMAXCPSYrr: 6971 case X86::VMAXCSDrr: 6972 case X86::VMAXCSSrr: 6973 case X86::VMINCPDrr: 6974 case X86::VMINCPSrr: 6975 case X86::VMINCPDYrr: 6976 case X86::VMINCPSYrr: 6977 case X86::VMINCSDrr: 6978 case X86::VMINCSSrr: 6979 return true; 6980 case X86::ADDPDrr: 6981 case X86::ADDPSrr: 6982 case X86::ADDSDrr: 6983 case X86::ADDSSrr: 6984 case X86::MULPDrr: 6985 case X86::MULPSrr: 6986 case X86::MULSDrr: 6987 case X86::MULSSrr: 6988 case X86::VADDPDrr: 6989 case X86::VADDPSrr: 6990 case X86::VADDPDYrr: 6991 case X86::VADDPSYrr: 6992 case X86::VADDSDrr: 6993 case X86::VADDSSrr: 6994 case X86::VMULPDrr: 6995 case X86::VMULPSrr: 6996 case X86::VMULPDYrr: 6997 case X86::VMULPSYrr: 6998 case X86::VMULSDrr: 6999 case X86::VMULSSrr: 7000 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath; 7001 default: 7002 return false; 7003 } 7004 } 7005 7006 /// This is an architecture-specific helper function of reassociateOps. 7007 /// Set special operand attributes for new instructions after reassociation. 7008 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1, 7009 MachineInstr &OldMI2, 7010 MachineInstr &NewMI1, 7011 MachineInstr &NewMI2) const { 7012 // Integer instructions define an implicit EFLAGS source register operand as 7013 // the third source (fourth total) operand. 7014 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4) 7015 return; 7016 7017 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 && 7018 "Unexpected instruction type for reassociation"); 7019 7020 MachineOperand &OldOp1 = OldMI1.getOperand(3); 7021 MachineOperand &OldOp2 = OldMI2.getOperand(3); 7022 MachineOperand &NewOp1 = NewMI1.getOperand(3); 7023 MachineOperand &NewOp2 = NewMI2.getOperand(3); 7024 7025 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() && 7026 "Must have dead EFLAGS operand in reassociable instruction"); 7027 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() && 7028 "Must have dead EFLAGS operand in reassociable instruction"); 7029 7030 (void)OldOp1; 7031 (void)OldOp2; 7032 7033 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS && 7034 "Unexpected operand in reassociable instruction"); 7035 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS && 7036 "Unexpected operand in reassociable instruction"); 7037 7038 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations 7039 // of this pass or other passes. The EFLAGS operands must be dead in these new 7040 // instructions because the EFLAGS operands in the original instructions must 7041 // be dead in order for reassociation to occur. 7042 NewOp1.setIsDead(); 7043 NewOp2.setIsDead(); 7044 } 7045 7046 std::pair<unsigned, unsigned> 7047 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { 7048 return std::make_pair(TF, 0u); 7049 } 7050 7051 ArrayRef<std::pair<unsigned, const char *>> 7052 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const { 7053 using namespace X86II; 7054 static const std::pair<unsigned, const char *> TargetFlags[] = { 7055 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"}, 7056 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"}, 7057 {MO_GOT, "x86-got"}, 7058 {MO_GOTOFF, "x86-gotoff"}, 7059 {MO_GOTPCREL, "x86-gotpcrel"}, 7060 {MO_PLT, "x86-plt"}, 7061 {MO_TLSGD, "x86-tlsgd"}, 7062 {MO_TLSLD, "x86-tlsld"}, 7063 {MO_TLSLDM, "x86-tlsldm"}, 7064 {MO_GOTTPOFF, "x86-gottpoff"}, 7065 {MO_INDNTPOFF, "x86-indntpoff"}, 7066 {MO_TPOFF, "x86-tpoff"}, 7067 {MO_DTPOFF, "x86-dtpoff"}, 7068 {MO_NTPOFF, "x86-ntpoff"}, 7069 {MO_GOTNTPOFF, "x86-gotntpoff"}, 7070 {MO_DLLIMPORT, "x86-dllimport"}, 7071 {MO_DARWIN_STUB, "x86-darwin-stub"}, 7072 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"}, 7073 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"}, 7074 {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"}, 7075 {MO_TLVP, "x86-tlvp"}, 7076 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"}, 7077 {MO_SECREL, "x86-secrel"}}; 7078 return makeArrayRef(TargetFlags); 7079 } 7080 7081 namespace { 7082 /// Create Global Base Reg pass. This initializes the PIC 7083 /// global base register for x86-32. 7084 struct CGBR : public MachineFunctionPass { 7085 static char ID; 7086 CGBR() : MachineFunctionPass(ID) {} 7087 7088 bool runOnMachineFunction(MachineFunction &MF) override { 7089 const X86TargetMachine *TM = 7090 static_cast<const X86TargetMachine *>(&MF.getTarget()); 7091 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>(); 7092 7093 // Don't do anything if this is 64-bit as 64-bit PIC 7094 // uses RIP relative addressing. 7095 if (STI.is64Bit()) 7096 return false; 7097 7098 // Only emit a global base reg in PIC mode. 7099 if (TM->getRelocationModel() != Reloc::PIC_) 7100 return false; 7101 7102 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 7103 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 7104 7105 // If we didn't need a GlobalBaseReg, don't insert code. 7106 if (GlobalBaseReg == 0) 7107 return false; 7108 7109 // Insert the set of GlobalBaseReg into the first MBB of the function 7110 MachineBasicBlock &FirstMBB = MF.front(); 7111 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 7112 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 7113 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 7114 const X86InstrInfo *TII = STI.getInstrInfo(); 7115 7116 unsigned PC; 7117 if (STI.isPICStyleGOT()) 7118 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 7119 else 7120 PC = GlobalBaseReg; 7121 7122 // Operand of MovePCtoStack is completely ignored by asm printer. It's 7123 // only used in JIT code emission as displacement to pc. 7124 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 7125 7126 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 7127 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 7128 if (STI.isPICStyleGOT()) { 7129 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 7130 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 7131 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 7132 X86II::MO_GOT_ABSOLUTE_ADDRESS); 7133 } 7134 7135 return true; 7136 } 7137 7138 const char *getPassName() const override { 7139 return "X86 PIC Global Base Reg Initialization"; 7140 } 7141 7142 void getAnalysisUsage(AnalysisUsage &AU) const override { 7143 AU.setPreservesCFG(); 7144 MachineFunctionPass::getAnalysisUsage(AU); 7145 } 7146 }; 7147 } 7148 7149 char CGBR::ID = 0; 7150 FunctionPass* 7151 llvm::createX86GlobalBaseRegPass() { return new CGBR(); } 7152 7153 namespace { 7154 struct LDTLSCleanup : public MachineFunctionPass { 7155 static char ID; 7156 LDTLSCleanup() : MachineFunctionPass(ID) {} 7157 7158 bool runOnMachineFunction(MachineFunction &MF) override { 7159 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 7160 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 7161 // No point folding accesses if there isn't at least two. 7162 return false; 7163 } 7164 7165 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 7166 return VisitNode(DT->getRootNode(), 0); 7167 } 7168 7169 // Visit the dominator subtree rooted at Node in pre-order. 7170 // If TLSBaseAddrReg is non-null, then use that to replace any 7171 // TLS_base_addr instructions. Otherwise, create the register 7172 // when the first such instruction is seen, and then use it 7173 // as we encounter more instructions. 7174 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 7175 MachineBasicBlock *BB = Node->getBlock(); 7176 bool Changed = false; 7177 7178 // Traverse the current block. 7179 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 7180 ++I) { 7181 switch (I->getOpcode()) { 7182 case X86::TLS_base_addr32: 7183 case X86::TLS_base_addr64: 7184 if (TLSBaseAddrReg) 7185 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 7186 else 7187 I = SetRegister(I, &TLSBaseAddrReg); 7188 Changed = true; 7189 break; 7190 default: 7191 break; 7192 } 7193 } 7194 7195 // Visit the children of this block in the dominator tree. 7196 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 7197 I != E; ++I) { 7198 Changed |= VisitNode(*I, TLSBaseAddrReg); 7199 } 7200 7201 return Changed; 7202 } 7203 7204 // Replace the TLS_base_addr instruction I with a copy from 7205 // TLSBaseAddrReg, returning the new instruction. 7206 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 7207 unsigned TLSBaseAddrReg) { 7208 MachineFunction *MF = I->getParent()->getParent(); 7209 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>(); 7210 const bool is64Bit = STI.is64Bit(); 7211 const X86InstrInfo *TII = STI.getInstrInfo(); 7212 7213 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 7214 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 7215 TII->get(TargetOpcode::COPY), 7216 is64Bit ? X86::RAX : X86::EAX) 7217 .addReg(TLSBaseAddrReg); 7218 7219 // Erase the TLS_base_addr instruction. 7220 I->eraseFromParent(); 7221 7222 return Copy; 7223 } 7224 7225 // Create a virtal register in *TLSBaseAddrReg, and populate it by 7226 // inserting a copy instruction after I. Returns the new instruction. 7227 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 7228 MachineFunction *MF = I->getParent()->getParent(); 7229 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>(); 7230 const bool is64Bit = STI.is64Bit(); 7231 const X86InstrInfo *TII = STI.getInstrInfo(); 7232 7233 // Create a virtual register for the TLS base address. 7234 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 7235 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 7236 ? &X86::GR64RegClass 7237 : &X86::GR32RegClass); 7238 7239 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 7240 MachineInstr *Next = I->getNextNode(); 7241 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 7242 TII->get(TargetOpcode::COPY), 7243 *TLSBaseAddrReg) 7244 .addReg(is64Bit ? X86::RAX : X86::EAX); 7245 7246 return Copy; 7247 } 7248 7249 const char *getPassName() const override { 7250 return "Local Dynamic TLS Access Clean-up"; 7251 } 7252 7253 void getAnalysisUsage(AnalysisUsage &AU) const override { 7254 AU.setPreservesCFG(); 7255 AU.addRequired<MachineDominatorTree>(); 7256 MachineFunctionPass::getAnalysisUsage(AU); 7257 } 7258 }; 7259 } 7260 7261 char LDTLSCleanup::ID = 0; 7262 FunctionPass* 7263 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 7264