1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "x86-instr-info"
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47 
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60 
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_4    = 4,
69   TB_INDEX_MASK = 0xf,
70 
71   // Do not insert the reverse map (MemOp -> RegOp) into the table.
72   // This may be needed because there is a many -> one mapping.
73   TB_NO_REVERSE   = 1 << 4,
74 
75   // Do not insert the forward map (RegOp -> MemOp) into the table.
76   // This is needed for Native Client, which prohibits branch
77   // instructions from using a memory operand.
78   TB_NO_FORWARD   = 1 << 5,
79 
80   TB_FOLDED_LOAD  = 1 << 6,
81   TB_FOLDED_STORE = 1 << 7,
82 
83   // Minimum alignment required for load/store.
84   // Used for RegOp->MemOp conversion.
85   // (stored in bits 8 - 15)
86   TB_ALIGN_SHIFT = 8,
87   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92 };
93 
94 struct X86MemoryFoldTableEntry {
95   uint16_t RegOp;
96   uint16_t MemOp;
97   uint16_t Flags;
98 };
99 
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
102 
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104     : X86GenInstrInfo(
105           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107       Subtarget(STI), RI(STI) {
108 
109   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
110     { X86::ADC32ri,     X86::ADC32mi,    0 },
111     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
112     { X86::ADC32rr,     X86::ADC32mr,    0 },
113     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
114     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
115     { X86::ADC64rr,     X86::ADC64mr,    0 },
116     { X86::ADD16ri,     X86::ADD16mi,    0 },
117     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
118     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
119     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
120     { X86::ADD16rr,     X86::ADD16mr,    0 },
121     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
122     { X86::ADD32ri,     X86::ADD32mi,    0 },
123     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
124     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
125     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
126     { X86::ADD32rr,     X86::ADD32mr,    0 },
127     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
128     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
129     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
130     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
131     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
132     { X86::ADD64rr,     X86::ADD64mr,    0 },
133     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
134     { X86::ADD8ri,      X86::ADD8mi,     0 },
135     { X86::ADD8rr,      X86::ADD8mr,     0 },
136     { X86::AND16ri,     X86::AND16mi,    0 },
137     { X86::AND16ri8,    X86::AND16mi8,   0 },
138     { X86::AND16rr,     X86::AND16mr,    0 },
139     { X86::AND32ri,     X86::AND32mi,    0 },
140     { X86::AND32ri8,    X86::AND32mi8,   0 },
141     { X86::AND32rr,     X86::AND32mr,    0 },
142     { X86::AND64ri32,   X86::AND64mi32,  0 },
143     { X86::AND64ri8,    X86::AND64mi8,   0 },
144     { X86::AND64rr,     X86::AND64mr,    0 },
145     { X86::AND8ri,      X86::AND8mi,     0 },
146     { X86::AND8rr,      X86::AND8mr,     0 },
147     { X86::DEC16r,      X86::DEC16m,     0 },
148     { X86::DEC32r,      X86::DEC32m,     0 },
149     { X86::DEC64r,      X86::DEC64m,     0 },
150     { X86::DEC8r,       X86::DEC8m,      0 },
151     { X86::INC16r,      X86::INC16m,     0 },
152     { X86::INC32r,      X86::INC32m,     0 },
153     { X86::INC64r,      X86::INC64m,     0 },
154     { X86::INC8r,       X86::INC8m,      0 },
155     { X86::NEG16r,      X86::NEG16m,     0 },
156     { X86::NEG32r,      X86::NEG32m,     0 },
157     { X86::NEG64r,      X86::NEG64m,     0 },
158     { X86::NEG8r,       X86::NEG8m,      0 },
159     { X86::NOT16r,      X86::NOT16m,     0 },
160     { X86::NOT32r,      X86::NOT32m,     0 },
161     { X86::NOT64r,      X86::NOT64m,     0 },
162     { X86::NOT8r,       X86::NOT8m,      0 },
163     { X86::OR16ri,      X86::OR16mi,     0 },
164     { X86::OR16ri8,     X86::OR16mi8,    0 },
165     { X86::OR16rr,      X86::OR16mr,     0 },
166     { X86::OR32ri,      X86::OR32mi,     0 },
167     { X86::OR32ri8,     X86::OR32mi8,    0 },
168     { X86::OR32rr,      X86::OR32mr,     0 },
169     { X86::OR64ri32,    X86::OR64mi32,   0 },
170     { X86::OR64ri8,     X86::OR64mi8,    0 },
171     { X86::OR64rr,      X86::OR64mr,     0 },
172     { X86::OR8ri,       X86::OR8mi,      0 },
173     { X86::OR8rr,       X86::OR8mr,      0 },
174     { X86::ROL16r1,     X86::ROL16m1,    0 },
175     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
176     { X86::ROL16ri,     X86::ROL16mi,    0 },
177     { X86::ROL32r1,     X86::ROL32m1,    0 },
178     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
179     { X86::ROL32ri,     X86::ROL32mi,    0 },
180     { X86::ROL64r1,     X86::ROL64m1,    0 },
181     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
182     { X86::ROL64ri,     X86::ROL64mi,    0 },
183     { X86::ROL8r1,      X86::ROL8m1,     0 },
184     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
185     { X86::ROL8ri,      X86::ROL8mi,     0 },
186     { X86::ROR16r1,     X86::ROR16m1,    0 },
187     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
188     { X86::ROR16ri,     X86::ROR16mi,    0 },
189     { X86::ROR32r1,     X86::ROR32m1,    0 },
190     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
191     { X86::ROR32ri,     X86::ROR32mi,    0 },
192     { X86::ROR64r1,     X86::ROR64m1,    0 },
193     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
194     { X86::ROR64ri,     X86::ROR64mi,    0 },
195     { X86::ROR8r1,      X86::ROR8m1,     0 },
196     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
197     { X86::ROR8ri,      X86::ROR8mi,     0 },
198     { X86::SAR16r1,     X86::SAR16m1,    0 },
199     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
200     { X86::SAR16ri,     X86::SAR16mi,    0 },
201     { X86::SAR32r1,     X86::SAR32m1,    0 },
202     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
203     { X86::SAR32ri,     X86::SAR32mi,    0 },
204     { X86::SAR64r1,     X86::SAR64m1,    0 },
205     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
206     { X86::SAR64ri,     X86::SAR64mi,    0 },
207     { X86::SAR8r1,      X86::SAR8m1,     0 },
208     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
209     { X86::SAR8ri,      X86::SAR8mi,     0 },
210     { X86::SBB32ri,     X86::SBB32mi,    0 },
211     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
212     { X86::SBB32rr,     X86::SBB32mr,    0 },
213     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
214     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
215     { X86::SBB64rr,     X86::SBB64mr,    0 },
216     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
217     { X86::SHL16ri,     X86::SHL16mi,    0 },
218     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
219     { X86::SHL32ri,     X86::SHL32mi,    0 },
220     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
221     { X86::SHL64ri,     X86::SHL64mi,    0 },
222     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
223     { X86::SHL8ri,      X86::SHL8mi,     0 },
224     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
225     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
226     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
227     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
228     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
229     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
230     { X86::SHR16r1,     X86::SHR16m1,    0 },
231     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
232     { X86::SHR16ri,     X86::SHR16mi,    0 },
233     { X86::SHR32r1,     X86::SHR32m1,    0 },
234     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
235     { X86::SHR32ri,     X86::SHR32mi,    0 },
236     { X86::SHR64r1,     X86::SHR64m1,    0 },
237     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
238     { X86::SHR64ri,     X86::SHR64mi,    0 },
239     { X86::SHR8r1,      X86::SHR8m1,     0 },
240     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
241     { X86::SHR8ri,      X86::SHR8mi,     0 },
242     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
243     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
244     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
245     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
246     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
247     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
248     { X86::SUB16ri,     X86::SUB16mi,    0 },
249     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
250     { X86::SUB16rr,     X86::SUB16mr,    0 },
251     { X86::SUB32ri,     X86::SUB32mi,    0 },
252     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
253     { X86::SUB32rr,     X86::SUB32mr,    0 },
254     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
255     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
256     { X86::SUB64rr,     X86::SUB64mr,    0 },
257     { X86::SUB8ri,      X86::SUB8mi,     0 },
258     { X86::SUB8rr,      X86::SUB8mr,     0 },
259     { X86::XOR16ri,     X86::XOR16mi,    0 },
260     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
261     { X86::XOR16rr,     X86::XOR16mr,    0 },
262     { X86::XOR32ri,     X86::XOR32mi,    0 },
263     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
264     { X86::XOR32rr,     X86::XOR32mr,    0 },
265     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
266     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
267     { X86::XOR64rr,     X86::XOR64mr,    0 },
268     { X86::XOR8ri,      X86::XOR8mi,     0 },
269     { X86::XOR8rr,      X86::XOR8mr,     0 }
270   };
271 
272   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable2Addr); i != e; ++i) {
273     unsigned RegOp = MemoryFoldTable2Addr[i].RegOp;
274     unsigned MemOp = MemoryFoldTable2Addr[i].MemOp;
275     unsigned Flags = MemoryFoldTable2Addr[i].Flags;
276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                   RegOp, MemOp,
278                   // Index 0, folded load and store, no alignment requirement.
279                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280   }
281 
282   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
338     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
339     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
340     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
341     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
342     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
343     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
344     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
345     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
346     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
347     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
348     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
349     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
350     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
351     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
352     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
353     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
354     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
355     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
356     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
357     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
358     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
359     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
360     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
361 
362     // AVX 128-bit versions of foldable instructions
363     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
364     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
368     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
369     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
371     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
372     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
373     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
374     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
375     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
376 
377     // AVX 256-bit foldable instructions
378     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
379     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
380     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
381     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
382     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
383     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
384 
385     // AVX-512 foldable instructions
386     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
387     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
388     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
389     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
390     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
391     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
392     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
393     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
394     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
395     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
396     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
397 
398     // AVX-512 foldable instructions (256-bit versions)
399     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
400     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
401     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
404     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
405     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
406     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
407     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
408     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
409 
410     // AVX-512 foldable instructions (128-bit versions)
411     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
412     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
413     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
414     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
415     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
416     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
417     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
418     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
419     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
420     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
421 
422     // F16C foldable instructions
423     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
424     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
425   };
426 
427   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable0); i != e; ++i) {
428     unsigned RegOp      = MemoryFoldTable0[i].RegOp;
429     unsigned MemOp      = MemoryFoldTable0[i].MemOp;
430     unsigned Flags      = MemoryFoldTable0[i].Flags;
431     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432                   RegOp, MemOp, TB_INDEX_0 | Flags);
433   }
434 
435   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
436     { X86::CMP16rr,         X86::CMP16rm,             0 },
437     { X86::CMP32rr,         X86::CMP32rm,             0 },
438     { X86::CMP64rr,         X86::CMP64rm,             0 },
439     { X86::CMP8rr,          X86::CMP8rm,              0 },
440     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
441     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
442     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
443     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
444     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
445     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
446     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
447     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
448     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
449     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
450     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
451     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
452     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
453     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
454     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
455     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
456     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
457     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
458     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
459     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
460     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
461     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
462     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
463     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
464     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
465     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
466     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
467     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
468     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
469     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
470     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
471     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
472     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
473     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
474     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
475     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
476     { X86::MOV16rr,         X86::MOV16rm,             0 },
477     { X86::MOV32rr,         X86::MOV32rm,             0 },
478     { X86::MOV64rr,         X86::MOV64rm,             0 },
479     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
480     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
481     { X86::MOV8rr,          X86::MOV8rm,              0 },
482     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
483     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
484     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
485     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
486     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
487     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
488     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
489     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
490     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
491     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
492     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
493     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
494     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
495     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
496     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
497     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
498     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
499     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
500     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
501     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
502     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
503     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
504     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
505     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
506     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
507     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
508     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
509     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
510     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
511     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
512     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
513     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
514     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
515     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
516     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
517     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
518     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
519     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
520     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
521     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
522     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
523     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
524     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
525     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
526     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
527     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
528     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
529     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
530     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
531     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
532     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
533     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
534     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
535     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
536     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
537     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
538     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
539     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
540     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
541     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
542     { X86::TEST16rr,        X86::TEST16rm,            0 },
543     { X86::TEST32rr,        X86::TEST32rm,            0 },
544     { X86::TEST64rr,        X86::TEST64rm,            0 },
545     { X86::TEST8rr,         X86::TEST8rm,             0 },
546     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
547     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
548     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
549 
550     // MMX version of foldable instructions
551     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
552     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
553     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
554     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
555     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
556     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
557     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
558     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
559     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
560     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
561 
562     // AVX 128-bit versions of foldable instructions
563     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
564     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
565     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
566     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
567     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
568     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
569     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
570     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
571     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
572     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
573     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
574     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
575     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
576     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
577     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
578     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
579     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
580     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
581     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
582     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
583     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
584     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
585     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
586     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
587     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
588     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
589     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
590     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
591     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
592     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
593     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
594     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
595     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
596     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
597     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
598     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
599     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
600     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
601     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
602     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
603     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
604     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
605     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
606     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
607     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
608     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
609     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
610     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
611     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
612     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
613     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
614     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
615     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
616     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
617     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
618     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
619     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
620     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
621     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
622     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
623     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
624     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
625     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
626     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
627     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
628     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
629     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
630     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
631     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
632     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
633     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
634     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
635     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
636     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
637     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
638     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
639 
640     // AVX 256-bit foldable instructions
641     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
642     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
643     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
644     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
645     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
646     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
647     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
648     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
649     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
650     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
651     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
652     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
653     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
654     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
655     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
656     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
657     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
658     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
659     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
660     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
661     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
662     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
663     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
664     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
665     { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      0 },
666     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
667     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
668     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
669     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
670 
671     // AVX2 foldable instructions
672 
673     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
674     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
675     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
676     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
677     // so they don't need an equivalent limitation.
678     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
679     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
680     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
681     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
682     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
683     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
684     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
685     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
686     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
687     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
688     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
689     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
690     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
691     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
692     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
693     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
694     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
695     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
696     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
697     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
698     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
699     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
700     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
701     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
702     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
703     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
704     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
705     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
706     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
707     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
708     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
709 
710     // XOP foldable instructions
711     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
712     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
713     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
714     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
715     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
716     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
717     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
718     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
719     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
720     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
721     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
722     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
723     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
724     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
725     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
726     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
727     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
728     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
729     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
730     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
731     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
732     { X86::VPROTBri,           X86::VPROTBmi,         0 },
733     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
734     { X86::VPROTDri,           X86::VPROTDmi,         0 },
735     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
736     { X86::VPROTQri,           X86::VPROTQmi,         0 },
737     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
738     { X86::VPROTWri,           X86::VPROTWmi,         0 },
739     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
740     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
741     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
742     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
743     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
744     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
745     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
746     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
747     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
748 
749     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
750     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
751     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
752     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
753     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
754     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
755     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
756     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
757     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
758     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
759     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
760     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
761     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
762     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
763     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
764     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
765     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
766     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
767     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
768     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
769     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
770     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
771     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
772     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
773     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
774     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
775     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
776     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
777     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
778     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
779     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
780     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
781     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
782     { X86::RORX32ri,        X86::RORX32mi,            0 },
783     { X86::RORX64ri,        X86::RORX64mi,            0 },
784     { X86::SARX32rr,        X86::SARX32rm,            0 },
785     { X86::SARX64rr,        X86::SARX64rm,            0 },
786     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
787     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
788     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
789     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
790     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
791     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
792     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
793     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
794     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
795     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
796     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
797 
798     // AVX-512 foldable instructions
799     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
800     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
801     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
802     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
803     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
804     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
805     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
806     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
807     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
808     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
809     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
810     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
811     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
812     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
813     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
814     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
815 
816     // AVX-512 foldable instructions (256-bit versions)
817     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
818     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
819     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
820     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
821     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
822     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
823     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
824     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
825     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
826     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
827     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
828     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
829 
830     // AVX-512 foldable instructions (256-bit versions)
831     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
832     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
833     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
834     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
835     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
836     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
837     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
838     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
839     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
840     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
841     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
842 
843     // F16C foldable instructions
844     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
845     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
846 
847     // AES foldable instructions
848     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
849     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
850     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
851     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
852   };
853 
854   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable1); i != e; ++i) {
855     unsigned RegOp = MemoryFoldTable1[i].RegOp;
856     unsigned MemOp = MemoryFoldTable1[i].MemOp;
857     unsigned Flags = MemoryFoldTable1[i].Flags;
858     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
859                   RegOp, MemOp,
860                   // Index 1, folded load
861                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
862   }
863 
864   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
865     { X86::ADC32rr,         X86::ADC32rm,       0 },
866     { X86::ADC64rr,         X86::ADC64rm,       0 },
867     { X86::ADD16rr,         X86::ADD16rm,       0 },
868     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
869     { X86::ADD32rr,         X86::ADD32rm,       0 },
870     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
871     { X86::ADD64rr,         X86::ADD64rm,       0 },
872     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
873     { X86::ADD8rr,          X86::ADD8rm,        0 },
874     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
875     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
876     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
877     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
878     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
879     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
880     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
881     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
882     { X86::AND16rr,         X86::AND16rm,       0 },
883     { X86::AND32rr,         X86::AND32rm,       0 },
884     { X86::AND64rr,         X86::AND64rm,       0 },
885     { X86::AND8rr,          X86::AND8rm,        0 },
886     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
887     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
888     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
889     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
890     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
891     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
892     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
893     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
894     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
895     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
896     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
897     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
898     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
899     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
900     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
901     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
902     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
903     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
904     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
905     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
906     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
907     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
908     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
909     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
910     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
911     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
912     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
913     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
914     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
915     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
916     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
917     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
918     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
919     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
920     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
921     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
922     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
923     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
924     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
925     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
926     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
927     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
928     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
929     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
930     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
931     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
932     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
933     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
934     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
935     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
936     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
937     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
938     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
939     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
940     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
941     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
942     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
943     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
944     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
945     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
946     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
947     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
948     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
949     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
950     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
951     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
952     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
953     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
954 
955     // FIXME: We should not be folding Fs* scalar loads into vector
956     // instructions because the vector instructions require vector-sized
957     // loads. Lowering should create vector-sized instructions (the Fv*
958     // variants below) to allow load folding.
959     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
960     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
961     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
962     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
963     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
964     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
965     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
966     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
967 
968     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
969     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
970     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
971     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
972     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
973     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
974     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
975     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
976     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
977     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
978     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
979     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
980     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
981     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
982     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
983     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
984     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
985     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
986     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
987     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
988     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
989     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
990     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
991     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
992     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
993     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
994     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
995     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
996     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
997     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
998     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
999     { X86::MINSDrr,         X86::MINSDrm,       0 },
1000     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1001     { X86::MINSSrr,         X86::MINSSrm,       0 },
1002     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1003     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1004     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1005     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1006     { X86::MULSDrr,         X86::MULSDrm,       0 },
1007     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1008     { X86::MULSSrr,         X86::MULSSrm,       0 },
1009     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1010     { X86::OR16rr,          X86::OR16rm,        0 },
1011     { X86::OR32rr,          X86::OR32rm,        0 },
1012     { X86::OR64rr,          X86::OR64rm,        0 },
1013     { X86::OR8rr,           X86::OR8rm,         0 },
1014     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1015     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1016     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1017     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1018     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1019     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1020     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1021     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1022     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1023     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1024     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1025     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1026     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1027     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1028     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1029     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1030     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1031     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1032     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1033     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1034     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1035     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1036     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1037     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1038     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1039     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1040     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1041     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1042     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1043     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1044     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1045     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1046     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1047     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1048     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1049     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1050     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1051     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1052     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1053     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1054     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1055     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1056     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1057     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1058     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1059     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1060     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1061     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1062     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1063     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1064     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1065     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1066     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1067     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1068     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1069     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1070     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1071     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1072     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1073     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1074     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1075     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1076     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1077     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1078     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
1079     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
1080     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
1081     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1082     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1083     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1084     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1085     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1086     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1087     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1088     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1089     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1090     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1091     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1092     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1093     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1094     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1095     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1096     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1097     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1098     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1099     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1100     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1101     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1102     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1103     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1104     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1105     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1106     { X86::SBB32rr,         X86::SBB32rm,       0 },
1107     { X86::SBB64rr,         X86::SBB64rm,       0 },
1108     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1109     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1110     { X86::SUB16rr,         X86::SUB16rm,       0 },
1111     { X86::SUB32rr,         X86::SUB32rm,       0 },
1112     { X86::SUB64rr,         X86::SUB64rm,       0 },
1113     { X86::SUB8rr,          X86::SUB8rm,        0 },
1114     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1115     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1116     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1117     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1118     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1119     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1120     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1121     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1122     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1123     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1124     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1125     { X86::XOR16rr,         X86::XOR16rm,       0 },
1126     { X86::XOR32rr,         X86::XOR32rm,       0 },
1127     { X86::XOR64rr,         X86::XOR64rm,       0 },
1128     { X86::XOR8rr,          X86::XOR8rm,        0 },
1129     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1130     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1131 
1132     // MMX version of foldable instructions
1133     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1134     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1135     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1136     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1137     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1138     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1139     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1140     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1141     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1142     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1143     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1144     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1145     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1146     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1147     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1148     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1149     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1150     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1151     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1152     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1153     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1154     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1155     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1156     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1157     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1158     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1159     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1160     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1161     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1162     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1163     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1164     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1165     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1166     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1167     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1168     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1169     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1170     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1171     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1172     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1173     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1174     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1175     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1176     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1177     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1178     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1179     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1180     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1181     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1182     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1183     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1184     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1185     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1186     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1187     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1188     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1189     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1190     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1191     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1192     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1193     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1194     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1195     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1196     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1197     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1198     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1199     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1200     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1201     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1202     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1203 
1204     // AVX 128-bit versions of foldable instructions
1205     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1206     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1207     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1208     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1209     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1210     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1211     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1212     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1213     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1214     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1215     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1216     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1217     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1218     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1219     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1220     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1221     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1222     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1223     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1224     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1225     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1226     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1227     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1228     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1229     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1230     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1231     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1232     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1233     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1234     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1235     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1236     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1237     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1238     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1239     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1240     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1241     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1242     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1243     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1244     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1245     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1246     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1247     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1248     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1249     // Do not fold VFs* loads because there are no scalar load variants for
1250     // these instructions. When folded, the load is required to be 128-bits, so
1251     // the load size would not match.
1252     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1253     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1254     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1255     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1256     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1257     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1258     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1259     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1260     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1261     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1262     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1263     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1264     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1265     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1266     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1267     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1268     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1269     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1270     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1271     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1272     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1273     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1274     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1275     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1276     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1277     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1278     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1279     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1280     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1281     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1282     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1283     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1284     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1285     { X86::VORPDrr,           X86::VORPDrm,            0 },
1286     { X86::VORPSrr,           X86::VORPSrm,            0 },
1287     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1288     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1289     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1290     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1291     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1292     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1293     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1294     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1295     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1296     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1297     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1298     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1299     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1300     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1301     { X86::VPANDrr,           X86::VPANDrm,            0 },
1302     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1303     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1304     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1305     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1306     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1307     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1308     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1309     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1310     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1311     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1312     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1313     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1314     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1315     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1316     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1317     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1318     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1319     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1320     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1321     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1322     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1323     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1324     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1325     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1326     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1327     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1328     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1329     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1330     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1331     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1332     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1333     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1334     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1335     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1336     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1337     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1338     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1339     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1340     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1341     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1342     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1343     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1344     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1345     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1346     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1347     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1348     { X86::VPORrr,            X86::VPORrm,             0 },
1349     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1350     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1351     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1352     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1353     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1354     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1355     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1356     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1357     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1358     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1359     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1360     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1361     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1362     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1363     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1364     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1365     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1366     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1367     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1368     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1369     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1370     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1371     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1372     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1373     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1374     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1375     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1376     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1377     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1378     { X86::VPXORrr,           X86::VPXORrm,            0 },
1379     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1380     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1381     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1382     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1383     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1384     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1385     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1386     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1387     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1388     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1389     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1390     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1391     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1392     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1393 
1394     // AVX 256-bit foldable instructions
1395     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1396     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1397     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1398     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1399     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1400     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1401     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1402     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1403     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1404     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1405     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1406     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1407     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1408     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1409     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1410     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1411     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1412     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1413     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1414     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1415     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1416     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1417     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1418     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1419     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1420     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1421     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1422     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1423     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1424     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1425     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1426     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1427     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1428     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1429     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1430     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1431     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1432     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1433     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1434     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1435     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1436     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1437     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1438 
1439     // AVX2 foldable instructions
1440     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1441     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1442     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1443     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1444     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1445     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1446     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1447     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1448     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1449     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1450     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1451     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1452     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1453     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1454     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1455     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1456     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1457     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1458     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1459     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1460     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1461     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1462     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1463     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1464     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1465     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1466     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1467     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1468     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1469     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1470     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1471     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1472     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1473     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1474     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1475     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1476     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1477     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1478     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1479     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1480     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1481     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1482     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1483     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1484     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1485     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1486     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1487     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1488     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1489     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1490     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1491     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1492     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1493     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1494     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1495     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1496     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1497     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1498     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1499     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1500     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1501     { X86::VPORYrr,           X86::VPORYrm,            0 },
1502     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1503     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1504     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1505     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1506     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1507     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1508     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1509     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1510     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1511     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1512     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1513     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1514     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1515     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1516     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1517     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1518     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1519     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1520     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1521     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1522     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1523     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1524     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1525     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1526     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1527     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1528     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1529     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1530     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1531     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1532     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1533     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1534     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1535     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1536     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1537     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1538     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1539     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1540     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1541     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1542 
1543     // FMA4 foldable patterns
1544     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0 },
1545     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0 },
1546     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        0 },
1547     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        0 },
1548     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       0 },
1549     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       0 },
1550     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0 },
1551     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0 },
1552     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       0 },
1553     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       0 },
1554     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      0 },
1555     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      0 },
1556     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0 },
1557     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0 },
1558     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        0 },
1559     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        0 },
1560     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       0 },
1561     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       0 },
1562     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0 },
1563     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0 },
1564     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       0 },
1565     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       0 },
1566     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      0 },
1567     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      0 },
1568     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     0 },
1569     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     0 },
1570     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    0 },
1571     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    0 },
1572     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     0 },
1573     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     0 },
1574     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    0 },
1575     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    0 },
1576 
1577     // XOP foldable instructions
1578     { X86::VPCMOVrr,          X86::VPCMOVmr,            0 },
1579     { X86::VPCMOVrrY,         X86::VPCMOVmrY,           0 },
1580     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1581     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1582     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1583     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1584     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1585     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1586     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1587     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1588     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1589     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1590     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1591     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1592     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1593     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1594     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1595     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1596     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1597     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1598     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1599     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1600     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1601     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1602     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1603     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1604     { X86::VPPERMrr,          X86::VPPERMmr,            0 },
1605     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1606     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1607     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1608     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1609     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1610     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1611     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1612     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1613     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1614     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1615     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1616     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1617 
1618     // BMI/BMI2 foldable instructions
1619     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1620     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1621     { X86::MULX32rr,          X86::MULX32rm,            0 },
1622     { X86::MULX64rr,          X86::MULX64rm,            0 },
1623     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1624     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1625     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1626     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1627 
1628     // AVX-512 foldable instructions
1629     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1630     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1631     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1632     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1633     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1634     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1635     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1636     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1637     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1638     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1639     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1640     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1641     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1642     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1643     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1644     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1645     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1646     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1647     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1648     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1649     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1650     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1651     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1652     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1653     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1654     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1655     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1656     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1657     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1658     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1659     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1660     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1661     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1662     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1663     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1664     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1665     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1666     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1667     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1668 
1669     // AVX-512{F,VL} foldable instructions
1670     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1671     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1672     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1673 
1674     // AVX-512{F,VL} foldable instructions
1675     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1676     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1677     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1678     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1679 
1680     // AES foldable instructions
1681     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1682     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1683     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1684     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1685     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1686     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1687     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1688     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1689 
1690     // SHA foldable instructions
1691     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1692     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1693     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1694     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1695     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1696     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1697     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1698   };
1699 
1700   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable2); i != e; ++i) {
1701     unsigned RegOp = MemoryFoldTable2[i].RegOp;
1702     unsigned MemOp = MemoryFoldTable2[i].MemOp;
1703     unsigned Flags = MemoryFoldTable2[i].Flags;
1704     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1705                   RegOp, MemOp,
1706                   // Index 2, folded load
1707                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1708   }
1709 
1710   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1711     // FMA foldable instructions
1712     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1713     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1714     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1715     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1716     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1717     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1718 
1719     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1720     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1721     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1722     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1723     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1724     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1725     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1726     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1727     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1728     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1729     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1730     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1731 
1732     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1733     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1734     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1735     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1736     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1737     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1738 
1739     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1740     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1741     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1742     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1743     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1744     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1745     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1746     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1747     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1748     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1749     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1750     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1751 
1752     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1753     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1754     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1755     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1756     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1757     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1758 
1759     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1760     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1761     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1762     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1763     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1764     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1765     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1766     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1767     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1768     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1769     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1770     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1771 
1772     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1773     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1774     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1775     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1776     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1777     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1778 
1779     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1780     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1781     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1782     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1783     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1784     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1785     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1786     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1787     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1788     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1789     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1790     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1791 
1792     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1793     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1794     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1795     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1796     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1797     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1798     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1799     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1800     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1801     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1802     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1803     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1804 
1805     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1806     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1807     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1808     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1809     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1810     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1811     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1812     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1813     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1814     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1815     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1816     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1817 
1818     // FMA4 foldable patterns
1819     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1820     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1821     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1822     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1823     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1824     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1825     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1826     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1827     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1828     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1829     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1830     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1831     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1832     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1833     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1834     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1835     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1836     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1837     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1838     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1839     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1840     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1841     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1842     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1843     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1844     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1845     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1846     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1847     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1848     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1849     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1850     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1851 
1852     // XOP foldable instructions
1853     { X86::VPCMOVrr,              X86::VPCMOVrm,              0 },
1854     { X86::VPCMOVrrY,             X86::VPCMOVrmY,             0 },
1855     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1856     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1857     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1858     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1859     { X86::VPPERMrr,              X86::VPPERMrm,              0 },
1860 
1861     // AVX-512 VPERMI instructions with 3 source operands.
1862     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1863     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1864     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1865     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1866     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1867     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1868     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1869     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1870     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1871     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1872     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1873     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1874     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1875      // AVX-512 arithmetic instructions
1876     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1877     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1878     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1879     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1880     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1881     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1882     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1883     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1884     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1885     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1886     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1887     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1888     // AVX-512{F,VL} arithmetic instructions 256-bit
1889     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1890     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1891     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1892     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1893     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1894     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1895     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1896     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1897     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1898     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1899     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1900     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1901     // AVX-512{F,VL} arithmetic instructions 128-bit
1902     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1903     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1904     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1905     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1906     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1907     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1908     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1909     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1910     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1911     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1912     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1913     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1914   };
1915 
1916   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable3); i != e; ++i) {
1917     unsigned RegOp = MemoryFoldTable3[i].RegOp;
1918     unsigned MemOp = MemoryFoldTable3[i].MemOp;
1919     unsigned Flags = MemoryFoldTable3[i].Flags;
1920     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1921                   RegOp, MemOp,
1922                   // Index 3, folded load
1923                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1924   }
1925 
1926   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1927      // AVX-512 foldable instructions
1928     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1929     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1930     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1931     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1932     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1933     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1934     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1935     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1936     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1937     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1938     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1939     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1940     // AVX-512{F,VL} foldable instructions 256-bit
1941     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1942     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1943     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1944     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1945     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1946     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1947     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1948     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1949     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1950     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
1951     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
1952     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
1953     // AVX-512{F,VL} foldable instructions 128-bit
1954     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
1955     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
1956     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
1957     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
1958     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
1959     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
1960     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
1961     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
1962     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
1963     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
1964     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
1965     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
1966   };
1967 
1968   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable4); i != e; ++i) {
1969     unsigned RegOp = MemoryFoldTable4[i].RegOp;
1970     unsigned MemOp = MemoryFoldTable4[i].MemOp;
1971     unsigned Flags = MemoryFoldTable4[i].Flags;
1972     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1973                   RegOp, MemOp,
1974                   // Index 4, folded load
1975                   Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1976   }
1977 }
1978 
1979 void
1980 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1981                             MemOp2RegOpTableType &M2RTable,
1982                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1983     if ((Flags & TB_NO_FORWARD) == 0) {
1984       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1985       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1986     }
1987     if ((Flags & TB_NO_REVERSE) == 0) {
1988       assert(!M2RTable.count(MemOp) &&
1989            "Duplicated entries in unfolding maps?");
1990       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1991     }
1992 }
1993 
1994 bool
1995 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1996                                     unsigned &SrcReg, unsigned &DstReg,
1997                                     unsigned &SubIdx) const {
1998   switch (MI.getOpcode()) {
1999   default: break;
2000   case X86::MOVSX16rr8:
2001   case X86::MOVZX16rr8:
2002   case X86::MOVSX32rr8:
2003   case X86::MOVZX32rr8:
2004   case X86::MOVSX64rr8:
2005     if (!Subtarget.is64Bit())
2006       // It's not always legal to reference the low 8-bit of the larger
2007       // register in 32-bit mode.
2008       return false;
2009   case X86::MOVSX32rr16:
2010   case X86::MOVZX32rr16:
2011   case X86::MOVSX64rr16:
2012   case X86::MOVSX64rr32: {
2013     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2014       // Be conservative.
2015       return false;
2016     SrcReg = MI.getOperand(1).getReg();
2017     DstReg = MI.getOperand(0).getReg();
2018     switch (MI.getOpcode()) {
2019     default: llvm_unreachable("Unreachable!");
2020     case X86::MOVSX16rr8:
2021     case X86::MOVZX16rr8:
2022     case X86::MOVSX32rr8:
2023     case X86::MOVZX32rr8:
2024     case X86::MOVSX64rr8:
2025       SubIdx = X86::sub_8bit;
2026       break;
2027     case X86::MOVSX32rr16:
2028     case X86::MOVZX32rr16:
2029     case X86::MOVSX64rr16:
2030       SubIdx = X86::sub_16bit;
2031       break;
2032     case X86::MOVSX64rr32:
2033       SubIdx = X86::sub_32bit;
2034       break;
2035     }
2036     return true;
2037   }
2038   }
2039   return false;
2040 }
2041 
2042 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2043   const MachineFunction *MF = MI->getParent()->getParent();
2044   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2045 
2046   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2047       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2048     unsigned StackAlign = TFI->getStackAlignment();
2049     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2050                  StackAlign;
2051 
2052     SPAdj -= MI->getOperand(1).getImm();
2053 
2054     if (MI->getOpcode() == getCallFrameSetupOpcode())
2055       return SPAdj;
2056     else
2057       return -SPAdj;
2058   }
2059 
2060   // To know whether a call adjusts the stack, we need information
2061   // that is bound to the following ADJCALLSTACKUP pseudo.
2062   // Look for the next ADJCALLSTACKUP that follows the call.
2063   if (MI->isCall()) {
2064     const MachineBasicBlock* MBB = MI->getParent();
2065     auto I = ++MachineBasicBlock::const_iterator(MI);
2066     for (auto E = MBB->end(); I != E; ++I) {
2067       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2068           I->isCall())
2069         break;
2070     }
2071 
2072     // If we could not find a frame destroy opcode, then it has already
2073     // been simplified, so we don't care.
2074     if (I->getOpcode() != getCallFrameDestroyOpcode())
2075       return 0;
2076 
2077     return -(I->getOperand(1).getImm());
2078   }
2079 
2080   // Currently handle only PUSHes we can reasonably expect to see
2081   // in call sequences
2082   switch (MI->getOpcode()) {
2083   default:
2084     return 0;
2085   case X86::PUSH32i8:
2086   case X86::PUSH32r:
2087   case X86::PUSH32rmm:
2088   case X86::PUSH32rmr:
2089   case X86::PUSHi32:
2090     return 4;
2091   }
2092 }
2093 
2094 /// Return true and the FrameIndex if the specified
2095 /// operand and follow operands form a reference to the stack frame.
2096 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2097                                   int &FrameIndex) const {
2098   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2099       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2100       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2101       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2102       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2103       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2104       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2105     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2106     return true;
2107   }
2108   return false;
2109 }
2110 
2111 static bool isFrameLoadOpcode(int Opcode) {
2112   switch (Opcode) {
2113   default:
2114     return false;
2115   case X86::MOV8rm:
2116   case X86::MOV16rm:
2117   case X86::MOV32rm:
2118   case X86::MOV64rm:
2119   case X86::LD_Fp64m:
2120   case X86::MOVSSrm:
2121   case X86::MOVSDrm:
2122   case X86::MOVAPSrm:
2123   case X86::MOVAPDrm:
2124   case X86::MOVDQArm:
2125   case X86::VMOVSSrm:
2126   case X86::VMOVSDrm:
2127   case X86::VMOVAPSrm:
2128   case X86::VMOVAPDrm:
2129   case X86::VMOVDQArm:
2130   case X86::VMOVUPSYrm:
2131   case X86::VMOVAPSYrm:
2132   case X86::VMOVUPDYrm:
2133   case X86::VMOVAPDYrm:
2134   case X86::VMOVDQUYrm:
2135   case X86::VMOVDQAYrm:
2136   case X86::MMX_MOVD64rm:
2137   case X86::MMX_MOVQ64rm:
2138   case X86::VMOVAPSZrm:
2139   case X86::VMOVUPSZrm:
2140     return true;
2141   }
2142 }
2143 
2144 static bool isFrameStoreOpcode(int Opcode) {
2145   switch (Opcode) {
2146   default: break;
2147   case X86::MOV8mr:
2148   case X86::MOV16mr:
2149   case X86::MOV32mr:
2150   case X86::MOV64mr:
2151   case X86::ST_FpP64m:
2152   case X86::MOVSSmr:
2153   case X86::MOVSDmr:
2154   case X86::MOVAPSmr:
2155   case X86::MOVAPDmr:
2156   case X86::MOVDQAmr:
2157   case X86::VMOVSSmr:
2158   case X86::VMOVSDmr:
2159   case X86::VMOVAPSmr:
2160   case X86::VMOVAPDmr:
2161   case X86::VMOVDQAmr:
2162   case X86::VMOVUPSYmr:
2163   case X86::VMOVAPSYmr:
2164   case X86::VMOVUPDYmr:
2165   case X86::VMOVAPDYmr:
2166   case X86::VMOVDQUYmr:
2167   case X86::VMOVDQAYmr:
2168   case X86::VMOVUPSZmr:
2169   case X86::VMOVAPSZmr:
2170   case X86::MMX_MOVD64mr:
2171   case X86::MMX_MOVQ64mr:
2172   case X86::MMX_MOVNTQmr:
2173     return true;
2174   }
2175   return false;
2176 }
2177 
2178 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2179                                            int &FrameIndex) const {
2180   if (isFrameLoadOpcode(MI->getOpcode()))
2181     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2182       return MI->getOperand(0).getReg();
2183   return 0;
2184 }
2185 
2186 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2187                                                  int &FrameIndex) const {
2188   if (isFrameLoadOpcode(MI->getOpcode())) {
2189     unsigned Reg;
2190     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2191       return Reg;
2192     // Check for post-frame index elimination operations
2193     const MachineMemOperand *Dummy;
2194     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2195   }
2196   return 0;
2197 }
2198 
2199 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2200                                           int &FrameIndex) const {
2201   if (isFrameStoreOpcode(MI->getOpcode()))
2202     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2203         isFrameOperand(MI, 0, FrameIndex))
2204       return MI->getOperand(X86::AddrNumOperands).getReg();
2205   return 0;
2206 }
2207 
2208 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2209                                                 int &FrameIndex) const {
2210   if (isFrameStoreOpcode(MI->getOpcode())) {
2211     unsigned Reg;
2212     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2213       return Reg;
2214     // Check for post-frame index elimination operations
2215     const MachineMemOperand *Dummy;
2216     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2217   }
2218   return 0;
2219 }
2220 
2221 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2222 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2223   // Don't waste compile time scanning use-def chains of physregs.
2224   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2225     return false;
2226   bool isPICBase = false;
2227   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2228          E = MRI.def_instr_end(); I != E; ++I) {
2229     MachineInstr *DefMI = &*I;
2230     if (DefMI->getOpcode() != X86::MOVPC32r)
2231       return false;
2232     assert(!isPICBase && "More than one PIC base?");
2233     isPICBase = true;
2234   }
2235   return isPICBase;
2236 }
2237 
2238 bool
2239 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2240                                                 AliasAnalysis *AA) const {
2241   switch (MI->getOpcode()) {
2242   default: break;
2243   case X86::MOV8rm:
2244   case X86::MOV16rm:
2245   case X86::MOV32rm:
2246   case X86::MOV64rm:
2247   case X86::LD_Fp64m:
2248   case X86::MOVSSrm:
2249   case X86::MOVSDrm:
2250   case X86::MOVAPSrm:
2251   case X86::MOVUPSrm:
2252   case X86::MOVAPDrm:
2253   case X86::MOVDQArm:
2254   case X86::MOVDQUrm:
2255   case X86::VMOVSSrm:
2256   case X86::VMOVSDrm:
2257   case X86::VMOVAPSrm:
2258   case X86::VMOVUPSrm:
2259   case X86::VMOVAPDrm:
2260   case X86::VMOVDQArm:
2261   case X86::VMOVDQUrm:
2262   case X86::VMOVAPSYrm:
2263   case X86::VMOVUPSYrm:
2264   case X86::VMOVAPDYrm:
2265   case X86::VMOVDQAYrm:
2266   case X86::VMOVDQUYrm:
2267   case X86::MMX_MOVD64rm:
2268   case X86::MMX_MOVQ64rm:
2269   case X86::FsVMOVAPSrm:
2270   case X86::FsVMOVAPDrm:
2271   case X86::FsMOVAPSrm:
2272   case X86::FsMOVAPDrm: {
2273     // Loads from constant pools are trivially rematerializable.
2274     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2275         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2276         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2277         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2278         MI->isInvariantLoad(AA)) {
2279       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2280       if (BaseReg == 0 || BaseReg == X86::RIP)
2281         return true;
2282       // Allow re-materialization of PIC load.
2283       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2284         return false;
2285       const MachineFunction &MF = *MI->getParent()->getParent();
2286       const MachineRegisterInfo &MRI = MF.getRegInfo();
2287       return regIsPICBase(BaseReg, MRI);
2288     }
2289     return false;
2290   }
2291 
2292   case X86::LEA32r:
2293   case X86::LEA64r: {
2294     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2295         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2296         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2297         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2298       // lea fi#, lea GV, etc. are all rematerializable.
2299       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2300         return true;
2301       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2302       if (BaseReg == 0)
2303         return true;
2304       // Allow re-materialization of lea PICBase + x.
2305       const MachineFunction &MF = *MI->getParent()->getParent();
2306       const MachineRegisterInfo &MRI = MF.getRegInfo();
2307       return regIsPICBase(BaseReg, MRI);
2308     }
2309     return false;
2310   }
2311   }
2312 
2313   // All other instructions marked M_REMATERIALIZABLE are always trivially
2314   // rematerializable.
2315   return true;
2316 }
2317 
2318 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2319                                          MachineBasicBlock::iterator I) const {
2320   MachineBasicBlock::iterator E = MBB.end();
2321 
2322   // For compile time consideration, if we are not able to determine the
2323   // safety after visiting 4 instructions in each direction, we will assume
2324   // it's not safe.
2325   MachineBasicBlock::iterator Iter = I;
2326   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2327     bool SeenDef = false;
2328     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2329       MachineOperand &MO = Iter->getOperand(j);
2330       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2331         SeenDef = true;
2332       if (!MO.isReg())
2333         continue;
2334       if (MO.getReg() == X86::EFLAGS) {
2335         if (MO.isUse())
2336           return false;
2337         SeenDef = true;
2338       }
2339     }
2340 
2341     if (SeenDef)
2342       // This instruction defines EFLAGS, no need to look any further.
2343       return true;
2344     ++Iter;
2345     // Skip over DBG_VALUE.
2346     while (Iter != E && Iter->isDebugValue())
2347       ++Iter;
2348   }
2349 
2350   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2351   // live in.
2352   if (Iter == E) {
2353     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2354            SE = MBB.succ_end(); SI != SE; ++SI)
2355       if ((*SI)->isLiveIn(X86::EFLAGS))
2356         return false;
2357     return true;
2358   }
2359 
2360   MachineBasicBlock::iterator B = MBB.begin();
2361   Iter = I;
2362   for (unsigned i = 0; i < 4; ++i) {
2363     // If we make it to the beginning of the block, it's safe to clobber
2364     // EFLAGS iff EFLAGS is not live-in.
2365     if (Iter == B)
2366       return !MBB.isLiveIn(X86::EFLAGS);
2367 
2368     --Iter;
2369     // Skip over DBG_VALUE.
2370     while (Iter != B && Iter->isDebugValue())
2371       --Iter;
2372 
2373     bool SawKill = false;
2374     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2375       MachineOperand &MO = Iter->getOperand(j);
2376       // A register mask may clobber EFLAGS, but we should still look for a
2377       // live EFLAGS def.
2378       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2379         SawKill = true;
2380       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2381         if (MO.isDef()) return MO.isDead();
2382         if (MO.isKill()) SawKill = true;
2383       }
2384     }
2385 
2386     if (SawKill)
2387       // This instruction kills EFLAGS and doesn't redefine it, so
2388       // there's no need to look further.
2389       return true;
2390   }
2391 
2392   // Conservative answer.
2393   return false;
2394 }
2395 
2396 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2397                                  MachineBasicBlock::iterator I,
2398                                  unsigned DestReg, unsigned SubIdx,
2399                                  const MachineInstr *Orig,
2400                                  const TargetRegisterInfo &TRI) const {
2401   // MOV32r0 is implemented with a xor which clobbers condition code.
2402   // Re-materialize it as movri instructions to avoid side effects.
2403   unsigned Opc = Orig->getOpcode();
2404   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2405     DebugLoc DL = Orig->getDebugLoc();
2406     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2407       .addImm(0);
2408   } else {
2409     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2410     MBB.insert(I, MI);
2411   }
2412 
2413   MachineInstr *NewMI = std::prev(I);
2414   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2415 }
2416 
2417 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2418 static bool hasLiveCondCodeDef(MachineInstr *MI) {
2419   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2420     MachineOperand &MO = MI->getOperand(i);
2421     if (MO.isReg() && MO.isDef() &&
2422         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2423       return true;
2424     }
2425   }
2426   return false;
2427 }
2428 
2429 /// Check whether the shift count for a machine operand is non-zero.
2430 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2431                                               unsigned ShiftAmtOperandIdx) {
2432   // The shift count is six bits with the REX.W prefix and five bits without.
2433   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2434   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2435   return Imm & ShiftCountMask;
2436 }
2437 
2438 /// Check whether the given shift count is appropriate
2439 /// can be represented by a LEA instruction.
2440 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2441   // Left shift instructions can be transformed into load-effective-address
2442   // instructions if we can encode them appropriately.
2443   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2444   // The SIB.scale field is two bits wide which means that we can encode any
2445   // shift amount less than 4.
2446   return ShAmt < 4 && ShAmt > 0;
2447 }
2448 
2449 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2450                                   unsigned Opc, bool AllowSP,
2451                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2452                                   MachineOperand &ImplicitOp) const {
2453   MachineFunction &MF = *MI->getParent()->getParent();
2454   const TargetRegisterClass *RC;
2455   if (AllowSP) {
2456     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2457   } else {
2458     RC = Opc != X86::LEA32r ?
2459       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2460   }
2461   unsigned SrcReg = Src.getReg();
2462 
2463   // For both LEA64 and LEA32 the register already has essentially the right
2464   // type (32-bit or 64-bit) we may just need to forbid SP.
2465   if (Opc != X86::LEA64_32r) {
2466     NewSrc = SrcReg;
2467     isKill = Src.isKill();
2468     isUndef = Src.isUndef();
2469 
2470     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2471         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2472       return false;
2473 
2474     return true;
2475   }
2476 
2477   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2478   // another we need to add 64-bit registers to the final MI.
2479   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2480     ImplicitOp = Src;
2481     ImplicitOp.setImplicit();
2482 
2483     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2484     MachineBasicBlock::LivenessQueryResult LQR =
2485       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2486 
2487     switch (LQR) {
2488     case MachineBasicBlock::LQR_Unknown:
2489       // We can't give sane liveness flags to the instruction, abandon LEA
2490       // formation.
2491       return false;
2492     case MachineBasicBlock::LQR_Live:
2493       isKill = MI->killsRegister(SrcReg);
2494       isUndef = false;
2495       break;
2496     default:
2497       // The physreg itself is dead, so we have to use it as an <undef>.
2498       isKill = false;
2499       isUndef = true;
2500       break;
2501     }
2502   } else {
2503     // Virtual register of the wrong class, we have to create a temporary 64-bit
2504     // vreg to feed into the LEA.
2505     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2506     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2507             get(TargetOpcode::COPY))
2508       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2509         .addOperand(Src);
2510 
2511     // Which is obviously going to be dead after we're done with it.
2512     isKill = true;
2513     isUndef = false;
2514   }
2515 
2516   // We've set all the parameters without issue.
2517   return true;
2518 }
2519 
2520 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2521 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2522 /// truncating back down to a 16-bit subregister.
2523 MachineInstr *
2524 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2525                                            MachineFunction::iterator &MFI,
2526                                            MachineBasicBlock::iterator &MBBI,
2527                                            LiveVariables *LV) const {
2528   MachineInstr *MI = MBBI;
2529   unsigned Dest = MI->getOperand(0).getReg();
2530   unsigned Src = MI->getOperand(1).getReg();
2531   bool isDead = MI->getOperand(0).isDead();
2532   bool isKill = MI->getOperand(1).isKill();
2533 
2534   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2535   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2536   unsigned Opc, leaInReg;
2537   if (Subtarget.is64Bit()) {
2538     Opc = X86::LEA64_32r;
2539     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2540   } else {
2541     Opc = X86::LEA32r;
2542     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2543   }
2544 
2545   // Build and insert into an implicit UNDEF value. This is OK because
2546   // well be shifting and then extracting the lower 16-bits.
2547   // This has the potential to cause partial register stall. e.g.
2548   //   movw    (%rbp,%rcx,2), %dx
2549   //   leal    -65(%rdx), %esi
2550   // But testing has shown this *does* help performance in 64-bit mode (at
2551   // least on modern x86 machines).
2552   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2553   MachineInstr *InsMI =
2554     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2555     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2556     .addReg(Src, getKillRegState(isKill));
2557 
2558   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2559                                     get(Opc), leaOutReg);
2560   switch (MIOpc) {
2561   default: llvm_unreachable("Unreachable!");
2562   case X86::SHL16ri: {
2563     unsigned ShAmt = MI->getOperand(2).getImm();
2564     MIB.addReg(0).addImm(1 << ShAmt)
2565        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2566     break;
2567   }
2568   case X86::INC16r:
2569     addRegOffset(MIB, leaInReg, true, 1);
2570     break;
2571   case X86::DEC16r:
2572     addRegOffset(MIB, leaInReg, true, -1);
2573     break;
2574   case X86::ADD16ri:
2575   case X86::ADD16ri8:
2576   case X86::ADD16ri_DB:
2577   case X86::ADD16ri8_DB:
2578     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2579     break;
2580   case X86::ADD16rr:
2581   case X86::ADD16rr_DB: {
2582     unsigned Src2 = MI->getOperand(2).getReg();
2583     bool isKill2 = MI->getOperand(2).isKill();
2584     unsigned leaInReg2 = 0;
2585     MachineInstr *InsMI2 = nullptr;
2586     if (Src == Src2) {
2587       // ADD16rr %reg1028<kill>, %reg1028
2588       // just a single insert_subreg.
2589       addRegReg(MIB, leaInReg, true, leaInReg, false);
2590     } else {
2591       if (Subtarget.is64Bit())
2592         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2593       else
2594         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2595       // Build and insert into an implicit UNDEF value. This is OK because
2596       // well be shifting and then extracting the lower 16-bits.
2597       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2598       InsMI2 =
2599         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2600         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2601         .addReg(Src2, getKillRegState(isKill2));
2602       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2603     }
2604     if (LV && isKill2 && InsMI2)
2605       LV->replaceKillInstruction(Src2, MI, InsMI2);
2606     break;
2607   }
2608   }
2609 
2610   MachineInstr *NewMI = MIB;
2611   MachineInstr *ExtMI =
2612     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2613     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2614     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2615 
2616   if (LV) {
2617     // Update live variables
2618     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2619     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2620     if (isKill)
2621       LV->replaceKillInstruction(Src, MI, InsMI);
2622     if (isDead)
2623       LV->replaceKillInstruction(Dest, MI, ExtMI);
2624   }
2625 
2626   return ExtMI;
2627 }
2628 
2629 /// This method must be implemented by targets that
2630 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2631 /// may be able to convert a two-address instruction into a true
2632 /// three-address instruction on demand.  This allows the X86 target (for
2633 /// example) to convert ADD and SHL instructions into LEA instructions if they
2634 /// would require register copies due to two-addressness.
2635 ///
2636 /// This method returns a null pointer if the transformation cannot be
2637 /// performed, otherwise it returns the new instruction.
2638 ///
2639 MachineInstr *
2640 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2641                                     MachineBasicBlock::iterator &MBBI,
2642                                     LiveVariables *LV) const {
2643   MachineInstr *MI = MBBI;
2644 
2645   // The following opcodes also sets the condition code register(s). Only
2646   // convert them to equivalent lea if the condition code register def's
2647   // are dead!
2648   if (hasLiveCondCodeDef(MI))
2649     return nullptr;
2650 
2651   MachineFunction &MF = *MI->getParent()->getParent();
2652   // All instructions input are two-addr instructions.  Get the known operands.
2653   const MachineOperand &Dest = MI->getOperand(0);
2654   const MachineOperand &Src = MI->getOperand(1);
2655 
2656   MachineInstr *NewMI = nullptr;
2657   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2658   // we have better subtarget support, enable the 16-bit LEA generation here.
2659   // 16-bit LEA is also slow on Core2.
2660   bool DisableLEA16 = true;
2661   bool is64Bit = Subtarget.is64Bit();
2662 
2663   unsigned MIOpc = MI->getOpcode();
2664   switch (MIOpc) {
2665   default: return nullptr;
2666   case X86::SHL64ri: {
2667     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2668     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2669     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2670 
2671     // LEA can't handle RSP.
2672     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2673         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2674                                            &X86::GR64_NOSPRegClass))
2675       return nullptr;
2676 
2677     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2678       .addOperand(Dest)
2679       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2680     break;
2681   }
2682   case X86::SHL32ri: {
2683     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2684     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2685     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2686 
2687     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2688 
2689     // LEA can't handle ESP.
2690     bool isKill, isUndef;
2691     unsigned SrcReg;
2692     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2693     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2694                         SrcReg, isKill, isUndef, ImplicitOp))
2695       return nullptr;
2696 
2697     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2698       .addOperand(Dest)
2699       .addReg(0).addImm(1 << ShAmt)
2700       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2701       .addImm(0).addReg(0);
2702     if (ImplicitOp.getReg() != 0)
2703       MIB.addOperand(ImplicitOp);
2704     NewMI = MIB;
2705 
2706     break;
2707   }
2708   case X86::SHL16ri: {
2709     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2710     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2711     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2712 
2713     if (DisableLEA16)
2714       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2715     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2716       .addOperand(Dest)
2717       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2718     break;
2719   }
2720   case X86::INC64r:
2721   case X86::INC32r: {
2722     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2723     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2724       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2725     bool isKill, isUndef;
2726     unsigned SrcReg;
2727     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2728     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2729                         SrcReg, isKill, isUndef, ImplicitOp))
2730       return nullptr;
2731 
2732     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2733         .addOperand(Dest)
2734         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2735     if (ImplicitOp.getReg() != 0)
2736       MIB.addOperand(ImplicitOp);
2737 
2738     NewMI = addOffset(MIB, 1);
2739     break;
2740   }
2741   case X86::INC16r:
2742     if (DisableLEA16)
2743       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2744                      : nullptr;
2745     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2746     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2747                       .addOperand(Dest).addOperand(Src), 1);
2748     break;
2749   case X86::DEC64r:
2750   case X86::DEC32r: {
2751     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2752     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2753       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2754 
2755     bool isKill, isUndef;
2756     unsigned SrcReg;
2757     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2758     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2759                         SrcReg, isKill, isUndef, ImplicitOp))
2760       return nullptr;
2761 
2762     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2763         .addOperand(Dest)
2764         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2765     if (ImplicitOp.getReg() != 0)
2766       MIB.addOperand(ImplicitOp);
2767 
2768     NewMI = addOffset(MIB, -1);
2769 
2770     break;
2771   }
2772   case X86::DEC16r:
2773     if (DisableLEA16)
2774       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2775                      : nullptr;
2776     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2777     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2778                       .addOperand(Dest).addOperand(Src), -1);
2779     break;
2780   case X86::ADD64rr:
2781   case X86::ADD64rr_DB:
2782   case X86::ADD32rr:
2783   case X86::ADD32rr_DB: {
2784     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2785     unsigned Opc;
2786     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2787       Opc = X86::LEA64r;
2788     else
2789       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2790 
2791     bool isKill, isUndef;
2792     unsigned SrcReg;
2793     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2794     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2795                         SrcReg, isKill, isUndef, ImplicitOp))
2796       return nullptr;
2797 
2798     const MachineOperand &Src2 = MI->getOperand(2);
2799     bool isKill2, isUndef2;
2800     unsigned SrcReg2;
2801     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2802     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2803                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2804       return nullptr;
2805 
2806     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2807       .addOperand(Dest);
2808     if (ImplicitOp.getReg() != 0)
2809       MIB.addOperand(ImplicitOp);
2810     if (ImplicitOp2.getReg() != 0)
2811       MIB.addOperand(ImplicitOp2);
2812 
2813     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2814 
2815     // Preserve undefness of the operands.
2816     NewMI->getOperand(1).setIsUndef(isUndef);
2817     NewMI->getOperand(3).setIsUndef(isUndef2);
2818 
2819     if (LV && Src2.isKill())
2820       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2821     break;
2822   }
2823   case X86::ADD16rr:
2824   case X86::ADD16rr_DB: {
2825     if (DisableLEA16)
2826       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2827                      : nullptr;
2828     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2829     unsigned Src2 = MI->getOperand(2).getReg();
2830     bool isKill2 = MI->getOperand(2).isKill();
2831     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2832                       .addOperand(Dest),
2833                       Src.getReg(), Src.isKill(), Src2, isKill2);
2834 
2835     // Preserve undefness of the operands.
2836     bool isUndef = MI->getOperand(1).isUndef();
2837     bool isUndef2 = MI->getOperand(2).isUndef();
2838     NewMI->getOperand(1).setIsUndef(isUndef);
2839     NewMI->getOperand(3).setIsUndef(isUndef2);
2840 
2841     if (LV && isKill2)
2842       LV->replaceKillInstruction(Src2, MI, NewMI);
2843     break;
2844   }
2845   case X86::ADD64ri32:
2846   case X86::ADD64ri8:
2847   case X86::ADD64ri32_DB:
2848   case X86::ADD64ri8_DB:
2849     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2850     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2851                       .addOperand(Dest).addOperand(Src),
2852                       MI->getOperand(2).getImm());
2853     break;
2854   case X86::ADD32ri:
2855   case X86::ADD32ri8:
2856   case X86::ADD32ri_DB:
2857   case X86::ADD32ri8_DB: {
2858     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2859     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2860 
2861     bool isKill, isUndef;
2862     unsigned SrcReg;
2863     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2864     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2865                         SrcReg, isKill, isUndef, ImplicitOp))
2866       return nullptr;
2867 
2868     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2869         .addOperand(Dest)
2870         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2871     if (ImplicitOp.getReg() != 0)
2872       MIB.addOperand(ImplicitOp);
2873 
2874     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2875     break;
2876   }
2877   case X86::ADD16ri:
2878   case X86::ADD16ri8:
2879   case X86::ADD16ri_DB:
2880   case X86::ADD16ri8_DB:
2881     if (DisableLEA16)
2882       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2883                      : nullptr;
2884     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2885     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2886                       .addOperand(Dest).addOperand(Src),
2887                       MI->getOperand(2).getImm());
2888     break;
2889   }
2890 
2891   if (!NewMI) return nullptr;
2892 
2893   if (LV) {  // Update live variables
2894     if (Src.isKill())
2895       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2896     if (Dest.isDead())
2897       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2898   }
2899 
2900   MFI->insert(MBBI, NewMI);          // Insert the new inst
2901   return NewMI;
2902 }
2903 
2904 /// We have a few instructions that must be hacked on to commute them.
2905 ///
2906 MachineInstr *
2907 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2908   switch (MI->getOpcode()) {
2909   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2910   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2911   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2912   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2913   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2914   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2915     unsigned Opc;
2916     unsigned Size;
2917     switch (MI->getOpcode()) {
2918     default: llvm_unreachable("Unreachable!");
2919     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2920     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2921     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2922     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2923     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2924     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2925     }
2926     unsigned Amt = MI->getOperand(3).getImm();
2927     if (NewMI) {
2928       MachineFunction &MF = *MI->getParent()->getParent();
2929       MI = MF.CloneMachineInstr(MI);
2930       NewMI = false;
2931     }
2932     MI->setDesc(get(Opc));
2933     MI->getOperand(3).setImm(Size-Amt);
2934     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2935   }
2936   case X86::BLENDPDrri:
2937   case X86::BLENDPSrri:
2938   case X86::PBLENDWrri:
2939   case X86::VBLENDPDrri:
2940   case X86::VBLENDPSrri:
2941   case X86::VBLENDPDYrri:
2942   case X86::VBLENDPSYrri:
2943   case X86::VPBLENDDrri:
2944   case X86::VPBLENDWrri:
2945   case X86::VPBLENDDYrri:
2946   case X86::VPBLENDWYrri:{
2947     unsigned Mask;
2948     switch (MI->getOpcode()) {
2949     default: llvm_unreachable("Unreachable!");
2950     case X86::BLENDPDrri:    Mask = 0x03; break;
2951     case X86::BLENDPSrri:    Mask = 0x0F; break;
2952     case X86::PBLENDWrri:    Mask = 0xFF; break;
2953     case X86::VBLENDPDrri:   Mask = 0x03; break;
2954     case X86::VBLENDPSrri:   Mask = 0x0F; break;
2955     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
2956     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
2957     case X86::VPBLENDDrri:   Mask = 0x0F; break;
2958     case X86::VPBLENDWrri:   Mask = 0xFF; break;
2959     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
2960     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
2961     }
2962     // Only the least significant bits of Imm are used.
2963     unsigned Imm = MI->getOperand(3).getImm() & Mask;
2964     if (NewMI) {
2965       MachineFunction &MF = *MI->getParent()->getParent();
2966       MI = MF.CloneMachineInstr(MI);
2967       NewMI = false;
2968     }
2969     MI->getOperand(3).setImm(Mask ^ Imm);
2970     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2971   }
2972   case X86::PCLMULQDQrr:
2973   case X86::VPCLMULQDQrr:{
2974     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2975     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2976     unsigned Imm = MI->getOperand(3).getImm();
2977     unsigned Src1Hi = Imm & 0x01;
2978     unsigned Src2Hi = Imm & 0x10;
2979     if (NewMI) {
2980       MachineFunction &MF = *MI->getParent()->getParent();
2981       MI = MF.CloneMachineInstr(MI);
2982       NewMI = false;
2983     }
2984     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2985     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2986   }
2987   case X86::CMPPDrri:
2988   case X86::CMPPSrri:
2989   case X86::VCMPPDrri:
2990   case X86::VCMPPSrri:
2991   case X86::VCMPPDYrri:
2992   case X86::VCMPPSYrri: {
2993     // Float comparison can be safely commuted for
2994     // Ordered/Unordered/Equal/NotEqual tests
2995     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2996     switch (Imm) {
2997     case 0x00: // EQUAL
2998     case 0x03: // UNORDERED
2999     case 0x04: // NOT EQUAL
3000     case 0x07: // ORDERED
3001       if (NewMI) {
3002         MachineFunction &MF = *MI->getParent()->getParent();
3003         MI = MF.CloneMachineInstr(MI);
3004         NewMI = false;
3005       }
3006       return TargetInstrInfo::commuteInstruction(MI, NewMI);
3007     default:
3008       return nullptr;
3009     }
3010   }
3011   case X86::VPCOMBri: case X86::VPCOMUBri:
3012   case X86::VPCOMDri: case X86::VPCOMUDri:
3013   case X86::VPCOMQri: case X86::VPCOMUQri:
3014   case X86::VPCOMWri: case X86::VPCOMUWri: {
3015     // Flip comparison mode immediate (if necessary).
3016     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3017     switch (Imm) {
3018     case 0x00: Imm = 0x02; break; // LT -> GT
3019     case 0x01: Imm = 0x03; break; // LE -> GE
3020     case 0x02: Imm = 0x00; break; // GT -> LT
3021     case 0x03: Imm = 0x01; break; // GE -> LE
3022     case 0x04: // EQ
3023     case 0x05: // NE
3024     case 0x06: // FALSE
3025     case 0x07: // TRUE
3026     default:
3027       break;
3028     }
3029     if (NewMI) {
3030       MachineFunction &MF = *MI->getParent()->getParent();
3031       MI = MF.CloneMachineInstr(MI);
3032       NewMI = false;
3033     }
3034     MI->getOperand(3).setImm(Imm);
3035     return TargetInstrInfo::commuteInstruction(MI, NewMI);
3036   }
3037   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3038   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3039   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3040   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3041   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3042   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3043   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3044   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3045   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3046   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3047   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3048   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3049   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3050   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3051   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3052   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3053     unsigned Opc;
3054     switch (MI->getOpcode()) {
3055     default: llvm_unreachable("Unreachable!");
3056     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3057     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3058     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3059     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3060     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3061     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3062     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3063     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3064     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3065     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3066     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3067     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3068     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3069     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3070     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3071     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3072     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3073     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3074     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3075     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3076     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3077     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3078     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3079     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3080     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3081     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3082     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3083     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3084     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3085     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3086     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3087     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3088     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3089     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3090     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3091     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3092     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3093     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3094     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3095     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3096     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3097     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3098     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3099     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3100     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3101     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3102     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3103     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3104     }
3105     if (NewMI) {
3106       MachineFunction &MF = *MI->getParent()->getParent();
3107       MI = MF.CloneMachineInstr(MI);
3108       NewMI = false;
3109     }
3110     MI->setDesc(get(Opc));
3111     // Fallthrough intended.
3112   }
3113   default:
3114     return TargetInstrInfo::commuteInstruction(MI, NewMI);
3115   }
3116 }
3117 
3118 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
3119                                          unsigned &SrcOpIdx2) const {
3120   switch (MI->getOpcode()) {
3121     case X86::CMPPDrri:
3122     case X86::CMPPSrri:
3123     case X86::VCMPPDrri:
3124     case X86::VCMPPSrri:
3125     case X86::VCMPPDYrri:
3126     case X86::VCMPPSYrri: {
3127       // Float comparison can be safely commuted for
3128       // Ordered/Unordered/Equal/NotEqual tests
3129       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3130       switch (Imm) {
3131       case 0x00: // EQUAL
3132       case 0x03: // UNORDERED
3133       case 0x04: // NOT EQUAL
3134       case 0x07: // ORDERED
3135         SrcOpIdx1 = 1;
3136         SrcOpIdx2 = 2;
3137         return true;
3138       }
3139       return false;
3140     }
3141     case X86::VFMADDPDr231r:
3142     case X86::VFMADDPSr231r:
3143     case X86::VFMADDSDr231r:
3144     case X86::VFMADDSSr231r:
3145     case X86::VFMSUBPDr231r:
3146     case X86::VFMSUBPSr231r:
3147     case X86::VFMSUBSDr231r:
3148     case X86::VFMSUBSSr231r:
3149     case X86::VFNMADDPDr231r:
3150     case X86::VFNMADDPSr231r:
3151     case X86::VFNMADDSDr231r:
3152     case X86::VFNMADDSSr231r:
3153     case X86::VFNMSUBPDr231r:
3154     case X86::VFNMSUBPSr231r:
3155     case X86::VFNMSUBSDr231r:
3156     case X86::VFNMSUBSSr231r:
3157     case X86::VFMADDPDr231rY:
3158     case X86::VFMADDPSr231rY:
3159     case X86::VFMSUBPDr231rY:
3160     case X86::VFMSUBPSr231rY:
3161     case X86::VFNMADDPDr231rY:
3162     case X86::VFNMADDPSr231rY:
3163     case X86::VFNMSUBPDr231rY:
3164     case X86::VFNMSUBPSr231rY:
3165       SrcOpIdx1 = 2;
3166       SrcOpIdx2 = 3;
3167       return true;
3168     default:
3169       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3170   }
3171 }
3172 
3173 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3174   switch (BrOpc) {
3175   default: return X86::COND_INVALID;
3176   case X86::JE_1:  return X86::COND_E;
3177   case X86::JNE_1: return X86::COND_NE;
3178   case X86::JL_1:  return X86::COND_L;
3179   case X86::JLE_1: return X86::COND_LE;
3180   case X86::JG_1:  return X86::COND_G;
3181   case X86::JGE_1: return X86::COND_GE;
3182   case X86::JB_1:  return X86::COND_B;
3183   case X86::JBE_1: return X86::COND_BE;
3184   case X86::JA_1:  return X86::COND_A;
3185   case X86::JAE_1: return X86::COND_AE;
3186   case X86::JS_1:  return X86::COND_S;
3187   case X86::JNS_1: return X86::COND_NS;
3188   case X86::JP_1:  return X86::COND_P;
3189   case X86::JNP_1: return X86::COND_NP;
3190   case X86::JO_1:  return X86::COND_O;
3191   case X86::JNO_1: return X86::COND_NO;
3192   }
3193 }
3194 
3195 /// Return condition code of a SET opcode.
3196 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3197   switch (Opc) {
3198   default: return X86::COND_INVALID;
3199   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3200   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3201   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3202   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3203   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3204   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3205   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3206   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3207   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3208   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3209   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3210   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3211   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3212   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3213   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3214   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3215   }
3216 }
3217 
3218 /// Return condition code of a CMov opcode.
3219 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3220   switch (Opc) {
3221   default: return X86::COND_INVALID;
3222   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3223   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3224     return X86::COND_A;
3225   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3226   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3227     return X86::COND_AE;
3228   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3229   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3230     return X86::COND_B;
3231   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3232   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3233     return X86::COND_BE;
3234   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3235   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3236     return X86::COND_E;
3237   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3238   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3239     return X86::COND_G;
3240   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3241   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3242     return X86::COND_GE;
3243   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3244   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3245     return X86::COND_L;
3246   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3247   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3248     return X86::COND_LE;
3249   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3250   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3251     return X86::COND_NE;
3252   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3253   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3254     return X86::COND_NO;
3255   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3256   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3257     return X86::COND_NP;
3258   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3259   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3260     return X86::COND_NS;
3261   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3262   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3263     return X86::COND_O;
3264   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3265   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3266     return X86::COND_P;
3267   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3268   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3269     return X86::COND_S;
3270   }
3271 }
3272 
3273 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3274   switch (CC) {
3275   default: llvm_unreachable("Illegal condition code!");
3276   case X86::COND_E:  return X86::JE_1;
3277   case X86::COND_NE: return X86::JNE_1;
3278   case X86::COND_L:  return X86::JL_1;
3279   case X86::COND_LE: return X86::JLE_1;
3280   case X86::COND_G:  return X86::JG_1;
3281   case X86::COND_GE: return X86::JGE_1;
3282   case X86::COND_B:  return X86::JB_1;
3283   case X86::COND_BE: return X86::JBE_1;
3284   case X86::COND_A:  return X86::JA_1;
3285   case X86::COND_AE: return X86::JAE_1;
3286   case X86::COND_S:  return X86::JS_1;
3287   case X86::COND_NS: return X86::JNS_1;
3288   case X86::COND_P:  return X86::JP_1;
3289   case X86::COND_NP: return X86::JNP_1;
3290   case X86::COND_O:  return X86::JO_1;
3291   case X86::COND_NO: return X86::JNO_1;
3292   }
3293 }
3294 
3295 /// Return the inverse of the specified condition,
3296 /// e.g. turning COND_E to COND_NE.
3297 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3298   switch (CC) {
3299   default: llvm_unreachable("Illegal condition code!");
3300   case X86::COND_E:  return X86::COND_NE;
3301   case X86::COND_NE: return X86::COND_E;
3302   case X86::COND_L:  return X86::COND_GE;
3303   case X86::COND_LE: return X86::COND_G;
3304   case X86::COND_G:  return X86::COND_LE;
3305   case X86::COND_GE: return X86::COND_L;
3306   case X86::COND_B:  return X86::COND_AE;
3307   case X86::COND_BE: return X86::COND_A;
3308   case X86::COND_A:  return X86::COND_BE;
3309   case X86::COND_AE: return X86::COND_B;
3310   case X86::COND_S:  return X86::COND_NS;
3311   case X86::COND_NS: return X86::COND_S;
3312   case X86::COND_P:  return X86::COND_NP;
3313   case X86::COND_NP: return X86::COND_P;
3314   case X86::COND_O:  return X86::COND_NO;
3315   case X86::COND_NO: return X86::COND_O;
3316   }
3317 }
3318 
3319 /// Assuming the flags are set by MI(a,b), return the condition code if we
3320 /// modify the instructions such that flags are set by MI(b,a).
3321 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3322   switch (CC) {
3323   default: return X86::COND_INVALID;
3324   case X86::COND_E:  return X86::COND_E;
3325   case X86::COND_NE: return X86::COND_NE;
3326   case X86::COND_L:  return X86::COND_G;
3327   case X86::COND_LE: return X86::COND_GE;
3328   case X86::COND_G:  return X86::COND_L;
3329   case X86::COND_GE: return X86::COND_LE;
3330   case X86::COND_B:  return X86::COND_A;
3331   case X86::COND_BE: return X86::COND_AE;
3332   case X86::COND_A:  return X86::COND_B;
3333   case X86::COND_AE: return X86::COND_BE;
3334   }
3335 }
3336 
3337 /// Return a set opcode for the given condition and
3338 /// whether it has memory operand.
3339 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3340   static const uint16_t Opc[16][2] = {
3341     { X86::SETAr,  X86::SETAm  },
3342     { X86::SETAEr, X86::SETAEm },
3343     { X86::SETBr,  X86::SETBm  },
3344     { X86::SETBEr, X86::SETBEm },
3345     { X86::SETEr,  X86::SETEm  },
3346     { X86::SETGr,  X86::SETGm  },
3347     { X86::SETGEr, X86::SETGEm },
3348     { X86::SETLr,  X86::SETLm  },
3349     { X86::SETLEr, X86::SETLEm },
3350     { X86::SETNEr, X86::SETNEm },
3351     { X86::SETNOr, X86::SETNOm },
3352     { X86::SETNPr, X86::SETNPm },
3353     { X86::SETNSr, X86::SETNSm },
3354     { X86::SETOr,  X86::SETOm  },
3355     { X86::SETPr,  X86::SETPm  },
3356     { X86::SETSr,  X86::SETSm  }
3357   };
3358 
3359   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3360   return Opc[CC][HasMemoryOperand ? 1 : 0];
3361 }
3362 
3363 /// Return a cmov opcode for the given condition,
3364 /// register size in bytes, and operand type.
3365 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3366                               bool HasMemoryOperand) {
3367   static const uint16_t Opc[32][3] = {
3368     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3369     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3370     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3371     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3372     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3373     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3374     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3375     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3376     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3377     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3378     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3379     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3380     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3381     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3382     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3383     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3384     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3385     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3386     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3387     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3388     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3389     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3390     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3391     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3392     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3393     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3394     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3395     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3396     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3397     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3398     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3399     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3400   };
3401 
3402   assert(CC < 16 && "Can only handle standard cond codes");
3403   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3404   switch(RegBytes) {
3405   default: llvm_unreachable("Illegal register size!");
3406   case 2: return Opc[Idx][0];
3407   case 4: return Opc[Idx][1];
3408   case 8: return Opc[Idx][2];
3409   }
3410 }
3411 
3412 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3413   if (!MI->isTerminator()) return false;
3414 
3415   // Conditional branch is a special case.
3416   if (MI->isBranch() && !MI->isBarrier())
3417     return true;
3418   if (!MI->isPredicable())
3419     return true;
3420   return !isPredicated(MI);
3421 }
3422 
3423 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3424                                  MachineBasicBlock *&TBB,
3425                                  MachineBasicBlock *&FBB,
3426                                  SmallVectorImpl<MachineOperand> &Cond,
3427                                  bool AllowModify) const {
3428   // Start from the bottom of the block and work up, examining the
3429   // terminator instructions.
3430   MachineBasicBlock::iterator I = MBB.end();
3431   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3432   while (I != MBB.begin()) {
3433     --I;
3434     if (I->isDebugValue())
3435       continue;
3436 
3437     // Working from the bottom, when we see a non-terminator instruction, we're
3438     // done.
3439     if (!isUnpredicatedTerminator(I))
3440       break;
3441 
3442     // A terminator that isn't a branch can't easily be handled by this
3443     // analysis.
3444     if (!I->isBranch())
3445       return true;
3446 
3447     // Handle unconditional branches.
3448     if (I->getOpcode() == X86::JMP_1) {
3449       UnCondBrIter = I;
3450 
3451       if (!AllowModify) {
3452         TBB = I->getOperand(0).getMBB();
3453         continue;
3454       }
3455 
3456       // If the block has any instructions after a JMP, delete them.
3457       while (std::next(I) != MBB.end())
3458         std::next(I)->eraseFromParent();
3459 
3460       Cond.clear();
3461       FBB = nullptr;
3462 
3463       // Delete the JMP if it's equivalent to a fall-through.
3464       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3465         TBB = nullptr;
3466         I->eraseFromParent();
3467         I = MBB.end();
3468         UnCondBrIter = MBB.end();
3469         continue;
3470       }
3471 
3472       // TBB is used to indicate the unconditional destination.
3473       TBB = I->getOperand(0).getMBB();
3474       continue;
3475     }
3476 
3477     // Handle conditional branches.
3478     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3479     if (BranchCode == X86::COND_INVALID)
3480       return true;  // Can't handle indirect branch.
3481 
3482     // Working from the bottom, handle the first conditional branch.
3483     if (Cond.empty()) {
3484       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3485       if (AllowModify && UnCondBrIter != MBB.end() &&
3486           MBB.isLayoutSuccessor(TargetBB)) {
3487         // If we can modify the code and it ends in something like:
3488         //
3489         //     jCC L1
3490         //     jmp L2
3491         //   L1:
3492         //     ...
3493         //   L2:
3494         //
3495         // Then we can change this to:
3496         //
3497         //     jnCC L2
3498         //   L1:
3499         //     ...
3500         //   L2:
3501         //
3502         // Which is a bit more efficient.
3503         // We conditionally jump to the fall-through block.
3504         BranchCode = GetOppositeBranchCondition(BranchCode);
3505         unsigned JNCC = GetCondBranchFromCond(BranchCode);
3506         MachineBasicBlock::iterator OldInst = I;
3507 
3508         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3509           .addMBB(UnCondBrIter->getOperand(0).getMBB());
3510         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3511           .addMBB(TargetBB);
3512 
3513         OldInst->eraseFromParent();
3514         UnCondBrIter->eraseFromParent();
3515 
3516         // Restart the analysis.
3517         UnCondBrIter = MBB.end();
3518         I = MBB.end();
3519         continue;
3520       }
3521 
3522       FBB = TBB;
3523       TBB = I->getOperand(0).getMBB();
3524       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3525       continue;
3526     }
3527 
3528     // Handle subsequent conditional branches. Only handle the case where all
3529     // conditional branches branch to the same destination and their condition
3530     // opcodes fit one of the special multi-branch idioms.
3531     assert(Cond.size() == 1);
3532     assert(TBB);
3533 
3534     // Only handle the case where all conditional branches branch to the same
3535     // destination.
3536     if (TBB != I->getOperand(0).getMBB())
3537       return true;
3538 
3539     // If the conditions are the same, we can leave them alone.
3540     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3541     if (OldBranchCode == BranchCode)
3542       continue;
3543 
3544     // If they differ, see if they fit one of the known patterns. Theoretically,
3545     // we could handle more patterns here, but we shouldn't expect to see them
3546     // if instruction selection has done a reasonable job.
3547     if ((OldBranchCode == X86::COND_NP &&
3548          BranchCode == X86::COND_E) ||
3549         (OldBranchCode == X86::COND_E &&
3550          BranchCode == X86::COND_NP))
3551       BranchCode = X86::COND_NP_OR_E;
3552     else if ((OldBranchCode == X86::COND_P &&
3553               BranchCode == X86::COND_NE) ||
3554              (OldBranchCode == X86::COND_NE &&
3555               BranchCode == X86::COND_P))
3556       BranchCode = X86::COND_NE_OR_P;
3557     else
3558       return true;
3559 
3560     // Update the MachineOperand.
3561     Cond[0].setImm(BranchCode);
3562   }
3563 
3564   return false;
3565 }
3566 
3567 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3568   MachineBasicBlock::iterator I = MBB.end();
3569   unsigned Count = 0;
3570 
3571   while (I != MBB.begin()) {
3572     --I;
3573     if (I->isDebugValue())
3574       continue;
3575     if (I->getOpcode() != X86::JMP_1 &&
3576         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3577       break;
3578     // Remove the branch.
3579     I->eraseFromParent();
3580     I = MBB.end();
3581     ++Count;
3582   }
3583 
3584   return Count;
3585 }
3586 
3587 unsigned
3588 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3589                            MachineBasicBlock *FBB,
3590                            const SmallVectorImpl<MachineOperand> &Cond,
3591                            DebugLoc DL) const {
3592   // Shouldn't be a fall through.
3593   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3594   assert((Cond.size() == 1 || Cond.size() == 0) &&
3595          "X86 branch conditions have one component!");
3596 
3597   if (Cond.empty()) {
3598     // Unconditional branch?
3599     assert(!FBB && "Unconditional branch with multiple successors!");
3600     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3601     return 1;
3602   }
3603 
3604   // Conditional branch.
3605   unsigned Count = 0;
3606   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3607   switch (CC) {
3608   case X86::COND_NP_OR_E:
3609     // Synthesize NP_OR_E with two branches.
3610     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
3611     ++Count;
3612     BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
3613     ++Count;
3614     break;
3615   case X86::COND_NE_OR_P:
3616     // Synthesize NE_OR_P with two branches.
3617     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
3618     ++Count;
3619     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
3620     ++Count;
3621     break;
3622   default: {
3623     unsigned Opc = GetCondBranchFromCond(CC);
3624     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3625     ++Count;
3626   }
3627   }
3628   if (FBB) {
3629     // Two-way Conditional branch. Insert the second branch.
3630     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3631     ++Count;
3632   }
3633   return Count;
3634 }
3635 
3636 bool X86InstrInfo::
3637 canInsertSelect(const MachineBasicBlock &MBB,
3638                 const SmallVectorImpl<MachineOperand> &Cond,
3639                 unsigned TrueReg, unsigned FalseReg,
3640                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3641   // Not all subtargets have cmov instructions.
3642   if (!Subtarget.hasCMov())
3643     return false;
3644   if (Cond.size() != 1)
3645     return false;
3646   // We cannot do the composite conditions, at least not in SSA form.
3647   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3648     return false;
3649 
3650   // Check register classes.
3651   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3652   const TargetRegisterClass *RC =
3653     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3654   if (!RC)
3655     return false;
3656 
3657   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3658   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3659       X86::GR32RegClass.hasSubClassEq(RC) ||
3660       X86::GR64RegClass.hasSubClassEq(RC)) {
3661     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3662     // Bridge. Probably Ivy Bridge as well.
3663     CondCycles = 2;
3664     TrueCycles = 2;
3665     FalseCycles = 2;
3666     return true;
3667   }
3668 
3669   // Can't do vectors.
3670   return false;
3671 }
3672 
3673 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3674                                 MachineBasicBlock::iterator I, DebugLoc DL,
3675                                 unsigned DstReg,
3676                                 const SmallVectorImpl<MachineOperand> &Cond,
3677                                 unsigned TrueReg, unsigned FalseReg) const {
3678    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3679    assert(Cond.size() == 1 && "Invalid Cond array");
3680    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3681                                   MRI.getRegClass(DstReg)->getSize(),
3682                                   false/*HasMemoryOperand*/);
3683    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3684 }
3685 
3686 /// Test if the given register is a physical h register.
3687 static bool isHReg(unsigned Reg) {
3688   return X86::GR8_ABCD_HRegClass.contains(Reg);
3689 }
3690 
3691 // Try and copy between VR128/VR64 and GR64 registers.
3692 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3693                                         const X86Subtarget &Subtarget) {
3694 
3695   // SrcReg(VR128) -> DestReg(GR64)
3696   // SrcReg(VR64)  -> DestReg(GR64)
3697   // SrcReg(GR64)  -> DestReg(VR128)
3698   // SrcReg(GR64)  -> DestReg(VR64)
3699 
3700   bool HasAVX = Subtarget.hasAVX();
3701   bool HasAVX512 = Subtarget.hasAVX512();
3702   if (X86::GR64RegClass.contains(DestReg)) {
3703     if (X86::VR128XRegClass.contains(SrcReg))
3704       // Copy from a VR128 register to a GR64 register.
3705       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3706                                                X86::MOVPQIto64rr);
3707     if (X86::VR64RegClass.contains(SrcReg))
3708       // Copy from a VR64 register to a GR64 register.
3709       return X86::MOVSDto64rr;
3710   } else if (X86::GR64RegClass.contains(SrcReg)) {
3711     // Copy from a GR64 register to a VR128 register.
3712     if (X86::VR128XRegClass.contains(DestReg))
3713       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3714                                                X86::MOV64toPQIrr);
3715     // Copy from a GR64 register to a VR64 register.
3716     if (X86::VR64RegClass.contains(DestReg))
3717       return X86::MOV64toSDrr;
3718   }
3719 
3720   // SrcReg(FR32) -> DestReg(GR32)
3721   // SrcReg(GR32) -> DestReg(FR32)
3722 
3723   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3724     // Copy from a FR32 register to a GR32 register.
3725     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3726 
3727   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3728     // Copy from a GR32 register to a FR32 register.
3729     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3730   return 0;
3731 }
3732 
3733 inline static bool MaskRegClassContains(unsigned Reg) {
3734   return X86::VK8RegClass.contains(Reg) ||
3735          X86::VK16RegClass.contains(Reg) ||
3736          X86::VK32RegClass.contains(Reg) ||
3737          X86::VK64RegClass.contains(Reg) ||
3738          X86::VK1RegClass.contains(Reg);
3739 }
3740 static
3741 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3742   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3743       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3744       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3745      DestReg = get512BitSuperRegister(DestReg);
3746      SrcReg = get512BitSuperRegister(SrcReg);
3747      return X86::VMOVAPSZrr;
3748   }
3749   if (MaskRegClassContains(DestReg) &&
3750       MaskRegClassContains(SrcReg))
3751     return X86::KMOVWkk;
3752   if (MaskRegClassContains(DestReg) &&
3753       (X86::GR32RegClass.contains(SrcReg) ||
3754        X86::GR16RegClass.contains(SrcReg) ||
3755        X86::GR8RegClass.contains(SrcReg))) {
3756     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3757     return X86::KMOVWkr;
3758   }
3759   if ((X86::GR32RegClass.contains(DestReg) ||
3760        X86::GR16RegClass.contains(DestReg) ||
3761        X86::GR8RegClass.contains(DestReg)) &&
3762        MaskRegClassContains(SrcReg)) {
3763     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3764     return X86::KMOVWrk;
3765   }
3766   return 0;
3767 }
3768 
3769 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3770                                MachineBasicBlock::iterator MI, DebugLoc DL,
3771                                unsigned DestReg, unsigned SrcReg,
3772                                bool KillSrc) const {
3773   // First deal with the normal symmetric copies.
3774   bool HasAVX = Subtarget.hasAVX();
3775   bool HasAVX512 = Subtarget.hasAVX512();
3776   unsigned Opc = 0;
3777   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3778     Opc = X86::MOV64rr;
3779   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3780     Opc = X86::MOV32rr;
3781   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3782     Opc = X86::MOV16rr;
3783   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3784     // Copying to or from a physical H register on x86-64 requires a NOREX
3785     // move.  Otherwise use a normal move.
3786     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3787         Subtarget.is64Bit()) {
3788       Opc = X86::MOV8rr_NOREX;
3789       // Both operands must be encodable without an REX prefix.
3790       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3791              "8-bit H register can not be copied outside GR8_NOREX");
3792     } else
3793       Opc = X86::MOV8rr;
3794   }
3795   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3796     Opc = X86::MMX_MOVQ64rr;
3797   else if (HasAVX512)
3798     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3799   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3800     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3801   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3802     Opc = X86::VMOVAPSYrr;
3803   if (!Opc)
3804     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3805 
3806   if (Opc) {
3807     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3808       .addReg(SrcReg, getKillRegState(KillSrc));
3809     return;
3810   }
3811 
3812   // Moving EFLAGS to / from another register requires a push and a pop.
3813   // Notice that we have to adjust the stack if we don't want to clobber the
3814   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3815   if (SrcReg == X86::EFLAGS) {
3816     if (X86::GR64RegClass.contains(DestReg)) {
3817       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3818       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3819       return;
3820     }
3821     if (X86::GR32RegClass.contains(DestReg)) {
3822       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3823       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3824       return;
3825     }
3826   }
3827   if (DestReg == X86::EFLAGS) {
3828     if (X86::GR64RegClass.contains(SrcReg)) {
3829       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3830         .addReg(SrcReg, getKillRegState(KillSrc));
3831       BuildMI(MBB, MI, DL, get(X86::POPF64));
3832       return;
3833     }
3834     if (X86::GR32RegClass.contains(SrcReg)) {
3835       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3836         .addReg(SrcReg, getKillRegState(KillSrc));
3837       BuildMI(MBB, MI, DL, get(X86::POPF32));
3838       return;
3839     }
3840   }
3841 
3842   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3843                << " to " << RI.getName(DestReg) << '\n');
3844   llvm_unreachable("Cannot emit physreg copy instruction");
3845 }
3846 
3847 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3848                                       const TargetRegisterClass *RC,
3849                                       bool isStackAligned,
3850                                       const X86Subtarget &STI,
3851                                       bool load) {
3852   if (STI.hasAVX512()) {
3853     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3854       X86::VK16RegClass.hasSubClassEq(RC))
3855       return load ? X86::KMOVWkm : X86::KMOVWmk;
3856     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3857       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3858     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3859       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3860     if (X86::VR512RegClass.hasSubClassEq(RC))
3861       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3862   }
3863 
3864   bool HasAVX = STI.hasAVX();
3865   switch (RC->getSize()) {
3866   default:
3867     llvm_unreachable("Unknown spill size");
3868   case 1:
3869     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3870     if (STI.is64Bit())
3871       // Copying to or from a physical H register on x86-64 requires a NOREX
3872       // move.  Otherwise use a normal move.
3873       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3874         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3875     return load ? X86::MOV8rm : X86::MOV8mr;
3876   case 2:
3877     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3878     return load ? X86::MOV16rm : X86::MOV16mr;
3879   case 4:
3880     if (X86::GR32RegClass.hasSubClassEq(RC))
3881       return load ? X86::MOV32rm : X86::MOV32mr;
3882     if (X86::FR32RegClass.hasSubClassEq(RC))
3883       return load ?
3884         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3885         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3886     if (X86::RFP32RegClass.hasSubClassEq(RC))
3887       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3888     llvm_unreachable("Unknown 4-byte regclass");
3889   case 8:
3890     if (X86::GR64RegClass.hasSubClassEq(RC))
3891       return load ? X86::MOV64rm : X86::MOV64mr;
3892     if (X86::FR64RegClass.hasSubClassEq(RC))
3893       return load ?
3894         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3895         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3896     if (X86::VR64RegClass.hasSubClassEq(RC))
3897       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3898     if (X86::RFP64RegClass.hasSubClassEq(RC))
3899       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3900     llvm_unreachable("Unknown 8-byte regclass");
3901   case 10:
3902     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3903     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3904   case 16: {
3905     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3906             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3907     // If stack is realigned we can use aligned stores.
3908     if (isStackAligned)
3909       return load ?
3910         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3911         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3912     else
3913       return load ?
3914         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3915         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3916   }
3917   case 32:
3918     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3919             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3920     // If stack is realigned we can use aligned stores.
3921     if (isStackAligned)
3922       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3923     else
3924       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3925   case 64:
3926     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3927     if (isStackAligned)
3928       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3929     else
3930       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3931   }
3932 }
3933 
3934 static unsigned getStoreRegOpcode(unsigned SrcReg,
3935                                   const TargetRegisterClass *RC,
3936                                   bool isStackAligned,
3937                                   const X86Subtarget &STI) {
3938   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3939 }
3940 
3941 
3942 static unsigned getLoadRegOpcode(unsigned DestReg,
3943                                  const TargetRegisterClass *RC,
3944                                  bool isStackAligned,
3945                                  const X86Subtarget &STI) {
3946   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3947 }
3948 
3949 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3950                                        MachineBasicBlock::iterator MI,
3951                                        unsigned SrcReg, bool isKill, int FrameIdx,
3952                                        const TargetRegisterClass *RC,
3953                                        const TargetRegisterInfo *TRI) const {
3954   const MachineFunction &MF = *MBB.getParent();
3955   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3956          "Stack slot too small for store");
3957   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3958   bool isAligned =
3959       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3960       RI.canRealignStack(MF);
3961   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3962   DebugLoc DL = MBB.findDebugLoc(MI);
3963   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3964     .addReg(SrcReg, getKillRegState(isKill));
3965 }
3966 
3967 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3968                                   bool isKill,
3969                                   SmallVectorImpl<MachineOperand> &Addr,
3970                                   const TargetRegisterClass *RC,
3971                                   MachineInstr::mmo_iterator MMOBegin,
3972                                   MachineInstr::mmo_iterator MMOEnd,
3973                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3974   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3975   bool isAligned = MMOBegin != MMOEnd &&
3976                    (*MMOBegin)->getAlignment() >= Alignment;
3977   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3978   DebugLoc DL;
3979   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3980   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3981     MIB.addOperand(Addr[i]);
3982   MIB.addReg(SrcReg, getKillRegState(isKill));
3983   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3984   NewMIs.push_back(MIB);
3985 }
3986 
3987 
3988 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3989                                         MachineBasicBlock::iterator MI,
3990                                         unsigned DestReg, int FrameIdx,
3991                                         const TargetRegisterClass *RC,
3992                                         const TargetRegisterInfo *TRI) const {
3993   const MachineFunction &MF = *MBB.getParent();
3994   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3995   bool isAligned =
3996       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3997       RI.canRealignStack(MF);
3998   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3999   DebugLoc DL = MBB.findDebugLoc(MI);
4000   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4001 }
4002 
4003 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4004                                  SmallVectorImpl<MachineOperand> &Addr,
4005                                  const TargetRegisterClass *RC,
4006                                  MachineInstr::mmo_iterator MMOBegin,
4007                                  MachineInstr::mmo_iterator MMOEnd,
4008                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4009   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4010   bool isAligned = MMOBegin != MMOEnd &&
4011                    (*MMOBegin)->getAlignment() >= Alignment;
4012   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4013   DebugLoc DL;
4014   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4015   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4016     MIB.addOperand(Addr[i]);
4017   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4018   NewMIs.push_back(MIB);
4019 }
4020 
4021 bool X86InstrInfo::
4022 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4023                int &CmpMask, int &CmpValue) const {
4024   switch (MI->getOpcode()) {
4025   default: break;
4026   case X86::CMP64ri32:
4027   case X86::CMP64ri8:
4028   case X86::CMP32ri:
4029   case X86::CMP32ri8:
4030   case X86::CMP16ri:
4031   case X86::CMP16ri8:
4032   case X86::CMP8ri:
4033     SrcReg = MI->getOperand(0).getReg();
4034     SrcReg2 = 0;
4035     CmpMask = ~0;
4036     CmpValue = MI->getOperand(1).getImm();
4037     return true;
4038   // A SUB can be used to perform comparison.
4039   case X86::SUB64rm:
4040   case X86::SUB32rm:
4041   case X86::SUB16rm:
4042   case X86::SUB8rm:
4043     SrcReg = MI->getOperand(1).getReg();
4044     SrcReg2 = 0;
4045     CmpMask = ~0;
4046     CmpValue = 0;
4047     return true;
4048   case X86::SUB64rr:
4049   case X86::SUB32rr:
4050   case X86::SUB16rr:
4051   case X86::SUB8rr:
4052     SrcReg = MI->getOperand(1).getReg();
4053     SrcReg2 = MI->getOperand(2).getReg();
4054     CmpMask = ~0;
4055     CmpValue = 0;
4056     return true;
4057   case X86::SUB64ri32:
4058   case X86::SUB64ri8:
4059   case X86::SUB32ri:
4060   case X86::SUB32ri8:
4061   case X86::SUB16ri:
4062   case X86::SUB16ri8:
4063   case X86::SUB8ri:
4064     SrcReg = MI->getOperand(1).getReg();
4065     SrcReg2 = 0;
4066     CmpMask = ~0;
4067     CmpValue = MI->getOperand(2).getImm();
4068     return true;
4069   case X86::CMP64rr:
4070   case X86::CMP32rr:
4071   case X86::CMP16rr:
4072   case X86::CMP8rr:
4073     SrcReg = MI->getOperand(0).getReg();
4074     SrcReg2 = MI->getOperand(1).getReg();
4075     CmpMask = ~0;
4076     CmpValue = 0;
4077     return true;
4078   case X86::TEST8rr:
4079   case X86::TEST16rr:
4080   case X86::TEST32rr:
4081   case X86::TEST64rr:
4082     SrcReg = MI->getOperand(0).getReg();
4083     if (MI->getOperand(1).getReg() != SrcReg) return false;
4084     // Compare against zero.
4085     SrcReg2 = 0;
4086     CmpMask = ~0;
4087     CmpValue = 0;
4088     return true;
4089   }
4090   return false;
4091 }
4092 
4093 /// Check whether the first instruction, whose only
4094 /// purpose is to update flags, can be made redundant.
4095 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4096 /// This function can be extended later on.
4097 /// SrcReg, SrcRegs: register operands for FlagI.
4098 /// ImmValue: immediate for FlagI if it takes an immediate.
4099 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4100                                         unsigned SrcReg2, int ImmValue,
4101                                         MachineInstr *OI) {
4102   if (((FlagI->getOpcode() == X86::CMP64rr &&
4103         OI->getOpcode() == X86::SUB64rr) ||
4104        (FlagI->getOpcode() == X86::CMP32rr &&
4105         OI->getOpcode() == X86::SUB32rr)||
4106        (FlagI->getOpcode() == X86::CMP16rr &&
4107         OI->getOpcode() == X86::SUB16rr)||
4108        (FlagI->getOpcode() == X86::CMP8rr &&
4109         OI->getOpcode() == X86::SUB8rr)) &&
4110       ((OI->getOperand(1).getReg() == SrcReg &&
4111         OI->getOperand(2).getReg() == SrcReg2) ||
4112        (OI->getOperand(1).getReg() == SrcReg2 &&
4113         OI->getOperand(2).getReg() == SrcReg)))
4114     return true;
4115 
4116   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4117         OI->getOpcode() == X86::SUB64ri32) ||
4118        (FlagI->getOpcode() == X86::CMP64ri8 &&
4119         OI->getOpcode() == X86::SUB64ri8) ||
4120        (FlagI->getOpcode() == X86::CMP32ri &&
4121         OI->getOpcode() == X86::SUB32ri) ||
4122        (FlagI->getOpcode() == X86::CMP32ri8 &&
4123         OI->getOpcode() == X86::SUB32ri8) ||
4124        (FlagI->getOpcode() == X86::CMP16ri &&
4125         OI->getOpcode() == X86::SUB16ri) ||
4126        (FlagI->getOpcode() == X86::CMP16ri8 &&
4127         OI->getOpcode() == X86::SUB16ri8) ||
4128        (FlagI->getOpcode() == X86::CMP8ri &&
4129         OI->getOpcode() == X86::SUB8ri)) &&
4130       OI->getOperand(1).getReg() == SrcReg &&
4131       OI->getOperand(2).getImm() == ImmValue)
4132     return true;
4133   return false;
4134 }
4135 
4136 /// Check whether the definition can be converted
4137 /// to remove a comparison against zero.
4138 inline static bool isDefConvertible(MachineInstr *MI) {
4139   switch (MI->getOpcode()) {
4140   default: return false;
4141 
4142   // The shift instructions only modify ZF if their shift count is non-zero.
4143   // N.B.: The processor truncates the shift count depending on the encoding.
4144   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4145   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4146      return getTruncatedShiftCount(MI, 2) != 0;
4147 
4148   // Some left shift instructions can be turned into LEA instructions but only
4149   // if their flags aren't used. Avoid transforming such instructions.
4150   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4151     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4152     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4153     return ShAmt != 0;
4154   }
4155 
4156   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4157   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4158      return getTruncatedShiftCount(MI, 3) != 0;
4159 
4160   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4161   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4162   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4163   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4164   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4165   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4166   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4167   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4168   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4169   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4170   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4171   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4172   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4173   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4174   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4175   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4176   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4177   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4178   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4179   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4180   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4181   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4182   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4183   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4184   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4185   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4186   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4187   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4188   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4189   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4190   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4191   case X86::ADC32ri:   case X86::ADC32ri8:
4192   case X86::ADC32rr:   case X86::ADC64ri32:
4193   case X86::ADC64ri8:  case X86::ADC64rr:
4194   case X86::SBB32ri:   case X86::SBB32ri8:
4195   case X86::SBB32rr:   case X86::SBB64ri32:
4196   case X86::SBB64ri8:  case X86::SBB64rr:
4197   case X86::ANDN32rr:  case X86::ANDN32rm:
4198   case X86::ANDN64rr:  case X86::ANDN64rm:
4199   case X86::BEXTR32rr: case X86::BEXTR64rr:
4200   case X86::BEXTR32rm: case X86::BEXTR64rm:
4201   case X86::BLSI32rr:  case X86::BLSI32rm:
4202   case X86::BLSI64rr:  case X86::BLSI64rm:
4203   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4204   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4205   case X86::BLSR32rr:  case X86::BLSR32rm:
4206   case X86::BLSR64rr:  case X86::BLSR64rm:
4207   case X86::BZHI32rr:  case X86::BZHI32rm:
4208   case X86::BZHI64rr:  case X86::BZHI64rm:
4209   case X86::LZCNT16rr: case X86::LZCNT16rm:
4210   case X86::LZCNT32rr: case X86::LZCNT32rm:
4211   case X86::LZCNT64rr: case X86::LZCNT64rm:
4212   case X86::POPCNT16rr:case X86::POPCNT16rm:
4213   case X86::POPCNT32rr:case X86::POPCNT32rm:
4214   case X86::POPCNT64rr:case X86::POPCNT64rm:
4215   case X86::TZCNT16rr: case X86::TZCNT16rm:
4216   case X86::TZCNT32rr: case X86::TZCNT32rm:
4217   case X86::TZCNT64rr: case X86::TZCNT64rm:
4218     return true;
4219   }
4220 }
4221 
4222 /// Check whether the use can be converted to remove a comparison against zero.
4223 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4224   switch (MI->getOpcode()) {
4225   default: return X86::COND_INVALID;
4226   case X86::LZCNT16rr: case X86::LZCNT16rm:
4227   case X86::LZCNT32rr: case X86::LZCNT32rm:
4228   case X86::LZCNT64rr: case X86::LZCNT64rm:
4229     return X86::COND_B;
4230   case X86::POPCNT16rr:case X86::POPCNT16rm:
4231   case X86::POPCNT32rr:case X86::POPCNT32rm:
4232   case X86::POPCNT64rr:case X86::POPCNT64rm:
4233     return X86::COND_E;
4234   case X86::TZCNT16rr: case X86::TZCNT16rm:
4235   case X86::TZCNT32rr: case X86::TZCNT32rm:
4236   case X86::TZCNT64rr: case X86::TZCNT64rm:
4237     return X86::COND_B;
4238   }
4239 }
4240 
4241 /// Check if there exists an earlier instruction that
4242 /// operates on the same source operands and sets flags in the same way as
4243 /// Compare; remove Compare if possible.
4244 bool X86InstrInfo::
4245 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4246                      int CmpMask, int CmpValue,
4247                      const MachineRegisterInfo *MRI) const {
4248   // Check whether we can replace SUB with CMP.
4249   unsigned NewOpcode = 0;
4250   switch (CmpInstr->getOpcode()) {
4251   default: break;
4252   case X86::SUB64ri32:
4253   case X86::SUB64ri8:
4254   case X86::SUB32ri:
4255   case X86::SUB32ri8:
4256   case X86::SUB16ri:
4257   case X86::SUB16ri8:
4258   case X86::SUB8ri:
4259   case X86::SUB64rm:
4260   case X86::SUB32rm:
4261   case X86::SUB16rm:
4262   case X86::SUB8rm:
4263   case X86::SUB64rr:
4264   case X86::SUB32rr:
4265   case X86::SUB16rr:
4266   case X86::SUB8rr: {
4267     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4268       return false;
4269     // There is no use of the destination register, we can replace SUB with CMP.
4270     switch (CmpInstr->getOpcode()) {
4271     default: llvm_unreachable("Unreachable!");
4272     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4273     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4274     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4275     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4276     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4277     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4278     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4279     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4280     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4281     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4282     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4283     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4284     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4285     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4286     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4287     }
4288     CmpInstr->setDesc(get(NewOpcode));
4289     CmpInstr->RemoveOperand(0);
4290     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4291     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4292         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4293       return false;
4294   }
4295   }
4296 
4297   // Get the unique definition of SrcReg.
4298   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4299   if (!MI) return false;
4300 
4301   // CmpInstr is the first instruction of the BB.
4302   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4303 
4304   // If we are comparing against zero, check whether we can use MI to update
4305   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4306   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
4307   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
4308     return false;
4309 
4310   // If we have a use of the source register between the def and our compare
4311   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4312   // right way.
4313   bool ShouldUpdateCC = false;
4314   X86::CondCode NewCC = X86::COND_INVALID;
4315   if (IsCmpZero && !isDefConvertible(MI)) {
4316     // Scan forward from the use until we hit the use we're looking for or the
4317     // compare instruction.
4318     for (MachineBasicBlock::iterator J = MI;; ++J) {
4319       // Do we have a convertible instruction?
4320       NewCC = isUseDefConvertible(J);
4321       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4322           J->getOperand(1).getReg() == SrcReg) {
4323         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4324         ShouldUpdateCC = true; // Update CC later on.
4325         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4326         // with the new def.
4327         MI = Def = J;
4328         break;
4329       }
4330 
4331       if (J == I)
4332         return false;
4333     }
4334   }
4335 
4336   // We are searching for an earlier instruction that can make CmpInstr
4337   // redundant and that instruction will be saved in Sub.
4338   MachineInstr *Sub = nullptr;
4339   const TargetRegisterInfo *TRI = &getRegisterInfo();
4340 
4341   // We iterate backward, starting from the instruction before CmpInstr and
4342   // stop when reaching the definition of a source register or done with the BB.
4343   // RI points to the instruction before CmpInstr.
4344   // If the definition is in this basic block, RE points to the definition;
4345   // otherwise, RE is the rend of the basic block.
4346   MachineBasicBlock::reverse_iterator
4347       RI = MachineBasicBlock::reverse_iterator(I),
4348       RE = CmpInstr->getParent() == MI->getParent() ?
4349            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4350            CmpInstr->getParent()->rend();
4351   MachineInstr *Movr0Inst = nullptr;
4352   for (; RI != RE; ++RI) {
4353     MachineInstr *Instr = &*RI;
4354     // Check whether CmpInstr can be made redundant by the current instruction.
4355     if (!IsCmpZero &&
4356         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
4357       Sub = Instr;
4358       break;
4359     }
4360 
4361     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
4362         Instr->readsRegister(X86::EFLAGS, TRI)) {
4363       // This instruction modifies or uses EFLAGS.
4364 
4365       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4366       // They are safe to move up, if the definition to EFLAGS is dead and
4367       // earlier instructions do not read or write EFLAGS.
4368       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
4369           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4370         Movr0Inst = Instr;
4371         continue;
4372       }
4373 
4374       // We can't remove CmpInstr.
4375       return false;
4376     }
4377   }
4378 
4379   // Return false if no candidates exist.
4380   if (!IsCmpZero && !Sub)
4381     return false;
4382 
4383   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4384                     Sub->getOperand(2).getReg() == SrcReg);
4385 
4386   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4387   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4388   // If we are done with the basic block, we need to check whether EFLAGS is
4389   // live-out.
4390   bool IsSafe = false;
4391   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4392   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4393   for (++I; I != E; ++I) {
4394     const MachineInstr &Instr = *I;
4395     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4396     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4397     // We should check the usage if this instruction uses and updates EFLAGS.
4398     if (!UseEFLAGS && ModifyEFLAGS) {
4399       // It is safe to remove CmpInstr if EFLAGS is updated again.
4400       IsSafe = true;
4401       break;
4402     }
4403     if (!UseEFLAGS && !ModifyEFLAGS)
4404       continue;
4405 
4406     // EFLAGS is used by this instruction.
4407     X86::CondCode OldCC = X86::COND_INVALID;
4408     bool OpcIsSET = false;
4409     if (IsCmpZero || IsSwapped) {
4410       // We decode the condition code from opcode.
4411       if (Instr.isBranch())
4412         OldCC = getCondFromBranchOpc(Instr.getOpcode());
4413       else {
4414         OldCC = getCondFromSETOpc(Instr.getOpcode());
4415         if (OldCC != X86::COND_INVALID)
4416           OpcIsSET = true;
4417         else
4418           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
4419       }
4420       if (OldCC == X86::COND_INVALID) return false;
4421     }
4422     if (IsCmpZero) {
4423       switch (OldCC) {
4424       default: break;
4425       case X86::COND_A: case X86::COND_AE:
4426       case X86::COND_B: case X86::COND_BE:
4427       case X86::COND_G: case X86::COND_GE:
4428       case X86::COND_L: case X86::COND_LE:
4429       case X86::COND_O: case X86::COND_NO:
4430         // CF and OF are used, we can't perform this optimization.
4431         return false;
4432       }
4433 
4434       // If we're updating the condition code check if we have to reverse the
4435       // condition.
4436       if (ShouldUpdateCC)
4437         switch (OldCC) {
4438         default:
4439           return false;
4440         case X86::COND_E:
4441           break;
4442         case X86::COND_NE:
4443           NewCC = GetOppositeBranchCondition(NewCC);
4444           break;
4445         }
4446     } else if (IsSwapped) {
4447       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4448       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4449       // We swap the condition code and synthesize the new opcode.
4450       NewCC = getSwappedCondition(OldCC);
4451       if (NewCC == X86::COND_INVALID) return false;
4452     }
4453 
4454     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4455       // Synthesize the new opcode.
4456       bool HasMemoryOperand = Instr.hasOneMemOperand();
4457       unsigned NewOpc;
4458       if (Instr.isBranch())
4459         NewOpc = GetCondBranchFromCond(NewCC);
4460       else if(OpcIsSET)
4461         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4462       else {
4463         unsigned DstReg = Instr.getOperand(0).getReg();
4464         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4465                                  HasMemoryOperand);
4466       }
4467 
4468       // Push the MachineInstr to OpsToUpdate.
4469       // If it is safe to remove CmpInstr, the condition code of these
4470       // instructions will be modified.
4471       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4472     }
4473     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4474       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4475       IsSafe = true;
4476       break;
4477     }
4478   }
4479 
4480   // If EFLAGS is not killed nor re-defined, we should check whether it is
4481   // live-out. If it is live-out, do not optimize.
4482   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4483     MachineBasicBlock *MBB = CmpInstr->getParent();
4484     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4485              SE = MBB->succ_end(); SI != SE; ++SI)
4486       if ((*SI)->isLiveIn(X86::EFLAGS))
4487         return false;
4488   }
4489 
4490   // The instruction to be updated is either Sub or MI.
4491   Sub = IsCmpZero ? MI : Sub;
4492   // Move Movr0Inst to the appropriate place before Sub.
4493   if (Movr0Inst) {
4494     // Look backwards until we find a def that doesn't use the current EFLAGS.
4495     Def = Sub;
4496     MachineBasicBlock::reverse_iterator
4497       InsertI = MachineBasicBlock::reverse_iterator(++Def),
4498                 InsertE = Sub->getParent()->rend();
4499     for (; InsertI != InsertE; ++InsertI) {
4500       MachineInstr *Instr = &*InsertI;
4501       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4502           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4503         Sub->getParent()->remove(Movr0Inst);
4504         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4505                                    Movr0Inst);
4506         break;
4507       }
4508     }
4509     if (InsertI == InsertE)
4510       return false;
4511   }
4512 
4513   // Make sure Sub instruction defines EFLAGS and mark the def live.
4514   unsigned i = 0, e = Sub->getNumOperands();
4515   for (; i != e; ++i) {
4516     MachineOperand &MO = Sub->getOperand(i);
4517     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4518       MO.setIsDead(false);
4519       break;
4520     }
4521   }
4522   assert(i != e && "Unable to locate a def EFLAGS operand");
4523 
4524   CmpInstr->eraseFromParent();
4525 
4526   // Modify the condition code of instructions in OpsToUpdate.
4527   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4528     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4529   return true;
4530 }
4531 
4532 /// Try to remove the load by folding it to a register
4533 /// operand at the use. We fold the load instructions if load defines a virtual
4534 /// register, the virtual register is used once in the same BB, and the
4535 /// instructions in-between do not load or store, and have no side effects.
4536 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4537                                               const MachineRegisterInfo *MRI,
4538                                               unsigned &FoldAsLoadDefReg,
4539                                               MachineInstr *&DefMI) const {
4540   if (FoldAsLoadDefReg == 0)
4541     return nullptr;
4542   // To be conservative, if there exists another load, clear the load candidate.
4543   if (MI->mayLoad()) {
4544     FoldAsLoadDefReg = 0;
4545     return nullptr;
4546   }
4547 
4548   // Check whether we can move DefMI here.
4549   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4550   assert(DefMI);
4551   bool SawStore = false;
4552   if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4553     return nullptr;
4554 
4555   // Collect information about virtual register operands of MI.
4556   unsigned SrcOperandId = 0;
4557   bool FoundSrcOperand = false;
4558   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4559     MachineOperand &MO = MI->getOperand(i);
4560     if (!MO.isReg())
4561       continue;
4562     unsigned Reg = MO.getReg();
4563     if (Reg != FoldAsLoadDefReg)
4564       continue;
4565     // Do not fold if we have a subreg use or a def or multiple uses.
4566     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4567       return nullptr;
4568 
4569     SrcOperandId = i;
4570     FoundSrcOperand = true;
4571   }
4572   if (!FoundSrcOperand)
4573     return nullptr;
4574 
4575   // Check whether we can fold the def into SrcOperandId.
4576   SmallVector<unsigned, 8> Ops;
4577   Ops.push_back(SrcOperandId);
4578   MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4579   if (FoldMI) {
4580     FoldAsLoadDefReg = 0;
4581     return FoldMI;
4582   }
4583 
4584   return nullptr;
4585 }
4586 
4587 /// Expand a single-def pseudo instruction to a two-addr
4588 /// instruction with two undef reads of the register being defined.
4589 /// This is used for mapping:
4590 ///   %xmm4 = V_SET0
4591 /// to:
4592 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4593 ///
4594 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4595                              const MCInstrDesc &Desc) {
4596   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4597   unsigned Reg = MIB->getOperand(0).getReg();
4598   MIB->setDesc(Desc);
4599 
4600   // MachineInstr::addOperand() will insert explicit operands before any
4601   // implicit operands.
4602   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4603   // But we don't trust that.
4604   assert(MIB->getOperand(1).getReg() == Reg &&
4605          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4606   return true;
4607 }
4608 
4609 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4610 // code sequence is needed for other targets.
4611 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4612                                  const TargetInstrInfo &TII) {
4613   MachineBasicBlock &MBB = *MIB->getParent();
4614   DebugLoc DL = MIB->getDebugLoc();
4615   unsigned Reg = MIB->getOperand(0).getReg();
4616   const GlobalValue *GV =
4617       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4618   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4619   MachineMemOperand *MMO = MBB.getParent()->
4620       getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
4621   MachineBasicBlock::iterator I = MIB.getInstr();
4622 
4623   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4624       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4625       .addMemOperand(MMO);
4626   MIB->setDebugLoc(DL);
4627   MIB->setDesc(TII.get(X86::MOV64rm));
4628   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4629 }
4630 
4631 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4632   bool HasAVX = Subtarget.hasAVX();
4633   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4634   switch (MI->getOpcode()) {
4635   case X86::MOV32r0:
4636     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4637   case X86::SETB_C8r:
4638     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4639   case X86::SETB_C16r:
4640     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4641   case X86::SETB_C32r:
4642     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4643   case X86::SETB_C64r:
4644     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4645   case X86::V_SET0:
4646   case X86::FsFLD0SS:
4647   case X86::FsFLD0SD:
4648     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4649   case X86::AVX_SET0:
4650     assert(HasAVX && "AVX not supported");
4651     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4652   case X86::AVX512_512_SET0:
4653     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4654   case X86::V_SETALLONES:
4655     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4656   case X86::AVX2_SETALLONES:
4657     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4658   case X86::TEST8ri_NOREX:
4659     MI->setDesc(get(X86::TEST8ri));
4660     return true;
4661   case X86::KSET0B:
4662   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4663   case X86::KSET1B:
4664   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4665   case TargetOpcode::LOAD_STACK_GUARD:
4666     expandLoadStackGuard(MIB, *this);
4667     return true;
4668   }
4669   return false;
4670 }
4671 
4672 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4673                                      const SmallVectorImpl<MachineOperand> &MOs,
4674                                      MachineInstr *MI,
4675                                      const TargetInstrInfo &TII) {
4676   // Create the base instruction with the memory operand as the first part.
4677   // Omit the implicit operands, something BuildMI can't do.
4678   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4679                                               MI->getDebugLoc(), true);
4680   MachineInstrBuilder MIB(MF, NewMI);
4681   unsigned NumAddrOps = MOs.size();
4682   for (unsigned i = 0; i != NumAddrOps; ++i)
4683     MIB.addOperand(MOs[i]);
4684   if (NumAddrOps < 4)  // FrameIndex only
4685     addOffset(MIB, 0);
4686 
4687   // Loop over the rest of the ri operands, converting them over.
4688   unsigned NumOps = MI->getDesc().getNumOperands()-2;
4689   for (unsigned i = 0; i != NumOps; ++i) {
4690     MachineOperand &MO = MI->getOperand(i+2);
4691     MIB.addOperand(MO);
4692   }
4693   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4694     MachineOperand &MO = MI->getOperand(i);
4695     MIB.addOperand(MO);
4696   }
4697   return MIB;
4698 }
4699 
4700 static MachineInstr *FuseInst(MachineFunction &MF,
4701                               unsigned Opcode, unsigned OpNo,
4702                               const SmallVectorImpl<MachineOperand> &MOs,
4703                               MachineInstr *MI, const TargetInstrInfo &TII) {
4704   // Omit the implicit operands, something BuildMI can't do.
4705   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4706                                               MI->getDebugLoc(), true);
4707   MachineInstrBuilder MIB(MF, NewMI);
4708 
4709   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4710     MachineOperand &MO = MI->getOperand(i);
4711     if (i == OpNo) {
4712       assert(MO.isReg() && "Expected to fold into reg operand!");
4713       unsigned NumAddrOps = MOs.size();
4714       for (unsigned i = 0; i != NumAddrOps; ++i)
4715         MIB.addOperand(MOs[i]);
4716       if (NumAddrOps < 4)  // FrameIndex only
4717         addOffset(MIB, 0);
4718     } else {
4719       MIB.addOperand(MO);
4720     }
4721   }
4722   return MIB;
4723 }
4724 
4725 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4726                                 const SmallVectorImpl<MachineOperand> &MOs,
4727                                 MachineInstr *MI) {
4728   MachineFunction &MF = *MI->getParent()->getParent();
4729   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4730 
4731   unsigned NumAddrOps = MOs.size();
4732   for (unsigned i = 0; i != NumAddrOps; ++i)
4733     MIB.addOperand(MOs[i]);
4734   if (NumAddrOps < 4)  // FrameIndex only
4735     addOffset(MIB, 0);
4736   return MIB.addImm(0);
4737 }
4738 
4739 MachineInstr*
4740 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4741                                     MachineInstr *MI, unsigned OpNum,
4742                                     const SmallVectorImpl<MachineOperand> &MOs,
4743                                     unsigned Size, unsigned Align,
4744                                     bool AllowCommute) const {
4745   const DenseMap<unsigned,
4746                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4747   bool isCallRegIndirect = Subtarget.callRegIndirect();
4748   bool isTwoAddrFold = false;
4749 
4750   // For CPUs that favor the register form of a call,
4751   // do not fold loads into calls.
4752   if (isCallRegIndirect &&
4753     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r))
4754     return nullptr;
4755 
4756   unsigned NumOps = MI->getDesc().getNumOperands();
4757   bool isTwoAddr = NumOps > 1 &&
4758     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4759 
4760   // FIXME: AsmPrinter doesn't know how to handle
4761   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4762   if (MI->getOpcode() == X86::ADD32ri &&
4763       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4764     return nullptr;
4765 
4766   MachineInstr *NewMI = nullptr;
4767   // Folding a memory location into the two-address part of a two-address
4768   // instruction is different than folding it other places.  It requires
4769   // replacing the *two* registers with the memory location.
4770   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
4771       MI->getOperand(0).isReg() &&
4772       MI->getOperand(1).isReg() &&
4773       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4774     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4775     isTwoAddrFold = true;
4776   } else if (OpNum == 0) {
4777     if (MI->getOpcode() == X86::MOV32r0) {
4778       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4779       if (NewMI)
4780         return NewMI;
4781     }
4782 
4783     OpcodeTablePtr = &RegOp2MemOpTable0;
4784   } else if (OpNum == 1) {
4785     OpcodeTablePtr = &RegOp2MemOpTable1;
4786   } else if (OpNum == 2) {
4787     OpcodeTablePtr = &RegOp2MemOpTable2;
4788   } else if (OpNum == 3) {
4789     OpcodeTablePtr = &RegOp2MemOpTable3;
4790   } else if (OpNum == 4) {
4791     OpcodeTablePtr = &RegOp2MemOpTable4;
4792   }
4793 
4794   // If table selected...
4795   if (OpcodeTablePtr) {
4796     // Find the Opcode to fuse
4797     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4798       OpcodeTablePtr->find(MI->getOpcode());
4799     if (I != OpcodeTablePtr->end()) {
4800       unsigned Opcode = I->second.first;
4801       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4802       if (Align < MinAlign)
4803         return nullptr;
4804       bool NarrowToMOV32rm = false;
4805       if (Size) {
4806         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
4807         if (Size < RCSize) {
4808           // Check if it's safe to fold the load. If the size of the object is
4809           // narrower than the load width, then it's not.
4810           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4811             return nullptr;
4812           // If this is a 64-bit load, but the spill slot is 32, then we can do
4813           // a 32-bit load which is implicitly zero-extended. This likely is
4814           // due to live interval analysis remat'ing a load from stack slot.
4815           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4816             return nullptr;
4817           Opcode = X86::MOV32rm;
4818           NarrowToMOV32rm = true;
4819         }
4820       }
4821 
4822       if (isTwoAddrFold)
4823         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4824       else
4825         NewMI = FuseInst(MF, Opcode, OpNum, MOs, MI, *this);
4826 
4827       if (NarrowToMOV32rm) {
4828         // If this is the special case where we use a MOV32rm to load a 32-bit
4829         // value and zero-extend the top bits. Change the destination register
4830         // to a 32-bit one.
4831         unsigned DstReg = NewMI->getOperand(0).getReg();
4832         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4833           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4834         else
4835           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4836       }
4837       return NewMI;
4838     }
4839   }
4840 
4841   // If the instruction and target operand are commutable, commute the
4842   // instruction and try again.
4843   if (AllowCommute) {
4844     unsigned OriginalOpIdx = OpNum, CommuteOpIdx1, CommuteOpIdx2;
4845     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4846       bool HasDef = MI->getDesc().getNumDefs();
4847       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4848       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4849       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4850       bool Tied0 =
4851           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4852       bool Tied1 =
4853           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4854 
4855       // If either of the commutable operands are tied to the destination
4856       // then we can not commute + fold.
4857       if ((HasDef && Reg0 == Reg1 && Tied0) ||
4858           (HasDef && Reg0 == Reg2 && Tied1))
4859         return nullptr;
4860 
4861       if ((CommuteOpIdx1 == OriginalOpIdx) ||
4862           (CommuteOpIdx2 == OriginalOpIdx)) {
4863         MachineInstr *CommutedMI = commuteInstruction(MI, false);
4864         if (!CommutedMI) {
4865           // Unable to commute.
4866           return nullptr;
4867         }
4868         if (CommutedMI != MI) {
4869           // New instruction. We can't fold from this.
4870           CommutedMI->eraseFromParent();
4871           return nullptr;
4872         }
4873 
4874         // Attempt to fold with the commuted version of the instruction.
4875         unsigned CommuteOp =
4876             (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4877         NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4878                                       /*AllowCommute=*/false);
4879         if (NewMI)
4880           return NewMI;
4881 
4882         // Folding failed again - undo the commute before returning.
4883         MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4884         if (!UncommutedMI) {
4885           // Unable to commute.
4886           return nullptr;
4887         }
4888         if (UncommutedMI != MI) {
4889           // New instruction. It doesn't need to be kept.
4890           UncommutedMI->eraseFromParent();
4891           return nullptr;
4892         }
4893 
4894         // Return here to prevent duplicate fuse failure report.
4895         return nullptr;
4896       }
4897     }
4898   }
4899 
4900   // No fusion
4901   if (PrintFailedFusing && !MI->isCopy())
4902     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
4903   return nullptr;
4904 }
4905 
4906 /// Return true for all instructions that only update
4907 /// the first 32 or 64-bits of the destination register and leave the rest
4908 /// unmodified. This can be used to avoid folding loads if the instructions
4909 /// only update part of the destination register, and the non-updated part is
4910 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4911 /// instructions breaks the partial register dependency and it can improve
4912 /// performance. e.g.:
4913 ///
4914 ///   movss (%rdi), %xmm0
4915 ///   cvtss2sd %xmm0, %xmm0
4916 ///
4917 /// Instead of
4918 ///   cvtss2sd (%rdi), %xmm0
4919 ///
4920 /// FIXME: This should be turned into a TSFlags.
4921 ///
4922 static bool hasPartialRegUpdate(unsigned Opcode) {
4923   switch (Opcode) {
4924   case X86::CVTSI2SSrr:
4925   case X86::CVTSI2SSrm:
4926   case X86::CVTSI2SS64rr:
4927   case X86::CVTSI2SS64rm:
4928   case X86::CVTSI2SDrr:
4929   case X86::CVTSI2SDrm:
4930   case X86::CVTSI2SD64rr:
4931   case X86::CVTSI2SD64rm:
4932   case X86::CVTSD2SSrr:
4933   case X86::CVTSD2SSrm:
4934   case X86::Int_CVTSD2SSrr:
4935   case X86::Int_CVTSD2SSrm:
4936   case X86::CVTSS2SDrr:
4937   case X86::CVTSS2SDrm:
4938   case X86::Int_CVTSS2SDrr:
4939   case X86::Int_CVTSS2SDrm:
4940   case X86::RCPSSr:
4941   case X86::RCPSSm:
4942   case X86::RCPSSr_Int:
4943   case X86::RCPSSm_Int:
4944   case X86::ROUNDSDr:
4945   case X86::ROUNDSDm:
4946   case X86::ROUNDSDr_Int:
4947   case X86::ROUNDSSr:
4948   case X86::ROUNDSSm:
4949   case X86::ROUNDSSr_Int:
4950   case X86::RSQRTSSr:
4951   case X86::RSQRTSSm:
4952   case X86::RSQRTSSr_Int:
4953   case X86::RSQRTSSm_Int:
4954   case X86::SQRTSSr:
4955   case X86::SQRTSSm:
4956   case X86::SQRTSSr_Int:
4957   case X86::SQRTSSm_Int:
4958   case X86::SQRTSDr:
4959   case X86::SQRTSDm:
4960   case X86::SQRTSDr_Int:
4961   case X86::SQRTSDm_Int:
4962     return true;
4963   }
4964 
4965   return false;
4966 }
4967 
4968 /// Inform the ExeDepsFix pass how many idle
4969 /// instructions we would like before a partial register update.
4970 unsigned X86InstrInfo::
4971 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4972                              const TargetRegisterInfo *TRI) const {
4973   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4974     return 0;
4975 
4976   // If MI is marked as reading Reg, the partial register update is wanted.
4977   const MachineOperand &MO = MI->getOperand(0);
4978   unsigned Reg = MO.getReg();
4979   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4980     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4981       return 0;
4982   } else {
4983     if (MI->readsRegister(Reg, TRI))
4984       return 0;
4985   }
4986 
4987   // If any of the preceding 16 instructions are reading Reg, insert a
4988   // dependency breaking instruction.  The magic number is based on a few
4989   // Nehalem experiments.
4990   return 16;
4991 }
4992 
4993 // Return true for any instruction the copies the high bits of the first source
4994 // operand into the unused high bits of the destination operand.
4995 static bool hasUndefRegUpdate(unsigned Opcode) {
4996   switch (Opcode) {
4997   case X86::VCVTSI2SSrr:
4998   case X86::VCVTSI2SSrm:
4999   case X86::Int_VCVTSI2SSrr:
5000   case X86::Int_VCVTSI2SSrm:
5001   case X86::VCVTSI2SS64rr:
5002   case X86::VCVTSI2SS64rm:
5003   case X86::Int_VCVTSI2SS64rr:
5004   case X86::Int_VCVTSI2SS64rm:
5005   case X86::VCVTSI2SDrr:
5006   case X86::VCVTSI2SDrm:
5007   case X86::Int_VCVTSI2SDrr:
5008   case X86::Int_VCVTSI2SDrm:
5009   case X86::VCVTSI2SD64rr:
5010   case X86::VCVTSI2SD64rm:
5011   case X86::Int_VCVTSI2SD64rr:
5012   case X86::Int_VCVTSI2SD64rm:
5013   case X86::VCVTSD2SSrr:
5014   case X86::VCVTSD2SSrm:
5015   case X86::Int_VCVTSD2SSrr:
5016   case X86::Int_VCVTSD2SSrm:
5017   case X86::VCVTSS2SDrr:
5018   case X86::VCVTSS2SDrm:
5019   case X86::Int_VCVTSS2SDrr:
5020   case X86::Int_VCVTSS2SDrm:
5021   case X86::VRCPSSr:
5022   case X86::VRCPSSm:
5023   case X86::VRCPSSm_Int:
5024   case X86::VROUNDSDr:
5025   case X86::VROUNDSDm:
5026   case X86::VROUNDSDr_Int:
5027   case X86::VROUNDSSr:
5028   case X86::VROUNDSSm:
5029   case X86::VROUNDSSr_Int:
5030   case X86::VRSQRTSSr:
5031   case X86::VRSQRTSSm:
5032   case X86::VRSQRTSSm_Int:
5033   case X86::VSQRTSSr:
5034   case X86::VSQRTSSm:
5035   case X86::VSQRTSSm_Int:
5036   case X86::VSQRTSDr:
5037   case X86::VSQRTSDm:
5038   case X86::VSQRTSDm_Int:
5039     // AVX-512
5040   case X86::VCVTSD2SSZrr:
5041   case X86::VCVTSD2SSZrm:
5042   case X86::VCVTSS2SDZrr:
5043   case X86::VCVTSS2SDZrm:
5044     return true;
5045   }
5046 
5047   return false;
5048 }
5049 
5050 /// Inform the ExeDepsFix pass how many idle instructions we would like before
5051 /// certain undef register reads.
5052 ///
5053 /// This catches the VCVTSI2SD family of instructions:
5054 ///
5055 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5056 ///
5057 /// We should to be careful *not* to catch VXOR idioms which are presumably
5058 /// handled specially in the pipeline:
5059 ///
5060 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5061 ///
5062 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5063 /// high bits that are passed-through are not live.
5064 unsigned X86InstrInfo::
5065 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5066                      const TargetRegisterInfo *TRI) const {
5067   if (!hasUndefRegUpdate(MI->getOpcode()))
5068     return 0;
5069 
5070   // Set the OpNum parameter to the first source operand.
5071   OpNum = 1;
5072 
5073   const MachineOperand &MO = MI->getOperand(OpNum);
5074   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5075     // Use the same magic number as getPartialRegUpdateClearance.
5076     return 16;
5077   }
5078   return 0;
5079 }
5080 
5081 void X86InstrInfo::
5082 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5083                           const TargetRegisterInfo *TRI) const {
5084   unsigned Reg = MI->getOperand(OpNum).getReg();
5085   // If MI kills this register, the false dependence is already broken.
5086   if (MI->killsRegister(Reg, TRI))
5087     return;
5088   if (X86::VR128RegClass.contains(Reg)) {
5089     // These instructions are all floating point domain, so xorps is the best
5090     // choice.
5091     bool HasAVX = Subtarget.hasAVX();
5092     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5093     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5094       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5095   } else if (X86::VR256RegClass.contains(Reg)) {
5096     // Use vxorps to clear the full ymm register.
5097     // It wants to read and write the xmm sub-register.
5098     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5099     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5100       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5101       .addReg(Reg, RegState::ImplicitDefine);
5102   } else
5103     return;
5104   MI->addRegisterKilled(Reg, TRI, true);
5105 }
5106 
5107 MachineInstr*
5108 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
5109                                     const SmallVectorImpl<unsigned> &Ops,
5110                                     int FrameIndex) const {
5111   // Check switch flag
5112   if (NoFusing) return nullptr;
5113 
5114   // Unless optimizing for size, don't fold to avoid partial
5115   // register update stalls
5116   if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
5117       hasPartialRegUpdate(MI->getOpcode()))
5118     return nullptr;
5119 
5120   const MachineFrameInfo *MFI = MF.getFrameInfo();
5121   unsigned Size = MFI->getObjectSize(FrameIndex);
5122   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
5123   // If the function stack isn't realigned we don't want to fold instructions
5124   // that need increased alignment.
5125   if (!RI.needsStackRealignment(MF))
5126     Alignment =
5127         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5128   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5129     unsigned NewOpc = 0;
5130     unsigned RCSize = 0;
5131     switch (MI->getOpcode()) {
5132     default: return nullptr;
5133     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5134     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5135     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5136     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5137     }
5138     // Check if it's safe to fold the load. If the size of the object is
5139     // narrower than the load width, then it's not.
5140     if (Size < RCSize)
5141       return nullptr;
5142     // Change to CMPXXri r, 0 first.
5143     MI->setDesc(get(NewOpc));
5144     MI->getOperand(1).ChangeToImmediate(0);
5145   } else if (Ops.size() != 1)
5146     return nullptr;
5147 
5148   SmallVector<MachineOperand,4> MOs;
5149   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
5150   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5151                                Size, Alignment, /*AllowCommute=*/true);
5152 }
5153 
5154 static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
5155                                   const MachineFunction &MF) {
5156   unsigned Opc = LoadMI.getOpcode();
5157   unsigned RegSize =
5158       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5159 
5160   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
5161     // These instructions only load 32 bits, we can't fold them if the
5162     // destination register is wider than 32 bits (4 bytes).
5163     return true;
5164 
5165   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
5166     // These instructions only load 64 bits, we can't fold them if the
5167     // destination register is wider than 64 bits (8 bytes).
5168     return true;
5169 
5170   return false;
5171 }
5172 
5173 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
5174                                                   MachineInstr *MI,
5175                                            const SmallVectorImpl<unsigned> &Ops,
5176                                                   MachineInstr *LoadMI) const {
5177   // If loading from a FrameIndex, fold directly from the FrameIndex.
5178   unsigned NumOps = LoadMI->getDesc().getNumOperands();
5179   int FrameIndex;
5180   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5181     if (isPartialRegisterLoad(*LoadMI, MF))
5182       return nullptr;
5183     return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
5184   }
5185 
5186   // Check switch flag
5187   if (NoFusing) return nullptr;
5188 
5189   // Unless optimizing for size, don't fold to avoid partial
5190   // register update stalls
5191   if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
5192       hasPartialRegUpdate(MI->getOpcode()))
5193     return nullptr;
5194 
5195   // Determine the alignment of the load.
5196   unsigned Alignment = 0;
5197   if (LoadMI->hasOneMemOperand())
5198     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
5199   else
5200     switch (LoadMI->getOpcode()) {
5201     case X86::AVX2_SETALLONES:
5202     case X86::AVX_SET0:
5203       Alignment = 32;
5204       break;
5205     case X86::V_SET0:
5206     case X86::V_SETALLONES:
5207       Alignment = 16;
5208       break;
5209     case X86::FsFLD0SD:
5210       Alignment = 8;
5211       break;
5212     case X86::FsFLD0SS:
5213       Alignment = 4;
5214       break;
5215     default:
5216       return nullptr;
5217     }
5218   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5219     unsigned NewOpc = 0;
5220     switch (MI->getOpcode()) {
5221     default: return nullptr;
5222     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
5223     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5224     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5225     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5226     }
5227     // Change to CMPXXri r, 0 first.
5228     MI->setDesc(get(NewOpc));
5229     MI->getOperand(1).ChangeToImmediate(0);
5230   } else if (Ops.size() != 1)
5231     return nullptr;
5232 
5233   // Make sure the subregisters match.
5234   // Otherwise we risk changing the size of the load.
5235   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
5236     return nullptr;
5237 
5238   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5239   switch (LoadMI->getOpcode()) {
5240   case X86::V_SET0:
5241   case X86::V_SETALLONES:
5242   case X86::AVX2_SETALLONES:
5243   case X86::AVX_SET0:
5244   case X86::FsFLD0SD:
5245   case X86::FsFLD0SS: {
5246     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5247     // Create a constant-pool entry and operands to load from it.
5248 
5249     // Medium and large mode can't fold loads this way.
5250     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5251         MF.getTarget().getCodeModel() != CodeModel::Kernel)
5252       return nullptr;
5253 
5254     // x86-32 PIC requires a PIC base register for constant pools.
5255     unsigned PICBase = 0;
5256     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5257       if (Subtarget.is64Bit())
5258         PICBase = X86::RIP;
5259       else
5260         // FIXME: PICBase = getGlobalBaseReg(&MF);
5261         // This doesn't work for several reasons.
5262         // 1. GlobalBaseReg may have been spilled.
5263         // 2. It may not be live at MI.
5264         return nullptr;
5265     }
5266 
5267     // Create a constant-pool entry.
5268     MachineConstantPool &MCP = *MF.getConstantPool();
5269     Type *Ty;
5270     unsigned Opc = LoadMI->getOpcode();
5271     if (Opc == X86::FsFLD0SS)
5272       Ty = Type::getFloatTy(MF.getFunction()->getContext());
5273     else if (Opc == X86::FsFLD0SD)
5274       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
5275     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
5276       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
5277     else
5278       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
5279 
5280     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
5281     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5282                                     Constant::getNullValue(Ty);
5283     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5284 
5285     // Create operands to load from the constant pool entry.
5286     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5287     MOs.push_back(MachineOperand::CreateImm(1));
5288     MOs.push_back(MachineOperand::CreateReg(0, false));
5289     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5290     MOs.push_back(MachineOperand::CreateReg(0, false));
5291     break;
5292   }
5293   default: {
5294     if (isPartialRegisterLoad(*LoadMI, MF))
5295       return nullptr;
5296 
5297     // Folding a normal load. Just copy the load's address operands.
5298     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
5299       MOs.push_back(LoadMI->getOperand(i));
5300     break;
5301   }
5302   }
5303   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5304                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
5305 }
5306 
5307 
5308 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
5309                                   const SmallVectorImpl<unsigned> &Ops) const {
5310   // Check switch flag
5311   if (NoFusing) return 0;
5312 
5313   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5314     switch (MI->getOpcode()) {
5315     default: return false;
5316     case X86::TEST8rr:
5317     case X86::TEST16rr:
5318     case X86::TEST32rr:
5319     case X86::TEST64rr:
5320       return true;
5321     case X86::ADD32ri:
5322       // FIXME: AsmPrinter doesn't know how to handle
5323       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5324       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5325         return false;
5326       break;
5327     }
5328   }
5329 
5330   if (Ops.size() != 1)
5331     return false;
5332 
5333   unsigned OpNum = Ops[0];
5334   unsigned Opc = MI->getOpcode();
5335   unsigned NumOps = MI->getDesc().getNumOperands();
5336   bool isTwoAddr = NumOps > 1 &&
5337     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5338 
5339   // Folding a memory location into the two-address part of a two-address
5340   // instruction is different than folding it other places.  It requires
5341   // replacing the *two* registers with the memory location.
5342   const DenseMap<unsigned,
5343                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
5344   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
5345     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5346   } else if (OpNum == 0) {
5347     if (Opc == X86::MOV32r0)
5348       return true;
5349 
5350     OpcodeTablePtr = &RegOp2MemOpTable0;
5351   } else if (OpNum == 1) {
5352     OpcodeTablePtr = &RegOp2MemOpTable1;
5353   } else if (OpNum == 2) {
5354     OpcodeTablePtr = &RegOp2MemOpTable2;
5355   } else if (OpNum == 3) {
5356     OpcodeTablePtr = &RegOp2MemOpTable3;
5357   }
5358 
5359   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5360     return true;
5361   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
5362 }
5363 
5364 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5365                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
5366                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
5367   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5368     MemOp2RegOpTable.find(MI->getOpcode());
5369   if (I == MemOp2RegOpTable.end())
5370     return false;
5371   unsigned Opc = I->second.first;
5372   unsigned Index = I->second.second & TB_INDEX_MASK;
5373   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5374   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5375   if (UnfoldLoad && !FoldedLoad)
5376     return false;
5377   UnfoldLoad &= FoldedLoad;
5378   if (UnfoldStore && !FoldedStore)
5379     return false;
5380   UnfoldStore &= FoldedStore;
5381 
5382   const MCInstrDesc &MCID = get(Opc);
5383   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5384   if (!MI->hasOneMemOperand() &&
5385       RC == &X86::VR128RegClass &&
5386       !Subtarget.isUnalignedMemAccessFast())
5387     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5388     // conservatively assume the address is unaligned. That's bad for
5389     // performance.
5390     return false;
5391   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5392   SmallVector<MachineOperand,2> BeforeOps;
5393   SmallVector<MachineOperand,2> AfterOps;
5394   SmallVector<MachineOperand,4> ImpOps;
5395   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5396     MachineOperand &Op = MI->getOperand(i);
5397     if (i >= Index && i < Index + X86::AddrNumOperands)
5398       AddrOps.push_back(Op);
5399     else if (Op.isReg() && Op.isImplicit())
5400       ImpOps.push_back(Op);
5401     else if (i < Index)
5402       BeforeOps.push_back(Op);
5403     else if (i > Index)
5404       AfterOps.push_back(Op);
5405   }
5406 
5407   // Emit the load instruction.
5408   if (UnfoldLoad) {
5409     std::pair<MachineInstr::mmo_iterator,
5410               MachineInstr::mmo_iterator> MMOs =
5411       MF.extractLoadMemRefs(MI->memoperands_begin(),
5412                             MI->memoperands_end());
5413     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5414     if (UnfoldStore) {
5415       // Address operands cannot be marked isKill.
5416       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5417         MachineOperand &MO = NewMIs[0]->getOperand(i);
5418         if (MO.isReg())
5419           MO.setIsKill(false);
5420       }
5421     }
5422   }
5423 
5424   // Emit the data processing instruction.
5425   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
5426   MachineInstrBuilder MIB(MF, DataMI);
5427 
5428   if (FoldedStore)
5429     MIB.addReg(Reg, RegState::Define);
5430   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
5431     MIB.addOperand(BeforeOps[i]);
5432   if (FoldedLoad)
5433     MIB.addReg(Reg);
5434   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
5435     MIB.addOperand(AfterOps[i]);
5436   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5437     MachineOperand &MO = ImpOps[i];
5438     MIB.addReg(MO.getReg(),
5439                getDefRegState(MO.isDef()) |
5440                RegState::Implicit |
5441                getKillRegState(MO.isKill()) |
5442                getDeadRegState(MO.isDead()) |
5443                getUndefRegState(MO.isUndef()));
5444   }
5445   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5446   switch (DataMI->getOpcode()) {
5447   default: break;
5448   case X86::CMP64ri32:
5449   case X86::CMP64ri8:
5450   case X86::CMP32ri:
5451   case X86::CMP32ri8:
5452   case X86::CMP16ri:
5453   case X86::CMP16ri8:
5454   case X86::CMP8ri: {
5455     MachineOperand &MO0 = DataMI->getOperand(0);
5456     MachineOperand &MO1 = DataMI->getOperand(1);
5457     if (MO1.getImm() == 0) {
5458       unsigned NewOpc;
5459       switch (DataMI->getOpcode()) {
5460       default: llvm_unreachable("Unreachable!");
5461       case X86::CMP64ri8:
5462       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5463       case X86::CMP32ri8:
5464       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
5465       case X86::CMP16ri8:
5466       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
5467       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
5468       }
5469       DataMI->setDesc(get(NewOpc));
5470       MO1.ChangeToRegister(MO0.getReg(), false);
5471     }
5472   }
5473   }
5474   NewMIs.push_back(DataMI);
5475 
5476   // Emit the store instruction.
5477   if (UnfoldStore) {
5478     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5479     std::pair<MachineInstr::mmo_iterator,
5480               MachineInstr::mmo_iterator> MMOs =
5481       MF.extractStoreMemRefs(MI->memoperands_begin(),
5482                              MI->memoperands_end());
5483     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5484   }
5485 
5486   return true;
5487 }
5488 
5489 bool
5490 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5491                                   SmallVectorImpl<SDNode*> &NewNodes) const {
5492   if (!N->isMachineOpcode())
5493     return false;
5494 
5495   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5496     MemOp2RegOpTable.find(N->getMachineOpcode());
5497   if (I == MemOp2RegOpTable.end())
5498     return false;
5499   unsigned Opc = I->second.first;
5500   unsigned Index = I->second.second & TB_INDEX_MASK;
5501   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5502   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5503   const MCInstrDesc &MCID = get(Opc);
5504   MachineFunction &MF = DAG.getMachineFunction();
5505   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5506   unsigned NumDefs = MCID.NumDefs;
5507   std::vector<SDValue> AddrOps;
5508   std::vector<SDValue> BeforeOps;
5509   std::vector<SDValue> AfterOps;
5510   SDLoc dl(N);
5511   unsigned NumOps = N->getNumOperands();
5512   for (unsigned i = 0; i != NumOps-1; ++i) {
5513     SDValue Op = N->getOperand(i);
5514     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5515       AddrOps.push_back(Op);
5516     else if (i < Index-NumDefs)
5517       BeforeOps.push_back(Op);
5518     else if (i > Index-NumDefs)
5519       AfterOps.push_back(Op);
5520   }
5521   SDValue Chain = N->getOperand(NumOps-1);
5522   AddrOps.push_back(Chain);
5523 
5524   // Emit the load instruction.
5525   SDNode *Load = nullptr;
5526   if (FoldedLoad) {
5527     EVT VT = *RC->vt_begin();
5528     std::pair<MachineInstr::mmo_iterator,
5529               MachineInstr::mmo_iterator> MMOs =
5530       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5531                             cast<MachineSDNode>(N)->memoperands_end());
5532     if (!(*MMOs.first) &&
5533         RC == &X86::VR128RegClass &&
5534         !Subtarget.isUnalignedMemAccessFast())
5535       // Do not introduce a slow unaligned load.
5536       return false;
5537     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5538     bool isAligned = (*MMOs.first) &&
5539                      (*MMOs.first)->getAlignment() >= Alignment;
5540     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5541                               VT, MVT::Other, AddrOps);
5542     NewNodes.push_back(Load);
5543 
5544     // Preserve memory reference information.
5545     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5546   }
5547 
5548   // Emit the data processing instruction.
5549   std::vector<EVT> VTs;
5550   const TargetRegisterClass *DstRC = nullptr;
5551   if (MCID.getNumDefs() > 0) {
5552     DstRC = getRegClass(MCID, 0, &RI, MF);
5553     VTs.push_back(*DstRC->vt_begin());
5554   }
5555   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5556     EVT VT = N->getValueType(i);
5557     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5558       VTs.push_back(VT);
5559   }
5560   if (Load)
5561     BeforeOps.push_back(SDValue(Load, 0));
5562   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
5563   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5564   NewNodes.push_back(NewNode);
5565 
5566   // Emit the store instruction.
5567   if (FoldedStore) {
5568     AddrOps.pop_back();
5569     AddrOps.push_back(SDValue(NewNode, 0));
5570     AddrOps.push_back(Chain);
5571     std::pair<MachineInstr::mmo_iterator,
5572               MachineInstr::mmo_iterator> MMOs =
5573       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5574                              cast<MachineSDNode>(N)->memoperands_end());
5575     if (!(*MMOs.first) &&
5576         RC == &X86::VR128RegClass &&
5577         !Subtarget.isUnalignedMemAccessFast())
5578       // Do not introduce a slow unaligned store.
5579       return false;
5580     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5581     bool isAligned = (*MMOs.first) &&
5582                      (*MMOs.first)->getAlignment() >= Alignment;
5583     SDNode *Store =
5584         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5585                            dl, MVT::Other, AddrOps);
5586     NewNodes.push_back(Store);
5587 
5588     // Preserve memory reference information.
5589     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
5590   }
5591 
5592   return true;
5593 }
5594 
5595 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5596                                       bool UnfoldLoad, bool UnfoldStore,
5597                                       unsigned *LoadRegIndex) const {
5598   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5599     MemOp2RegOpTable.find(Opc);
5600   if (I == MemOp2RegOpTable.end())
5601     return 0;
5602   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5603   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5604   if (UnfoldLoad && !FoldedLoad)
5605     return 0;
5606   if (UnfoldStore && !FoldedStore)
5607     return 0;
5608   if (LoadRegIndex)
5609     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5610   return I->second.first;
5611 }
5612 
5613 bool
5614 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5615                                      int64_t &Offset1, int64_t &Offset2) const {
5616   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5617     return false;
5618   unsigned Opc1 = Load1->getMachineOpcode();
5619   unsigned Opc2 = Load2->getMachineOpcode();
5620   switch (Opc1) {
5621   default: return false;
5622   case X86::MOV8rm:
5623   case X86::MOV16rm:
5624   case X86::MOV32rm:
5625   case X86::MOV64rm:
5626   case X86::LD_Fp32m:
5627   case X86::LD_Fp64m:
5628   case X86::LD_Fp80m:
5629   case X86::MOVSSrm:
5630   case X86::MOVSDrm:
5631   case X86::MMX_MOVD64rm:
5632   case X86::MMX_MOVQ64rm:
5633   case X86::FsMOVAPSrm:
5634   case X86::FsMOVAPDrm:
5635   case X86::MOVAPSrm:
5636   case X86::MOVUPSrm:
5637   case X86::MOVAPDrm:
5638   case X86::MOVDQArm:
5639   case X86::MOVDQUrm:
5640   // AVX load instructions
5641   case X86::VMOVSSrm:
5642   case X86::VMOVSDrm:
5643   case X86::FsVMOVAPSrm:
5644   case X86::FsVMOVAPDrm:
5645   case X86::VMOVAPSrm:
5646   case X86::VMOVUPSrm:
5647   case X86::VMOVAPDrm:
5648   case X86::VMOVDQArm:
5649   case X86::VMOVDQUrm:
5650   case X86::VMOVAPSYrm:
5651   case X86::VMOVUPSYrm:
5652   case X86::VMOVAPDYrm:
5653   case X86::VMOVDQAYrm:
5654   case X86::VMOVDQUYrm:
5655     break;
5656   }
5657   switch (Opc2) {
5658   default: return false;
5659   case X86::MOV8rm:
5660   case X86::MOV16rm:
5661   case X86::MOV32rm:
5662   case X86::MOV64rm:
5663   case X86::LD_Fp32m:
5664   case X86::LD_Fp64m:
5665   case X86::LD_Fp80m:
5666   case X86::MOVSSrm:
5667   case X86::MOVSDrm:
5668   case X86::MMX_MOVD64rm:
5669   case X86::MMX_MOVQ64rm:
5670   case X86::FsMOVAPSrm:
5671   case X86::FsMOVAPDrm:
5672   case X86::MOVAPSrm:
5673   case X86::MOVUPSrm:
5674   case X86::MOVAPDrm:
5675   case X86::MOVDQArm:
5676   case X86::MOVDQUrm:
5677   // AVX load instructions
5678   case X86::VMOVSSrm:
5679   case X86::VMOVSDrm:
5680   case X86::FsVMOVAPSrm:
5681   case X86::FsVMOVAPDrm:
5682   case X86::VMOVAPSrm:
5683   case X86::VMOVUPSrm:
5684   case X86::VMOVAPDrm:
5685   case X86::VMOVDQArm:
5686   case X86::VMOVDQUrm:
5687   case X86::VMOVAPSYrm:
5688   case X86::VMOVUPSYrm:
5689   case X86::VMOVAPDYrm:
5690   case X86::VMOVDQAYrm:
5691   case X86::VMOVDQUYrm:
5692     break;
5693   }
5694 
5695   // Check if chain operands and base addresses match.
5696   if (Load1->getOperand(0) != Load2->getOperand(0) ||
5697       Load1->getOperand(5) != Load2->getOperand(5))
5698     return false;
5699   // Segment operands should match as well.
5700   if (Load1->getOperand(4) != Load2->getOperand(4))
5701     return false;
5702   // Scale should be 1, Index should be Reg0.
5703   if (Load1->getOperand(1) == Load2->getOperand(1) &&
5704       Load1->getOperand(2) == Load2->getOperand(2)) {
5705     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5706       return false;
5707 
5708     // Now let's examine the displacements.
5709     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5710         isa<ConstantSDNode>(Load2->getOperand(3))) {
5711       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5712       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5713       return true;
5714     }
5715   }
5716   return false;
5717 }
5718 
5719 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5720                                            int64_t Offset1, int64_t Offset2,
5721                                            unsigned NumLoads) const {
5722   assert(Offset2 > Offset1);
5723   if ((Offset2 - Offset1) / 8 > 64)
5724     return false;
5725 
5726   unsigned Opc1 = Load1->getMachineOpcode();
5727   unsigned Opc2 = Load2->getMachineOpcode();
5728   if (Opc1 != Opc2)
5729     return false;  // FIXME: overly conservative?
5730 
5731   switch (Opc1) {
5732   default: break;
5733   case X86::LD_Fp32m:
5734   case X86::LD_Fp64m:
5735   case X86::LD_Fp80m:
5736   case X86::MMX_MOVD64rm:
5737   case X86::MMX_MOVQ64rm:
5738     return false;
5739   }
5740 
5741   EVT VT = Load1->getValueType(0);
5742   switch (VT.getSimpleVT().SimpleTy) {
5743   default:
5744     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5745     // have 16 of them to play with.
5746     if (Subtarget.is64Bit()) {
5747       if (NumLoads >= 3)
5748         return false;
5749     } else if (NumLoads) {
5750       return false;
5751     }
5752     break;
5753   case MVT::i8:
5754   case MVT::i16:
5755   case MVT::i32:
5756   case MVT::i64:
5757   case MVT::f32:
5758   case MVT::f64:
5759     if (NumLoads)
5760       return false;
5761     break;
5762   }
5763 
5764   return true;
5765 }
5766 
5767 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5768                                           MachineInstr *Second) const {
5769   // Check if this processor supports macro-fusion. Since this is a minor
5770   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5771   // proxy for SandyBridge+.
5772   if (!Subtarget.hasAVX())
5773     return false;
5774 
5775   enum {
5776     FuseTest,
5777     FuseCmp,
5778     FuseInc
5779   } FuseKind;
5780 
5781   switch(Second->getOpcode()) {
5782   default:
5783     return false;
5784   case X86::JE_1:
5785   case X86::JNE_1:
5786   case X86::JL_1:
5787   case X86::JLE_1:
5788   case X86::JG_1:
5789   case X86::JGE_1:
5790     FuseKind = FuseInc;
5791     break;
5792   case X86::JB_1:
5793   case X86::JBE_1:
5794   case X86::JA_1:
5795   case X86::JAE_1:
5796     FuseKind = FuseCmp;
5797     break;
5798   case X86::JS_1:
5799   case X86::JNS_1:
5800   case X86::JP_1:
5801   case X86::JNP_1:
5802   case X86::JO_1:
5803   case X86::JNO_1:
5804     FuseKind = FuseTest;
5805     break;
5806   }
5807   switch (First->getOpcode()) {
5808   default:
5809     return false;
5810   case X86::TEST8rr:
5811   case X86::TEST16rr:
5812   case X86::TEST32rr:
5813   case X86::TEST64rr:
5814   case X86::TEST8ri:
5815   case X86::TEST16ri:
5816   case X86::TEST32ri:
5817   case X86::TEST32i32:
5818   case X86::TEST64i32:
5819   case X86::TEST64ri32:
5820   case X86::TEST8rm:
5821   case X86::TEST16rm:
5822   case X86::TEST32rm:
5823   case X86::TEST64rm:
5824   case X86::TEST8ri_NOREX:
5825   case X86::AND16i16:
5826   case X86::AND16ri:
5827   case X86::AND16ri8:
5828   case X86::AND16rm:
5829   case X86::AND16rr:
5830   case X86::AND32i32:
5831   case X86::AND32ri:
5832   case X86::AND32ri8:
5833   case X86::AND32rm:
5834   case X86::AND32rr:
5835   case X86::AND64i32:
5836   case X86::AND64ri32:
5837   case X86::AND64ri8:
5838   case X86::AND64rm:
5839   case X86::AND64rr:
5840   case X86::AND8i8:
5841   case X86::AND8ri:
5842   case X86::AND8rm:
5843   case X86::AND8rr:
5844     return true;
5845   case X86::CMP16i16:
5846   case X86::CMP16ri:
5847   case X86::CMP16ri8:
5848   case X86::CMP16rm:
5849   case X86::CMP16rr:
5850   case X86::CMP32i32:
5851   case X86::CMP32ri:
5852   case X86::CMP32ri8:
5853   case X86::CMP32rm:
5854   case X86::CMP32rr:
5855   case X86::CMP64i32:
5856   case X86::CMP64ri32:
5857   case X86::CMP64ri8:
5858   case X86::CMP64rm:
5859   case X86::CMP64rr:
5860   case X86::CMP8i8:
5861   case X86::CMP8ri:
5862   case X86::CMP8rm:
5863   case X86::CMP8rr:
5864   case X86::ADD16i16:
5865   case X86::ADD16ri:
5866   case X86::ADD16ri8:
5867   case X86::ADD16ri8_DB:
5868   case X86::ADD16ri_DB:
5869   case X86::ADD16rm:
5870   case X86::ADD16rr:
5871   case X86::ADD16rr_DB:
5872   case X86::ADD32i32:
5873   case X86::ADD32ri:
5874   case X86::ADD32ri8:
5875   case X86::ADD32ri8_DB:
5876   case X86::ADD32ri_DB:
5877   case X86::ADD32rm:
5878   case X86::ADD32rr:
5879   case X86::ADD32rr_DB:
5880   case X86::ADD64i32:
5881   case X86::ADD64ri32:
5882   case X86::ADD64ri32_DB:
5883   case X86::ADD64ri8:
5884   case X86::ADD64ri8_DB:
5885   case X86::ADD64rm:
5886   case X86::ADD64rr:
5887   case X86::ADD64rr_DB:
5888   case X86::ADD8i8:
5889   case X86::ADD8mi:
5890   case X86::ADD8mr:
5891   case X86::ADD8ri:
5892   case X86::ADD8rm:
5893   case X86::ADD8rr:
5894   case X86::SUB16i16:
5895   case X86::SUB16ri:
5896   case X86::SUB16ri8:
5897   case X86::SUB16rm:
5898   case X86::SUB16rr:
5899   case X86::SUB32i32:
5900   case X86::SUB32ri:
5901   case X86::SUB32ri8:
5902   case X86::SUB32rm:
5903   case X86::SUB32rr:
5904   case X86::SUB64i32:
5905   case X86::SUB64ri32:
5906   case X86::SUB64ri8:
5907   case X86::SUB64rm:
5908   case X86::SUB64rr:
5909   case X86::SUB8i8:
5910   case X86::SUB8ri:
5911   case X86::SUB8rm:
5912   case X86::SUB8rr:
5913     return FuseKind == FuseCmp || FuseKind == FuseInc;
5914   case X86::INC16r:
5915   case X86::INC32r:
5916   case X86::INC64r:
5917   case X86::INC8r:
5918   case X86::DEC16r:
5919   case X86::DEC32r:
5920   case X86::DEC64r:
5921   case X86::DEC8r:
5922     return FuseKind == FuseInc;
5923   }
5924 }
5925 
5926 bool X86InstrInfo::
5927 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5928   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5929   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5930   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5931     return true;
5932   Cond[0].setImm(GetOppositeBranchCondition(CC));
5933   return false;
5934 }
5935 
5936 bool X86InstrInfo::
5937 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5938   // FIXME: Return false for x87 stack register classes for now. We can't
5939   // allow any loads of these registers before FpGet_ST0_80.
5940   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5941            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5942 }
5943 
5944 /// Return a virtual register initialized with the
5945 /// the global base register value. Output instructions required to
5946 /// initialize the register in the function entry block, if necessary.
5947 ///
5948 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5949 ///
5950 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5951   assert(!Subtarget.is64Bit() &&
5952          "X86-64 PIC uses RIP relative addressing");
5953 
5954   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5955   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5956   if (GlobalBaseReg != 0)
5957     return GlobalBaseReg;
5958 
5959   // Create the register. The code to initialize it is inserted
5960   // later, by the CGBR pass (below).
5961   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5962   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5963   X86FI->setGlobalBaseReg(GlobalBaseReg);
5964   return GlobalBaseReg;
5965 }
5966 
5967 // These are the replaceable SSE instructions. Some of these have Int variants
5968 // that we don't include here. We don't want to replace instructions selected
5969 // by intrinsics.
5970 static const uint16_t ReplaceableInstrs[][3] = {
5971   //PackedSingle     PackedDouble    PackedInt
5972   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5973   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5974   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5975   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5976   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5977   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5978   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5979   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5980   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5981   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5982   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5983   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5984   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5985   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5986   // AVX 128-bit support
5987   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5988   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5989   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5990   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5991   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5992   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5993   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5994   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5995   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5996   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5997   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5998   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5999   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6000   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6001   // AVX 256-bit support
6002   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6003   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6004   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6005   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6006   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6007   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
6008 };
6009 
6010 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6011   //PackedSingle       PackedDouble       PackedInt
6012   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6013   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6014   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6015   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6016   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6017   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6018   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6019   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6020   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6021   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6022   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6023   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6024   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6025   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6026   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6027   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6028   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6029   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6030   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6031   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6032 };
6033 
6034 // FIXME: Some shuffle and unpack instructions have equivalents in different
6035 // domains, but they require a bit more work than just switching opcodes.
6036 
6037 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
6038   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
6039     if (ReplaceableInstrs[i][domain-1] == opcode)
6040       return ReplaceableInstrs[i];
6041   return nullptr;
6042 }
6043 
6044 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
6045   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
6046     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
6047       return ReplaceableInstrsAVX2[i];
6048   return nullptr;
6049 }
6050 
6051 std::pair<uint16_t, uint16_t>
6052 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
6053   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6054   bool hasAVX2 = Subtarget.hasAVX2();
6055   uint16_t validDomains = 0;
6056   if (domain && lookup(MI->getOpcode(), domain))
6057     validDomains = 0xe;
6058   else if (domain && lookupAVX2(MI->getOpcode(), domain))
6059     validDomains = hasAVX2 ? 0xe : 0x6;
6060   return std::make_pair(domain, validDomains);
6061 }
6062 
6063 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
6064   assert(Domain>0 && Domain<4 && "Invalid execution domain");
6065   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6066   assert(dom && "Not an SSE instruction");
6067   const uint16_t *table = lookup(MI->getOpcode(), dom);
6068   if (!table) { // try the other table
6069     assert((Subtarget.hasAVX2() || Domain < 3) &&
6070            "256-bit vector operations only available in AVX2");
6071     table = lookupAVX2(MI->getOpcode(), dom);
6072   }
6073   assert(table && "Cannot change domain");
6074   MI->setDesc(get(table[Domain-1]));
6075 }
6076 
6077 /// Return the noop instruction to use for a noop.
6078 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6079   NopInst.setOpcode(X86::NOOP);
6080 }
6081 
6082 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6083 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6084 // on the encoding lengths of the instructions generated by
6085 // getUnconditionalBranch and getTrap.
6086 void X86InstrInfo::getUnconditionalBranch(
6087     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
6088   Branch.setOpcode(X86::JMP_1);
6089   Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
6090 }
6091 
6092 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6093 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6094 // on the encoding lengths of the instructions generated by
6095 // getUnconditionalBranch and getTrap.
6096 void X86InstrInfo::getTrap(MCInst &MI) const {
6097   MI.setOpcode(X86::TRAP);
6098 }
6099 
6100 // See getTrap and getUnconditionalBranch for conditions on the value returned
6101 // by this function.
6102 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6103   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6104   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6105   return 5;
6106 }
6107 
6108 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6109   switch (opc) {
6110   default: return false;
6111   case X86::DIVSDrm:
6112   case X86::DIVSDrm_Int:
6113   case X86::DIVSDrr:
6114   case X86::DIVSDrr_Int:
6115   case X86::DIVSSrm:
6116   case X86::DIVSSrm_Int:
6117   case X86::DIVSSrr:
6118   case X86::DIVSSrr_Int:
6119   case X86::SQRTPDm:
6120   case X86::SQRTPDr:
6121   case X86::SQRTPSm:
6122   case X86::SQRTPSr:
6123   case X86::SQRTSDm:
6124   case X86::SQRTSDm_Int:
6125   case X86::SQRTSDr:
6126   case X86::SQRTSDr_Int:
6127   case X86::SQRTSSm:
6128   case X86::SQRTSSm_Int:
6129   case X86::SQRTSSr:
6130   case X86::SQRTSSr_Int:
6131   // AVX instructions with high latency
6132   case X86::VDIVSDrm:
6133   case X86::VDIVSDrm_Int:
6134   case X86::VDIVSDrr:
6135   case X86::VDIVSDrr_Int:
6136   case X86::VDIVSSrm:
6137   case X86::VDIVSSrm_Int:
6138   case X86::VDIVSSrr:
6139   case X86::VDIVSSrr_Int:
6140   case X86::VSQRTPDm:
6141   case X86::VSQRTPDr:
6142   case X86::VSQRTPSm:
6143   case X86::VSQRTPSr:
6144   case X86::VSQRTSDm:
6145   case X86::VSQRTSDm_Int:
6146   case X86::VSQRTSDr:
6147   case X86::VSQRTSSm:
6148   case X86::VSQRTSSm_Int:
6149   case X86::VSQRTSSr:
6150   case X86::VSQRTPDZm:
6151   case X86::VSQRTPDZr:
6152   case X86::VSQRTPSZm:
6153   case X86::VSQRTPSZr:
6154   case X86::VSQRTSDZm:
6155   case X86::VSQRTSDZm_Int:
6156   case X86::VSQRTSDZr:
6157   case X86::VSQRTSSZm_Int:
6158   case X86::VSQRTSSZr:
6159   case X86::VSQRTSSZm:
6160   case X86::VDIVSDZrm:
6161   case X86::VDIVSDZrr:
6162   case X86::VDIVSSZrm:
6163   case X86::VDIVSSZrr:
6164 
6165   case X86::VGATHERQPSZrm:
6166   case X86::VGATHERQPDZrm:
6167   case X86::VGATHERDPDZrm:
6168   case X86::VGATHERDPSZrm:
6169   case X86::VPGATHERQDZrm:
6170   case X86::VPGATHERQQZrm:
6171   case X86::VPGATHERDDZrm:
6172   case X86::VPGATHERDQZrm:
6173   case X86::VSCATTERQPDZmr:
6174   case X86::VSCATTERQPSZmr:
6175   case X86::VSCATTERDPDZmr:
6176   case X86::VSCATTERDPSZmr:
6177   case X86::VPSCATTERQDZmr:
6178   case X86::VPSCATTERQQZmr:
6179   case X86::VPSCATTERDDZmr:
6180   case X86::VPSCATTERDQZmr:
6181     return true;
6182   }
6183 }
6184 
6185 bool X86InstrInfo::
6186 hasHighOperandLatency(const InstrItineraryData *ItinData,
6187                       const MachineRegisterInfo *MRI,
6188                       const MachineInstr *DefMI, unsigned DefIdx,
6189                       const MachineInstr *UseMI, unsigned UseIdx) const {
6190   return isHighLatencyDef(DefMI->getOpcode());
6191 }
6192 
6193 namespace {
6194   /// Create Global Base Reg pass. This initializes the PIC
6195   /// global base register for x86-32.
6196   struct CGBR : public MachineFunctionPass {
6197     static char ID;
6198     CGBR() : MachineFunctionPass(ID) {}
6199 
6200     bool runOnMachineFunction(MachineFunction &MF) override {
6201       const X86TargetMachine *TM =
6202         static_cast<const X86TargetMachine *>(&MF.getTarget());
6203       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
6204 
6205       // Don't do anything if this is 64-bit as 64-bit PIC
6206       // uses RIP relative addressing.
6207       if (STI.is64Bit())
6208         return false;
6209 
6210       // Only emit a global base reg in PIC mode.
6211       if (TM->getRelocationModel() != Reloc::PIC_)
6212         return false;
6213 
6214       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6215       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6216 
6217       // If we didn't need a GlobalBaseReg, don't insert code.
6218       if (GlobalBaseReg == 0)
6219         return false;
6220 
6221       // Insert the set of GlobalBaseReg into the first MBB of the function
6222       MachineBasicBlock &FirstMBB = MF.front();
6223       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6224       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6225       MachineRegisterInfo &RegInfo = MF.getRegInfo();
6226       const X86InstrInfo *TII = STI.getInstrInfo();
6227 
6228       unsigned PC;
6229       if (STI.isPICStyleGOT())
6230         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
6231       else
6232         PC = GlobalBaseReg;
6233 
6234       // Operand of MovePCtoStack is completely ignored by asm printer. It's
6235       // only used in JIT code emission as displacement to pc.
6236       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
6237 
6238       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6239       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
6240       if (STI.isPICStyleGOT()) {
6241         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6242         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6243           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6244                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
6245       }
6246 
6247       return true;
6248     }
6249 
6250     const char *getPassName() const override {
6251       return "X86 PIC Global Base Reg Initialization";
6252     }
6253 
6254     void getAnalysisUsage(AnalysisUsage &AU) const override {
6255       AU.setPreservesCFG();
6256       MachineFunctionPass::getAnalysisUsage(AU);
6257     }
6258   };
6259 }
6260 
6261 char CGBR::ID = 0;
6262 FunctionPass*
6263 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
6264 
6265 namespace {
6266   struct LDTLSCleanup : public MachineFunctionPass {
6267     static char ID;
6268     LDTLSCleanup() : MachineFunctionPass(ID) {}
6269 
6270     bool runOnMachineFunction(MachineFunction &MF) override {
6271       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6272       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6273         // No point folding accesses if there isn't at least two.
6274         return false;
6275       }
6276 
6277       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6278       return VisitNode(DT->getRootNode(), 0);
6279     }
6280 
6281     // Visit the dominator subtree rooted at Node in pre-order.
6282     // If TLSBaseAddrReg is non-null, then use that to replace any
6283     // TLS_base_addr instructions. Otherwise, create the register
6284     // when the first such instruction is seen, and then use it
6285     // as we encounter more instructions.
6286     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6287       MachineBasicBlock *BB = Node->getBlock();
6288       bool Changed = false;
6289 
6290       // Traverse the current block.
6291       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6292            ++I) {
6293         switch (I->getOpcode()) {
6294           case X86::TLS_base_addr32:
6295           case X86::TLS_base_addr64:
6296             if (TLSBaseAddrReg)
6297               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6298             else
6299               I = SetRegister(I, &TLSBaseAddrReg);
6300             Changed = true;
6301             break;
6302           default:
6303             break;
6304         }
6305       }
6306 
6307       // Visit the children of this block in the dominator tree.
6308       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6309            I != E; ++I) {
6310         Changed |= VisitNode(*I, TLSBaseAddrReg);
6311       }
6312 
6313       return Changed;
6314     }
6315 
6316     // Replace the TLS_base_addr instruction I with a copy from
6317     // TLSBaseAddrReg, returning the new instruction.
6318     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6319                                          unsigned TLSBaseAddrReg) {
6320       MachineFunction *MF = I->getParent()->getParent();
6321       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6322       const bool is64Bit = STI.is64Bit();
6323       const X86InstrInfo *TII = STI.getInstrInfo();
6324 
6325       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6326       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6327                                    TII->get(TargetOpcode::COPY),
6328                                    is64Bit ? X86::RAX : X86::EAX)
6329                                    .addReg(TLSBaseAddrReg);
6330 
6331       // Erase the TLS_base_addr instruction.
6332       I->eraseFromParent();
6333 
6334       return Copy;
6335     }
6336 
6337     // Create a virtal register in *TLSBaseAddrReg, and populate it by
6338     // inserting a copy instruction after I. Returns the new instruction.
6339     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6340       MachineFunction *MF = I->getParent()->getParent();
6341       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6342       const bool is64Bit = STI.is64Bit();
6343       const X86InstrInfo *TII = STI.getInstrInfo();
6344 
6345       // Create a virtual register for the TLS base address.
6346       MachineRegisterInfo &RegInfo = MF->getRegInfo();
6347       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6348                                                       ? &X86::GR64RegClass
6349                                                       : &X86::GR32RegClass);
6350 
6351       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6352       MachineInstr *Next = I->getNextNode();
6353       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6354                                    TII->get(TargetOpcode::COPY),
6355                                    *TLSBaseAddrReg)
6356                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
6357 
6358       return Copy;
6359     }
6360 
6361     const char *getPassName() const override {
6362       return "Local Dynamic TLS Access Clean-up";
6363     }
6364 
6365     void getAnalysisUsage(AnalysisUsage &AU) const override {
6366       AU.setPreservesCFG();
6367       AU.addRequired<MachineDominatorTree>();
6368       MachineFunctionPass::getAnalysisUsage(AU);
6369     }
6370   };
6371 }
6372 
6373 char LDTLSCleanup::ID = 0;
6374 FunctionPass*
6375 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
6376