1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(128), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16r1,     X86::SHL16m1,    0 },
232     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
233     { X86::SHL16ri,     X86::SHL16mi,    0 },
234     { X86::SHL32r1,     X86::SHL32m1,    0 },
235     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
236     { X86::SHL32ri,     X86::SHL32mi,    0 },
237     { X86::SHL64r1,     X86::SHL64m1,    0 },
238     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
239     { X86::SHL64ri,     X86::SHL64mi,    0 },
240     { X86::SHL8r1,      X86::SHL8m1,     0 },
241     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
242     { X86::SHL8ri,      X86::SHL8mi,     0 },
243     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
244     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
245     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
246     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
247     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
248     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
249     { X86::SHR16r1,     X86::SHR16m1,    0 },
250     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
251     { X86::SHR16ri,     X86::SHR16mi,    0 },
252     { X86::SHR32r1,     X86::SHR32m1,    0 },
253     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
254     { X86::SHR32ri,     X86::SHR32mi,    0 },
255     { X86::SHR64r1,     X86::SHR64m1,    0 },
256     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
257     { X86::SHR64ri,     X86::SHR64mi,    0 },
258     { X86::SHR8r1,      X86::SHR8m1,     0 },
259     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
260     { X86::SHR8ri,      X86::SHR8mi,     0 },
261     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
262     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
263     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
264     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
265     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
266     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
267     { X86::SUB16ri,     X86::SUB16mi,    0 },
268     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
269     { X86::SUB16rr,     X86::SUB16mr,    0 },
270     { X86::SUB32ri,     X86::SUB32mi,    0 },
271     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
272     { X86::SUB32rr,     X86::SUB32mr,    0 },
273     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
274     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
275     { X86::SUB64rr,     X86::SUB64mr,    0 },
276     { X86::SUB8ri,      X86::SUB8mi,     0 },
277     { X86::SUB8rr,      X86::SUB8mr,     0 },
278     { X86::XOR16ri,     X86::XOR16mi,    0 },
279     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
280     { X86::XOR16rr,     X86::XOR16mr,    0 },
281     { X86::XOR32ri,     X86::XOR32mi,    0 },
282     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
283     { X86::XOR32rr,     X86::XOR32mr,    0 },
284     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
285     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
286     { X86::XOR64rr,     X86::XOR64mr,    0 },
287     { X86::XOR8ri,      X86::XOR8mi,     0 },
288     { X86::XOR8rr,      X86::XOR8mr,     0 }
289   };
290 
291   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
292     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
293                   Entry.RegOp, Entry.MemOp,
294                   // Index 0, folded load and store, no alignment requirement.
295                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
296   }
297 
298   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
299     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
300     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
301     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
302     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
303     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
304     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
305     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
306     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
307     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
308     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
309     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
310     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
311     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
312     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
313     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
314     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
315     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
316     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
317     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
318     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
319     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
320     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
321     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
322     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
323     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
324     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
325     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
326     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
327     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
328     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
329     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
330     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
331     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
332     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
333     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
334     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
335     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
336     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
337     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
338     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
339     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
340     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
341     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
342     { X86::MOVDQUrr,    X86::MOVDQUmr,      TB_FOLDED_STORE },
343     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
344     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
345     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
346     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
347     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
348     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
349     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
350     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
351     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
352     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
353     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
354     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
355     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
356     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
357     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
358     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
359     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
360     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
361     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
362     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
363     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
364     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
365     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
366     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
367     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
368     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
369     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
370     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
371     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
372     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
373     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
374     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
375     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
376     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
377     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
378     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
379     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
380     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
381 
382     // AVX 128-bit versions of foldable instructions
383     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
384     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
385     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
386     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
387     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
388     { X86::VMOVDQUrr,   X86::VMOVDQUmr,     TB_FOLDED_STORE },
389     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
390     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
391     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
392     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
393     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
394     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
395     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
396     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
397 
398     // AVX 256-bit foldable instructions
399     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
400     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
401     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVDQUYrr,  X86::VMOVDQUYmr,    TB_FOLDED_STORE },
404     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
405     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
406 
407     // AVX-512 foldable instructions
408     { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
409     { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
410     { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
411     { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
412     { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
413     { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
414     { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
415     { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
416     { X86::VEXTRACTPSZrr,   X86::VEXTRACTPSZmr,    TB_FOLDED_STORE },
417     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
418     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
419     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
420     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
421     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
422     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
424     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
425     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
426     { X86::VMOVPQIto64Zrr,  X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },
427     { X86::VMOVSDto64Zrr,   X86::VMOVSDto64Zmr, TB_FOLDED_STORE },
428     { X86::VMOVSS2DIZrr,    X86::VMOVSS2DIZmr,  TB_FOLDED_STORE },
429     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
430     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
431     { X86::VPEXTRDZrr,      X86::VPEXTRDZmr,    TB_FOLDED_STORE },
432     { X86::VPEXTRQZrr,      X86::VPEXTRQZmr,    TB_FOLDED_STORE },
433     { X86::VPMOVDBZrr,      X86::VPMOVDBZmr,    TB_FOLDED_STORE },
434     { X86::VPMOVDWZrr,      X86::VPMOVDWZmr,    TB_FOLDED_STORE },
435     { X86::VPMOVQDZrr,      X86::VPMOVQDZmr,    TB_FOLDED_STORE },
436     { X86::VPMOVQWZrr,      X86::VPMOVQWZmr,    TB_FOLDED_STORE },
437     { X86::VPMOVWBZrr,      X86::VPMOVWBZmr,    TB_FOLDED_STORE },
438     { X86::VPMOVSDBZrr,     X86::VPMOVSDBZmr,   TB_FOLDED_STORE },
439     { X86::VPMOVSDWZrr,     X86::VPMOVSDWZmr,   TB_FOLDED_STORE },
440     { X86::VPMOVSQDZrr,     X86::VPMOVSQDZmr,   TB_FOLDED_STORE },
441     { X86::VPMOVSQWZrr,     X86::VPMOVSQWZmr,   TB_FOLDED_STORE },
442     { X86::VPMOVSWBZrr,     X86::VPMOVSWBZmr,   TB_FOLDED_STORE },
443     { X86::VPMOVUSDBZrr,    X86::VPMOVUSDBZmr,  TB_FOLDED_STORE },
444     { X86::VPMOVUSDWZrr,    X86::VPMOVUSDWZmr,  TB_FOLDED_STORE },
445     { X86::VPMOVUSQDZrr,    X86::VPMOVUSQDZmr,  TB_FOLDED_STORE },
446     { X86::VPMOVUSQWZrr,    X86::VPMOVUSQWZmr,  TB_FOLDED_STORE },
447     { X86::VPMOVUSWBZrr,    X86::VPMOVUSWBZmr,  TB_FOLDED_STORE },
448 
449     // AVX-512 foldable instructions (256-bit versions)
450     { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
451     { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
452     { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
453     { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
454     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
455     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
456     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
457     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
458     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
459     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
460     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
461     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
462     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
463     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
464     { X86::VPMOVDWZ256rr,      X86::VPMOVDWZ256mr,    TB_FOLDED_STORE },
465     { X86::VPMOVQDZ256rr,      X86::VPMOVQDZ256mr,    TB_FOLDED_STORE },
466     { X86::VPMOVWBZ256rr,      X86::VPMOVWBZ256mr,    TB_FOLDED_STORE },
467     { X86::VPMOVSDWZ256rr,     X86::VPMOVSDWZ256mr,   TB_FOLDED_STORE },
468     { X86::VPMOVSQDZ256rr,     X86::VPMOVSQDZ256mr,   TB_FOLDED_STORE },
469     { X86::VPMOVSWBZ256rr,     X86::VPMOVSWBZ256mr,   TB_FOLDED_STORE },
470     { X86::VPMOVUSDWZ256rr,    X86::VPMOVUSDWZ256mr,  TB_FOLDED_STORE },
471     { X86::VPMOVUSQDZ256rr,    X86::VPMOVUSQDZ256mr,  TB_FOLDED_STORE },
472     { X86::VPMOVUSWBZ256rr,    X86::VPMOVUSWBZ256mr,  TB_FOLDED_STORE },
473 
474     // AVX-512 foldable instructions (128-bit versions)
475     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
476     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
477     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
478     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
479     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
480     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
481     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
482     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
483     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
484     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
485 
486     // F16C foldable instructions
487     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
488     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
489   };
490 
491   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
492     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
493                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
494   }
495 
496   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
497     { X86::BSF16rr,         X86::BSF16rm,             0 },
498     { X86::BSF32rr,         X86::BSF32rm,             0 },
499     { X86::BSF64rr,         X86::BSF64rm,             0 },
500     { X86::BSR16rr,         X86::BSR16rm,             0 },
501     { X86::BSR32rr,         X86::BSR32rm,             0 },
502     { X86::BSR64rr,         X86::BSR64rm,             0 },
503     { X86::CMP16rr,         X86::CMP16rm,             0 },
504     { X86::CMP32rr,         X86::CMP32rm,             0 },
505     { X86::CMP64rr,         X86::CMP64rm,             0 },
506     { X86::CMP8rr,          X86::CMP8rm,              0 },
507     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
508     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
509     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
510     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
511     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
512     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
513     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
514     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
515     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
516     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
517     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
518     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
519     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
520     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
521     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
522     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
523     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        TB_NO_REVERSE },
524     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        TB_NO_REVERSE },
525     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        TB_NO_REVERSE },
526     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          TB_NO_REVERSE },
527     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        TB_NO_REVERSE },
528     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          TB_NO_REVERSE },
529     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_NO_REVERSE },
530     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
531     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
532     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
533     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
534     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_NO_REVERSE },
535     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
536     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
537     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  TB_NO_REVERSE },
538     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     TB_NO_REVERSE },
539     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  TB_NO_REVERSE },
540     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     TB_NO_REVERSE },
541     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       TB_NO_REVERSE },
542     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       TB_NO_REVERSE },
543     { X86::MOV16rr,         X86::MOV16rm,             0 },
544     { X86::MOV32rr,         X86::MOV32rm,             0 },
545     { X86::MOV64rr,         X86::MOV64rm,             0 },
546     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
547     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
548     { X86::MOV8rr,          X86::MOV8rm,              0 },
549     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
550     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
551     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           TB_NO_REVERSE },
552     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
553     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
554     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
555     { X86::MOVDQUrr,        X86::MOVDQUrm,            0 },
556     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
557     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
558     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
559     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
560     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
561     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
562     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
563     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
564     { X86::MOVUPDrr,        X86::MOVUPDrm,            0 },
565     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
566     { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm,         TB_NO_REVERSE },
567     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
568     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
569     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
570     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
571     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
572     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
573     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
574     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
575     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
576     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
577     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
578     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
579     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_NO_REVERSE },
580     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_NO_REVERSE },
581     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_NO_REVERSE },
582     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_NO_REVERSE },
583     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_NO_REVERSE },
584     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_NO_REVERSE },
585     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_NO_REVERSE },
586     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_NO_REVERSE },
587     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_NO_REVERSE },
588     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_NO_REVERSE },
589     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_NO_REVERSE },
590     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_NO_REVERSE },
591     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
592     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
593     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
594     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
595     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
596     { X86::RCPSSr,          X86::RCPSSm,              0 },
597     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          TB_NO_REVERSE },
598     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
599     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
600     { X86::ROUNDSDr,        X86::ROUNDSDm,            0 },
601     { X86::ROUNDSSr,        X86::ROUNDSSm,            0 },
602     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
603     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
604     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        TB_NO_REVERSE },
605     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
606     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
607     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
608     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         TB_NO_REVERSE },
609     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
610     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         TB_NO_REVERSE },
611     { X86::TEST16rr,        X86::TEST16rm,            0 },
612     { X86::TEST32rr,        X86::TEST32rm,            0 },
613     { X86::TEST64rr,        X86::TEST64rm,            0 },
614     { X86::TEST8rr,         X86::TEST8rm,             0 },
615     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
616     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
617     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
618 
619     // MMX version of foldable instructions
620     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
621     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
622     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
623     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
624     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
625     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
626     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
627     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
628     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
629     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
630 
631     // 3DNow! version of foldable instructions
632     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
633     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
634     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
635     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
636     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
637     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
638     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
639 
640     // AVX 128-bit versions of foldable instructions
641     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       TB_NO_REVERSE },
642     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       TB_NO_REVERSE },
643     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      TB_NO_REVERSE },
644     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      TB_NO_REVERSE },
645     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
646     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,TB_NO_REVERSE },
647     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
648     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    TB_NO_REVERSE },
649     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
650     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,TB_NO_REVERSE },
651     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
652     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    TB_NO_REVERSE },
653     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       TB_NO_REVERSE },
654     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         TB_NO_REVERSE },
655     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       TB_NO_REVERSE },
656     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         TB_NO_REVERSE },
657     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         TB_NO_REVERSE },
658     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
659     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQrm,         0 },
660     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSrm,         0 },
661     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
662     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         TB_NO_REVERSE },
663     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQrm,        0 },
664     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
665     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
666     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
667     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
668     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
669     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          TB_NO_REVERSE },
670     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
671     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
672     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
673     { X86::VMOVDQUrr,       X86::VMOVDQUrm,           0 },
674     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
675     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
676     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
677     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
678     { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm,        TB_NO_REVERSE },
679     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
680     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
681     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
682     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
683     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
684     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
685     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
686     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
687     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
688     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
689     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         TB_NO_REVERSE },
690     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         TB_NO_REVERSE },
691     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         TB_NO_REVERSE },
692     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         TB_NO_REVERSE },
693     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         TB_NO_REVERSE },
694     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         TB_NO_REVERSE },
695     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         TB_NO_REVERSE },
696     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         TB_NO_REVERSE },
697     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         TB_NO_REVERSE },
698     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         TB_NO_REVERSE },
699     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         TB_NO_REVERSE },
700     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         TB_NO_REVERSE },
701     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
702     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
703     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
704     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
705     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
706     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
707     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
708     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
709     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
710     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
711     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
712     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
713     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
714     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
715 
716     // AVX 256-bit foldable instructions
717     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        TB_NO_REVERSE },
718     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
719     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
720     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
721     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
722     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        TB_NO_REVERSE },
723     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
724     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
725     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
726     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
727     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
728     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
729     { X86::VMOVDQUYrr,      X86::VMOVDQUYrm,          0 },
730     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
731     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
732     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
733     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
734     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
735     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
736     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
737     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
738     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
739     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
740     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
741     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
742     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
743     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
744     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
745 
746     // AVX2 foldable instructions
747 
748     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
749     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
750     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
751     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
752     // so they don't need an equivalent limitation.
753     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
754     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
755     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
756     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
757     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
758     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
759     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      TB_NO_REVERSE },
760     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     TB_NO_REVERSE },
761     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      TB_NO_REVERSE },
762     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     TB_NO_REVERSE },
763     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      TB_NO_REVERSE },
764     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     TB_NO_REVERSE },
765     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      TB_NO_REVERSE },
766     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     TB_NO_REVERSE },
767     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
768     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
769     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        TB_NO_REVERSE },
770     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        TB_NO_REVERSE },
771     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
772     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
773     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
774     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        TB_NO_REVERSE },
775     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        TB_NO_REVERSE },
776     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        TB_NO_REVERSE },
777     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
778     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
779     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
780     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        TB_NO_REVERSE },
781     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
782     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
783     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
784 
785     // XOP foldable instructions
786     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
787     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
788     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
789     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
790     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
791     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
792     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
793     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
794     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
795     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
796     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
797     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
798     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
799     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
800     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
801     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
802     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
803     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
804     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
805     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
806     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
807     { X86::VPROTBri,           X86::VPROTBmi,         0 },
808     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
809     { X86::VPROTDri,           X86::VPROTDmi,         0 },
810     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
811     { X86::VPROTQri,           X86::VPROTQmi,         0 },
812     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
813     { X86::VPROTWri,           X86::VPROTWmi,         0 },
814     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
815     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
816     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
817     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
818     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
819     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
820     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
821     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
822     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
823 
824     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
825     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
826     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
827     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
828     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
829     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
830     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
831     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
832     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
833     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
834     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
835     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
836     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
837     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
838     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
839     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
840     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
841     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
842     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
843     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
844     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
845     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
846     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
847     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
848     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
849     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
850     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
851     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
852     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
853     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
854     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
855     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
856     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
857     { X86::RORX32ri,        X86::RORX32mi,            0 },
858     { X86::RORX64ri,        X86::RORX64mi,            0 },
859     { X86::SARX32rr,        X86::SARX32rm,            0 },
860     { X86::SARX64rr,        X86::SARX64rm,            0 },
861     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
862     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
863     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
864     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
865     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
866     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
867     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
868     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
869     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
870     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
871     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
872 
873     // AVX-512 foldable instructions
874     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
875     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
876     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
877     { X86::VMOV64toSDZrr,    X86::VMOV64toSDZrm,      0 },
878     { X86::VMOVDI2PDIZrr,    X86::VMOVDI2PDIZrm,      0 },
879     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
880     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
881     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
882     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
883     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
884     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
885     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
886     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
887     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
888     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
889     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
890     { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm,      TB_NO_REVERSE },
891     { X86::VPABSBZrr,        X86::VPABSBZrm,          0 },
892     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
893     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
894     { X86::VPABSWZrr,        X86::VPABSWZrm,          0 },
895     { X86::VPERMILPDZri,     X86::VPERMILPDZmi,       0 },
896     { X86::VPERMILPSZri,     X86::VPERMILPSZmi,       0 },
897     { X86::VPERMPDZri,       X86::VPERMPDZmi,         0 },
898     { X86::VPERMQZri,        X86::VPERMQZmi,          0 },
899     { X86::VPMOVSXBDZrr,     X86::VPMOVSXBDZrm,       0 },
900     { X86::VPMOVSXBQZrr,     X86::VPMOVSXBQZrm,       TB_NO_REVERSE },
901     { X86::VPMOVSXBWZrr,     X86::VPMOVSXBWZrm,       0 },
902     { X86::VPMOVSXDQZrr,     X86::VPMOVSXDQZrm,       0 },
903     { X86::VPMOVSXWDZrr,     X86::VPMOVSXWDZrm,       0 },
904     { X86::VPMOVSXWQZrr,     X86::VPMOVSXWQZrm,       0 },
905     { X86::VPMOVZXBDZrr,     X86::VPMOVZXBDZrm,       0 },
906     { X86::VPMOVZXBQZrr,     X86::VPMOVZXBQZrm,       TB_NO_REVERSE },
907     { X86::VPMOVZXBWZrr,     X86::VPMOVZXBWZrm,       0 },
908     { X86::VPMOVZXDQZrr,     X86::VPMOVZXDQZrm,       0 },
909     { X86::VPMOVZXWDZrr,     X86::VPMOVZXWDZrm,       0 },
910     { X86::VPMOVZXWQZrr,     X86::VPMOVZXWQZrm,       0 },
911     { X86::VPSHUFDZri,       X86::VPSHUFDZmi,         0 },
912     { X86::VPSHUFHWZri,      X86::VPSHUFHWZmi,        0 },
913     { X86::VPSHUFLWZri,      X86::VPSHUFLWZmi,        0 },
914     { X86::VPSLLDQZ512rr,    X86::VPSLLDQZ512rm,      0 },
915     { X86::VPSLLDZri,        X86::VPSLLDZmi,          0 },
916     { X86::VPSLLQZri,        X86::VPSLLQZmi,          0 },
917     { X86::VPSLLWZri,        X86::VPSLLWZmi,          0 },
918     { X86::VPSRADZri,        X86::VPSRADZmi,          0 },
919     { X86::VPSRAQZri,        X86::VPSRAQZmi,          0 },
920     { X86::VPSRAWZri,        X86::VPSRAWZmi,          0 },
921     { X86::VPSRLDQZ512rr,    X86::VPSRLDQZ512rm,      0 },
922     { X86::VPSRLDZri,        X86::VPSRLDZmi,          0 },
923     { X86::VPSRLQZri,        X86::VPSRLQZmi,          0 },
924     { X86::VPSRLWZri,        X86::VPSRLWZmi,          0 },
925 
926     // AVX-512 foldable instructions (256-bit versions)
927     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
928     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
929     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
930     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
931     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
932     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
933     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
934     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
935     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
936     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
937     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
938     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
939     { X86::VPABSBZ256rr,         X86::VPABSBZ256rm,         0 },
940     { X86::VPABSDZ256rr,         X86::VPABSDZ256rm,         0 },
941     { X86::VPABSQZ256rr,         X86::VPABSQZ256rm,         0 },
942     { X86::VPABSWZ256rr,         X86::VPABSWZ256rm,         0 },
943     { X86::VPERMILPDZ256ri,      X86::VPERMILPDZ256mi,      0 },
944     { X86::VPERMILPSZ256ri,      X86::VPERMILPSZ256mi,      0 },
945     { X86::VPERMPDZ256ri,        X86::VPERMPDZ256mi,        0 },
946     { X86::VPERMQZ256ri,         X86::VPERMQZ256mi,         0 },
947     { X86::VPMOVSXBDZ256rr,      X86::VPMOVSXBDZ256rm,      TB_NO_REVERSE },
948     { X86::VPMOVSXBQZ256rr,      X86::VPMOVSXBQZ256rm,      TB_NO_REVERSE },
949     { X86::VPMOVSXBWZ256rr,      X86::VPMOVSXBWZ256rm,      0 },
950     { X86::VPMOVSXDQZ256rr,      X86::VPMOVSXDQZ256rm,      0 },
951     { X86::VPMOVSXWDZ256rr,      X86::VPMOVSXWDZ256rm,      0 },
952     { X86::VPMOVSXWQZ256rr,      X86::VPMOVSXWQZ256rm,      TB_NO_REVERSE },
953     { X86::VPMOVZXBDZ256rr,      X86::VPMOVZXBDZ256rm,      TB_NO_REVERSE },
954     { X86::VPMOVZXBQZ256rr,      X86::VPMOVZXBQZ256rm,      TB_NO_REVERSE },
955     { X86::VPMOVZXBWZ256rr,      X86::VPMOVZXBWZ256rm,      0 },
956     { X86::VPMOVZXDQZ256rr,      X86::VPMOVZXDQZ256rm,      0 },
957     { X86::VPMOVZXWDZ256rr,      X86::VPMOVZXWDZ256rm,      0 },
958     { X86::VPMOVZXWQZ256rr,      X86::VPMOVZXWQZ256rm,      TB_NO_REVERSE },
959     { X86::VPSHUFDZ256ri,        X86::VPSHUFDZ256mi,        0 },
960     { X86::VPSHUFHWZ256ri,       X86::VPSHUFHWZ256mi,       0 },
961     { X86::VPSHUFLWZ256ri,       X86::VPSHUFLWZ256mi,       0 },
962     { X86::VPSLLDQZ256rr,        X86::VPSLLDQZ256rm,        0 },
963     { X86::VPSLLDZ256ri,         X86::VPSLLDZ256mi,         0 },
964     { X86::VPSLLQZ256ri,         X86::VPSLLQZ256mi,         0 },
965     { X86::VPSLLWZ256ri,         X86::VPSLLWZ256mi,         0 },
966     { X86::VPSRADZ256ri,         X86::VPSRADZ256mi,         0 },
967     { X86::VPSRAQZ256ri,         X86::VPSRAQZ256mi,         0 },
968     { X86::VPSRAWZ256ri,         X86::VPSRAWZ256mi,         0 },
969     { X86::VPSRLDQZ256rr,        X86::VPSRLDQZ256rm,        0 },
970     { X86::VPSRLDZ256ri,         X86::VPSRLDZ256mi,         0 },
971     { X86::VPSRLQZ256ri,         X86::VPSRLQZ256mi,         0 },
972     { X86::VPSRLWZ256ri,         X86::VPSRLWZ256mi,         0 },
973 
974     // AVX-512 foldable instructions (128-bit versions)
975     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
976     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
977     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
978     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
979     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
980     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
981     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
982     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
983     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
984     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
985     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
986     { X86::VPABSBZ128rr,         X86::VPABSBZ128rm,         0 },
987     { X86::VPABSDZ128rr,         X86::VPABSDZ128rm,         0 },
988     { X86::VPABSQZ128rr,         X86::VPABSQZ128rm,         0 },
989     { X86::VPABSWZ128rr,         X86::VPABSWZ128rm,         0 },
990     { X86::VPERMILPDZ128ri,      X86::VPERMILPDZ128mi,      0 },
991     { X86::VPERMILPSZ128ri,      X86::VPERMILPSZ128mi,      0 },
992     { X86::VPMOVSXBDZ128rr,      X86::VPMOVSXBDZ128rm,      TB_NO_REVERSE },
993     { X86::VPMOVSXBQZ128rr,      X86::VPMOVSXBQZ128rm,      TB_NO_REVERSE },
994     { X86::VPMOVSXBWZ128rr,      X86::VPMOVSXBWZ128rm,      TB_NO_REVERSE },
995     { X86::VPMOVSXDQZ128rr,      X86::VPMOVSXDQZ128rm,      TB_NO_REVERSE },
996     { X86::VPMOVSXWDZ128rr,      X86::VPMOVSXWDZ128rm,      TB_NO_REVERSE },
997     { X86::VPMOVSXWQZ128rr,      X86::VPMOVSXWQZ128rm,      TB_NO_REVERSE },
998     { X86::VPMOVZXBDZ128rr,      X86::VPMOVZXBDZ128rm,      TB_NO_REVERSE },
999     { X86::VPMOVZXBQZ128rr,      X86::VPMOVZXBQZ128rm,      TB_NO_REVERSE },
1000     { X86::VPMOVZXBWZ128rr,      X86::VPMOVZXBWZ128rm,      TB_NO_REVERSE },
1001     { X86::VPMOVZXDQZ128rr,      X86::VPMOVZXDQZ128rm,      TB_NO_REVERSE },
1002     { X86::VPMOVZXWDZ128rr,      X86::VPMOVZXWDZ128rm,      TB_NO_REVERSE },
1003     { X86::VPMOVZXWQZ128rr,      X86::VPMOVZXWQZ128rm,      TB_NO_REVERSE },
1004     { X86::VPSHUFDZ128ri,        X86::VPSHUFDZ128mi,        0 },
1005     { X86::VPSHUFHWZ128ri,       X86::VPSHUFHWZ128mi,       0 },
1006     { X86::VPSHUFLWZ128ri,       X86::VPSHUFLWZ128mi,       0 },
1007     { X86::VPSLLDQZ128rr,        X86::VPSLLDQZ128rm,        0 },
1008     { X86::VPSLLDZ128ri,         X86::VPSLLDZ128mi,         0 },
1009     { X86::VPSLLQZ128ri,         X86::VPSLLQZ128mi,         0 },
1010     { X86::VPSLLWZ128ri,         X86::VPSLLWZ128mi,         0 },
1011     { X86::VPSRADZ128ri,         X86::VPSRADZ128mi,         0 },
1012     { X86::VPSRAQZ128ri,         X86::VPSRAQZ128mi,         0 },
1013     { X86::VPSRAWZ128ri,         X86::VPSRAWZ128mi,         0 },
1014     { X86::VPSRLDQZ128rr,        X86::VPSRLDQZ128rm,        0 },
1015     { X86::VPSRLDZ128ri,         X86::VPSRLDZ128mi,         0 },
1016     { X86::VPSRLQZ128ri,         X86::VPSRLQZ128mi,         0 },
1017     { X86::VPSRLWZ128ri,         X86::VPSRLWZ128mi,         0 },
1018 
1019     // F16C foldable instructions
1020     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
1021     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
1022 
1023     // AES foldable instructions
1024     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
1025     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
1026     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
1027     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
1028   };
1029 
1030   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
1031     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
1032                   Entry.RegOp, Entry.MemOp,
1033                   // Index 1, folded load
1034                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
1035   }
1036 
1037   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
1038     { X86::ADC32rr,         X86::ADC32rm,       0 },
1039     { X86::ADC64rr,         X86::ADC64rm,       0 },
1040     { X86::ADD16rr,         X86::ADD16rm,       0 },
1041     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
1042     { X86::ADD32rr,         X86::ADD32rm,       0 },
1043     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
1044     { X86::ADD64rr,         X86::ADD64rm,       0 },
1045     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
1046     { X86::ADD8rr,          X86::ADD8rm,        0 },
1047     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
1048     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
1049     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
1050     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   TB_NO_REVERSE },
1051     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
1052     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   TB_NO_REVERSE },
1053     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
1054     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
1055     { X86::AND16rr,         X86::AND16rm,       0 },
1056     { X86::AND32rr,         X86::AND32rm,       0 },
1057     { X86::AND64rr,         X86::AND64rm,       0 },
1058     { X86::AND8rr,          X86::AND8rm,        0 },
1059     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
1060     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
1061     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
1062     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
1063     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
1064     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
1065     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
1066     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
1067     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
1068     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
1069     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
1070     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
1071     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
1072     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
1073     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
1074     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
1075     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
1076     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
1077     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
1078     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
1079     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
1080     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
1081     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
1082     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
1083     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
1084     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
1085     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
1086     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
1087     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
1088     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
1089     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
1090     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
1091     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
1092     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
1093     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
1094     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
1095     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
1096     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
1097     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
1098     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
1099     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
1100     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
1101     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
1102     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
1103     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
1104     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
1105     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
1106     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
1107     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
1108     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
1109     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
1110     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
1111     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
1112     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
1113     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
1114     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
1115     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
1116     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
1117     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
1118     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
1119     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
1120     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
1121     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
1122     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
1123     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
1124     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   TB_NO_REVERSE },
1125     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
1126     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   TB_NO_REVERSE },
1127     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
1128     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
1129     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
1130     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
1131     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
1132     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
1133     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
1134     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
1135     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
1136     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   TB_NO_REVERSE },
1137     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   TB_NO_REVERSE },
1138     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      TB_NO_REVERSE },
1139     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1140     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1141     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1142     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1143     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      TB_NO_REVERSE },
1144     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1145     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
1146     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1147     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
1148     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1149     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
1150     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   TB_NO_REVERSE },
1151     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1152     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1153     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   TB_NO_REVERSE },
1154     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1155     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1156     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1157     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1158     { X86::MINSDrr,         X86::MINSDrm,       0 },
1159     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1160     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   TB_NO_REVERSE },
1161     { X86::MINSSrr,         X86::MINSSrm,       0 },
1162     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1163     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   TB_NO_REVERSE },
1164     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1165     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1166     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1167     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1168     { X86::MULSDrr,         X86::MULSDrm,       0 },
1169     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   TB_NO_REVERSE },
1170     { X86::MULSSrr,         X86::MULSSrm,       0 },
1171     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   TB_NO_REVERSE },
1172     { X86::OR16rr,          X86::OR16rm,        0 },
1173     { X86::OR32rr,          X86::OR32rm,        0 },
1174     { X86::OR64rr,          X86::OR64rm,        0 },
1175     { X86::OR8rr,           X86::OR8rm,         0 },
1176     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1177     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1178     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1179     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1180     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1181     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1182     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1183     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1184     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1185     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1186     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1187     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1188     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1189     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1190     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1191     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1192     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1193     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1194     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1195     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1196     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1197     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1198     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1199     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1200     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1201     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1202     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1203     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1204     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1205     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1206     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1207     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1208     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1209     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1210     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1211     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1212     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1213     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1214     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1215     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1216     { X86::PMADDUBSWrr,     X86::PMADDUBSWrm,   TB_ALIGN_16 },
1217     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1218     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1219     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1220     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1221     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1222     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1223     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1224     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1225     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1226     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1227     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1228     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1229     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1230     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1231     { X86::PMULHRSWrr,      X86::PMULHRSWrm,    TB_ALIGN_16 },
1232     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1233     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1234     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1235     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1236     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1237     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1238     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1239     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1240     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1241     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1242     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1243     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1244     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1245     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1246     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1247     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1248     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1249     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1250     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1251     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1252     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1253     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1254     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1255     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1256     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1257     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1258     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1259     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1260     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1261     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1262     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1263     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1264     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1265     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1266     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1267     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1268     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  TB_NO_REVERSE },
1269     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  TB_NO_REVERSE },
1270     { X86::SBB32rr,         X86::SBB32rm,       0 },
1271     { X86::SBB64rr,         X86::SBB64rm,       0 },
1272     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1273     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1274     { X86::SUB16rr,         X86::SUB16rm,       0 },
1275     { X86::SUB32rr,         X86::SUB32rm,       0 },
1276     { X86::SUB64rr,         X86::SUB64rm,       0 },
1277     { X86::SUB8rr,          X86::SUB8rm,        0 },
1278     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1279     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1280     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1281     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   TB_NO_REVERSE },
1282     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1283     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   TB_NO_REVERSE },
1284     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1285     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1286     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1287     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1288     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1289     { X86::XOR16rr,         X86::XOR16rm,       0 },
1290     { X86::XOR32rr,         X86::XOR32rm,       0 },
1291     { X86::XOR64rr,         X86::XOR64rm,       0 },
1292     { X86::XOR8rr,          X86::XOR8rm,        0 },
1293     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1294     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1295 
1296     // MMX version of foldable instructions
1297     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1298     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1299     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1300     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1301     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1302     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1303     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1304     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1305     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1306     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1307     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1308     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1309     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1310     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1311     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1312     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1313     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1314     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1315     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1316     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1317     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1318     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1319     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1320     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1321     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1322     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1323     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1324     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1325     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1326     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1327     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1328     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1329     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1330     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1331     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1332     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1333     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1334     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1335     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1336     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1337     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1338     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1339     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1340     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1341     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1342     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1343     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1344     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1345     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1346     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1347     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1348     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1349     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1350     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1351     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1352     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1353     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1354     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1355     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1356     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1357     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1358     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1359     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1360     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1361     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1362     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1363     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1364     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1365     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1366     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1367 
1368     // 3DNow! version of foldable instructions
1369     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1370     { X86::PFACCrr,           X86::PFACCrm,           0 },
1371     { X86::PFADDrr,           X86::PFADDrm,           0 },
1372     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1373     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1374     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1375     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1376     { X86::PFMINrr,           X86::PFMINrm,           0 },
1377     { X86::PFMULrr,           X86::PFMULrm,           0 },
1378     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1379     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1380     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1381     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1382     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1383     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1384     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1385     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1386 
1387     // AVX 128-bit versions of foldable instructions
1388     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1389     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1390     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1391     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1392     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1393     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1394     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1395     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1396     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1397     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1398     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1399     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       TB_NO_REVERSE },
1400     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1401     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       TB_NO_REVERSE },
1402     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1403     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1404     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1405     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1406     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1407     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1408     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1409     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1410     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1411     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1412     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1413     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1414     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1415     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1416     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1417     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1418     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1419     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       TB_NO_REVERSE },
1420     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1421     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       TB_NO_REVERSE },
1422     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1423     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1424     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1425     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1426     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1427     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1428     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       TB_NO_REVERSE },
1429     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       TB_NO_REVERSE },
1430     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1431     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1432     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1433     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1434     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1435     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1436     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1437     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       TB_NO_REVERSE },
1438     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1439     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       TB_NO_REVERSE },
1440     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1441     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1442     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1443     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1444     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1445     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1446     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1447     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       TB_NO_REVERSE },
1448     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1449     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       TB_NO_REVERSE },
1450     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1451     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1452     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1453     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1454     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1455     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       TB_NO_REVERSE },
1456     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1457     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       TB_NO_REVERSE },
1458     { X86::VORPDrr,           X86::VORPDrm,            0 },
1459     { X86::VORPSrr,           X86::VORPSrm,            0 },
1460     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1461     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1462     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1463     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1464     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1465     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1466     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1467     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1468     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1469     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1470     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1471     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1472     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1473     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1474     { X86::VPANDrr,           X86::VPANDrm,            0 },
1475     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1476     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1477     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1478     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1479     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1480     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1481     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1482     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1483     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1484     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1485     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1486     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1487     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1488     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1489     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1490     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1491     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1492     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1493     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1494     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1495     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1496     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1497     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1498     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1499     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1500     { X86::VPMADDUBSWrr,      X86::VPMADDUBSWrm,       0 },
1501     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1502     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1503     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1504     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1505     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1506     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1507     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1508     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1509     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1510     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1511     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1512     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1513     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1514     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1515     { X86::VPMULHRSWrr,       X86::VPMULHRSWrm,        0 },
1516     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1517     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1518     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1519     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1520     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1521     { X86::VPORrr,            X86::VPORrm,             0 },
1522     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1523     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1524     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1525     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1526     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1527     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1528     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1529     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1530     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1531     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1532     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1533     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1534     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1535     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1536     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1537     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1538     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1539     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1540     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1541     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1542     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1543     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1544     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1545     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1546     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1547     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1548     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1549     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1550     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1551     { X86::VPXORrr,           X86::VPXORrm,            0 },
1552     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1553     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        TB_NO_REVERSE },
1554     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1555     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      TB_NO_REVERSE },
1556     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1557     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      TB_NO_REVERSE },
1558     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1559     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      TB_NO_REVERSE },
1560     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1561     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1562     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1563     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       TB_NO_REVERSE },
1564     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1565     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       TB_NO_REVERSE },
1566     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1567     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1568     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1569     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       TB_NO_REVERSE },
1570     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1571     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       TB_NO_REVERSE },
1572     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1573     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1574     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1575     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1576     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1577     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1578 
1579     // AVX 256-bit foldable instructions
1580     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1581     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1582     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1583     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1584     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1585     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1586     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1587     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1588     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1589     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1590     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1591     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1592     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1593     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1594     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1595     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1596     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1597     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1598     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1599     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1600     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1601     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1602     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1603     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1604     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1605     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1606     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1607     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1608     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1609     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1610     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1611     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1612     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1613     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1614     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1615     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1616     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1617     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1618     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1619     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1620     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1621     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1622     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1623     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1624     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1625     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1626     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1627 
1628     // AVX2 foldable instructions
1629     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1630     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1631     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1632     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1633     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1634     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1635     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1636     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1637     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1638     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1639     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1640     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1641     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1642     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1643     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1644     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1645     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1646     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1647     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1648     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1649     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1650     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1651     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1652     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1653     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1654     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1655     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1656     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1657     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1658     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1659     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1660     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1661     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1662     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1663     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1664     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1665     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1666     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1667     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1668     { X86::VPMADDUBSWYrr,     X86::VPMADDUBSWYrm,      0 },
1669     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1670     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1671     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1672     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1673     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1674     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1675     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1676     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1677     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1678     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1679     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1680     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1681     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1682     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1683     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1684     { X86::VPMULHRSWYrr,      X86::VPMULHRSWYrm,       0 },
1685     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1686     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1687     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1688     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1689     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1690     { X86::VPORYrr,           X86::VPORYrm,            0 },
1691     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1692     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1693     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1694     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1695     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1696     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1697     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1698     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1699     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1700     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1701     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1702     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1703     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1704     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1705     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1706     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1707     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1708     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1709     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1710     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1711     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1712     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1713     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1714     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1715     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1716     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1717     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1718     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1719     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1720     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1721     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1722     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1723     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1724     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1725     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1726     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1727     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1728     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1729     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1730     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1731 
1732     // FMA4 foldable patterns
1733     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1734     { X86::VFMADDSS4rr_Int,   X86::VFMADDSS4mr_Int,    TB_NO_REVERSE },
1735     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1736     { X86::VFMADDSD4rr_Int,   X86::VFMADDSD4mr_Int,    TB_NO_REVERSE },
1737     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1738     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1739     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1740     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1741     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1742     { X86::VFNMADDSS4rr_Int,  X86::VFNMADDSS4mr_Int,   TB_NO_REVERSE },
1743     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1744     { X86::VFNMADDSD4rr_Int,  X86::VFNMADDSD4mr_Int,   TB_NO_REVERSE },
1745     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1746     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1747     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1748     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1749     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1750     { X86::VFMSUBSS4rr_Int,   X86::VFMSUBSS4mr_Int,    TB_NO_REVERSE },
1751     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1752     { X86::VFMSUBSD4rr_Int,   X86::VFMSUBSD4mr_Int,    TB_NO_REVERSE },
1753     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1754     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1755     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1756     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1757     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1758     { X86::VFNMSUBSS4rr_Int,  X86::VFNMSUBSS4mr_Int,   TB_NO_REVERSE },
1759     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1760     { X86::VFNMSUBSD4rr_Int,  X86::VFNMSUBSD4mr_Int,   TB_NO_REVERSE },
1761     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1762     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1763     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1764     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1765     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1766     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1767     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1768     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1769     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1770     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1771     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1772     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1773 
1774     // XOP foldable instructions
1775     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1776     { X86::VPCMOVYrrr,        X86::VPCMOVYrmr,          0 },
1777     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1778     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1779     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1780     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1781     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1782     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1783     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1784     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1785     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1786     { X86::VPERMIL2PDYrr,     X86::VPERMIL2PDYmr,       0 },
1787     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1788     { X86::VPERMIL2PSYrr,     X86::VPERMIL2PSYmr,       0 },
1789     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1790     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1791     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1792     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1793     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1794     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1795     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1796     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1797     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1798     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1799     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1800     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1801     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1802     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1803     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1804     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1805     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1806     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1807     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1808     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1809     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1810     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1811     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1812     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1813     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1814 
1815     // BMI/BMI2 foldable instructions
1816     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1817     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1818     { X86::MULX32rr,          X86::MULX32rm,            0 },
1819     { X86::MULX64rr,          X86::MULX64rm,            0 },
1820     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1821     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1822     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1823     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1824 
1825     // ADX foldable instructions
1826     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1827     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1828     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1829     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1830 
1831     // AVX-512 foldable instructions
1832     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1833     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1834     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1835     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       TB_NO_REVERSE },
1836     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1837     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       TB_NO_REVERSE },
1838     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1839     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1840     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1841     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1842     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1843     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1844     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1845     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1846     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1847     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       TB_NO_REVERSE },
1848     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1849     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       TB_NO_REVERSE },
1850     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1851     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1852     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1853     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       TB_NO_REVERSE },
1854     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1855     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       TB_NO_REVERSE },
1856     { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrm,     0 },
1857     { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrm,     0 },
1858     { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrm,     0 },
1859     { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrm,     0 },
1860     { X86::VINSERTI32x4Zrr,   X86::VINSERTI32x4Zrm,     0 },
1861     { X86::VINSERTI32x8Zrr,   X86::VINSERTI32x8Zrm,     0 },
1862     { X86::VINSERTI64x2Zrr,   X86::VINSERTI64x2Zrm,     0 },
1863     { X86::VINSERTI64x4Zrr,   X86::VINSERTI64x4Zrm,     0 },
1864     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1865     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1866     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1867     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1868     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1869     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1870     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1871     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       TB_NO_REVERSE },
1872     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1873     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       TB_NO_REVERSE },
1874     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1875     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1876     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1877     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1878     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1879     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1880     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1881     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       TB_NO_REVERSE },
1882     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1883     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       TB_NO_REVERSE },
1884     { X86::VMOVLHPSZrr,       X86::VMOVHPSZ128rm,       TB_NO_REVERSE },
1885     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1886     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1887     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1888     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       TB_NO_REVERSE },
1889     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1890     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       TB_NO_REVERSE },
1891     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1892     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
1893     { X86::VPACKSSDWZrr,      X86::VPACKSSDWZrm,        0 },
1894     { X86::VPACKSSWBZrr,      X86::VPACKSSWBZrm,        0 },
1895     { X86::VPACKUSDWZrr,      X86::VPACKUSDWZrm,        0 },
1896     { X86::VPACKUSWBZrr,      X86::VPACKUSWBZrm,        0 },
1897     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
1898     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1899     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1900     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
1901     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
1902     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
1903     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
1904     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
1905     { X86::VPALIGNRZrri,      X86::VPALIGNRZrmi,        0 },
1906     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
1907     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
1908     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
1909     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
1910     { X86::VPAVGBZrr,         X86::VPAVGBZrm,           0 },
1911     { X86::VPAVGWZrr,         X86::VPAVGWZrm,           0 },
1912     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
1913     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
1914     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
1915     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
1916     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
1917     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
1918     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
1919     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
1920     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
1921     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
1922     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
1923     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
1924     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
1925     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
1926     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
1927     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
1928     { X86::VPERMBZrr,         X86::VPERMBZrm,           0 },
1929     { X86::VPERMDZrr,         X86::VPERMDZrm,           0 },
1930     { X86::VPERMILPDZrr,      X86::VPERMILPDZrm,        0 },
1931     { X86::VPERMILPSZrr,      X86::VPERMILPSZrm,        0 },
1932     { X86::VPERMPDZrr,        X86::VPERMPDZrm,          0 },
1933     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1934     { X86::VPERMQZrr,         X86::VPERMQZrm,           0 },
1935     { X86::VPERMWZrr,         X86::VPERMWZrm,           0 },
1936     { X86::VPINSRBZrr,        X86::VPINSRBZrm,          0 },
1937     { X86::VPINSRDZrr,        X86::VPINSRDZrm,          0 },
1938     { X86::VPINSRQZrr,        X86::VPINSRQZrm,          0 },
1939     { X86::VPINSRWZrr,        X86::VPINSRWZrm,          0 },
1940     { X86::VPMADDUBSWZrr,     X86::VPMADDUBSWZrm,       0 },
1941     { X86::VPMADDWDZrr,       X86::VPMADDWDZrm,         0 },
1942     { X86::VPMAXSBZrr,        X86::VPMAXSBZrm,          0 },
1943     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1944     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1945     { X86::VPMAXSWZrr,        X86::VPMAXSWZrm,          0 },
1946     { X86::VPMAXUBZrr,        X86::VPMAXUBZrm,          0 },
1947     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1948     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1949     { X86::VPMAXUWZrr,        X86::VPMAXUWZrm,          0 },
1950     { X86::VPMINSBZrr,        X86::VPMINSBZrm,          0 },
1951     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1952     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1953     { X86::VPMINSWZrr,        X86::VPMINSWZrm,          0 },
1954     { X86::VPMINUBZrr,        X86::VPMINUBZrm,          0 },
1955     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1956     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1957     { X86::VPMINUWZrr,        X86::VPMINUWZrm,          0 },
1958     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1959     { X86::VPMULLDZrr,        X86::VPMULLDZrm,          0 },
1960     { X86::VPMULLQZrr,        X86::VPMULLQZrm,          0 },
1961     { X86::VPMULLWZrr,        X86::VPMULLWZrm,          0 },
1962     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1963     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
1964     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
1965     { X86::VPSADBWZ512rr,     X86::VPSADBWZ512rm,       0 },
1966     { X86::VPSHUFBZrr,        X86::VPSHUFBZrm,          0 },
1967     { X86::VPSLLDZrr,         X86::VPSLLDZrm,           0 },
1968     { X86::VPSLLQZrr,         X86::VPSLLQZrm,           0 },
1969     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1970     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1971     { X86::VPSLLVWZrr,        X86::VPSLLVWZrm,          0 },
1972     { X86::VPSLLWZrr,         X86::VPSLLWZrm,           0 },
1973     { X86::VPSRADZrr,         X86::VPSRADZrm,           0 },
1974     { X86::VPSRAQZrr,         X86::VPSRAQZrm,           0 },
1975     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1976     { X86::VPSRAVQZrr,        X86::VPSRAVQZrm,          0 },
1977     { X86::VPSRAVWZrr,        X86::VPSRAVWZrm,          0 },
1978     { X86::VPSRAWZrr,         X86::VPSRAWZrm,           0 },
1979     { X86::VPSRLDZrr,         X86::VPSRLDZrm,           0 },
1980     { X86::VPSRLQZrr,         X86::VPSRLQZrm,           0 },
1981     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1982     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1983     { X86::VPSRLVWZrr,        X86::VPSRLVWZrm,          0 },
1984     { X86::VPSRLWZrr,         X86::VPSRLWZrm,           0 },
1985     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
1986     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1987     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1988     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
1989     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
1990     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
1991     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
1992     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
1993     { X86::VPUNPCKHBWZrr,     X86::VPUNPCKHBWZrm,       0 },
1994     { X86::VPUNPCKHDQZrr,     X86::VPUNPCKHDQZrm,       0 },
1995     { X86::VPUNPCKHQDQZrr,    X86::VPUNPCKHQDQZrm,      0 },
1996     { X86::VPUNPCKHWDZrr,     X86::VPUNPCKHWDZrm,       0 },
1997     { X86::VPUNPCKLBWZrr,     X86::VPUNPCKLBWZrm,       0 },
1998     { X86::VPUNPCKLDQZrr,     X86::VPUNPCKLDQZrm,       0 },
1999     { X86::VPUNPCKLQDQZrr,    X86::VPUNPCKLQDQZrm,      0 },
2000     { X86::VPUNPCKLWDZrr,     X86::VPUNPCKLWDZrm,       0 },
2001     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
2002     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
2003     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
2004     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
2005     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
2006     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
2007     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
2008     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       TB_NO_REVERSE },
2009     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
2010     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       TB_NO_REVERSE },
2011     { X86::VUNPCKHPDZrr,      X86::VUNPCKHPDZrm,        0 },
2012     { X86::VUNPCKHPSZrr,      X86::VUNPCKHPSZrm,        0 },
2013     { X86::VUNPCKLPDZrr,      X86::VUNPCKLPDZrm,        0 },
2014     { X86::VUNPCKLPSZrr,      X86::VUNPCKLPSZrm,        0 },
2015     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
2016     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
2017 
2018     // AVX-512{F,VL} foldable instructions
2019     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
2020     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
2021     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
2022     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
2023     { X86::VALIGNDZ128rri,    X86::VALIGNDZ128rmi,      0 },
2024     { X86::VALIGNDZ256rri,    X86::VALIGNDZ256rmi,      0 },
2025     { X86::VALIGNQZ128rri,    X86::VALIGNQZ128rmi,      0 },
2026     { X86::VALIGNQZ256rri,    X86::VALIGNQZ256rmi,      0 },
2027     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
2028     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
2029     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
2030     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
2031     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
2032     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
2033     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
2034     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
2035     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
2036     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
2037     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
2038     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
2039     { X86::VDIVPDZ128rr,      X86::VDIVPDZ128rm,        0 },
2040     { X86::VDIVPDZ256rr,      X86::VDIVPDZ256rm,        0 },
2041     { X86::VDIVPSZ128rr,      X86::VDIVPSZ128rm,        0 },
2042     { X86::VDIVPSZ256rr,      X86::VDIVPSZ256rm,        0 },
2043     { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm,  0 },
2044     { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm,  0 },
2045     { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm,  0 },
2046     { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm,  0 },
2047     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
2048     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
2049     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
2050     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
2051     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
2052     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
2053     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
2054     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
2055     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
2056     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
2057     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
2058     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
2059     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
2060     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
2061     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
2062     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
2063     { X86::VMULPDZ128rr,      X86::VMULPDZ128rm,        0 },
2064     { X86::VMULPDZ256rr,      X86::VMULPDZ256rm,        0 },
2065     { X86::VMULPSZ128rr,      X86::VMULPSZ128rm,        0 },
2066     { X86::VMULPSZ256rr,      X86::VMULPSZ256rm,        0 },
2067     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
2068     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
2069     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
2070     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
2071     { X86::VPACKSSDWZ256rr,   X86::VPACKSSDWZ256rm,     0 },
2072     { X86::VPACKSSDWZ128rr,   X86::VPACKSSDWZ128rm,     0 },
2073     { X86::VPACKSSWBZ256rr,   X86::VPACKSSWBZ256rm,     0 },
2074     { X86::VPACKSSWBZ128rr,   X86::VPACKSSWBZ128rm,     0 },
2075     { X86::VPACKUSDWZ256rr,   X86::VPACKUSDWZ256rm,     0 },
2076     { X86::VPACKUSDWZ128rr,   X86::VPACKUSDWZ128rm,     0 },
2077     { X86::VPACKUSWBZ256rr,   X86::VPACKUSWBZ256rm,     0 },
2078     { X86::VPACKUSWBZ128rr,   X86::VPACKUSWBZ128rm,     0 },
2079     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
2080     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
2081     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
2082     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
2083     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
2084     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
2085     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
2086     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
2087     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
2088     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
2089     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
2090     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
2091     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
2092     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
2093     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
2094     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
2095     { X86::VPALIGNRZ128rri,   X86::VPALIGNRZ128rmi,     0 },
2096     { X86::VPALIGNRZ256rri,   X86::VPALIGNRZ256rmi,     0 },
2097     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
2098     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
2099     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
2100     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
2101     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
2102     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
2103     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
2104     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
2105     { X86::VPAVGBZ128rr,      X86::VPAVGBZ128rm,        0 },
2106     { X86::VPAVGBZ256rr,      X86::VPAVGBZ256rm,        0 },
2107     { X86::VPAVGWZ128rr,      X86::VPAVGWZ128rm,        0 },
2108     { X86::VPAVGWZ256rr,      X86::VPAVGWZ256rm,        0 },
2109     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
2110     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
2111     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
2112     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
2113     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
2114     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
2115     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
2116     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
2117     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
2118     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
2119     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
2120     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
2121     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
2122     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
2123     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
2124     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
2125     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
2126     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
2127     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
2128     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
2129     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
2130     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
2131     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
2132     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
2133     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
2134     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
2135     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
2136     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
2137     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
2138     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
2139     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
2140     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
2141     { X86::VPERMBZ128rr,      X86::VPERMBZ128rm,        0 },
2142     { X86::VPERMBZ256rr,      X86::VPERMBZ256rm,        0 },
2143     { X86::VPERMDZ256rr,      X86::VPERMDZ256rm,        0 },
2144     { X86::VPERMILPDZ128rr,   X86::VPERMILPDZ128rm,     0 },
2145     { X86::VPERMILPDZ256rr,   X86::VPERMILPDZ256rm,     0 },
2146     { X86::VPERMILPSZ128rr,   X86::VPERMILPSZ128rm,     0 },
2147     { X86::VPERMILPSZ256rr,   X86::VPERMILPSZ256rm,     0 },
2148     { X86::VPERMPDZ256rr,     X86::VPERMPDZ256rm,       0 },
2149     { X86::VPERMPSZ256rr,     X86::VPERMPSZ256rm,       0 },
2150     { X86::VPERMQZ256rr,      X86::VPERMQZ256rm,        0 },
2151     { X86::VPERMWZ128rr,      X86::VPERMWZ128rm,        0 },
2152     { X86::VPERMWZ256rr,      X86::VPERMWZ256rm,        0 },
2153     { X86::VPMADDUBSWZ128rr,  X86::VPMADDUBSWZ128rm,    0 },
2154     { X86::VPMADDUBSWZ256rr,  X86::VPMADDUBSWZ256rm,    0 },
2155     { X86::VPMADDWDZ128rr,    X86::VPMADDWDZ128rm,      0 },
2156     { X86::VPMADDWDZ256rr,    X86::VPMADDWDZ256rm,      0 },
2157     { X86::VPMAXSBZ128rr,     X86::VPMAXSBZ128rm,       0 },
2158     { X86::VPMAXSBZ256rr,     X86::VPMAXSBZ256rm,       0 },
2159     { X86::VPMAXSDZ128rr,     X86::VPMAXSDZ128rm,       0 },
2160     { X86::VPMAXSDZ256rr,     X86::VPMAXSDZ256rm,       0 },
2161     { X86::VPMAXSQZ128rr,     X86::VPMAXSQZ128rm,       0 },
2162     { X86::VPMAXSQZ256rr,     X86::VPMAXSQZ256rm,       0 },
2163     { X86::VPMAXSWZ128rr,     X86::VPMAXSWZ128rm,       0 },
2164     { X86::VPMAXSWZ256rr,     X86::VPMAXSWZ256rm,       0 },
2165     { X86::VPMAXUBZ128rr,     X86::VPMAXUBZ128rm,       0 },
2166     { X86::VPMAXUBZ256rr,     X86::VPMAXUBZ256rm,       0 },
2167     { X86::VPMAXUDZ128rr,     X86::VPMAXUDZ128rm,       0 },
2168     { X86::VPMAXUDZ256rr,     X86::VPMAXUDZ256rm,       0 },
2169     { X86::VPMAXUQZ128rr,     X86::VPMAXUQZ128rm,       0 },
2170     { X86::VPMAXUQZ256rr,     X86::VPMAXUQZ256rm,       0 },
2171     { X86::VPMAXUWZ128rr,     X86::VPMAXUWZ128rm,       0 },
2172     { X86::VPMAXUWZ256rr,     X86::VPMAXUWZ256rm,       0 },
2173     { X86::VPMINSBZ128rr,     X86::VPMINSBZ128rm,       0 },
2174     { X86::VPMINSBZ256rr,     X86::VPMINSBZ256rm,       0 },
2175     { X86::VPMINSDZ128rr,     X86::VPMINSDZ128rm,       0 },
2176     { X86::VPMINSDZ256rr,     X86::VPMINSDZ256rm,       0 },
2177     { X86::VPMINSQZ128rr,     X86::VPMINSQZ128rm,       0 },
2178     { X86::VPMINSQZ256rr,     X86::VPMINSQZ256rm,       0 },
2179     { X86::VPMINSWZ128rr,     X86::VPMINSWZ128rm,       0 },
2180     { X86::VPMINSWZ256rr,     X86::VPMINSWZ256rm,       0 },
2181     { X86::VPMINUBZ128rr,     X86::VPMINUBZ128rm,       0 },
2182     { X86::VPMINUBZ256rr,     X86::VPMINUBZ256rm,       0 },
2183     { X86::VPMINUDZ128rr,     X86::VPMINUDZ128rm,       0 },
2184     { X86::VPMINUDZ256rr,     X86::VPMINUDZ256rm,       0 },
2185     { X86::VPMINUQZ128rr,     X86::VPMINUQZ128rm,       0 },
2186     { X86::VPMINUQZ256rr,     X86::VPMINUQZ256rm,       0 },
2187     { X86::VPMINUWZ128rr,     X86::VPMINUWZ128rm,       0 },
2188     { X86::VPMINUWZ256rr,     X86::VPMINUWZ256rm,       0 },
2189     { X86::VPMULDQZ128rr,     X86::VPMULDQZ128rm,       0 },
2190     { X86::VPMULDQZ256rr,     X86::VPMULDQZ256rm,       0 },
2191     { X86::VPMULLDZ128rr,     X86::VPMULLDZ128rm,       0 },
2192     { X86::VPMULLDZ256rr,     X86::VPMULLDZ256rm,       0 },
2193     { X86::VPMULLQZ128rr,     X86::VPMULLQZ128rm,       0 },
2194     { X86::VPMULLQZ256rr,     X86::VPMULLQZ256rm,       0 },
2195     { X86::VPMULLWZ128rr,     X86::VPMULLWZ128rm,       0 },
2196     { X86::VPMULLWZ256rr,     X86::VPMULLWZ256rm,       0 },
2197     { X86::VPMULUDQZ128rr,    X86::VPMULUDQZ128rm,      0 },
2198     { X86::VPMULUDQZ256rr,    X86::VPMULUDQZ256rm,      0 },
2199     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
2200     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
2201     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
2202     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
2203     { X86::VPSADBWZ128rr,     X86::VPSADBWZ128rm,       0 },
2204     { X86::VPSADBWZ256rr,     X86::VPSADBWZ256rm,       0 },
2205     { X86::VPSHUFBZ128rr,     X86::VPSHUFBZ128rm,       0 },
2206     { X86::VPSHUFBZ256rr,     X86::VPSHUFBZ256rm,       0 },
2207     { X86::VPSLLDZ128rr,      X86::VPSLLDZ128rm,        0 },
2208     { X86::VPSLLDZ256rr,      X86::VPSLLDZ256rm,        0 },
2209     { X86::VPSLLQZ128rr,      X86::VPSLLQZ128rm,        0 },
2210     { X86::VPSLLQZ256rr,      X86::VPSLLQZ256rm,        0 },
2211     { X86::VPSLLVDZ128rr,     X86::VPSLLVDZ128rm,       0 },
2212     { X86::VPSLLVDZ256rr,     X86::VPSLLVDZ256rm,       0 },
2213     { X86::VPSLLVQZ128rr,     X86::VPSLLVQZ128rm,       0 },
2214     { X86::VPSLLVQZ256rr,     X86::VPSLLVQZ256rm,       0 },
2215     { X86::VPSLLVWZ128rr,     X86::VPSLLVWZ128rm,       0 },
2216     { X86::VPSLLVWZ256rr,     X86::VPSLLVWZ256rm,       0 },
2217     { X86::VPSLLWZ128rr,      X86::VPSLLWZ128rm,        0 },
2218     { X86::VPSLLWZ256rr,      X86::VPSLLWZ256rm,        0 },
2219     { X86::VPSRADZ128rr,      X86::VPSRADZ128rm,        0 },
2220     { X86::VPSRADZ256rr,      X86::VPSRADZ256rm,        0 },
2221     { X86::VPSRAQZ128rr,      X86::VPSRAQZ128rm,        0 },
2222     { X86::VPSRAQZ256rr,      X86::VPSRAQZ256rm,        0 },
2223     { X86::VPSRAVDZ128rr,     X86::VPSRAVDZ128rm,       0 },
2224     { X86::VPSRAVDZ256rr,     X86::VPSRAVDZ256rm,       0 },
2225     { X86::VPSRAVQZ128rr,     X86::VPSRAVQZ128rm,       0 },
2226     { X86::VPSRAVQZ256rr,     X86::VPSRAVQZ256rm,       0 },
2227     { X86::VPSRAVWZ128rr,     X86::VPSRAVWZ128rm,       0 },
2228     { X86::VPSRAVWZ256rr,     X86::VPSRAVWZ256rm,       0 },
2229     { X86::VPSRAWZ128rr,      X86::VPSRAWZ128rm,        0 },
2230     { X86::VPSRAWZ256rr,      X86::VPSRAWZ256rm,        0 },
2231     { X86::VPSRLDZ128rr,      X86::VPSRLDZ128rm,        0 },
2232     { X86::VPSRLDZ256rr,      X86::VPSRLDZ256rm,        0 },
2233     { X86::VPSRLQZ128rr,      X86::VPSRLQZ128rm,        0 },
2234     { X86::VPSRLQZ256rr,      X86::VPSRLQZ256rm,        0 },
2235     { X86::VPSRLVDZ128rr,     X86::VPSRLVDZ128rm,       0 },
2236     { X86::VPSRLVDZ256rr,     X86::VPSRLVDZ256rm,       0 },
2237     { X86::VPSRLVQZ128rr,     X86::VPSRLVQZ128rm,       0 },
2238     { X86::VPSRLVQZ256rr,     X86::VPSRLVQZ256rm,       0 },
2239     { X86::VPSRLVWZ128rr,     X86::VPSRLVWZ128rm,       0 },
2240     { X86::VPSRLVWZ256rr,     X86::VPSRLVWZ256rm,       0 },
2241     { X86::VPSRLWZ128rr,      X86::VPSRLWZ128rm,        0 },
2242     { X86::VPSRLWZ256rr,      X86::VPSRLWZ256rm,        0 },
2243     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
2244     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
2245     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
2246     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
2247     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
2248     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
2249     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
2250     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
2251     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
2252     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
2253     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
2254     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
2255     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
2256     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
2257     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
2258     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
2259     { X86::VPUNPCKHBWZ128rr,  X86::VPUNPCKHBWZ128rm,    0 },
2260     { X86::VPUNPCKHBWZ256rr,  X86::VPUNPCKHBWZ256rm,    0 },
2261     { X86::VPUNPCKHDQZ128rr,  X86::VPUNPCKHDQZ128rm,    0 },
2262     { X86::VPUNPCKHDQZ256rr,  X86::VPUNPCKHDQZ256rm,    0 },
2263     { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm,   0 },
2264     { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm,   0 },
2265     { X86::VPUNPCKHWDZ128rr,  X86::VPUNPCKHWDZ128rm,    0 },
2266     { X86::VPUNPCKHWDZ256rr,  X86::VPUNPCKHWDZ256rm,    0 },
2267     { X86::VPUNPCKLBWZ128rr,  X86::VPUNPCKLBWZ128rm,    0 },
2268     { X86::VPUNPCKLBWZ256rr,  X86::VPUNPCKLBWZ256rm,    0 },
2269     { X86::VPUNPCKLDQZ128rr,  X86::VPUNPCKLDQZ128rm,    0 },
2270     { X86::VPUNPCKLDQZ256rr,  X86::VPUNPCKLDQZ256rm,    0 },
2271     { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm,   0 },
2272     { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm,   0 },
2273     { X86::VPUNPCKLWDZ128rr,  X86::VPUNPCKLWDZ128rm,    0 },
2274     { X86::VPUNPCKLWDZ256rr,  X86::VPUNPCKLWDZ256rm,    0 },
2275     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
2276     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
2277     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
2278     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
2279     { X86::VSHUFPDZ128rri,    X86::VSHUFPDZ128rmi,      0 },
2280     { X86::VSHUFPDZ256rri,    X86::VSHUFPDZ256rmi,      0 },
2281     { X86::VSHUFPSZ128rri,    X86::VSHUFPSZ128rmi,      0 },
2282     { X86::VSHUFPSZ256rri,    X86::VSHUFPSZ256rmi,      0 },
2283     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
2284     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
2285     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
2286     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
2287     { X86::VUNPCKHPDZ128rr,   X86::VUNPCKHPDZ128rm,     0 },
2288     { X86::VUNPCKHPDZ256rr,   X86::VUNPCKHPDZ256rm,     0 },
2289     { X86::VUNPCKHPSZ128rr,   X86::VUNPCKHPSZ128rm,     0 },
2290     { X86::VUNPCKHPSZ256rr,   X86::VUNPCKHPSZ256rm,     0 },
2291     { X86::VUNPCKLPDZ128rr,   X86::VUNPCKLPDZ128rm,     0 },
2292     { X86::VUNPCKLPDZ256rr,   X86::VUNPCKLPDZ256rm,     0 },
2293     { X86::VUNPCKLPSZ128rr,   X86::VUNPCKLPSZ128rm,     0 },
2294     { X86::VUNPCKLPSZ256rr,   X86::VUNPCKLPSZ256rm,     0 },
2295     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
2296     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
2297     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
2298     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
2299 
2300     // AVX-512 masked foldable instructions
2301     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
2302     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
2303     { X86::VPABSBZrrkz,       X86::VPABSBZrmkz,         0 },
2304     { X86::VPABSDZrrkz,       X86::VPABSDZrmkz,         0 },
2305     { X86::VPABSQZrrkz,       X86::VPABSQZrmkz,         0 },
2306     { X86::VPABSWZrrkz,       X86::VPABSWZrmkz,         0 },
2307     { X86::VPERMILPDZrikz,    X86::VPERMILPDZmikz,      0 },
2308     { X86::VPERMILPSZrikz,    X86::VPERMILPSZmikz,      0 },
2309     { X86::VPERMPDZrikz,      X86::VPERMPDZmikz,        0 },
2310     { X86::VPERMQZrikz,       X86::VPERMQZmikz,         0 },
2311     { X86::VPMOVSXBDZrrkz,    X86::VPMOVSXBDZrmkz,      0 },
2312     { X86::VPMOVSXBQZrrkz,    X86::VPMOVSXBQZrmkz,      TB_NO_REVERSE },
2313     { X86::VPMOVSXBWZrrkz,    X86::VPMOVSXBWZrmkz,      0 },
2314     { X86::VPMOVSXDQZrrkz,    X86::VPMOVSXDQZrmkz,      0 },
2315     { X86::VPMOVSXWDZrrkz,    X86::VPMOVSXWDZrmkz,      0 },
2316     { X86::VPMOVSXWQZrrkz,    X86::VPMOVSXWQZrmkz,      0 },
2317     { X86::VPMOVZXBDZrrkz,    X86::VPMOVZXBDZrmkz,      0 },
2318     { X86::VPMOVZXBQZrrkz,    X86::VPMOVZXBQZrmkz,      TB_NO_REVERSE },
2319     { X86::VPMOVZXBWZrrkz,    X86::VPMOVZXBWZrmkz,      0 },
2320     { X86::VPMOVZXDQZrrkz,    X86::VPMOVZXDQZrmkz,      0 },
2321     { X86::VPMOVZXWDZrrkz,    X86::VPMOVZXWDZrmkz,      0 },
2322     { X86::VPMOVZXWQZrrkz,    X86::VPMOVZXWQZrmkz,      0 },
2323     { X86::VPSHUFDZrikz,      X86::VPSHUFDZmikz,        0 },
2324     { X86::VPSHUFHWZrikz,     X86::VPSHUFHWZmikz,       0 },
2325     { X86::VPSHUFLWZrikz,     X86::VPSHUFLWZmikz,       0 },
2326     { X86::VPSLLDZrikz,       X86::VPSLLDZmikz,         0 },
2327     { X86::VPSLLQZrikz,       X86::VPSLLQZmikz,         0 },
2328     { X86::VPSLLWZrikz,       X86::VPSLLWZmikz,         0 },
2329     { X86::VPSRADZrikz,       X86::VPSRADZmikz,         0 },
2330     { X86::VPSRAQZrikz,       X86::VPSRAQZmikz,         0 },
2331     { X86::VPSRAWZrikz,       X86::VPSRAWZmikz,         0 },
2332     { X86::VPSRLDZrikz,       X86::VPSRLDZmikz,         0 },
2333     { X86::VPSRLQZrikz,       X86::VPSRLQZmikz,         0 },
2334     { X86::VPSRLWZrikz,       X86::VPSRLWZmikz,         0 },
2335 
2336     // AVX-512VL 256-bit masked foldable instructions
2337     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
2338     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
2339     { X86::VPABSBZ256rrkz,    X86::VPABSBZ256rmkz,      0 },
2340     { X86::VPABSDZ256rrkz,    X86::VPABSDZ256rmkz,      0 },
2341     { X86::VPABSQZ256rrkz,    X86::VPABSQZ256rmkz,      0 },
2342     { X86::VPABSWZ256rrkz,    X86::VPABSWZ256rmkz,      0 },
2343     { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz,   0 },
2344     { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz,   0 },
2345     { X86::VPERMPDZ256rikz,   X86::VPERMPDZ256mikz,     0 },
2346     { X86::VPERMQZ256rikz,    X86::VPERMQZ256mikz,      0 },
2347     { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,   TB_NO_REVERSE },
2348     { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,   TB_NO_REVERSE },
2349     { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz,   0 },
2350     { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz,   0 },
2351     { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz,   0 },
2352     { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,   TB_NO_REVERSE },
2353     { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,   TB_NO_REVERSE },
2354     { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,   TB_NO_REVERSE },
2355     { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz,   0 },
2356     { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz,   0 },
2357     { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz,   0 },
2358     { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,   TB_NO_REVERSE },
2359     { X86::VPSHUFDZ256rikz,   X86::VPSHUFDZ256mikz,     0 },
2360     { X86::VPSHUFHWZ256rikz,  X86::VPSHUFHWZ256mikz,    0 },
2361     { X86::VPSHUFLWZ256rikz,  X86::VPSHUFLWZ256mikz,    0 },
2362     { X86::VPSLLDZ256rikz,    X86::VPSLLDZ256mikz,      0 },
2363     { X86::VPSLLQZ256rikz,    X86::VPSLLQZ256mikz,      0 },
2364     { X86::VPSLLWZ256rikz,    X86::VPSLLWZ256mikz,      0 },
2365     { X86::VPSRADZ256rikz,    X86::VPSRADZ256mikz,      0 },
2366     { X86::VPSRAQZ256rikz,    X86::VPSRAQZ256mikz,      0 },
2367     { X86::VPSRAWZ256rikz,    X86::VPSRAWZ256mikz,      0 },
2368     { X86::VPSRLDZ256rikz,    X86::VPSRLDZ256mikz,      0 },
2369     { X86::VPSRLQZ256rikz,    X86::VPSRLQZ256mikz,      0 },
2370     { X86::VPSRLWZ256rikz,    X86::VPSRLWZ256mikz,      0 },
2371 
2372     // AVX-512VL 128-bit masked foldable instructions
2373     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
2374     { X86::VPABSBZ128rrkz,    X86::VPABSBZ128rmkz,      0 },
2375     { X86::VPABSDZ128rrkz,    X86::VPABSDZ128rmkz,      0 },
2376     { X86::VPABSQZ128rrkz,    X86::VPABSQZ128rmkz,      0 },
2377     { X86::VPABSWZ128rrkz,    X86::VPABSWZ128rmkz,      0 },
2378     { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz,   0 },
2379     { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz,   0 },
2380     { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,   TB_NO_REVERSE },
2381     { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,   TB_NO_REVERSE },
2382     { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,   TB_NO_REVERSE },
2383     { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,   TB_NO_REVERSE },
2384     { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,   TB_NO_REVERSE },
2385     { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,   TB_NO_REVERSE },
2386     { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,   TB_NO_REVERSE },
2387     { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,   TB_NO_REVERSE },
2388     { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,   TB_NO_REVERSE },
2389     { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,   TB_NO_REVERSE },
2390     { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,   TB_NO_REVERSE },
2391     { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,   TB_NO_REVERSE },
2392     { X86::VPSHUFDZ128rikz,   X86::VPSHUFDZ128mikz,     0 },
2393     { X86::VPSHUFHWZ128rikz,  X86::VPSHUFHWZ128mikz,    0 },
2394     { X86::VPSHUFLWZ128rikz,  X86::VPSHUFLWZ128mikz,    0 },
2395     { X86::VPSLLDZ128rikz,    X86::VPSLLDZ128mikz,      0 },
2396     { X86::VPSLLQZ128rikz,    X86::VPSLLQZ128mikz,      0 },
2397     { X86::VPSLLWZ128rikz,    X86::VPSLLWZ128mikz,      0 },
2398     { X86::VPSRADZ128rikz,    X86::VPSRADZ128mikz,      0 },
2399     { X86::VPSRAQZ128rikz,    X86::VPSRAQZ128mikz,      0 },
2400     { X86::VPSRAWZ128rikz,    X86::VPSRAWZ128mikz,      0 },
2401     { X86::VPSRLDZ128rikz,    X86::VPSRLDZ128mikz,      0 },
2402     { X86::VPSRLQZ128rikz,    X86::VPSRLQZ128mikz,      0 },
2403     { X86::VPSRLWZ128rikz,    X86::VPSRLWZ128mikz,      0 },
2404 
2405     // AES foldable instructions
2406     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
2407     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
2408     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
2409     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
2410     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
2411     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
2412     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
2413     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
2414 
2415     // SHA foldable instructions
2416     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
2417     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
2418     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
2419     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
2420     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
2421     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
2422     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
2423   };
2424 
2425   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2426     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2427                   Entry.RegOp, Entry.MemOp,
2428                   // Index 2, folded load
2429                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2430   }
2431 
2432   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2433     // FMA4 foldable patterns
2434     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
2435     { X86::VFMADDSS4rr_Int,       X86::VFMADDSS4rm_Int,       TB_NO_REVERSE },
2436     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
2437     { X86::VFMADDSD4rr_Int,       X86::VFMADDSD4rm_Int,       TB_NO_REVERSE },
2438     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
2439     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
2440     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
2441     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
2442     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
2443     { X86::VFNMADDSS4rr_Int,      X86::VFNMADDSS4rm_Int,      TB_NO_REVERSE },
2444     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
2445     { X86::VFNMADDSD4rr_Int,      X86::VFNMADDSD4rm_Int,      TB_NO_REVERSE },
2446     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
2447     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
2448     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
2449     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
2450     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
2451     { X86::VFMSUBSS4rr_Int,       X86::VFMSUBSS4rm_Int,       TB_NO_REVERSE },
2452     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
2453     { X86::VFMSUBSD4rr_Int,       X86::VFMSUBSD4rm_Int,       TB_NO_REVERSE },
2454     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
2455     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
2456     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
2457     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
2458     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
2459     { X86::VFNMSUBSS4rr_Int,      X86::VFNMSUBSS4rm_Int,      TB_NO_REVERSE },
2460     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
2461     { X86::VFNMSUBSD4rr_Int,      X86::VFNMSUBSD4rm_Int,      TB_NO_REVERSE },
2462     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
2463     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
2464     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
2465     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
2466     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
2467     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
2468     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
2469     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
2470     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
2471     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
2472     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
2473     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
2474 
2475     // XOP foldable instructions
2476     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
2477     { X86::VPCMOVYrrr,            X86::VPCMOVYrrm,            0 },
2478     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
2479     { X86::VPERMIL2PDYrr,         X86::VPERMIL2PDYrm,         0 },
2480     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2481     { X86::VPERMIL2PSYrr,         X86::VPERMIL2PSYrm,         0 },
2482     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2483 
2484     // AVX-512 instructions with 3 source operands.
2485     { X86::VPERMI2Brr,            X86::VPERMI2Brm,            0 },
2486     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2487     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2488     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2489     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2490     { X86::VPERMI2Wrr,            X86::VPERMI2Wrm,            0 },
2491     { X86::VPERMT2Brr,            X86::VPERMT2Brm,            0 },
2492     { X86::VPERMT2Drr,            X86::VPERMT2Drm,            0 },
2493     { X86::VPERMT2PSrr,           X86::VPERMT2PSrm,           0 },
2494     { X86::VPERMT2PDrr,           X86::VPERMT2PDrm,           0 },
2495     { X86::VPERMT2Qrr,            X86::VPERMT2Qrm,            0 },
2496     { X86::VPERMT2Wrr,            X86::VPERMT2Wrm,            0 },
2497     { X86::VPTERNLOGDZrri,        X86::VPTERNLOGDZrmi,        0 },
2498     { X86::VPTERNLOGQZrri,        X86::VPTERNLOGQZrmi,        0 },
2499 
2500     // AVX-512VL 256-bit instructions with 3 source operands.
2501     { X86::VPERMI2B256rr,         X86::VPERMI2B256rm,         0 },
2502     { X86::VPERMI2D256rr,         X86::VPERMI2D256rm,         0 },
2503     { X86::VPERMI2PD256rr,        X86::VPERMI2PD256rm,        0 },
2504     { X86::VPERMI2PS256rr,        X86::VPERMI2PS256rm,        0 },
2505     { X86::VPERMI2Q256rr,         X86::VPERMI2Q256rm,         0 },
2506     { X86::VPERMI2W256rr,         X86::VPERMI2W256rm,         0 },
2507     { X86::VPERMT2B256rr,         X86::VPERMT2B256rm,         0 },
2508     { X86::VPERMT2D256rr,         X86::VPERMT2D256rm,         0 },
2509     { X86::VPERMT2PD256rr,        X86::VPERMT2PD256rm,        0 },
2510     { X86::VPERMT2PS256rr,        X86::VPERMT2PS256rm,        0 },
2511     { X86::VPERMT2Q256rr,         X86::VPERMT2Q256rm,         0 },
2512     { X86::VPERMT2W256rr,         X86::VPERMT2W256rm,         0 },
2513     { X86::VPTERNLOGDZ256rri,     X86::VPTERNLOGDZ256rmi,     0 },
2514     { X86::VPTERNLOGQZ256rri,     X86::VPTERNLOGQZ256rmi,     0 },
2515 
2516     // AVX-512VL 128-bit instructions with 3 source operands.
2517     { X86::VPERMI2B128rr,         X86::VPERMI2B128rm,         0 },
2518     { X86::VPERMI2D128rr,         X86::VPERMI2D128rm,         0 },
2519     { X86::VPERMI2PD128rr,        X86::VPERMI2PD128rm,        0 },
2520     { X86::VPERMI2PS128rr,        X86::VPERMI2PS128rm,        0 },
2521     { X86::VPERMI2Q128rr,         X86::VPERMI2Q128rm,         0 },
2522     { X86::VPERMI2W128rr,         X86::VPERMI2W128rm,         0 },
2523     { X86::VPERMT2B128rr,         X86::VPERMT2B128rm,         0 },
2524     { X86::VPERMT2D128rr,         X86::VPERMT2D128rm,         0 },
2525     { X86::VPERMT2PD128rr,        X86::VPERMT2PD128rm,        0 },
2526     { X86::VPERMT2PS128rr,        X86::VPERMT2PS128rm,        0 },
2527     { X86::VPERMT2Q128rr,         X86::VPERMT2Q128rm,         0 },
2528     { X86::VPERMT2W128rr,         X86::VPERMT2W128rm,         0 },
2529     { X86::VPTERNLOGDZ128rri,     X86::VPTERNLOGDZ128rmi,     0 },
2530     { X86::VPTERNLOGQZ128rri,     X86::VPTERNLOGQZ128rmi,     0 },
2531 
2532     // AVX-512 masked instructions
2533     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2534     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2535     { X86::VADDSDZrr_Intkz,       X86::VADDSDZrm_Intkz,       TB_NO_REVERSE },
2536     { X86::VADDSSZrr_Intkz,       X86::VADDSSZrm_Intkz,       TB_NO_REVERSE },
2537     { X86::VALIGNDZrrikz,         X86::VALIGNDZrmikz,         0 },
2538     { X86::VALIGNQZrrikz,         X86::VALIGNQZrmikz,         0 },
2539     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2540     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2541     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2542     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2543     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2544     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2545     { X86::VDIVSDZrr_Intkz,       X86::VDIVSDZrm_Intkz,       TB_NO_REVERSE },
2546     { X86::VDIVSSZrr_Intkz,       X86::VDIVSSZrm_Intkz,       TB_NO_REVERSE },
2547     { X86::VINSERTF32x4Zrrkz,     X86::VINSERTF32x4Zrmkz,     0 },
2548     { X86::VINSERTF32x8Zrrkz,     X86::VINSERTF32x8Zrmkz,     0 },
2549     { X86::VINSERTF64x2Zrrkz,     X86::VINSERTF64x2Zrmkz,     0 },
2550     { X86::VINSERTF64x4Zrrkz,     X86::VINSERTF64x4Zrmkz,     0 },
2551     { X86::VINSERTI32x4Zrrkz,     X86::VINSERTI32x4Zrmkz,     0 },
2552     { X86::VINSERTI32x8Zrrkz,     X86::VINSERTI32x8Zrmkz,     0 },
2553     { X86::VINSERTI64x2Zrrkz,     X86::VINSERTI64x2Zrmkz,     0 },
2554     { X86::VINSERTI64x4Zrrkz,     X86::VINSERTI64x4Zrmkz,     0 },
2555     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2556     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2557     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2558     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2559     { X86::VMAXSDZrr_Intkz,       X86::VMAXSDZrm_Intkz,       0 },
2560     { X86::VMAXSSZrr_Intkz,       X86::VMAXSSZrm_Intkz,       0 },
2561     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2562     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2563     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2564     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2565     { X86::VMINSDZrr_Intkz,       X86::VMINSDZrm_Intkz,       0 },
2566     { X86::VMINSSZrr_Intkz,       X86::VMINSSZrm_Intkz,       0 },
2567     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2568     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2569     { X86::VMULSDZrr_Intkz,       X86::VMULSDZrm_Intkz,       TB_NO_REVERSE },
2570     { X86::VMULSSZrr_Intkz,       X86::VMULSSZrm_Intkz,       TB_NO_REVERSE },
2571     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2572     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2573     { X86::VPACKSSDWZrrkz,        X86::VPACKSSDWZrmkz,        0 },
2574     { X86::VPACKSSWBZrrkz,        X86::VPACKSSWBZrmkz,        0 },
2575     { X86::VPACKUSDWZrrkz,        X86::VPACKUSDWZrmkz,        0 },
2576     { X86::VPACKUSWBZrrkz,        X86::VPACKUSWBZrmkz,        0 },
2577     { X86::VPADDBZrrkz,           X86::VPADDBZrmkz,           0 },
2578     { X86::VPADDDZrrkz,           X86::VPADDDZrmkz,           0 },
2579     { X86::VPADDQZrrkz,           X86::VPADDQZrmkz,           0 },
2580     { X86::VPADDSBZrrkz,          X86::VPADDSBZrmkz,          0 },
2581     { X86::VPADDSWZrrkz,          X86::VPADDSWZrmkz,          0 },
2582     { X86::VPADDUSBZrrkz,         X86::VPADDUSBZrmkz,         0 },
2583     { X86::VPADDUSWZrrkz,         X86::VPADDUSWZrmkz,         0 },
2584     { X86::VPADDWZrrkz,           X86::VPADDWZrmkz,           0 },
2585     { X86::VPALIGNRZrrikz,        X86::VPALIGNRZrmikz,        0 },
2586     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2587     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2588     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2589     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2590     { X86::VPAVGBZrrkz,           X86::VPAVGBZrmkz,           0 },
2591     { X86::VPAVGWZrrkz,           X86::VPAVGWZrmkz,           0 },
2592     { X86::VPERMBZrrkz,           X86::VPERMBZrmkz,           0 },
2593     { X86::VPERMDZrrkz,           X86::VPERMDZrmkz,           0 },
2594     { X86::VPERMILPDZrrkz,        X86::VPERMILPDZrmkz,        0 },
2595     { X86::VPERMILPSZrrkz,        X86::VPERMILPSZrmkz,        0 },
2596     { X86::VPERMPDZrrkz,          X86::VPERMPDZrmkz,          0 },
2597     { X86::VPERMPSZrrkz,          X86::VPERMPSZrmkz,          0 },
2598     { X86::VPERMQZrrkz,           X86::VPERMQZrmkz,           0 },
2599     { X86::VPERMWZrrkz,           X86::VPERMWZrmkz,           0 },
2600     { X86::VPMADDUBSWZrrkz,       X86::VPMADDUBSWZrmkz,       0 },
2601     { X86::VPMADDWDZrrkz,         X86::VPMADDWDZrmkz,         0 },
2602     { X86::VPMAXSBZrrkz,          X86::VPMAXSBZrmkz,          0 },
2603     { X86::VPMAXSDZrrkz,          X86::VPMAXSDZrmkz,          0 },
2604     { X86::VPMAXSQZrrkz,          X86::VPMAXSQZrmkz,          0 },
2605     { X86::VPMAXSWZrrkz,          X86::VPMAXSWZrmkz,          0 },
2606     { X86::VPMAXUBZrrkz,          X86::VPMAXUBZrmkz,          0 },
2607     { X86::VPMAXUDZrrkz,          X86::VPMAXUDZrmkz,          0 },
2608     { X86::VPMAXUQZrrkz,          X86::VPMAXUQZrmkz,          0 },
2609     { X86::VPMAXUWZrrkz,          X86::VPMAXUWZrmkz,          0 },
2610     { X86::VPMINSBZrrkz,          X86::VPMINSBZrmkz,          0 },
2611     { X86::VPMINSDZrrkz,          X86::VPMINSDZrmkz,          0 },
2612     { X86::VPMINSQZrrkz,          X86::VPMINSQZrmkz,          0 },
2613     { X86::VPMINSWZrrkz,          X86::VPMINSWZrmkz,          0 },
2614     { X86::VPMINUBZrrkz,          X86::VPMINUBZrmkz,          0 },
2615     { X86::VPMINUDZrrkz,          X86::VPMINUDZrmkz,          0 },
2616     { X86::VPMINUQZrrkz,          X86::VPMINUQZrmkz,          0 },
2617     { X86::VPMINUWZrrkz,          X86::VPMINUWZrmkz,          0 },
2618     { X86::VPMULLDZrrkz,          X86::VPMULLDZrmkz,          0 },
2619     { X86::VPMULLQZrrkz,          X86::VPMULLQZrmkz,          0 },
2620     { X86::VPMULLWZrrkz,          X86::VPMULLWZrmkz,          0 },
2621     { X86::VPMULDQZrrkz,          X86::VPMULDQZrmkz,          0 },
2622     { X86::VPMULUDQZrrkz,         X86::VPMULUDQZrmkz,         0 },
2623     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2624     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2625     { X86::VPSHUFBZrrkz,          X86::VPSHUFBZrmkz,          0 },
2626     { X86::VPSLLDZrrkz,           X86::VPSLLDZrmkz,           0 },
2627     { X86::VPSLLQZrrkz,           X86::VPSLLQZrmkz,           0 },
2628     { X86::VPSLLVDZrrkz,          X86::VPSLLVDZrmkz,          0 },
2629     { X86::VPSLLVQZrrkz,          X86::VPSLLVQZrmkz,          0 },
2630     { X86::VPSLLVWZrrkz,          X86::VPSLLVWZrmkz,          0 },
2631     { X86::VPSLLWZrrkz,           X86::VPSLLWZrmkz,           0 },
2632     { X86::VPSRADZrrkz,           X86::VPSRADZrmkz,           0 },
2633     { X86::VPSRAQZrrkz,           X86::VPSRAQZrmkz,           0 },
2634     { X86::VPSRAVDZrrkz,          X86::VPSRAVDZrmkz,          0 },
2635     { X86::VPSRAVQZrrkz,          X86::VPSRAVQZrmkz,          0 },
2636     { X86::VPSRAVWZrrkz,          X86::VPSRAVWZrmkz,          0 },
2637     { X86::VPSRAWZrrkz,           X86::VPSRAWZrmkz,           0 },
2638     { X86::VPSRLDZrrkz,           X86::VPSRLDZrmkz,           0 },
2639     { X86::VPSRLQZrrkz,           X86::VPSRLQZrmkz,           0 },
2640     { X86::VPSRLVDZrrkz,          X86::VPSRLVDZrmkz,          0 },
2641     { X86::VPSRLVQZrrkz,          X86::VPSRLVQZrmkz,          0 },
2642     { X86::VPSRLVWZrrkz,          X86::VPSRLVWZrmkz,          0 },
2643     { X86::VPSRLWZrrkz,           X86::VPSRLWZrmkz,           0 },
2644     { X86::VPSUBBZrrkz,           X86::VPSUBBZrmkz,           0 },
2645     { X86::VPSUBDZrrkz,           X86::VPSUBDZrmkz,           0 },
2646     { X86::VPSUBQZrrkz,           X86::VPSUBQZrmkz,           0 },
2647     { X86::VPSUBSBZrrkz,          X86::VPSUBSBZrmkz,          0 },
2648     { X86::VPSUBSWZrrkz,          X86::VPSUBSWZrmkz,          0 },
2649     { X86::VPSUBUSBZrrkz,         X86::VPSUBUSBZrmkz,         0 },
2650     { X86::VPSUBUSWZrrkz,         X86::VPSUBUSWZrmkz,         0 },
2651     { X86::VPSUBWZrrkz,           X86::VPSUBWZrmkz,           0 },
2652     { X86::VPUNPCKHBWZrrkz,       X86::VPUNPCKHBWZrmkz,       0 },
2653     { X86::VPUNPCKHDQZrrkz,       X86::VPUNPCKHDQZrmkz,       0 },
2654     { X86::VPUNPCKHQDQZrrkz,      X86::VPUNPCKHQDQZrmkz,      0 },
2655     { X86::VPUNPCKHWDZrrkz,       X86::VPUNPCKHWDZrmkz,       0 },
2656     { X86::VPUNPCKLBWZrrkz,       X86::VPUNPCKLBWZrmkz,       0 },
2657     { X86::VPUNPCKLDQZrrkz,       X86::VPUNPCKLDQZrmkz,       0 },
2658     { X86::VPUNPCKLQDQZrrkz,      X86::VPUNPCKLQDQZrmkz,      0 },
2659     { X86::VPUNPCKLWDZrrkz,       X86::VPUNPCKLWDZrmkz,       0 },
2660     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2661     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2662     { X86::VSHUFPDZrrikz,         X86::VSHUFPDZrmikz,         0 },
2663     { X86::VSHUFPSZrrikz,         X86::VSHUFPSZrmikz,         0 },
2664     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2665     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2666     { X86::VSUBSDZrr_Intkz,       X86::VSUBSDZrm_Intkz,       TB_NO_REVERSE },
2667     { X86::VSUBSSZrr_Intkz,       X86::VSUBSSZrm_Intkz,       TB_NO_REVERSE },
2668     { X86::VUNPCKHPDZrrkz,        X86::VUNPCKHPDZrmkz,        0 },
2669     { X86::VUNPCKHPSZrrkz,        X86::VUNPCKHPSZrmkz,        0 },
2670     { X86::VUNPCKLPDZrrkz,        X86::VUNPCKLPDZrmkz,        0 },
2671     { X86::VUNPCKLPSZrrkz,        X86::VUNPCKLPSZrmkz,        0 },
2672     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2673     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2674 
2675     // AVX-512{F,VL} masked arithmetic instructions 256-bit
2676     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2677     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2678     { X86::VALIGNDZ256rrikz,      X86::VALIGNDZ256rmikz,      0 },
2679     { X86::VALIGNQZ256rrikz,      X86::VALIGNQZ256rmikz,      0 },
2680     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2681     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2682     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2683     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2684     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2685     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2686     { X86::VINSERTF32x4Z256rrkz,  X86::VINSERTF32x4Z256rmkz,  0 },
2687     { X86::VINSERTF64x2Z256rrkz,  X86::VINSERTF64x2Z256rmkz,  0 },
2688     { X86::VINSERTI32x4Z256rrkz,  X86::VINSERTI32x4Z256rmkz,  0 },
2689     { X86::VINSERTI64x2Z256rrkz,  X86::VINSERTI64x2Z256rmkz,  0 },
2690     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2691     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2692     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2693     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2694     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2695     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2696     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2697     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2698     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2699     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2700     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2701     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2702     { X86::VPACKSSDWZ256rrkz,     X86::VPACKSSDWZ256rmkz,     0 },
2703     { X86::VPACKSSWBZ256rrkz,     X86::VPACKSSWBZ256rmkz,     0 },
2704     { X86::VPACKUSDWZ256rrkz,     X86::VPACKUSDWZ256rmkz,     0 },
2705     { X86::VPACKUSWBZ256rrkz,     X86::VPACKUSWBZ256rmkz,     0 },
2706     { X86::VPADDBZ256rrkz,        X86::VPADDBZ256rmkz,        0 },
2707     { X86::VPADDDZ256rrkz,        X86::VPADDDZ256rmkz,        0 },
2708     { X86::VPADDQZ256rrkz,        X86::VPADDQZ256rmkz,        0 },
2709     { X86::VPADDSBZ256rrkz,       X86::VPADDSBZ256rmkz,       0 },
2710     { X86::VPADDSWZ256rrkz,       X86::VPADDSWZ256rmkz,       0 },
2711     { X86::VPADDUSBZ256rrkz,      X86::VPADDUSBZ256rmkz,      0 },
2712     { X86::VPADDUSWZ256rrkz,      X86::VPADDUSWZ256rmkz,      0 },
2713     { X86::VPADDWZ256rrkz,        X86::VPADDWZ256rmkz,        0 },
2714     { X86::VPALIGNRZ256rrikz,     X86::VPALIGNRZ256rmikz,     0 },
2715     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2716     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2717     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2718     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2719     { X86::VPAVGBZ256rrkz,        X86::VPAVGBZ256rmkz,        0 },
2720     { X86::VPAVGWZ256rrkz,        X86::VPAVGWZ256rmkz,        0 },
2721     { X86::VPERMBZ256rrkz,        X86::VPERMBZ256rmkz,        0 },
2722     { X86::VPERMDZ256rrkz,        X86::VPERMDZ256rmkz,        0 },
2723     { X86::VPERMILPDZ256rrkz,     X86::VPERMILPDZ256rmkz,     0 },
2724     { X86::VPERMILPSZ256rrkz,     X86::VPERMILPSZ256rmkz,     0 },
2725     { X86::VPERMPDZ256rrkz,       X86::VPERMPDZ256rmkz,       0 },
2726     { X86::VPERMPSZ256rrkz,       X86::VPERMPSZ256rmkz,       0 },
2727     { X86::VPERMQZ256rrkz,        X86::VPERMQZ256rmkz,        0 },
2728     { X86::VPERMWZ256rrkz,        X86::VPERMWZ256rmkz,        0 },
2729     { X86::VPMADDUBSWZ256rrkz,    X86::VPMADDUBSWZ256rmkz,    0 },
2730     { X86::VPMADDWDZ256rrkz,      X86::VPMADDWDZ256rmkz,      0 },
2731     { X86::VPMAXSBZ256rrkz,       X86::VPMAXSBZ256rmkz,       0 },
2732     { X86::VPMAXSDZ256rrkz,       X86::VPMAXSDZ256rmkz,       0 },
2733     { X86::VPMAXSQZ256rrkz,       X86::VPMAXSQZ256rmkz,       0 },
2734     { X86::VPMAXSWZ256rrkz,       X86::VPMAXSWZ256rmkz,       0 },
2735     { X86::VPMAXUBZ256rrkz,       X86::VPMAXUBZ256rmkz,       0 },
2736     { X86::VPMAXUDZ256rrkz,       X86::VPMAXUDZ256rmkz,       0 },
2737     { X86::VPMAXUQZ256rrkz,       X86::VPMAXUQZ256rmkz,       0 },
2738     { X86::VPMAXUWZ256rrkz,       X86::VPMAXUWZ256rmkz,       0 },
2739     { X86::VPMINSBZ256rrkz,       X86::VPMINSBZ256rmkz,       0 },
2740     { X86::VPMINSDZ256rrkz,       X86::VPMINSDZ256rmkz,       0 },
2741     { X86::VPMINSQZ256rrkz,       X86::VPMINSQZ256rmkz,       0 },
2742     { X86::VPMINSWZ256rrkz,       X86::VPMINSWZ256rmkz,       0 },
2743     { X86::VPMINUBZ256rrkz,       X86::VPMINUBZ256rmkz,       0 },
2744     { X86::VPMINUDZ256rrkz,       X86::VPMINUDZ256rmkz,       0 },
2745     { X86::VPMINUQZ256rrkz,       X86::VPMINUQZ256rmkz,       0 },
2746     { X86::VPMINUWZ256rrkz,       X86::VPMINUWZ256rmkz,       0 },
2747     { X86::VPMULDQZ256rrkz,       X86::VPMULDQZ256rmkz,       0 },
2748     { X86::VPMULLDZ256rrkz,       X86::VPMULLDZ256rmkz,       0 },
2749     { X86::VPMULLQZ256rrkz,       X86::VPMULLQZ256rmkz,       0 },
2750     { X86::VPMULLWZ256rrkz,       X86::VPMULLWZ256rmkz,       0 },
2751     { X86::VPMULUDQZ256rrkz,      X86::VPMULUDQZ256rmkz,      0 },
2752     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2753     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2754     { X86::VPSHUFBZ256rrkz,       X86::VPSHUFBZ256rmkz,       0 },
2755     { X86::VPSLLDZ256rrkz,        X86::VPSLLDZ256rmkz,        0 },
2756     { X86::VPSLLQZ256rrkz,        X86::VPSLLQZ256rmkz,        0 },
2757     { X86::VPSLLVDZ256rrkz,       X86::VPSLLVDZ256rmkz,       0 },
2758     { X86::VPSLLVQZ256rrkz,       X86::VPSLLVQZ256rmkz,       0 },
2759     { X86::VPSLLVWZ256rrkz,       X86::VPSLLVWZ256rmkz,       0 },
2760     { X86::VPSLLWZ256rrkz,        X86::VPSLLWZ256rmkz,        0 },
2761     { X86::VPSRADZ256rrkz,        X86::VPSRADZ256rmkz,        0 },
2762     { X86::VPSRAQZ256rrkz,        X86::VPSRAQZ256rmkz,        0 },
2763     { X86::VPSRAVDZ256rrkz,       X86::VPSRAVDZ256rmkz,       0 },
2764     { X86::VPSRAVQZ256rrkz,       X86::VPSRAVQZ256rmkz,       0 },
2765     { X86::VPSRAVWZ256rrkz,       X86::VPSRAVWZ256rmkz,       0 },
2766     { X86::VPSRAWZ256rrkz,        X86::VPSRAWZ256rmkz,        0 },
2767     { X86::VPSRLDZ256rrkz,        X86::VPSRLDZ256rmkz,        0 },
2768     { X86::VPSRLQZ256rrkz,        X86::VPSRLQZ256rmkz,        0 },
2769     { X86::VPSRLVDZ256rrkz,       X86::VPSRLVDZ256rmkz,       0 },
2770     { X86::VPSRLVQZ256rrkz,       X86::VPSRLVQZ256rmkz,       0 },
2771     { X86::VPSRLVWZ256rrkz,       X86::VPSRLVWZ256rmkz,       0 },
2772     { X86::VPSRLWZ256rrkz,        X86::VPSRLWZ256rmkz,        0 },
2773     { X86::VPSUBBZ256rrkz,        X86::VPSUBBZ256rmkz,        0 },
2774     { X86::VPSUBDZ256rrkz,        X86::VPSUBDZ256rmkz,        0 },
2775     { X86::VPSUBQZ256rrkz,        X86::VPSUBQZ256rmkz,        0 },
2776     { X86::VPSUBSBZ256rrkz,       X86::VPSUBSBZ256rmkz,       0 },
2777     { X86::VPSUBSWZ256rrkz,       X86::VPSUBSWZ256rmkz,       0 },
2778     { X86::VPSUBUSBZ256rrkz,      X86::VPSUBUSBZ256rmkz,      0 },
2779     { X86::VPSUBUSWZ256rrkz,      X86::VPSUBUSWZ256rmkz,      0 },
2780     { X86::VPSUBWZ256rrkz,        X86::VPSUBWZ256rmkz,        0 },
2781     { X86::VPUNPCKHBWZ256rrkz,    X86::VPUNPCKHBWZ256rmkz,    0 },
2782     { X86::VPUNPCKHDQZ256rrkz,    X86::VPUNPCKHDQZ256rmkz,    0 },
2783     { X86::VPUNPCKHQDQZ256rrkz,   X86::VPUNPCKHQDQZ256rmkz,   0 },
2784     { X86::VPUNPCKHWDZ256rrkz,    X86::VPUNPCKHWDZ256rmkz,    0 },
2785     { X86::VPUNPCKLBWZ256rrkz,    X86::VPUNPCKLBWZ256rmkz,    0 },
2786     { X86::VPUNPCKLDQZ256rrkz,    X86::VPUNPCKLDQZ256rmkz,    0 },
2787     { X86::VPUNPCKLQDQZ256rrkz,   X86::VPUNPCKLQDQZ256rmkz,   0 },
2788     { X86::VPUNPCKLWDZ256rrkz,    X86::VPUNPCKLWDZ256rmkz,    0 },
2789     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2790     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2791     { X86::VSHUFPDZ256rrikz,      X86::VSHUFPDZ256rmikz,      0 },
2792     { X86::VSHUFPSZ256rrikz,      X86::VSHUFPSZ256rmikz,      0 },
2793     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2794     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2795     { X86::VUNPCKHPDZ256rrkz,     X86::VUNPCKHPDZ256rmkz,     0 },
2796     { X86::VUNPCKHPSZ256rrkz,     X86::VUNPCKHPSZ256rmkz,     0 },
2797     { X86::VUNPCKLPDZ256rrkz,     X86::VUNPCKLPDZ256rmkz,     0 },
2798     { X86::VUNPCKLPSZ256rrkz,     X86::VUNPCKLPSZ256rmkz,     0 },
2799     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2800     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2801 
2802     // AVX-512{F,VL} masked arithmetic instructions 128-bit
2803     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2804     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2805     { X86::VALIGNDZ128rrikz,      X86::VALIGNDZ128rmikz,      0 },
2806     { X86::VALIGNQZ128rrikz,      X86::VALIGNQZ128rmikz,      0 },
2807     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2808     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2809     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2810     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2811     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2812     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2813     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2814     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2815     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2816     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2817     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2818     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2819     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2820     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2821     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2822     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2823     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2824     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2825     { X86::VPACKSSDWZ128rrkz,     X86::VPACKSSDWZ128rmkz,     0 },
2826     { X86::VPACKSSWBZ128rrkz,     X86::VPACKSSWBZ128rmkz,     0 },
2827     { X86::VPACKUSDWZ128rrkz,     X86::VPACKUSDWZ128rmkz,     0 },
2828     { X86::VPACKUSWBZ128rrkz,     X86::VPACKUSWBZ128rmkz,     0 },
2829     { X86::VPADDBZ128rrkz,        X86::VPADDBZ128rmkz,        0 },
2830     { X86::VPADDDZ128rrkz,        X86::VPADDDZ128rmkz,        0 },
2831     { X86::VPADDQZ128rrkz,        X86::VPADDQZ128rmkz,        0 },
2832     { X86::VPADDSBZ128rrkz,       X86::VPADDSBZ128rmkz,       0 },
2833     { X86::VPADDSWZ128rrkz,       X86::VPADDSWZ128rmkz,       0 },
2834     { X86::VPADDUSBZ128rrkz,      X86::VPADDUSBZ128rmkz,      0 },
2835     { X86::VPADDUSWZ128rrkz,      X86::VPADDUSWZ128rmkz,      0 },
2836     { X86::VPADDWZ128rrkz,        X86::VPADDWZ128rmkz,        0 },
2837     { X86::VPALIGNRZ128rrikz,     X86::VPALIGNRZ128rmikz,     0 },
2838     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2839     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2840     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2841     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2842     { X86::VPAVGBZ128rrkz,        X86::VPAVGBZ128rmkz,        0 },
2843     { X86::VPAVGWZ128rrkz,        X86::VPAVGWZ128rmkz,        0 },
2844     { X86::VPERMBZ128rrkz,        X86::VPERMBZ128rmkz,        0 },
2845     { X86::VPERMILPDZ128rrkz,     X86::VPERMILPDZ128rmkz,     0 },
2846     { X86::VPERMILPSZ128rrkz,     X86::VPERMILPSZ128rmkz,     0 },
2847     { X86::VPERMWZ128rrkz,        X86::VPERMWZ128rmkz,        0 },
2848     { X86::VPMADDUBSWZ128rrkz,    X86::VPMADDUBSWZ128rmkz,    0 },
2849     { X86::VPMADDWDZ128rrkz,      X86::VPMADDWDZ128rmkz,      0 },
2850     { X86::VPMAXSBZ128rrkz,       X86::VPMAXSBZ128rmkz,       0 },
2851     { X86::VPMAXSDZ128rrkz,       X86::VPMAXSDZ128rmkz,       0 },
2852     { X86::VPMAXSQZ128rrkz,       X86::VPMAXSQZ128rmkz,       0 },
2853     { X86::VPMAXSWZ128rrkz,       X86::VPMAXSWZ128rmkz,       0 },
2854     { X86::VPMAXUBZ128rrkz,       X86::VPMAXUBZ128rmkz,       0 },
2855     { X86::VPMAXUDZ128rrkz,       X86::VPMAXUDZ128rmkz,       0 },
2856     { X86::VPMAXUQZ128rrkz,       X86::VPMAXUQZ128rmkz,       0 },
2857     { X86::VPMAXUWZ128rrkz,       X86::VPMAXUWZ128rmkz,       0 },
2858     { X86::VPMINSBZ128rrkz,       X86::VPMINSBZ128rmkz,       0 },
2859     { X86::VPMINSDZ128rrkz,       X86::VPMINSDZ128rmkz,       0 },
2860     { X86::VPMINSQZ128rrkz,       X86::VPMINSQZ128rmkz,       0 },
2861     { X86::VPMINSWZ128rrkz,       X86::VPMINSWZ128rmkz,       0 },
2862     { X86::VPMINUBZ128rrkz,       X86::VPMINUBZ128rmkz,       0 },
2863     { X86::VPMINUDZ128rrkz,       X86::VPMINUDZ128rmkz,       0 },
2864     { X86::VPMINUQZ128rrkz,       X86::VPMINUQZ128rmkz,       0 },
2865     { X86::VPMINUWZ128rrkz,       X86::VPMINUWZ128rmkz,       0 },
2866     { X86::VPMULDQZ128rrkz,       X86::VPMULDQZ128rmkz,       0 },
2867     { X86::VPMULLDZ128rrkz,       X86::VPMULLDZ128rmkz,       0 },
2868     { X86::VPMULLQZ128rrkz,       X86::VPMULLQZ128rmkz,       0 },
2869     { X86::VPMULLWZ128rrkz,       X86::VPMULLWZ128rmkz,       0 },
2870     { X86::VPMULUDQZ128rrkz,      X86::VPMULUDQZ128rmkz,      0 },
2871     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
2872     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
2873     { X86::VPSHUFBZ128rrkz,       X86::VPSHUFBZ128rmkz,       0 },
2874     { X86::VPSLLDZ128rrkz,        X86::VPSLLDZ128rmkz,        0 },
2875     { X86::VPSLLQZ128rrkz,        X86::VPSLLQZ128rmkz,        0 },
2876     { X86::VPSLLVDZ128rrkz,       X86::VPSLLVDZ128rmkz,       0 },
2877     { X86::VPSLLVQZ128rrkz,       X86::VPSLLVQZ128rmkz,       0 },
2878     { X86::VPSLLVWZ128rrkz,       X86::VPSLLVWZ128rmkz,       0 },
2879     { X86::VPSLLWZ128rrkz,        X86::VPSLLWZ128rmkz,        0 },
2880     { X86::VPSRADZ128rrkz,        X86::VPSRADZ128rmkz,        0 },
2881     { X86::VPSRAQZ128rrkz,        X86::VPSRAQZ128rmkz,        0 },
2882     { X86::VPSRAVDZ128rrkz,       X86::VPSRAVDZ128rmkz,       0 },
2883     { X86::VPSRAVQZ128rrkz,       X86::VPSRAVQZ128rmkz,       0 },
2884     { X86::VPSRAVWZ128rrkz,       X86::VPSRAVWZ128rmkz,       0 },
2885     { X86::VPSRAWZ128rrkz,        X86::VPSRAWZ128rmkz,        0 },
2886     { X86::VPSRLDZ128rrkz,        X86::VPSRLDZ128rmkz,        0 },
2887     { X86::VPSRLQZ128rrkz,        X86::VPSRLQZ128rmkz,        0 },
2888     { X86::VPSRLVDZ128rrkz,       X86::VPSRLVDZ128rmkz,       0 },
2889     { X86::VPSRLVQZ128rrkz,       X86::VPSRLVQZ128rmkz,       0 },
2890     { X86::VPSRLVWZ128rrkz,       X86::VPSRLVWZ128rmkz,       0 },
2891     { X86::VPSRLWZ128rrkz,        X86::VPSRLWZ128rmkz,        0 },
2892     { X86::VPSUBBZ128rrkz,        X86::VPSUBBZ128rmkz,        0 },
2893     { X86::VPSUBDZ128rrkz,        X86::VPSUBDZ128rmkz,        0 },
2894     { X86::VPSUBQZ128rrkz,        X86::VPSUBQZ128rmkz,        0 },
2895     { X86::VPSUBSBZ128rrkz,       X86::VPSUBSBZ128rmkz,       0 },
2896     { X86::VPSUBSWZ128rrkz,       X86::VPSUBSWZ128rmkz,       0 },
2897     { X86::VPSUBUSBZ128rrkz,      X86::VPSUBUSBZ128rmkz,      0 },
2898     { X86::VPSUBUSWZ128rrkz,      X86::VPSUBUSWZ128rmkz,      0 },
2899     { X86::VPSUBWZ128rrkz,        X86::VPSUBWZ128rmkz,        0 },
2900     { X86::VPUNPCKHBWZ128rrkz,    X86::VPUNPCKHBWZ128rmkz,    0 },
2901     { X86::VPUNPCKHDQZ128rrkz,    X86::VPUNPCKHDQZ128rmkz,    0 },
2902     { X86::VPUNPCKHQDQZ128rrkz,   X86::VPUNPCKHQDQZ128rmkz,   0 },
2903     { X86::VPUNPCKHWDZ128rrkz,    X86::VPUNPCKHWDZ128rmkz,    0 },
2904     { X86::VPUNPCKLBWZ128rrkz,    X86::VPUNPCKLBWZ128rmkz,    0 },
2905     { X86::VPUNPCKLDQZ128rrkz,    X86::VPUNPCKLDQZ128rmkz,    0 },
2906     { X86::VPUNPCKLQDQZ128rrkz,   X86::VPUNPCKLQDQZ128rmkz,   0 },
2907     { X86::VPUNPCKLWDZ128rrkz,    X86::VPUNPCKLWDZ128rmkz,    0 },
2908     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
2909     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
2910     { X86::VSHUFPDZ128rrikz,      X86::VSHUFPDZ128rmikz,      0 },
2911     { X86::VSHUFPSZ128rrikz,      X86::VSHUFPSZ128rmikz,      0 },
2912     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
2913     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
2914     { X86::VUNPCKHPDZ128rrkz,     X86::VUNPCKHPDZ128rmkz,     0 },
2915     { X86::VUNPCKHPSZ128rrkz,     X86::VUNPCKHPSZ128rmkz,     0 },
2916     { X86::VUNPCKLPDZ128rrkz,     X86::VUNPCKLPDZ128rmkz,     0 },
2917     { X86::VUNPCKLPSZ128rrkz,     X86::VUNPCKLPSZ128rmkz,     0 },
2918     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
2919     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
2920 
2921     // AVX-512 masked foldable instructions
2922     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
2923     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
2924     { X86::VPABSBZrrk,            X86::VPABSBZrmk,            0 },
2925     { X86::VPABSDZrrk,            X86::VPABSDZrmk,            0 },
2926     { X86::VPABSQZrrk,            X86::VPABSQZrmk,            0 },
2927     { X86::VPABSWZrrk,            X86::VPABSWZrmk,            0 },
2928     { X86::VPERMILPDZrik,         X86::VPERMILPDZmik,         0 },
2929     { X86::VPERMILPSZrik,         X86::VPERMILPSZmik,         0 },
2930     { X86::VPERMPDZrik,           X86::VPERMPDZmik,           0 },
2931     { X86::VPERMQZrik,            X86::VPERMQZmik,            0 },
2932     { X86::VPMOVSXBDZrrk,         X86::VPMOVSXBDZrmk,         0 },
2933     { X86::VPMOVSXBQZrrk,         X86::VPMOVSXBQZrmk,         TB_NO_REVERSE },
2934     { X86::VPMOVSXBWZrrk,         X86::VPMOVSXBWZrmk,         0 },
2935     { X86::VPMOVSXDQZrrk,         X86::VPMOVSXDQZrmk,         0 },
2936     { X86::VPMOVSXWDZrrk,         X86::VPMOVSXWDZrmk,         0 },
2937     { X86::VPMOVSXWQZrrk,         X86::VPMOVSXWQZrmk,         0 },
2938     { X86::VPMOVZXBDZrrk,         X86::VPMOVZXBDZrmk,         0 },
2939     { X86::VPMOVZXBQZrrk,         X86::VPMOVZXBQZrmk,         TB_NO_REVERSE },
2940     { X86::VPMOVZXBWZrrk,         X86::VPMOVZXBWZrmk,         0 },
2941     { X86::VPMOVZXDQZrrk,         X86::VPMOVZXDQZrmk,         0 },
2942     { X86::VPMOVZXWDZrrk,         X86::VPMOVZXWDZrmk,         0 },
2943     { X86::VPMOVZXWQZrrk,         X86::VPMOVZXWQZrmk,         0 },
2944     { X86::VPSHUFDZrik,           X86::VPSHUFDZmik,           0 },
2945     { X86::VPSHUFHWZrik,          X86::VPSHUFHWZmik,          0 },
2946     { X86::VPSHUFLWZrik,          X86::VPSHUFLWZmik,          0 },
2947     { X86::VPSLLDZrik,            X86::VPSLLDZmik,            0 },
2948     { X86::VPSLLQZrik,            X86::VPSLLQZmik,            0 },
2949     { X86::VPSLLWZrik,            X86::VPSLLWZmik,            0 },
2950     { X86::VPSRADZrik,            X86::VPSRADZmik,            0 },
2951     { X86::VPSRAQZrik,            X86::VPSRAQZmik,            0 },
2952     { X86::VPSRAWZrik,            X86::VPSRAWZmik,            0 },
2953     { X86::VPSRLDZrik,            X86::VPSRLDZmik,            0 },
2954     { X86::VPSRLQZrik,            X86::VPSRLQZmik,            0 },
2955     { X86::VPSRLWZrik,            X86::VPSRLWZmik,            0 },
2956 
2957     // AVX-512VL 256-bit masked foldable instructions
2958     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
2959     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
2960     { X86::VPABSBZ256rrk,         X86::VPABSBZ256rmk,         0 },
2961     { X86::VPABSDZ256rrk,         X86::VPABSDZ256rmk,         0 },
2962     { X86::VPABSQZ256rrk,         X86::VPABSQZ256rmk,         0 },
2963     { X86::VPABSWZ256rrk,         X86::VPABSWZ256rmk,         0 },
2964     { X86::VPERMILPDZ256rik,      X86::VPERMILPDZ256mik,      0 },
2965     { X86::VPERMILPSZ256rik,      X86::VPERMILPSZ256mik,      0 },
2966     { X86::VPERMPDZ256rik,        X86::VPERMPDZ256mik,        0 },
2967     { X86::VPERMQZ256rik,         X86::VPERMQZ256mik,         0 },
2968     { X86::VPMOVSXBDZ256rrk,      X86::VPMOVSXBDZ256rmk,      TB_NO_REVERSE },
2969     { X86::VPMOVSXBQZ256rrk,      X86::VPMOVSXBQZ256rmk,      TB_NO_REVERSE },
2970     { X86::VPMOVSXBWZ256rrk,      X86::VPMOVSXBWZ256rmk,      0 },
2971     { X86::VPMOVSXDQZ256rrk,      X86::VPMOVSXDQZ256rmk,      0 },
2972     { X86::VPMOVSXWDZ256rrk,      X86::VPMOVSXWDZ256rmk,      0 },
2973     { X86::VPMOVSXWQZ256rrk,      X86::VPMOVSXWQZ256rmk,      TB_NO_REVERSE },
2974     { X86::VPMOVZXBDZ256rrk,      X86::VPMOVZXBDZ256rmk,      TB_NO_REVERSE },
2975     { X86::VPMOVZXBQZ256rrk,      X86::VPMOVZXBQZ256rmk,      TB_NO_REVERSE },
2976     { X86::VPMOVZXBWZ256rrk,      X86::VPMOVZXBWZ256rmk,      0 },
2977     { X86::VPMOVZXDQZ256rrk,      X86::VPMOVZXDQZ256rmk,      0 },
2978     { X86::VPMOVZXWDZ256rrk,      X86::VPMOVZXWDZ256rmk,      0 },
2979     { X86::VPMOVZXWQZ256rrk,      X86::VPMOVZXWQZ256rmk,      TB_NO_REVERSE },
2980     { X86::VPSHUFDZ256rik,        X86::VPSHUFDZ256mik,        0 },
2981     { X86::VPSHUFHWZ256rik,       X86::VPSHUFHWZ256mik,       0 },
2982     { X86::VPSHUFLWZ256rik,       X86::VPSHUFLWZ256mik,       0 },
2983     { X86::VPSLLDZ256rik,         X86::VPSLLDZ256mik,         0 },
2984     { X86::VPSLLQZ256rik,         X86::VPSLLQZ256mik,         0 },
2985     { X86::VPSLLWZ256rik,         X86::VPSLLWZ256mik,         0 },
2986     { X86::VPSRADZ256rik,         X86::VPSRADZ256mik,         0 },
2987     { X86::VPSRAQZ256rik,         X86::VPSRAQZ256mik,         0 },
2988     { X86::VPSRAWZ256rik,         X86::VPSRAWZ256mik,         0 },
2989     { X86::VPSRLDZ256rik,         X86::VPSRLDZ256mik,         0 },
2990     { X86::VPSRLQZ256rik,         X86::VPSRLQZ256mik,         0 },
2991     { X86::VPSRLWZ256rik,         X86::VPSRLWZ256mik,         0 },
2992 
2993     // AVX-512VL 128-bit masked foldable instructions
2994     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
2995     { X86::VPABSBZ128rrk,         X86::VPABSBZ128rmk,         0 },
2996     { X86::VPABSDZ128rrk,         X86::VPABSDZ128rmk,         0 },
2997     { X86::VPABSQZ128rrk,         X86::VPABSQZ128rmk,         0 },
2998     { X86::VPABSWZ128rrk,         X86::VPABSWZ128rmk,         0 },
2999     { X86::VPERMILPDZ128rik,      X86::VPERMILPDZ128mik,      0 },
3000     { X86::VPERMILPSZ128rik,      X86::VPERMILPSZ128mik,      0 },
3001     { X86::VPMOVSXBDZ128rrk,      X86::VPMOVSXBDZ128rmk,      TB_NO_REVERSE },
3002     { X86::VPMOVSXBQZ128rrk,      X86::VPMOVSXBQZ128rmk,      TB_NO_REVERSE },
3003     { X86::VPMOVSXBWZ128rrk,      X86::VPMOVSXBWZ128rmk,      TB_NO_REVERSE },
3004     { X86::VPMOVSXDQZ128rrk,      X86::VPMOVSXDQZ128rmk,      TB_NO_REVERSE },
3005     { X86::VPMOVSXWDZ128rrk,      X86::VPMOVSXWDZ128rmk,      TB_NO_REVERSE },
3006     { X86::VPMOVSXWQZ128rrk,      X86::VPMOVSXWQZ128rmk,      TB_NO_REVERSE },
3007     { X86::VPMOVZXBDZ128rrk,      X86::VPMOVZXBDZ128rmk,      TB_NO_REVERSE },
3008     { X86::VPMOVZXBQZ128rrk,      X86::VPMOVZXBQZ128rmk,      TB_NO_REVERSE },
3009     { X86::VPMOVZXBWZ128rrk,      X86::VPMOVZXBWZ128rmk,      TB_NO_REVERSE },
3010     { X86::VPMOVZXDQZ128rrk,      X86::VPMOVZXDQZ128rmk,      TB_NO_REVERSE },
3011     { X86::VPMOVZXWDZ128rrk,      X86::VPMOVZXWDZ128rmk,      TB_NO_REVERSE },
3012     { X86::VPMOVZXWQZ128rrk,      X86::VPMOVZXWQZ128rmk,      TB_NO_REVERSE },
3013     { X86::VPSHUFDZ128rik,        X86::VPSHUFDZ128mik,        0 },
3014     { X86::VPSHUFHWZ128rik,       X86::VPSHUFHWZ128mik,       0 },
3015     { X86::VPSHUFLWZ128rik,       X86::VPSHUFLWZ128mik,       0 },
3016     { X86::VPSLLDZ128rik,         X86::VPSLLDZ128mik,         0 },
3017     { X86::VPSLLQZ128rik,         X86::VPSLLQZ128mik,         0 },
3018     { X86::VPSLLWZ128rik,         X86::VPSLLWZ128mik,         0 },
3019     { X86::VPSRADZ128rik,         X86::VPSRADZ128mik,         0 },
3020     { X86::VPSRAQZ128rik,         X86::VPSRAQZ128mik,         0 },
3021     { X86::VPSRAWZ128rik,         X86::VPSRAWZ128mik,         0 },
3022     { X86::VPSRLDZ128rik,         X86::VPSRLDZ128mik,         0 },
3023     { X86::VPSRLQZ128rik,         X86::VPSRLQZ128mik,         0 },
3024     { X86::VPSRLWZ128rik,         X86::VPSRLWZ128mik,         0 },
3025   };
3026 
3027   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
3028     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3029                   Entry.RegOp, Entry.MemOp,
3030                   // Index 3, folded load
3031                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
3032   }
3033   auto I = X86InstrFMA3Info::rm_begin();
3034   auto E = X86InstrFMA3Info::rm_end();
3035   for (; I != E; ++I) {
3036     if (!I.getGroup()->isKMasked()) {
3037       // Intrinsic forms need to pass TB_NO_REVERSE.
3038       if (I.getGroup()->isIntrinsic()) {
3039         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3040                       I.getRegOpcode(), I.getMemOpcode(),
3041                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3042       } else {
3043         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3044                       I.getRegOpcode(), I.getMemOpcode(),
3045                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
3046       }
3047     }
3048   }
3049 
3050   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
3051     // AVX-512 foldable masked instructions
3052     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
3053     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
3054     { X86::VADDSDZrr_Intk,     X86::VADDSDZrm_Intk,       TB_NO_REVERSE },
3055     { X86::VADDSSZrr_Intk,     X86::VADDSSZrm_Intk,       TB_NO_REVERSE },
3056     { X86::VALIGNDZrrik,       X86::VALIGNDZrmik,         0 },
3057     { X86::VALIGNQZrrik,       X86::VALIGNQZrmik,         0 },
3058     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
3059     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
3060     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
3061     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
3062     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
3063     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
3064     { X86::VDIVSDZrr_Intk,     X86::VDIVSDZrm_Intk,       TB_NO_REVERSE },
3065     { X86::VDIVSSZrr_Intk,     X86::VDIVSSZrm_Intk,       TB_NO_REVERSE },
3066     { X86::VINSERTF32x4Zrrk,   X86::VINSERTF32x4Zrmk,     0 },
3067     { X86::VINSERTF32x8Zrrk,   X86::VINSERTF32x8Zrmk,     0 },
3068     { X86::VINSERTF64x2Zrrk,   X86::VINSERTF64x2Zrmk,     0 },
3069     { X86::VINSERTF64x4Zrrk,   X86::VINSERTF64x4Zrmk,     0 },
3070     { X86::VINSERTI32x4Zrrk,   X86::VINSERTI32x4Zrmk,     0 },
3071     { X86::VINSERTI32x8Zrrk,   X86::VINSERTI32x8Zrmk,     0 },
3072     { X86::VINSERTI64x2Zrrk,   X86::VINSERTI64x2Zrmk,     0 },
3073     { X86::VINSERTI64x4Zrrk,   X86::VINSERTI64x4Zrmk,     0 },
3074     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
3075     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
3076     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
3077     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
3078     { X86::VMAXSDZrr_Intk,     X86::VMAXSDZrm_Intk,       0 },
3079     { X86::VMAXSSZrr_Intk,     X86::VMAXSSZrm_Intk,       0 },
3080     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
3081     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
3082     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
3083     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
3084     { X86::VMINSDZrr_Intk,     X86::VMINSDZrm_Intk,       0 },
3085     { X86::VMINSSZrr_Intk,     X86::VMINSSZrm_Intk,       0 },
3086     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
3087     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
3088     { X86::VMULSDZrr_Intk,     X86::VMULSDZrm_Intk,       TB_NO_REVERSE },
3089     { X86::VMULSSZrr_Intk,     X86::VMULSSZrm_Intk,       TB_NO_REVERSE },
3090     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
3091     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
3092     { X86::VPACKSSDWZrrk,      X86::VPACKSSDWZrmk,        0 },
3093     { X86::VPACKSSWBZrrk,      X86::VPACKSSWBZrmk,        0 },
3094     { X86::VPACKUSDWZrrk,      X86::VPACKUSDWZrmk,        0 },
3095     { X86::VPACKUSWBZrrk,      X86::VPACKUSWBZrmk,        0 },
3096     { X86::VPADDBZrrk,         X86::VPADDBZrmk,           0 },
3097     { X86::VPADDDZrrk,         X86::VPADDDZrmk,           0 },
3098     { X86::VPADDQZrrk,         X86::VPADDQZrmk,           0 },
3099     { X86::VPADDSBZrrk,        X86::VPADDSBZrmk,          0 },
3100     { X86::VPADDSWZrrk,        X86::VPADDSWZrmk,          0 },
3101     { X86::VPADDUSBZrrk,       X86::VPADDUSBZrmk,         0 },
3102     { X86::VPADDUSWZrrk,       X86::VPADDUSWZrmk,         0 },
3103     { X86::VPADDWZrrk,         X86::VPADDWZrmk,           0 },
3104     { X86::VPALIGNRZrrik,      X86::VPALIGNRZrmik,        0 },
3105     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
3106     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
3107     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
3108     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
3109     { X86::VPAVGBZrrk,         X86::VPAVGBZrmk,           0 },
3110     { X86::VPAVGWZrrk,         X86::VPAVGWZrmk,           0 },
3111     { X86::VPERMBZrrk,         X86::VPERMBZrmk,           0 },
3112     { X86::VPERMDZrrk,         X86::VPERMDZrmk,           0 },
3113     { X86::VPERMI2Brrk,        X86::VPERMI2Brmk,          0 },
3114     { X86::VPERMI2Drrk,        X86::VPERMI2Drmk,          0 },
3115     { X86::VPERMI2PSrrk,       X86::VPERMI2PSrmk,         0 },
3116     { X86::VPERMI2PDrrk,       X86::VPERMI2PDrmk,         0 },
3117     { X86::VPERMI2Qrrk,        X86::VPERMI2Qrmk,          0 },
3118     { X86::VPERMI2Wrrk,        X86::VPERMI2Wrmk,          0 },
3119     { X86::VPERMILPDZrrk,      X86::VPERMILPDZrmk,        0 },
3120     { X86::VPERMILPSZrrk,      X86::VPERMILPSZrmk,        0 },
3121     { X86::VPERMPDZrrk,        X86::VPERMPDZrmk,          0 },
3122     { X86::VPERMPSZrrk,        X86::VPERMPSZrmk,          0 },
3123     { X86::VPERMQZrrk,         X86::VPERMQZrmk,           0 },
3124     { X86::VPERMT2Brrk,        X86::VPERMT2Brmk,          0 },
3125     { X86::VPERMT2Drrk,        X86::VPERMT2Drmk,          0 },
3126     { X86::VPERMT2PSrrk,       X86::VPERMT2PSrmk,         0 },
3127     { X86::VPERMT2PDrrk,       X86::VPERMT2PDrmk,         0 },
3128     { X86::VPERMT2Qrrk,        X86::VPERMT2Qrmk,          0 },
3129     { X86::VPERMT2Wrrk,        X86::VPERMT2Wrmk,          0 },
3130     { X86::VPERMWZrrk,         X86::VPERMWZrmk,           0 },
3131     { X86::VPMADDUBSWZrrk,     X86::VPMADDUBSWZrmk,       0 },
3132     { X86::VPMADDWDZrrk,       X86::VPMADDWDZrmk,         0 },
3133     { X86::VPMAXSBZrrk,        X86::VPMAXSBZrmk,          0 },
3134     { X86::VPMAXSDZrrk,        X86::VPMAXSDZrmk,          0 },
3135     { X86::VPMAXSQZrrk,        X86::VPMAXSQZrmk,          0 },
3136     { X86::VPMAXSWZrrk,        X86::VPMAXSWZrmk,          0 },
3137     { X86::VPMAXUBZrrk,        X86::VPMAXUBZrmk,          0 },
3138     { X86::VPMAXUDZrrk,        X86::VPMAXUDZrmk,          0 },
3139     { X86::VPMAXUQZrrk,        X86::VPMAXUQZrmk,          0 },
3140     { X86::VPMAXUWZrrk,        X86::VPMAXUWZrmk,          0 },
3141     { X86::VPMINSBZrrk,        X86::VPMINSBZrmk,          0 },
3142     { X86::VPMINSDZrrk,        X86::VPMINSDZrmk,          0 },
3143     { X86::VPMINSQZrrk,        X86::VPMINSQZrmk,          0 },
3144     { X86::VPMINSWZrrk,        X86::VPMINSWZrmk,          0 },
3145     { X86::VPMINUBZrrk,        X86::VPMINUBZrmk,          0 },
3146     { X86::VPMINUDZrrk,        X86::VPMINUDZrmk,          0 },
3147     { X86::VPMINUQZrrk,        X86::VPMINUQZrmk,          0 },
3148     { X86::VPMINUWZrrk,        X86::VPMINUWZrmk,          0 },
3149     { X86::VPMULDQZrrk,        X86::VPMULDQZrmk,          0 },
3150     { X86::VPMULLDZrrk,        X86::VPMULLDZrmk,          0 },
3151     { X86::VPMULLQZrrk,        X86::VPMULLQZrmk,          0 },
3152     { X86::VPMULLWZrrk,        X86::VPMULLWZrmk,          0 },
3153     { X86::VPMULUDQZrrk,       X86::VPMULUDQZrmk,         0 },
3154     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
3155     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
3156     { X86::VPSHUFBZrrk,        X86::VPSHUFBZrmk,          0 },
3157     { X86::VPSLLDZrrk,         X86::VPSLLDZrmk,           0 },
3158     { X86::VPSLLQZrrk,         X86::VPSLLQZrmk,           0 },
3159     { X86::VPSLLVDZrrk,        X86::VPSLLVDZrmk,          0 },
3160     { X86::VPSLLVQZrrk,        X86::VPSLLVQZrmk,          0 },
3161     { X86::VPSLLVWZrrk,        X86::VPSLLVWZrmk,          0 },
3162     { X86::VPSLLWZrrk,         X86::VPSLLWZrmk,           0 },
3163     { X86::VPSRADZrrk,         X86::VPSRADZrmk,           0 },
3164     { X86::VPSRAQZrrk,         X86::VPSRAQZrmk,           0 },
3165     { X86::VPSRAVDZrrk,        X86::VPSRAVDZrmk,          0 },
3166     { X86::VPSRAVQZrrk,        X86::VPSRAVQZrmk,          0 },
3167     { X86::VPSRAVWZrrk,        X86::VPSRAVWZrmk,          0 },
3168     { X86::VPSRAWZrrk,         X86::VPSRAWZrmk,           0 },
3169     { X86::VPSRLDZrrk,         X86::VPSRLDZrmk,           0 },
3170     { X86::VPSRLQZrrk,         X86::VPSRLQZrmk,           0 },
3171     { X86::VPSRLVDZrrk,        X86::VPSRLVDZrmk,          0 },
3172     { X86::VPSRLVQZrrk,        X86::VPSRLVQZrmk,          0 },
3173     { X86::VPSRLVWZrrk,        X86::VPSRLVWZrmk,          0 },
3174     { X86::VPSRLWZrrk,         X86::VPSRLWZrmk,           0 },
3175     { X86::VPSUBBZrrk,         X86::VPSUBBZrmk,           0 },
3176     { X86::VPSUBDZrrk,         X86::VPSUBDZrmk,           0 },
3177     { X86::VPSUBQZrrk,         X86::VPSUBQZrmk,           0 },
3178     { X86::VPSUBSBZrrk,        X86::VPSUBSBZrmk,          0 },
3179     { X86::VPSUBSWZrrk,        X86::VPSUBSWZrmk,          0 },
3180     { X86::VPSUBUSBZrrk,       X86::VPSUBUSBZrmk,         0 },
3181     { X86::VPSUBUSWZrrk,       X86::VPSUBUSWZrmk,         0 },
3182     { X86::VPTERNLOGDZrrik,    X86::VPTERNLOGDZrmik,      0 },
3183     { X86::VPTERNLOGQZrrik,    X86::VPTERNLOGQZrmik,      0 },
3184     { X86::VPUNPCKHBWZrrk,     X86::VPUNPCKHBWZrmk,       0 },
3185     { X86::VPUNPCKHDQZrrk,     X86::VPUNPCKHDQZrmk,       0 },
3186     { X86::VPUNPCKHQDQZrrk,    X86::VPUNPCKHQDQZrmk,      0 },
3187     { X86::VPUNPCKHWDZrrk,     X86::VPUNPCKHWDZrmk,       0 },
3188     { X86::VPUNPCKLBWZrrk,     X86::VPUNPCKLBWZrmk,       0 },
3189     { X86::VPUNPCKLDQZrrk,     X86::VPUNPCKLDQZrmk,       0 },
3190     { X86::VPUNPCKLQDQZrrk,    X86::VPUNPCKLQDQZrmk,      0 },
3191     { X86::VPUNPCKLWDZrrk,     X86::VPUNPCKLWDZrmk,       0 },
3192     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
3193     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
3194     { X86::VSHUFPDZrrik,       X86::VSHUFPDZrmik,         0 },
3195     { X86::VSHUFPSZrrik,       X86::VSHUFPSZrmik,         0 },
3196     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
3197     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
3198     { X86::VSUBSDZrr_Intk,     X86::VSUBSDZrm_Intk,       TB_NO_REVERSE },
3199     { X86::VSUBSSZrr_Intk,     X86::VSUBSSZrm_Intk,       TB_NO_REVERSE },
3200     { X86::VUNPCKHPDZrrk,      X86::VUNPCKHPDZrmk,        0 },
3201     { X86::VUNPCKHPSZrrk,      X86::VUNPCKHPSZrmk,        0 },
3202     { X86::VUNPCKLPDZrrk,      X86::VUNPCKLPDZrmk,        0 },
3203     { X86::VUNPCKLPSZrrk,      X86::VUNPCKLPSZrmk,        0 },
3204     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
3205     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
3206 
3207     // AVX-512{F,VL} foldable masked instructions 256-bit
3208     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
3209     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
3210     { X86::VALIGNDZ256rrik,    X86::VALIGNDZ256rmik,      0 },
3211     { X86::VALIGNQZ256rrik,    X86::VALIGNQZ256rmik,      0 },
3212     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
3213     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
3214     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
3215     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
3216     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
3217     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
3218     { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk,  0 },
3219     { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk,  0 },
3220     { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk,  0 },
3221     { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk,  0 },
3222     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
3223     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
3224     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
3225     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
3226     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
3227     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
3228     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
3229     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
3230     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
3231     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
3232     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
3233     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
3234     { X86::VPACKSSDWZ256rrk,   X86::VPACKSSDWZ256rmk,     0 },
3235     { X86::VPACKSSWBZ256rrk,   X86::VPACKSSWBZ256rmk,     0 },
3236     { X86::VPACKUSDWZ256rrk,   X86::VPACKUSDWZ256rmk,     0 },
3237     { X86::VPACKUSWBZ256rrk,   X86::VPACKUSWBZ256rmk,     0 },
3238     { X86::VPADDBZ256rrk,      X86::VPADDBZ256rmk,        0 },
3239     { X86::VPADDDZ256rrk,      X86::VPADDDZ256rmk,        0 },
3240     { X86::VPADDQZ256rrk,      X86::VPADDQZ256rmk,        0 },
3241     { X86::VPADDSBZ256rrk,     X86::VPADDSBZ256rmk,       0 },
3242     { X86::VPADDSWZ256rrk,     X86::VPADDSWZ256rmk,       0 },
3243     { X86::VPADDUSBZ256rrk,    X86::VPADDUSBZ256rmk,      0 },
3244     { X86::VPADDUSWZ256rrk,    X86::VPADDUSWZ256rmk,      0 },
3245     { X86::VPADDWZ256rrk,      X86::VPADDWZ256rmk,        0 },
3246     { X86::VPALIGNRZ256rrik,   X86::VPALIGNRZ256rmik,     0 },
3247     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
3248     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
3249     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
3250     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
3251     { X86::VPAVGBZ256rrk,      X86::VPAVGBZ256rmk,        0 },
3252     { X86::VPAVGWZ256rrk,      X86::VPAVGWZ256rmk,        0 },
3253     { X86::VPERMBZ256rrk,      X86::VPERMBZ256rmk,        0 },
3254     { X86::VPERMDZ256rrk,      X86::VPERMDZ256rmk,        0 },
3255     { X86::VPERMI2B256rrk,     X86::VPERMI2B256rmk,       0 },
3256     { X86::VPERMI2D256rrk,     X86::VPERMI2D256rmk,       0 },
3257     { X86::VPERMI2PD256rrk,    X86::VPERMI2PD256rmk,      0 },
3258     { X86::VPERMI2PS256rrk,    X86::VPERMI2PS256rmk,      0 },
3259     { X86::VPERMI2Q256rrk,     X86::VPERMI2Q256rmk,       0 },
3260     { X86::VPERMI2W256rrk,     X86::VPERMI2W256rmk,       0 },
3261     { X86::VPERMILPDZ256rrk,   X86::VPERMILPDZ256rmk,     0 },
3262     { X86::VPERMILPSZ256rrk,   X86::VPERMILPSZ256rmk,     0 },
3263     { X86::VPERMPDZ256rrk,     X86::VPERMPDZ256rmk,       0 },
3264     { X86::VPERMPSZ256rrk,     X86::VPERMPSZ256rmk,       0 },
3265     { X86::VPERMQZ256rrk,      X86::VPERMQZ256rmk,        0 },
3266     { X86::VPERMT2B256rrk,     X86::VPERMT2B256rmk,       0 },
3267     { X86::VPERMT2D256rrk,     X86::VPERMT2D256rmk,       0 },
3268     { X86::VPERMT2PD256rrk,    X86::VPERMT2PD256rmk,      0 },
3269     { X86::VPERMT2PS256rrk,    X86::VPERMT2PS256rmk,      0 },
3270     { X86::VPERMT2Q256rrk,     X86::VPERMT2Q256rmk,       0 },
3271     { X86::VPERMT2W256rrk,     X86::VPERMT2W256rmk,       0 },
3272     { X86::VPERMWZ256rrk,      X86::VPERMWZ256rmk,        0 },
3273     { X86::VPMADDUBSWZ256rrk,  X86::VPMADDUBSWZ256rmk,    0 },
3274     { X86::VPMADDWDZ256rrk,    X86::VPMADDWDZ256rmk,      0 },
3275     { X86::VPMAXSBZ256rrk,     X86::VPMAXSBZ256rmk,       0 },
3276     { X86::VPMAXSDZ256rrk,     X86::VPMAXSDZ256rmk,       0 },
3277     { X86::VPMAXSQZ256rrk,     X86::VPMAXSQZ256rmk,       0 },
3278     { X86::VPMAXSWZ256rrk,     X86::VPMAXSWZ256rmk,       0 },
3279     { X86::VPMAXUBZ256rrk,     X86::VPMAXUBZ256rmk,       0 },
3280     { X86::VPMAXUDZ256rrk,     X86::VPMAXUDZ256rmk,       0 },
3281     { X86::VPMAXUQZ256rrk,     X86::VPMAXUQZ256rmk,       0 },
3282     { X86::VPMAXUWZ256rrk,     X86::VPMAXUWZ256rmk,       0 },
3283     { X86::VPMINSBZ256rrk,     X86::VPMINSBZ256rmk,       0 },
3284     { X86::VPMINSDZ256rrk,     X86::VPMINSDZ256rmk,       0 },
3285     { X86::VPMINSQZ256rrk,     X86::VPMINSQZ256rmk,       0 },
3286     { X86::VPMINSWZ256rrk,     X86::VPMINSWZ256rmk,       0 },
3287     { X86::VPMINUBZ256rrk,     X86::VPMINUBZ256rmk,       0 },
3288     { X86::VPMINUDZ256rrk,     X86::VPMINUDZ256rmk,       0 },
3289     { X86::VPMINUQZ256rrk,     X86::VPMINUQZ256rmk,       0 },
3290     { X86::VPMINUWZ256rrk,     X86::VPMINUWZ256rmk,       0 },
3291     { X86::VPMULDQZ256rrk,     X86::VPMULDQZ256rmk,       0 },
3292     { X86::VPMULLDZ256rrk,     X86::VPMULLDZ256rmk,       0 },
3293     { X86::VPMULLQZ256rrk,     X86::VPMULLQZ256rmk,       0 },
3294     { X86::VPMULLWZ256rrk,     X86::VPMULLWZ256rmk,       0 },
3295     { X86::VPMULUDQZ256rrk,    X86::VPMULUDQZ256rmk,      0 },
3296     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
3297     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
3298     { X86::VPSHUFBZ256rrk,     X86::VPSHUFBZ256rmk,       0 },
3299     { X86::VPSLLDZ256rrk,      X86::VPSLLDZ256rmk,        0 },
3300     { X86::VPSLLQZ256rrk,      X86::VPSLLQZ256rmk,        0 },
3301     { X86::VPSLLVDZ256rrk,     X86::VPSLLVDZ256rmk,       0 },
3302     { X86::VPSLLVQZ256rrk,     X86::VPSLLVQZ256rmk,       0 },
3303     { X86::VPSLLVWZ256rrk,     X86::VPSLLVWZ256rmk,       0 },
3304     { X86::VPSLLWZ256rrk,      X86::VPSLLWZ256rmk,        0 },
3305     { X86::VPSRADZ256rrk,      X86::VPSRADZ256rmk,        0 },
3306     { X86::VPSRAQZ256rrk,      X86::VPSRAQZ256rmk,        0 },
3307     { X86::VPSRAVDZ256rrk,     X86::VPSRAVDZ256rmk,       0 },
3308     { X86::VPSRAVQZ256rrk,     X86::VPSRAVQZ256rmk,       0 },
3309     { X86::VPSRAVWZ256rrk,     X86::VPSRAVWZ256rmk,       0 },
3310     { X86::VPSRAWZ256rrk,      X86::VPSRAWZ256rmk,        0 },
3311     { X86::VPSRLDZ256rrk,      X86::VPSRLDZ256rmk,        0 },
3312     { X86::VPSRLQZ256rrk,      X86::VPSRLQZ256rmk,        0 },
3313     { X86::VPSRLVDZ256rrk,     X86::VPSRLVDZ256rmk,       0 },
3314     { X86::VPSRLVQZ256rrk,     X86::VPSRLVQZ256rmk,       0 },
3315     { X86::VPSRLVWZ256rrk,     X86::VPSRLVWZ256rmk,       0 },
3316     { X86::VPSRLWZ256rrk,      X86::VPSRLWZ256rmk,        0 },
3317     { X86::VPSUBBZ256rrk,      X86::VPSUBBZ256rmk,        0 },
3318     { X86::VPSUBDZ256rrk,      X86::VPSUBDZ256rmk,        0 },
3319     { X86::VPSUBQZ256rrk,      X86::VPSUBQZ256rmk,        0 },
3320     { X86::VPSUBSBZ256rrk,     X86::VPSUBSBZ256rmk,       0 },
3321     { X86::VPSUBSWZ256rrk,     X86::VPSUBSWZ256rmk,       0 },
3322     { X86::VPSUBUSBZ256rrk,    X86::VPSUBUSBZ256rmk,      0 },
3323     { X86::VPSUBUSWZ256rrk,    X86::VPSUBUSWZ256rmk,      0 },
3324     { X86::VPSUBWZ256rrk,      X86::VPSUBWZ256rmk,        0 },
3325     { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,   0 },
3326     { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,   0 },
3327     { X86::VPUNPCKHBWZ256rrk,  X86::VPUNPCKHBWZ256rmk,    0 },
3328     { X86::VPUNPCKHDQZ256rrk,  X86::VPUNPCKHDQZ256rmk,    0 },
3329     { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk,   0 },
3330     { X86::VPUNPCKHWDZ256rrk,  X86::VPUNPCKHWDZ256rmk,    0 },
3331     { X86::VPUNPCKLBWZ256rrk,  X86::VPUNPCKLBWZ256rmk,    0 },
3332     { X86::VPUNPCKLDQZ256rrk,  X86::VPUNPCKLDQZ256rmk,    0 },
3333     { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk,   0 },
3334     { X86::VPUNPCKLWDZ256rrk,  X86::VPUNPCKLWDZ256rmk,    0 },
3335     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
3336     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
3337     { X86::VSHUFPDZ256rrik,    X86::VSHUFPDZ256rmik,      0 },
3338     { X86::VSHUFPSZ256rrik,    X86::VSHUFPSZ256rmik,      0 },
3339     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
3340     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
3341     { X86::VUNPCKHPDZ256rrk,   X86::VUNPCKHPDZ256rmk,     0 },
3342     { X86::VUNPCKHPSZ256rrk,   X86::VUNPCKHPSZ256rmk,     0 },
3343     { X86::VUNPCKLPDZ256rrk,   X86::VUNPCKLPDZ256rmk,     0 },
3344     { X86::VUNPCKLPSZ256rrk,   X86::VUNPCKLPSZ256rmk,     0 },
3345     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
3346     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
3347 
3348     // AVX-512{F,VL} foldable instructions 128-bit
3349     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
3350     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
3351     { X86::VALIGNDZ128rrik,    X86::VALIGNDZ128rmik,      0 },
3352     { X86::VALIGNQZ128rrik,    X86::VALIGNQZ128rmik,      0 },
3353     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
3354     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
3355     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
3356     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
3357     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
3358     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
3359     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
3360     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
3361     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
3362     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
3363     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
3364     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
3365     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
3366     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
3367     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
3368     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
3369     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
3370     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
3371     { X86::VPACKSSDWZ128rrk,   X86::VPACKSSDWZ128rmk,     0 },
3372     { X86::VPACKSSWBZ128rrk,   X86::VPACKSSWBZ128rmk,     0 },
3373     { X86::VPACKUSDWZ128rrk,   X86::VPACKUSDWZ128rmk,     0 },
3374     { X86::VPACKUSWBZ128rrk,   X86::VPACKUSWBZ128rmk,     0 },
3375     { X86::VPADDBZ128rrk,      X86::VPADDBZ128rmk,        0 },
3376     { X86::VPADDDZ128rrk,      X86::VPADDDZ128rmk,        0 },
3377     { X86::VPADDQZ128rrk,      X86::VPADDQZ128rmk,        0 },
3378     { X86::VPADDSBZ128rrk,     X86::VPADDSBZ128rmk,       0 },
3379     { X86::VPADDSWZ128rrk,     X86::VPADDSWZ128rmk,       0 },
3380     { X86::VPADDUSBZ128rrk,    X86::VPADDUSBZ128rmk,      0 },
3381     { X86::VPADDUSWZ128rrk,    X86::VPADDUSWZ128rmk,      0 },
3382     { X86::VPADDWZ128rrk,      X86::VPADDWZ128rmk,        0 },
3383     { X86::VPALIGNRZ128rrik,   X86::VPALIGNRZ128rmik,     0 },
3384     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
3385     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
3386     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
3387     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
3388     { X86::VPAVGBZ128rrk,      X86::VPAVGBZ128rmk,        0 },
3389     { X86::VPAVGWZ128rrk,      X86::VPAVGWZ128rmk,        0 },
3390     { X86::VPERMBZ128rrk,      X86::VPERMBZ128rmk,        0 },
3391     { X86::VPERMI2B128rrk,     X86::VPERMI2B128rmk,       0 },
3392     { X86::VPERMI2D128rrk,     X86::VPERMI2D128rmk,       0 },
3393     { X86::VPERMI2PD128rrk,    X86::VPERMI2PD128rmk,      0 },
3394     { X86::VPERMI2PS128rrk,    X86::VPERMI2PS128rmk,      0 },
3395     { X86::VPERMI2Q128rrk,     X86::VPERMI2Q128rmk,       0 },
3396     { X86::VPERMI2W128rrk,     X86::VPERMI2W128rmk,       0 },
3397     { X86::VPERMILPDZ128rrk,   X86::VPERMILPDZ128rmk,     0 },
3398     { X86::VPERMILPSZ128rrk,   X86::VPERMILPSZ128rmk,     0 },
3399     { X86::VPERMT2B128rrk,     X86::VPERMT2B128rmk,       0 },
3400     { X86::VPERMT2D128rrk,     X86::VPERMT2D128rmk,       0 },
3401     { X86::VPERMT2PD128rrk,    X86::VPERMT2PD128rmk,      0 },
3402     { X86::VPERMT2PS128rrk,    X86::VPERMT2PS128rmk,      0 },
3403     { X86::VPERMT2Q128rrk,     X86::VPERMT2Q128rmk,       0 },
3404     { X86::VPERMT2W128rrk,     X86::VPERMT2W128rmk,       0 },
3405     { X86::VPERMWZ128rrk,      X86::VPERMWZ128rmk,        0 },
3406     { X86::VPMADDUBSWZ128rrk,  X86::VPMADDUBSWZ128rmk,    0 },
3407     { X86::VPMADDWDZ128rrk,    X86::VPMADDWDZ128rmk,      0 },
3408     { X86::VPMAXSBZ128rrk,     X86::VPMAXSBZ128rmk,       0 },
3409     { X86::VPMAXSDZ128rrk,     X86::VPMAXSDZ128rmk,       0 },
3410     { X86::VPMAXSQZ128rrk,     X86::VPMAXSQZ128rmk,       0 },
3411     { X86::VPMAXSWZ128rrk,     X86::VPMAXSWZ128rmk,       0 },
3412     { X86::VPMAXUBZ128rrk,     X86::VPMAXUBZ128rmk,       0 },
3413     { X86::VPMAXUDZ128rrk,     X86::VPMAXUDZ128rmk,       0 },
3414     { X86::VPMAXUQZ128rrk,     X86::VPMAXUQZ128rmk,       0 },
3415     { X86::VPMAXUWZ128rrk,     X86::VPMAXUWZ128rmk,       0 },
3416     { X86::VPMINSBZ128rrk,     X86::VPMINSBZ128rmk,       0 },
3417     { X86::VPMINSDZ128rrk,     X86::VPMINSDZ128rmk,       0 },
3418     { X86::VPMINSQZ128rrk,     X86::VPMINSQZ128rmk,       0 },
3419     { X86::VPMINSWZ128rrk,     X86::VPMINSWZ128rmk,       0 },
3420     { X86::VPMINUBZ128rrk,     X86::VPMINUBZ128rmk,       0 },
3421     { X86::VPMINUDZ128rrk,     X86::VPMINUDZ128rmk,       0 },
3422     { X86::VPMINUQZ128rrk,     X86::VPMINUQZ128rmk,       0 },
3423     { X86::VPMINUWZ128rrk,     X86::VPMINUWZ128rmk,       0 },
3424     { X86::VPMULDQZ128rrk,     X86::VPMULDQZ128rmk,       0 },
3425     { X86::VPMULLDZ128rrk,     X86::VPMULLDZ128rmk,       0 },
3426     { X86::VPMULLQZ128rrk,     X86::VPMULLQZ128rmk,       0 },
3427     { X86::VPMULLWZ128rrk,     X86::VPMULLWZ128rmk,       0 },
3428     { X86::VPMULUDQZ128rrk,    X86::VPMULUDQZ128rmk,      0 },
3429     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
3430     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
3431     { X86::VPSHUFBZ128rrk,     X86::VPSHUFBZ128rmk,       0 },
3432     { X86::VPSLLDZ128rrk,      X86::VPSLLDZ128rmk,        0 },
3433     { X86::VPSLLQZ128rrk,      X86::VPSLLQZ128rmk,        0 },
3434     { X86::VPSLLVDZ128rrk,     X86::VPSLLVDZ128rmk,       0 },
3435     { X86::VPSLLVQZ128rrk,     X86::VPSLLVQZ128rmk,       0 },
3436     { X86::VPSLLVWZ128rrk,     X86::VPSLLVWZ128rmk,       0 },
3437     { X86::VPSLLWZ128rrk,      X86::VPSLLWZ128rmk,        0 },
3438     { X86::VPSRADZ128rrk,      X86::VPSRADZ128rmk,        0 },
3439     { X86::VPSRAQZ128rrk,      X86::VPSRAQZ128rmk,        0 },
3440     { X86::VPSRAVDZ128rrk,     X86::VPSRAVDZ128rmk,       0 },
3441     { X86::VPSRAVQZ128rrk,     X86::VPSRAVQZ128rmk,       0 },
3442     { X86::VPSRAVWZ128rrk,     X86::VPSRAVWZ128rmk,       0 },
3443     { X86::VPSRAWZ128rrk,      X86::VPSRAWZ128rmk,        0 },
3444     { X86::VPSRLDZ128rrk,      X86::VPSRLDZ128rmk,        0 },
3445     { X86::VPSRLQZ128rrk,      X86::VPSRLQZ128rmk,        0 },
3446     { X86::VPSRLVDZ128rrk,     X86::VPSRLVDZ128rmk,       0 },
3447     { X86::VPSRLVQZ128rrk,     X86::VPSRLVQZ128rmk,       0 },
3448     { X86::VPSRLVWZ128rrk,     X86::VPSRLVWZ128rmk,       0 },
3449     { X86::VPSRLWZ128rrk,      X86::VPSRLWZ128rmk,        0 },
3450     { X86::VPSUBBZ128rrk,      X86::VPSUBBZ128rmk,        0 },
3451     { X86::VPSUBDZ128rrk,      X86::VPSUBDZ128rmk,        0 },
3452     { X86::VPSUBQZ128rrk,      X86::VPSUBQZ128rmk,        0 },
3453     { X86::VPSUBSBZ128rrk,     X86::VPSUBSBZ128rmk,       0 },
3454     { X86::VPSUBSWZ128rrk,     X86::VPSUBSWZ128rmk,       0 },
3455     { X86::VPSUBUSBZ128rrk,    X86::VPSUBUSBZ128rmk,      0 },
3456     { X86::VPSUBUSWZ128rrk,    X86::VPSUBUSWZ128rmk,      0 },
3457     { X86::VPSUBWZ128rrk,      X86::VPSUBWZ128rmk,        0 },
3458     { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,   0 },
3459     { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,   0 },
3460     { X86::VPUNPCKHBWZ128rrk,  X86::VPUNPCKHBWZ128rmk,    0 },
3461     { X86::VPUNPCKHDQZ128rrk,  X86::VPUNPCKHDQZ128rmk,    0 },
3462     { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk,   0 },
3463     { X86::VPUNPCKHWDZ128rrk,  X86::VPUNPCKHWDZ128rmk,    0 },
3464     { X86::VPUNPCKLBWZ128rrk,  X86::VPUNPCKLBWZ128rmk,    0 },
3465     { X86::VPUNPCKLDQZ128rrk,  X86::VPUNPCKLDQZ128rmk,    0 },
3466     { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk,   0 },
3467     { X86::VPUNPCKLWDZ128rrk,  X86::VPUNPCKLWDZ128rmk,    0 },
3468     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
3469     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
3470     { X86::VSHUFPDZ128rrik,    X86::VSHUFPDZ128rmik,      0 },
3471     { X86::VSHUFPSZ128rrik,    X86::VSHUFPSZ128rmik,      0 },
3472     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
3473     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
3474     { X86::VUNPCKHPDZ128rrk,   X86::VUNPCKHPDZ128rmk,     0 },
3475     { X86::VUNPCKHPSZ128rrk,   X86::VUNPCKHPSZ128rmk,     0 },
3476     { X86::VUNPCKLPDZ128rrk,   X86::VUNPCKLPDZ128rmk,     0 },
3477     { X86::VUNPCKLPSZ128rrk,   X86::VUNPCKLPSZ128rmk,     0 },
3478     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
3479     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
3480 
3481     // 512-bit three source instructions with zero masking.
3482     { X86::VPERMI2Brrkz,       X86::VPERMI2Brmkz,         0 },
3483     { X86::VPERMI2Drrkz,       X86::VPERMI2Drmkz,         0 },
3484     { X86::VPERMI2PSrrkz,      X86::VPERMI2PSrmkz,        0 },
3485     { X86::VPERMI2PDrrkz,      X86::VPERMI2PDrmkz,        0 },
3486     { X86::VPERMI2Qrrkz,       X86::VPERMI2Qrmkz,         0 },
3487     { X86::VPERMI2Wrrkz,       X86::VPERMI2Wrmkz,         0 },
3488     { X86::VPERMT2Brrkz,       X86::VPERMT2Brmkz,         0 },
3489     { X86::VPERMT2Drrkz,       X86::VPERMT2Drmkz,         0 },
3490     { X86::VPERMT2PSrrkz,      X86::VPERMT2PSrmkz,        0 },
3491     { X86::VPERMT2PDrrkz,      X86::VPERMT2PDrmkz,        0 },
3492     { X86::VPERMT2Qrrkz,       X86::VPERMT2Qrmkz,         0 },
3493     { X86::VPERMT2Wrrkz,       X86::VPERMT2Wrmkz,         0 },
3494     { X86::VPTERNLOGDZrrikz,   X86::VPTERNLOGDZrmikz,     0 },
3495     { X86::VPTERNLOGQZrrikz,   X86::VPTERNLOGQZrmikz,     0 },
3496 
3497     // 256-bit three source instructions with zero masking.
3498     { X86::VPERMI2B256rrkz,    X86::VPERMI2B256rmkz,      0 },
3499     { X86::VPERMI2D256rrkz,    X86::VPERMI2D256rmkz,      0 },
3500     { X86::VPERMI2PD256rrkz,   X86::VPERMI2PD256rmkz,     0 },
3501     { X86::VPERMI2PS256rrkz,   X86::VPERMI2PS256rmkz,     0 },
3502     { X86::VPERMI2Q256rrkz,    X86::VPERMI2Q256rmkz,      0 },
3503     { X86::VPERMI2W256rrkz,    X86::VPERMI2W256rmkz,      0 },
3504     { X86::VPERMT2B256rrkz,    X86::VPERMT2B256rmkz,      0 },
3505     { X86::VPERMT2D256rrkz,    X86::VPERMT2D256rmkz,      0 },
3506     { X86::VPERMT2PD256rrkz,   X86::VPERMT2PD256rmkz,     0 },
3507     { X86::VPERMT2PS256rrkz,   X86::VPERMT2PS256rmkz,     0 },
3508     { X86::VPERMT2Q256rrkz,    X86::VPERMT2Q256rmkz,      0 },
3509     { X86::VPERMT2W256rrkz,    X86::VPERMT2W256rmkz,      0 },
3510     { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz,  0 },
3511     { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz,  0 },
3512 
3513     // 128-bit three source instructions with zero masking.
3514     { X86::VPERMI2B128rrkz,    X86::VPERMI2B128rmkz,      0 },
3515     { X86::VPERMI2D128rrkz,    X86::VPERMI2D128rmkz,      0 },
3516     { X86::VPERMI2PD128rrkz,   X86::VPERMI2PD128rmkz,     0 },
3517     { X86::VPERMI2PS128rrkz,   X86::VPERMI2PS128rmkz,     0 },
3518     { X86::VPERMI2Q128rrkz,    X86::VPERMI2Q128rmkz,      0 },
3519     { X86::VPERMI2W128rrkz,    X86::VPERMI2W128rmkz,      0 },
3520     { X86::VPERMT2B128rrkz,    X86::VPERMT2B128rmkz,      0 },
3521     { X86::VPERMT2D128rrkz,    X86::VPERMT2D128rmkz,      0 },
3522     { X86::VPERMT2PD128rrkz,   X86::VPERMT2PD128rmkz,     0 },
3523     { X86::VPERMT2PS128rrkz,   X86::VPERMT2PS128rmkz,     0 },
3524     { X86::VPERMT2Q128rrkz,    X86::VPERMT2Q128rmkz,      0 },
3525     { X86::VPERMT2W128rrkz,    X86::VPERMT2W128rmkz,      0 },
3526     { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz,  0 },
3527     { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz,  0 },
3528   };
3529 
3530   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
3531     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3532                   Entry.RegOp, Entry.MemOp,
3533                   // Index 4, folded load
3534                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
3535   }
3536   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {
3537     if (I.getGroup()->isKMasked()) {
3538       // Intrinsics need to pass TB_NO_REVERSE.
3539       if (I.getGroup()->isIntrinsic()) {
3540         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3541                       I.getRegOpcode(), I.getMemOpcode(),
3542                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3543       } else {
3544         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3545                       I.getRegOpcode(), I.getMemOpcode(),
3546                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
3547       }
3548     }
3549   }
3550 }
3551 
3552 void
3553 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
3554                             MemOp2RegOpTableType &M2RTable,
3555                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
3556   if ((Flags & TB_NO_FORWARD) == 0) {
3557     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
3558     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
3559   }
3560   if ((Flags & TB_NO_REVERSE) == 0) {
3561     assert(!M2RTable.count(MemOp) &&
3562          "Duplicated entries in unfolding maps?");
3563     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
3564   }
3565 }
3566 
3567 bool
3568 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
3569                                     unsigned &SrcReg, unsigned &DstReg,
3570                                     unsigned &SubIdx) const {
3571   switch (MI.getOpcode()) {
3572   default: break;
3573   case X86::MOVSX16rr8:
3574   case X86::MOVZX16rr8:
3575   case X86::MOVSX32rr8:
3576   case X86::MOVZX32rr8:
3577   case X86::MOVSX64rr8:
3578     if (!Subtarget.is64Bit())
3579       // It's not always legal to reference the low 8-bit of the larger
3580       // register in 32-bit mode.
3581       return false;
3582   case X86::MOVSX32rr16:
3583   case X86::MOVZX32rr16:
3584   case X86::MOVSX64rr16:
3585   case X86::MOVSX64rr32: {
3586     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
3587       // Be conservative.
3588       return false;
3589     SrcReg = MI.getOperand(1).getReg();
3590     DstReg = MI.getOperand(0).getReg();
3591     switch (MI.getOpcode()) {
3592     default: llvm_unreachable("Unreachable!");
3593     case X86::MOVSX16rr8:
3594     case X86::MOVZX16rr8:
3595     case X86::MOVSX32rr8:
3596     case X86::MOVZX32rr8:
3597     case X86::MOVSX64rr8:
3598       SubIdx = X86::sub_8bit;
3599       break;
3600     case X86::MOVSX32rr16:
3601     case X86::MOVZX32rr16:
3602     case X86::MOVSX64rr16:
3603       SubIdx = X86::sub_16bit;
3604       break;
3605     case X86::MOVSX64rr32:
3606       SubIdx = X86::sub_32bit;
3607       break;
3608     }
3609     return true;
3610   }
3611   }
3612   return false;
3613 }
3614 
3615 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
3616   const MachineFunction *MF = MI.getParent()->getParent();
3617   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
3618 
3619   if (MI.getOpcode() == getCallFrameSetupOpcode() ||
3620       MI.getOpcode() == getCallFrameDestroyOpcode()) {
3621     unsigned StackAlign = TFI->getStackAlignment();
3622     int SPAdj =
3623         (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
3624 
3625     SPAdj -= MI.getOperand(1).getImm();
3626 
3627     if (MI.getOpcode() == getCallFrameSetupOpcode())
3628       return SPAdj;
3629     else
3630       return -SPAdj;
3631   }
3632 
3633   // To know whether a call adjusts the stack, we need information
3634   // that is bound to the following ADJCALLSTACKUP pseudo.
3635   // Look for the next ADJCALLSTACKUP that follows the call.
3636   if (MI.isCall()) {
3637     const MachineBasicBlock *MBB = MI.getParent();
3638     auto I = ++MachineBasicBlock::const_iterator(MI);
3639     for (auto E = MBB->end(); I != E; ++I) {
3640       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
3641           I->isCall())
3642         break;
3643     }
3644 
3645     // If we could not find a frame destroy opcode, then it has already
3646     // been simplified, so we don't care.
3647     if (I->getOpcode() != getCallFrameDestroyOpcode())
3648       return 0;
3649 
3650     return -(I->getOperand(1).getImm());
3651   }
3652 
3653   // Currently handle only PUSHes we can reasonably expect to see
3654   // in call sequences
3655   switch (MI.getOpcode()) {
3656   default:
3657     return 0;
3658   case X86::PUSH32i8:
3659   case X86::PUSH32r:
3660   case X86::PUSH32rmm:
3661   case X86::PUSH32rmr:
3662   case X86::PUSHi32:
3663     return 4;
3664   case X86::PUSH64i8:
3665   case X86::PUSH64r:
3666   case X86::PUSH64rmm:
3667   case X86::PUSH64rmr:
3668   case X86::PUSH64i32:
3669     return 8;
3670   }
3671 }
3672 
3673 /// Return true and the FrameIndex if the specified
3674 /// operand and follow operands form a reference to the stack frame.
3675 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
3676                                   int &FrameIndex) const {
3677   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
3678       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
3679       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
3680       MI.getOperand(Op + X86::AddrDisp).isImm() &&
3681       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
3682       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
3683       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
3684     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
3685     return true;
3686   }
3687   return false;
3688 }
3689 
3690 static bool isFrameLoadOpcode(int Opcode) {
3691   switch (Opcode) {
3692   default:
3693     return false;
3694   case X86::MOV8rm:
3695   case X86::MOV16rm:
3696   case X86::MOV32rm:
3697   case X86::MOV64rm:
3698   case X86::LD_Fp64m:
3699   case X86::MOVSSrm:
3700   case X86::MOVSDrm:
3701   case X86::MOVAPSrm:
3702   case X86::MOVUPSrm:
3703   case X86::MOVAPDrm:
3704   case X86::MOVUPDrm:
3705   case X86::MOVDQArm:
3706   case X86::MOVDQUrm:
3707   case X86::VMOVSSrm:
3708   case X86::VMOVSDrm:
3709   case X86::VMOVAPSrm:
3710   case X86::VMOVUPSrm:
3711   case X86::VMOVAPDrm:
3712   case X86::VMOVUPDrm:
3713   case X86::VMOVDQArm:
3714   case X86::VMOVDQUrm:
3715   case X86::VMOVUPSYrm:
3716   case X86::VMOVAPSYrm:
3717   case X86::VMOVUPDYrm:
3718   case X86::VMOVAPDYrm:
3719   case X86::VMOVDQUYrm:
3720   case X86::VMOVDQAYrm:
3721   case X86::MMX_MOVD64rm:
3722   case X86::MMX_MOVQ64rm:
3723   case X86::VMOVSSZrm:
3724   case X86::VMOVSDZrm:
3725   case X86::VMOVAPSZrm:
3726   case X86::VMOVAPSZ128rm:
3727   case X86::VMOVAPSZ256rm:
3728   case X86::VMOVAPSZ128rm_NOVLX:
3729   case X86::VMOVAPSZ256rm_NOVLX:
3730   case X86::VMOVUPSZrm:
3731   case X86::VMOVUPSZ128rm:
3732   case X86::VMOVUPSZ256rm:
3733   case X86::VMOVUPSZ128rm_NOVLX:
3734   case X86::VMOVUPSZ256rm_NOVLX:
3735   case X86::VMOVAPDZrm:
3736   case X86::VMOVAPDZ128rm:
3737   case X86::VMOVAPDZ256rm:
3738   case X86::VMOVUPDZrm:
3739   case X86::VMOVUPDZ128rm:
3740   case X86::VMOVUPDZ256rm:
3741   case X86::VMOVDQA32Zrm:
3742   case X86::VMOVDQA32Z128rm:
3743   case X86::VMOVDQA32Z256rm:
3744   case X86::VMOVDQU32Zrm:
3745   case X86::VMOVDQU32Z128rm:
3746   case X86::VMOVDQU32Z256rm:
3747   case X86::VMOVDQA64Zrm:
3748   case X86::VMOVDQA64Z128rm:
3749   case X86::VMOVDQA64Z256rm:
3750   case X86::VMOVDQU64Zrm:
3751   case X86::VMOVDQU64Z128rm:
3752   case X86::VMOVDQU64Z256rm:
3753   case X86::VMOVDQU8Zrm:
3754   case X86::VMOVDQU8Z128rm:
3755   case X86::VMOVDQU8Z256rm:
3756   case X86::VMOVDQU16Zrm:
3757   case X86::VMOVDQU16Z128rm:
3758   case X86::VMOVDQU16Z256rm:
3759   case X86::KMOVBkm:
3760   case X86::KMOVWkm:
3761   case X86::KMOVDkm:
3762   case X86::KMOVQkm:
3763     return true;
3764   }
3765 }
3766 
3767 static bool isFrameStoreOpcode(int Opcode) {
3768   switch (Opcode) {
3769   default: break;
3770   case X86::MOV8mr:
3771   case X86::MOV16mr:
3772   case X86::MOV32mr:
3773   case X86::MOV64mr:
3774   case X86::ST_FpP64m:
3775   case X86::MOVSSmr:
3776   case X86::MOVSDmr:
3777   case X86::MOVAPSmr:
3778   case X86::MOVUPSmr:
3779   case X86::MOVAPDmr:
3780   case X86::MOVUPDmr:
3781   case X86::MOVDQAmr:
3782   case X86::MOVDQUmr:
3783   case X86::VMOVSSmr:
3784   case X86::VMOVSDmr:
3785   case X86::VMOVAPSmr:
3786   case X86::VMOVUPSmr:
3787   case X86::VMOVAPDmr:
3788   case X86::VMOVUPDmr:
3789   case X86::VMOVDQAmr:
3790   case X86::VMOVDQUmr:
3791   case X86::VMOVUPSYmr:
3792   case X86::VMOVAPSYmr:
3793   case X86::VMOVUPDYmr:
3794   case X86::VMOVAPDYmr:
3795   case X86::VMOVDQUYmr:
3796   case X86::VMOVDQAYmr:
3797   case X86::VMOVSSZmr:
3798   case X86::VMOVSDZmr:
3799   case X86::VMOVUPSZmr:
3800   case X86::VMOVUPSZ128mr:
3801   case X86::VMOVUPSZ256mr:
3802   case X86::VMOVUPSZ128mr_NOVLX:
3803   case X86::VMOVUPSZ256mr_NOVLX:
3804   case X86::VMOVAPSZmr:
3805   case X86::VMOVAPSZ128mr:
3806   case X86::VMOVAPSZ256mr:
3807   case X86::VMOVAPSZ128mr_NOVLX:
3808   case X86::VMOVAPSZ256mr_NOVLX:
3809   case X86::VMOVUPDZmr:
3810   case X86::VMOVUPDZ128mr:
3811   case X86::VMOVUPDZ256mr:
3812   case X86::VMOVAPDZmr:
3813   case X86::VMOVAPDZ128mr:
3814   case X86::VMOVAPDZ256mr:
3815   case X86::VMOVDQA32Zmr:
3816   case X86::VMOVDQA32Z128mr:
3817   case X86::VMOVDQA32Z256mr:
3818   case X86::VMOVDQU32Zmr:
3819   case X86::VMOVDQU32Z128mr:
3820   case X86::VMOVDQU32Z256mr:
3821   case X86::VMOVDQA64Zmr:
3822   case X86::VMOVDQA64Z128mr:
3823   case X86::VMOVDQA64Z256mr:
3824   case X86::VMOVDQU64Zmr:
3825   case X86::VMOVDQU64Z128mr:
3826   case X86::VMOVDQU64Z256mr:
3827   case X86::VMOVDQU8Zmr:
3828   case X86::VMOVDQU8Z128mr:
3829   case X86::VMOVDQU8Z256mr:
3830   case X86::VMOVDQU16Zmr:
3831   case X86::VMOVDQU16Z128mr:
3832   case X86::VMOVDQU16Z256mr:
3833   case X86::MMX_MOVD64mr:
3834   case X86::MMX_MOVQ64mr:
3835   case X86::MMX_MOVNTQmr:
3836   case X86::KMOVBmk:
3837   case X86::KMOVWmk:
3838   case X86::KMOVDmk:
3839   case X86::KMOVQmk:
3840     return true;
3841   }
3842   return false;
3843 }
3844 
3845 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
3846                                            int &FrameIndex) const {
3847   if (isFrameLoadOpcode(MI.getOpcode()))
3848     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
3849       return MI.getOperand(0).getReg();
3850   return 0;
3851 }
3852 
3853 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
3854                                                  int &FrameIndex) const {
3855   if (isFrameLoadOpcode(MI.getOpcode())) {
3856     unsigned Reg;
3857     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
3858       return Reg;
3859     // Check for post-frame index elimination operations
3860     const MachineMemOperand *Dummy;
3861     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
3862   }
3863   return 0;
3864 }
3865 
3866 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
3867                                           int &FrameIndex) const {
3868   if (isFrameStoreOpcode(MI.getOpcode()))
3869     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
3870         isFrameOperand(MI, 0, FrameIndex))
3871       return MI.getOperand(X86::AddrNumOperands).getReg();
3872   return 0;
3873 }
3874 
3875 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
3876                                                 int &FrameIndex) const {
3877   if (isFrameStoreOpcode(MI.getOpcode())) {
3878     unsigned Reg;
3879     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
3880       return Reg;
3881     // Check for post-frame index elimination operations
3882     const MachineMemOperand *Dummy;
3883     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
3884   }
3885   return 0;
3886 }
3887 
3888 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
3889 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
3890   // Don't waste compile time scanning use-def chains of physregs.
3891   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
3892     return false;
3893   bool isPICBase = false;
3894   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
3895          E = MRI.def_instr_end(); I != E; ++I) {
3896     MachineInstr *DefMI = &*I;
3897     if (DefMI->getOpcode() != X86::MOVPC32r)
3898       return false;
3899     assert(!isPICBase && "More than one PIC base?");
3900     isPICBase = true;
3901   }
3902   return isPICBase;
3903 }
3904 
3905 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
3906                                                      AliasAnalysis *AA) const {
3907   switch (MI.getOpcode()) {
3908   default: break;
3909   case X86::MOV8rm:
3910   case X86::MOV8rm_NOREX:
3911   case X86::MOV16rm:
3912   case X86::MOV32rm:
3913   case X86::MOV64rm:
3914   case X86::LD_Fp64m:
3915   case X86::MOVSSrm:
3916   case X86::MOVSDrm:
3917   case X86::MOVAPSrm:
3918   case X86::MOVUPSrm:
3919   case X86::MOVAPDrm:
3920   case X86::MOVUPDrm:
3921   case X86::MOVDQArm:
3922   case X86::MOVDQUrm:
3923   case X86::VMOVSSrm:
3924   case X86::VMOVSDrm:
3925   case X86::VMOVAPSrm:
3926   case X86::VMOVUPSrm:
3927   case X86::VMOVAPDrm:
3928   case X86::VMOVUPDrm:
3929   case X86::VMOVDQArm:
3930   case X86::VMOVDQUrm:
3931   case X86::VMOVAPSYrm:
3932   case X86::VMOVUPSYrm:
3933   case X86::VMOVAPDYrm:
3934   case X86::VMOVUPDYrm:
3935   case X86::VMOVDQAYrm:
3936   case X86::VMOVDQUYrm:
3937   case X86::MMX_MOVD64rm:
3938   case X86::MMX_MOVQ64rm:
3939   // AVX-512
3940   case X86::VMOVSSZrm:
3941   case X86::VMOVSDZrm:
3942   case X86::VMOVAPDZ128rm:
3943   case X86::VMOVAPDZ256rm:
3944   case X86::VMOVAPDZrm:
3945   case X86::VMOVAPSZ128rm:
3946   case X86::VMOVAPSZ256rm:
3947   case X86::VMOVAPSZ128rm_NOVLX:
3948   case X86::VMOVAPSZ256rm_NOVLX:
3949   case X86::VMOVAPSZrm:
3950   case X86::VMOVDQA32Z128rm:
3951   case X86::VMOVDQA32Z256rm:
3952   case X86::VMOVDQA32Zrm:
3953   case X86::VMOVDQA64Z128rm:
3954   case X86::VMOVDQA64Z256rm:
3955   case X86::VMOVDQA64Zrm:
3956   case X86::VMOVDQU16Z128rm:
3957   case X86::VMOVDQU16Z256rm:
3958   case X86::VMOVDQU16Zrm:
3959   case X86::VMOVDQU32Z128rm:
3960   case X86::VMOVDQU32Z256rm:
3961   case X86::VMOVDQU32Zrm:
3962   case X86::VMOVDQU64Z128rm:
3963   case X86::VMOVDQU64Z256rm:
3964   case X86::VMOVDQU64Zrm:
3965   case X86::VMOVDQU8Z128rm:
3966   case X86::VMOVDQU8Z256rm:
3967   case X86::VMOVDQU8Zrm:
3968   case X86::VMOVUPDZ128rm:
3969   case X86::VMOVUPDZ256rm:
3970   case X86::VMOVUPDZrm:
3971   case X86::VMOVUPSZ128rm:
3972   case X86::VMOVUPSZ256rm:
3973   case X86::VMOVUPSZ128rm_NOVLX:
3974   case X86::VMOVUPSZ256rm_NOVLX:
3975   case X86::VMOVUPSZrm: {
3976     // Loads from constant pools are trivially rematerializable.
3977     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
3978         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3979         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
3980         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
3981         MI.isDereferenceableInvariantLoad(AA)) {
3982       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
3983       if (BaseReg == 0 || BaseReg == X86::RIP)
3984         return true;
3985       // Allow re-materialization of PIC load.
3986       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
3987         return false;
3988       const MachineFunction &MF = *MI.getParent()->getParent();
3989       const MachineRegisterInfo &MRI = MF.getRegInfo();
3990       return regIsPICBase(BaseReg, MRI);
3991     }
3992     return false;
3993   }
3994 
3995   case X86::LEA32r:
3996   case X86::LEA64r: {
3997     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3998         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
3999         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4000         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
4001       // lea fi#, lea GV, etc. are all rematerializable.
4002       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
4003         return true;
4004       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4005       if (BaseReg == 0)
4006         return true;
4007       // Allow re-materialization of lea PICBase + x.
4008       const MachineFunction &MF = *MI.getParent()->getParent();
4009       const MachineRegisterInfo &MRI = MF.getRegInfo();
4010       return regIsPICBase(BaseReg, MRI);
4011     }
4012     return false;
4013   }
4014   }
4015 
4016   // All other instructions marked M_REMATERIALIZABLE are always trivially
4017   // rematerializable.
4018   return true;
4019 }
4020 
4021 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
4022                                          MachineBasicBlock::iterator I) const {
4023   MachineBasicBlock::iterator E = MBB.end();
4024 
4025   // For compile time consideration, if we are not able to determine the
4026   // safety after visiting 4 instructions in each direction, we will assume
4027   // it's not safe.
4028   MachineBasicBlock::iterator Iter = I;
4029   for (unsigned i = 0; Iter != E && i < 4; ++i) {
4030     bool SeenDef = false;
4031     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4032       MachineOperand &MO = Iter->getOperand(j);
4033       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4034         SeenDef = true;
4035       if (!MO.isReg())
4036         continue;
4037       if (MO.getReg() == X86::EFLAGS) {
4038         if (MO.isUse())
4039           return false;
4040         SeenDef = true;
4041       }
4042     }
4043 
4044     if (SeenDef)
4045       // This instruction defines EFLAGS, no need to look any further.
4046       return true;
4047     ++Iter;
4048     // Skip over DBG_VALUE.
4049     while (Iter != E && Iter->isDebugValue())
4050       ++Iter;
4051   }
4052 
4053   // It is safe to clobber EFLAGS at the end of a block of no successor has it
4054   // live in.
4055   if (Iter == E) {
4056     for (MachineBasicBlock *S : MBB.successors())
4057       if (S->isLiveIn(X86::EFLAGS))
4058         return false;
4059     return true;
4060   }
4061 
4062   MachineBasicBlock::iterator B = MBB.begin();
4063   Iter = I;
4064   for (unsigned i = 0; i < 4; ++i) {
4065     // If we make it to the beginning of the block, it's safe to clobber
4066     // EFLAGS iff EFLAGS is not live-in.
4067     if (Iter == B)
4068       return !MBB.isLiveIn(X86::EFLAGS);
4069 
4070     --Iter;
4071     // Skip over DBG_VALUE.
4072     while (Iter != B && Iter->isDebugValue())
4073       --Iter;
4074 
4075     bool SawKill = false;
4076     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4077       MachineOperand &MO = Iter->getOperand(j);
4078       // A register mask may clobber EFLAGS, but we should still look for a
4079       // live EFLAGS def.
4080       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4081         SawKill = true;
4082       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
4083         if (MO.isDef()) return MO.isDead();
4084         if (MO.isKill()) SawKill = true;
4085       }
4086     }
4087 
4088     if (SawKill)
4089       // This instruction kills EFLAGS and doesn't redefine it, so
4090       // there's no need to look further.
4091       return true;
4092   }
4093 
4094   // Conservative answer.
4095   return false;
4096 }
4097 
4098 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
4099                                  MachineBasicBlock::iterator I,
4100                                  unsigned DestReg, unsigned SubIdx,
4101                                  const MachineInstr &Orig,
4102                                  const TargetRegisterInfo &TRI) const {
4103   bool ClobbersEFLAGS = false;
4104   for (const MachineOperand &MO : Orig.operands()) {
4105     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4106       ClobbersEFLAGS = true;
4107       break;
4108     }
4109   }
4110 
4111   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
4112     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
4113     // effects.
4114     int Value;
4115     switch (Orig.getOpcode()) {
4116     case X86::MOV32r0:  Value = 0; break;
4117     case X86::MOV32r1:  Value = 1; break;
4118     case X86::MOV32r_1: Value = -1; break;
4119     default:
4120       llvm_unreachable("Unexpected instruction!");
4121     }
4122 
4123     const DebugLoc &DL = Orig.getDebugLoc();
4124     BuildMI(MBB, I, DL, get(X86::MOV32ri))
4125         .add(Orig.getOperand(0))
4126         .addImm(Value);
4127   } else {
4128     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
4129     MBB.insert(I, MI);
4130   }
4131 
4132   MachineInstr &NewMI = *std::prev(I);
4133   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
4134 }
4135 
4136 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
4137 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
4138   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4139     MachineOperand &MO = MI.getOperand(i);
4140     if (MO.isReg() && MO.isDef() &&
4141         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
4142       return true;
4143     }
4144   }
4145   return false;
4146 }
4147 
4148 /// Check whether the shift count for a machine operand is non-zero.
4149 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
4150                                               unsigned ShiftAmtOperandIdx) {
4151   // The shift count is six bits with the REX.W prefix and five bits without.
4152   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
4153   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
4154   return Imm & ShiftCountMask;
4155 }
4156 
4157 /// Check whether the given shift count is appropriate
4158 /// can be represented by a LEA instruction.
4159 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
4160   // Left shift instructions can be transformed into load-effective-address
4161   // instructions if we can encode them appropriately.
4162   // A LEA instruction utilizes a SIB byte to encode its scale factor.
4163   // The SIB.scale field is two bits wide which means that we can encode any
4164   // shift amount less than 4.
4165   return ShAmt < 4 && ShAmt > 0;
4166 }
4167 
4168 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
4169                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
4170                                   bool &isKill, bool &isUndef,
4171                                   MachineOperand &ImplicitOp,
4172                                   LiveVariables *LV) const {
4173   MachineFunction &MF = *MI.getParent()->getParent();
4174   const TargetRegisterClass *RC;
4175   if (AllowSP) {
4176     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
4177   } else {
4178     RC = Opc != X86::LEA32r ?
4179       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
4180   }
4181   unsigned SrcReg = Src.getReg();
4182 
4183   // For both LEA64 and LEA32 the register already has essentially the right
4184   // type (32-bit or 64-bit) we may just need to forbid SP.
4185   if (Opc != X86::LEA64_32r) {
4186     NewSrc = SrcReg;
4187     isKill = Src.isKill();
4188     isUndef = Src.isUndef();
4189 
4190     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
4191         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
4192       return false;
4193 
4194     return true;
4195   }
4196 
4197   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
4198   // another we need to add 64-bit registers to the final MI.
4199   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
4200     ImplicitOp = Src;
4201     ImplicitOp.setImplicit();
4202 
4203     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
4204     isKill = Src.isKill();
4205     isUndef = Src.isUndef();
4206   } else {
4207     // Virtual register of the wrong class, we have to create a temporary 64-bit
4208     // vreg to feed into the LEA.
4209     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
4210     MachineInstr *Copy =
4211         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4212             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
4213             .add(Src);
4214 
4215     // Which is obviously going to be dead after we're done with it.
4216     isKill = true;
4217     isUndef = false;
4218 
4219     if (LV)
4220       LV->replaceKillInstruction(SrcReg, MI, *Copy);
4221   }
4222 
4223   // We've set all the parameters without issue.
4224   return true;
4225 }
4226 
4227 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
4228 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
4229 /// truncating back down to a 16-bit subregister.
4230 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
4231     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
4232     LiveVariables *LV) const {
4233   MachineBasicBlock::iterator MBBI = MI.getIterator();
4234   unsigned Dest = MI.getOperand(0).getReg();
4235   unsigned Src = MI.getOperand(1).getReg();
4236   bool isDead = MI.getOperand(0).isDead();
4237   bool isKill = MI.getOperand(1).isKill();
4238 
4239   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
4240   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4241   unsigned Opc, leaInReg;
4242   if (Subtarget.is64Bit()) {
4243     Opc = X86::LEA64_32r;
4244     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4245   } else {
4246     Opc = X86::LEA32r;
4247     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4248   }
4249 
4250   // Build and insert into an implicit UNDEF value. This is OK because
4251   // well be shifting and then extracting the lower 16-bits.
4252   // This has the potential to cause partial register stall. e.g.
4253   //   movw    (%rbp,%rcx,2), %dx
4254   //   leal    -65(%rdx), %esi
4255   // But testing has shown this *does* help performance in 64-bit mode (at
4256   // least on modern x86 machines).
4257   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
4258   MachineInstr *InsMI =
4259       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4260           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
4261           .addReg(Src, getKillRegState(isKill));
4262 
4263   MachineInstrBuilder MIB =
4264       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
4265   switch (MIOpc) {
4266   default: llvm_unreachable("Unreachable!");
4267   case X86::SHL16ri: {
4268     unsigned ShAmt = MI.getOperand(2).getImm();
4269     MIB.addReg(0).addImm(1ULL << ShAmt)
4270        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
4271     break;
4272   }
4273   case X86::INC16r:
4274     addRegOffset(MIB, leaInReg, true, 1);
4275     break;
4276   case X86::DEC16r:
4277     addRegOffset(MIB, leaInReg, true, -1);
4278     break;
4279   case X86::ADD16ri:
4280   case X86::ADD16ri8:
4281   case X86::ADD16ri_DB:
4282   case X86::ADD16ri8_DB:
4283     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
4284     break;
4285   case X86::ADD16rr:
4286   case X86::ADD16rr_DB: {
4287     unsigned Src2 = MI.getOperand(2).getReg();
4288     bool isKill2 = MI.getOperand(2).isKill();
4289     unsigned leaInReg2 = 0;
4290     MachineInstr *InsMI2 = nullptr;
4291     if (Src == Src2) {
4292       // ADD16rr %reg1028<kill>, %reg1028
4293       // just a single insert_subreg.
4294       addRegReg(MIB, leaInReg, true, leaInReg, false);
4295     } else {
4296       if (Subtarget.is64Bit())
4297         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4298       else
4299         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4300       // Build and insert into an implicit UNDEF value. This is OK because
4301       // well be shifting and then extracting the lower 16-bits.
4302       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
4303       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
4304                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
4305                    .addReg(Src2, getKillRegState(isKill2));
4306       addRegReg(MIB, leaInReg, true, leaInReg2, true);
4307     }
4308     if (LV && isKill2 && InsMI2)
4309       LV->replaceKillInstruction(Src2, MI, *InsMI2);
4310     break;
4311   }
4312   }
4313 
4314   MachineInstr *NewMI = MIB;
4315   MachineInstr *ExtMI =
4316       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4317           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
4318           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
4319 
4320   if (LV) {
4321     // Update live variables
4322     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
4323     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
4324     if (isKill)
4325       LV->replaceKillInstruction(Src, MI, *InsMI);
4326     if (isDead)
4327       LV->replaceKillInstruction(Dest, MI, *ExtMI);
4328   }
4329 
4330   return ExtMI;
4331 }
4332 
4333 /// This method must be implemented by targets that
4334 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
4335 /// may be able to convert a two-address instruction into a true
4336 /// three-address instruction on demand.  This allows the X86 target (for
4337 /// example) to convert ADD and SHL instructions into LEA instructions if they
4338 /// would require register copies due to two-addressness.
4339 ///
4340 /// This method returns a null pointer if the transformation cannot be
4341 /// performed, otherwise it returns the new instruction.
4342 ///
4343 MachineInstr *
4344 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
4345                                     MachineInstr &MI, LiveVariables *LV) const {
4346   // The following opcodes also sets the condition code register(s). Only
4347   // convert them to equivalent lea if the condition code register def's
4348   // are dead!
4349   if (hasLiveCondCodeDef(MI))
4350     return nullptr;
4351 
4352   MachineFunction &MF = *MI.getParent()->getParent();
4353   // All instructions input are two-addr instructions.  Get the known operands.
4354   const MachineOperand &Dest = MI.getOperand(0);
4355   const MachineOperand &Src = MI.getOperand(1);
4356 
4357   MachineInstr *NewMI = nullptr;
4358   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
4359   // we have better subtarget support, enable the 16-bit LEA generation here.
4360   // 16-bit LEA is also slow on Core2.
4361   bool DisableLEA16 = true;
4362   bool is64Bit = Subtarget.is64Bit();
4363 
4364   unsigned MIOpc = MI.getOpcode();
4365   switch (MIOpc) {
4366   default: return nullptr;
4367   case X86::SHL64ri: {
4368     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4369     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4370     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4371 
4372     // LEA can't handle RSP.
4373     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
4374         !MF.getRegInfo().constrainRegClass(Src.getReg(),
4375                                            &X86::GR64_NOSPRegClass))
4376       return nullptr;
4377 
4378     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
4379                 .add(Dest)
4380                 .addReg(0)
4381                 .addImm(1ULL << ShAmt)
4382                 .add(Src)
4383                 .addImm(0)
4384                 .addReg(0);
4385     break;
4386   }
4387   case X86::SHL32ri: {
4388     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4389     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4390     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4391 
4392     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4393 
4394     // LEA can't handle ESP.
4395     bool isKill, isUndef;
4396     unsigned SrcReg;
4397     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4398     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4399                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4400       return nullptr;
4401 
4402     MachineInstrBuilder MIB =
4403         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4404             .add(Dest)
4405             .addReg(0)
4406             .addImm(1ULL << ShAmt)
4407             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
4408             .addImm(0)
4409             .addReg(0);
4410     if (ImplicitOp.getReg() != 0)
4411       MIB.add(ImplicitOp);
4412     NewMI = MIB;
4413 
4414     break;
4415   }
4416   case X86::SHL16ri: {
4417     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4418     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4419     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4420 
4421     if (DisableLEA16)
4422       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4423                      : nullptr;
4424     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
4425                 .add(Dest)
4426                 .addReg(0)
4427                 .addImm(1ULL << ShAmt)
4428                 .add(Src)
4429                 .addImm(0)
4430                 .addReg(0);
4431     break;
4432   }
4433   case X86::INC64r:
4434   case X86::INC32r: {
4435     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4436     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
4437       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4438     bool isKill, isUndef;
4439     unsigned SrcReg;
4440     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4441     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4442                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4443       return nullptr;
4444 
4445     MachineInstrBuilder MIB =
4446         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4447             .add(Dest)
4448             .addReg(SrcReg,
4449                     getKillRegState(isKill) | getUndefRegState(isUndef));
4450     if (ImplicitOp.getReg() != 0)
4451       MIB.add(ImplicitOp);
4452 
4453     NewMI = addOffset(MIB, 1);
4454     break;
4455   }
4456   case X86::INC16r:
4457     if (DisableLEA16)
4458       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4459                      : nullptr;
4460     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4461     NewMI = addOffset(
4462         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 1);
4463     break;
4464   case X86::DEC64r:
4465   case X86::DEC32r: {
4466     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4467     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
4468       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4469 
4470     bool isKill, isUndef;
4471     unsigned SrcReg;
4472     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4473     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4474                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4475       return nullptr;
4476 
4477     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4478                                   .add(Dest)
4479                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4480                                                       getKillRegState(isKill));
4481     if (ImplicitOp.getReg() != 0)
4482       MIB.add(ImplicitOp);
4483 
4484     NewMI = addOffset(MIB, -1);
4485 
4486     break;
4487   }
4488   case X86::DEC16r:
4489     if (DisableLEA16)
4490       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4491                      : nullptr;
4492     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4493     NewMI = addOffset(
4494         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), -1);
4495     break;
4496   case X86::ADD64rr:
4497   case X86::ADD64rr_DB:
4498   case X86::ADD32rr:
4499   case X86::ADD32rr_DB: {
4500     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4501     unsigned Opc;
4502     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
4503       Opc = X86::LEA64r;
4504     else
4505       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4506 
4507     bool isKill, isUndef;
4508     unsigned SrcReg;
4509     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4510     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4511                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4512       return nullptr;
4513 
4514     const MachineOperand &Src2 = MI.getOperand(2);
4515     bool isKill2, isUndef2;
4516     unsigned SrcReg2;
4517     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
4518     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
4519                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
4520       return nullptr;
4521 
4522     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
4523     if (ImplicitOp.getReg() != 0)
4524       MIB.add(ImplicitOp);
4525     if (ImplicitOp2.getReg() != 0)
4526       MIB.add(ImplicitOp2);
4527 
4528     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
4529 
4530     // Preserve undefness of the operands.
4531     NewMI->getOperand(1).setIsUndef(isUndef);
4532     NewMI->getOperand(3).setIsUndef(isUndef2);
4533 
4534     if (LV && Src2.isKill())
4535       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
4536     break;
4537   }
4538   case X86::ADD16rr:
4539   case X86::ADD16rr_DB: {
4540     if (DisableLEA16)
4541       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4542                      : nullptr;
4543     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4544     unsigned Src2 = MI.getOperand(2).getReg();
4545     bool isKill2 = MI.getOperand(2).isKill();
4546     NewMI = addRegReg(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest),
4547                       Src.getReg(), Src.isKill(), Src2, isKill2);
4548 
4549     // Preserve undefness of the operands.
4550     bool isUndef = MI.getOperand(1).isUndef();
4551     bool isUndef2 = MI.getOperand(2).isUndef();
4552     NewMI->getOperand(1).setIsUndef(isUndef);
4553     NewMI->getOperand(3).setIsUndef(isUndef2);
4554 
4555     if (LV && isKill2)
4556       LV->replaceKillInstruction(Src2, MI, *NewMI);
4557     break;
4558   }
4559   case X86::ADD64ri32:
4560   case X86::ADD64ri8:
4561   case X86::ADD64ri32_DB:
4562   case X86::ADD64ri8_DB:
4563     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4564     NewMI = addOffset(
4565         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
4566         MI.getOperand(2));
4567     break;
4568   case X86::ADD32ri:
4569   case X86::ADD32ri8:
4570   case X86::ADD32ri_DB:
4571   case X86::ADD32ri8_DB: {
4572     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4573     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4574 
4575     bool isKill, isUndef;
4576     unsigned SrcReg;
4577     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4578     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4579                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4580       return nullptr;
4581 
4582     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4583                                   .add(Dest)
4584                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4585                                                       getKillRegState(isKill));
4586     if (ImplicitOp.getReg() != 0)
4587       MIB.add(ImplicitOp);
4588 
4589     NewMI = addOffset(MIB, MI.getOperand(2));
4590     break;
4591   }
4592   case X86::ADD16ri:
4593   case X86::ADD16ri8:
4594   case X86::ADD16ri_DB:
4595   case X86::ADD16ri8_DB:
4596     if (DisableLEA16)
4597       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4598                      : nullptr;
4599     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4600     NewMI = addOffset(
4601         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src),
4602         MI.getOperand(2));
4603     break;
4604 
4605   case X86::VMOVDQU8Z128rmk:
4606   case X86::VMOVDQU8Z256rmk:
4607   case X86::VMOVDQU8Zrmk:
4608   case X86::VMOVDQU16Z128rmk:
4609   case X86::VMOVDQU16Z256rmk:
4610   case X86::VMOVDQU16Zrmk:
4611   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
4612   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
4613   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
4614   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
4615   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
4616   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
4617   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
4618   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
4619   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
4620   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
4621   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
4622   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk: {
4623     unsigned Opc;
4624     switch (MIOpc) {
4625     default: llvm_unreachable("Unreachable!");
4626     case X86::VMOVDQU8Z128rmk:  Opc = X86::VPBLENDMBZ128rmk; break;
4627     case X86::VMOVDQU8Z256rmk:  Opc = X86::VPBLENDMBZ256rmk; break;
4628     case X86::VMOVDQU8Zrmk:     Opc = X86::VPBLENDMBZrmk;    break;
4629     case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
4630     case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
4631     case X86::VMOVDQU16Zrmk:    Opc = X86::VPBLENDMWZrmk;    break;
4632     case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4633     case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4634     case X86::VMOVDQU32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4635     case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4636     case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4637     case X86::VMOVDQU64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4638     case X86::VMOVUPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4639     case X86::VMOVUPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4640     case X86::VMOVUPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4641     case X86::VMOVUPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4642     case X86::VMOVUPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4643     case X86::VMOVUPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4644     case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4645     case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4646     case X86::VMOVDQA32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4647     case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4648     case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4649     case X86::VMOVDQA64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4650     case X86::VMOVAPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4651     case X86::VMOVAPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4652     case X86::VMOVAPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4653     case X86::VMOVAPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4654     case X86::VMOVAPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4655     case X86::VMOVAPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4656     }
4657 
4658     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4659               .add(Dest)
4660               .add(MI.getOperand(2))
4661               .add(Src)
4662               .add(MI.getOperand(3))
4663               .add(MI.getOperand(4))
4664               .add(MI.getOperand(5))
4665               .add(MI.getOperand(6))
4666               .add(MI.getOperand(7));
4667     break;
4668   }
4669   case X86::VMOVDQU8Z128rrk:
4670   case X86::VMOVDQU8Z256rrk:
4671   case X86::VMOVDQU8Zrrk:
4672   case X86::VMOVDQU16Z128rrk:
4673   case X86::VMOVDQU16Z256rrk:
4674   case X86::VMOVDQU16Zrrk:
4675   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
4676   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
4677   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
4678   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
4679   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
4680   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
4681   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
4682   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
4683   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
4684   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
4685   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
4686   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
4687     unsigned Opc;
4688     switch (MIOpc) {
4689     default: llvm_unreachable("Unreachable!");
4690     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
4691     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
4692     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
4693     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
4694     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
4695     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
4696     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4697     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4698     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4699     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4700     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4701     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4702     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4703     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4704     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4705     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4706     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4707     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4708     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4709     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4710     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4711     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4712     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4713     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4714     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4715     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4716     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4717     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4718     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4719     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4720     }
4721 
4722     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4723               .add(Dest)
4724               .add(MI.getOperand(2))
4725               .add(Src)
4726               .add(MI.getOperand(3));
4727     break;
4728   }
4729   }
4730 
4731   if (!NewMI) return nullptr;
4732 
4733   if (LV) {  // Update live variables
4734     if (Src.isKill())
4735       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
4736     if (Dest.isDead())
4737       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
4738   }
4739 
4740   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
4741   return NewMI;
4742 }
4743 
4744 /// This determines which of three possible cases of a three source commute
4745 /// the source indexes correspond to taking into account any mask operands.
4746 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
4747 /// possible.
4748 /// Case 0 - Possible to commute the first and second operands.
4749 /// Case 1 - Possible to commute the first and third operands.
4750 /// Case 2 - Possible to commute the second and third operands.
4751 static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
4752                                   unsigned SrcOpIdx2) {
4753   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4754   if (SrcOpIdx1 > SrcOpIdx2)
4755     std::swap(SrcOpIdx1, SrcOpIdx2);
4756 
4757   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
4758   if (X86II::isKMasked(TSFlags)) {
4759     // The k-mask operand cannot be commuted.
4760     if (SrcOpIdx1 == 2)
4761       return -1;
4762 
4763     // For k-zero-masked operations it is Ok to commute the first vector
4764     // operand.
4765     // For regular k-masked operations a conservative choice is done as the
4766     // elements of the first vector operand, for which the corresponding bit
4767     // in the k-mask operand is set to 0, are copied to the result of the
4768     // instruction.
4769     // TODO/FIXME: The commute still may be legal if it is known that the
4770     // k-mask operand is set to either all ones or all zeroes.
4771     // It is also Ok to commute the 1st operand if all users of MI use only
4772     // the elements enabled by the k-mask operand. For example,
4773     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
4774     //                                                     : v1[i];
4775     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
4776     //                                  // Ok, to commute v1 in FMADD213PSZrk.
4777     if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
4778       return -1;
4779     Op2++;
4780     Op3++;
4781   }
4782 
4783   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
4784     return 0;
4785   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
4786     return 1;
4787   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
4788     return 2;
4789   return -1;
4790 }
4791 
4792 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
4793     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
4794     const X86InstrFMA3Group &FMA3Group) const {
4795 
4796   unsigned Opc = MI.getOpcode();
4797 
4798   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4799   if (SrcOpIdx1 > SrcOpIdx2)
4800     std::swap(SrcOpIdx1, SrcOpIdx2);
4801 
4802   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
4803   // analysis. The commute optimization is legal only if all users of FMA*_Int
4804   // use only the lowest element of the FMA*_Int instruction. Such analysis are
4805   // not implemented yet. So, just return 0 in that case.
4806   // When such analysis are available this place will be the right place for
4807   // calling it.
4808   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
4809     return 0;
4810 
4811   // Determine which case this commute is or if it can't be done.
4812   int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
4813   if (Case < 0)
4814     return 0;
4815 
4816   // Define the FMA forms mapping array that helps to map input FMA form
4817   // to output FMA form to preserve the operation semantics after
4818   // commuting the operands.
4819   const unsigned Form132Index = 0;
4820   const unsigned Form213Index = 1;
4821   const unsigned Form231Index = 2;
4822   static const unsigned FormMapping[][3] = {
4823     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
4824     // FMA132 A, C, b; ==> FMA231 C, A, b;
4825     // FMA213 B, A, c; ==> FMA213 A, B, c;
4826     // FMA231 C, A, b; ==> FMA132 A, C, b;
4827     { Form231Index, Form213Index, Form132Index },
4828     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
4829     // FMA132 A, c, B; ==> FMA132 B, c, A;
4830     // FMA213 B, a, C; ==> FMA231 C, a, B;
4831     // FMA231 C, a, B; ==> FMA213 B, a, C;
4832     { Form132Index, Form231Index, Form213Index },
4833     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
4834     // FMA132 a, C, B; ==> FMA213 a, B, C;
4835     // FMA213 b, A, C; ==> FMA132 b, C, A;
4836     // FMA231 c, A, B; ==> FMA231 c, B, A;
4837     { Form213Index, Form132Index, Form231Index }
4838   };
4839 
4840   unsigned FMAForms[3];
4841   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
4842     FMAForms[0] = FMA3Group.getReg132Opcode();
4843     FMAForms[1] = FMA3Group.getReg213Opcode();
4844     FMAForms[2] = FMA3Group.getReg231Opcode();
4845   } else {
4846     FMAForms[0] = FMA3Group.getMem132Opcode();
4847     FMAForms[1] = FMA3Group.getMem213Opcode();
4848     FMAForms[2] = FMA3Group.getMem231Opcode();
4849   }
4850   unsigned FormIndex;
4851   for (FormIndex = 0; FormIndex < 3; FormIndex++)
4852     if (Opc == FMAForms[FormIndex])
4853       break;
4854 
4855   // Everything is ready, just adjust the FMA opcode and return it.
4856   FormIndex = FormMapping[Case][FormIndex];
4857   return FMAForms[FormIndex];
4858 }
4859 
4860 static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
4861                              unsigned SrcOpIdx2) {
4862   uint64_t TSFlags = MI.getDesc().TSFlags;
4863 
4864   // Determine which case this commute is or if it can't be done.
4865   int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
4866   if (Case < 0)
4867     return false;
4868 
4869   // For each case we need to swap two pairs of bits in the final immediate.
4870   static const uint8_t SwapMasks[3][4] = {
4871     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
4872     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
4873     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
4874   };
4875 
4876   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
4877   // Clear out the bits we are swapping.
4878   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
4879                            SwapMasks[Case][2] | SwapMasks[Case][3]);
4880   // If the immediate had a bit of the pair set, then set the opposite bit.
4881   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
4882   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
4883   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
4884   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
4885   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
4886 
4887   return true;
4888 }
4889 
4890 // Returns true if this is a VPERMI2 or VPERMT2 instrution that can be
4891 // commuted.
4892 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
4893 #define VPERM_CASES(Suffix) \
4894   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
4895   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
4896   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
4897   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
4898   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
4899   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
4900   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
4901   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
4902   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
4903   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
4904   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
4905   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
4906 
4907 #define VPERM_CASES_BROADCAST(Suffix) \
4908   VPERM_CASES(Suffix) \
4909   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
4910   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
4911   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
4912   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
4913   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
4914   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
4915 
4916   switch (Opcode) {
4917   default: return false;
4918   VPERM_CASES(B)
4919   VPERM_CASES_BROADCAST(D)
4920   VPERM_CASES_BROADCAST(PD)
4921   VPERM_CASES_BROADCAST(PS)
4922   VPERM_CASES_BROADCAST(Q)
4923   VPERM_CASES(W)
4924     return true;
4925   }
4926 #undef VPERM_CASES_BROADCAST
4927 #undef VPERM_CASES
4928 }
4929 
4930 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
4931 // from the I opcod to the T opcode and vice versa.
4932 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
4933 #define VPERM_CASES(Orig, New) \
4934   case X86::Orig##128rr:    return X86::New##128rr;   \
4935   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
4936   case X86::Orig##128rm:    return X86::New##128rm;   \
4937   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
4938   case X86::Orig##256rr:    return X86::New##256rr;   \
4939   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
4940   case X86::Orig##256rm:    return X86::New##256rm;   \
4941   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
4942   case X86::Orig##rr:       return X86::New##rr;      \
4943   case X86::Orig##rrkz:     return X86::New##rrkz;    \
4944   case X86::Orig##rm:       return X86::New##rm;      \
4945   case X86::Orig##rmkz:     return X86::New##rmkz;
4946 
4947 #define VPERM_CASES_BROADCAST(Orig, New) \
4948   VPERM_CASES(Orig, New) \
4949   case X86::Orig##128rmb:   return X86::New##128rmb;   \
4950   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
4951   case X86::Orig##256rmb:   return X86::New##256rmb;   \
4952   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
4953   case X86::Orig##rmb:      return X86::New##rmb;      \
4954   case X86::Orig##rmbkz:    return X86::New##rmbkz;
4955 
4956   switch (Opcode) {
4957   VPERM_CASES(VPERMI2B, VPERMT2B)
4958   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
4959   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
4960   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
4961   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
4962   VPERM_CASES(VPERMI2W, VPERMT2W)
4963   VPERM_CASES(VPERMT2B, VPERMI2B)
4964   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
4965   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
4966   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
4967   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
4968   VPERM_CASES(VPERMT2W, VPERMI2W)
4969   }
4970 
4971   llvm_unreachable("Unreachable!");
4972 #undef VPERM_CASES_BROADCAST
4973 #undef VPERM_CASES
4974 }
4975 
4976 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
4977                                                    unsigned OpIdx1,
4978                                                    unsigned OpIdx2) const {
4979   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
4980     if (NewMI)
4981       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
4982     return MI;
4983   };
4984 
4985   switch (MI.getOpcode()) {
4986   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
4987   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
4988   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
4989   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
4990   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
4991   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
4992     unsigned Opc;
4993     unsigned Size;
4994     switch (MI.getOpcode()) {
4995     default: llvm_unreachable("Unreachable!");
4996     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
4997     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
4998     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
4999     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
5000     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
5001     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
5002     }
5003     unsigned Amt = MI.getOperand(3).getImm();
5004     auto &WorkingMI = cloneIfNew(MI);
5005     WorkingMI.setDesc(get(Opc));
5006     WorkingMI.getOperand(3).setImm(Size - Amt);
5007     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5008                                                    OpIdx1, OpIdx2);
5009   }
5010   case X86::PFSUBrr:
5011   case X86::PFSUBRrr: {
5012     // PFSUB  x, y: x = x - y
5013     // PFSUBR x, y: x = y - x
5014     unsigned Opc =
5015         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
5016     auto &WorkingMI = cloneIfNew(MI);
5017     WorkingMI.setDesc(get(Opc));
5018     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5019                                                    OpIdx1, OpIdx2);
5020     break;
5021   }
5022   case X86::BLENDPDrri:
5023   case X86::BLENDPSrri:
5024   case X86::PBLENDWrri:
5025   case X86::VBLENDPDrri:
5026   case X86::VBLENDPSrri:
5027   case X86::VBLENDPDYrri:
5028   case X86::VBLENDPSYrri:
5029   case X86::VPBLENDDrri:
5030   case X86::VPBLENDWrri:
5031   case X86::VPBLENDDYrri:
5032   case X86::VPBLENDWYrri:{
5033     unsigned Mask;
5034     switch (MI.getOpcode()) {
5035     default: llvm_unreachable("Unreachable!");
5036     case X86::BLENDPDrri:    Mask = 0x03; break;
5037     case X86::BLENDPSrri:    Mask = 0x0F; break;
5038     case X86::PBLENDWrri:    Mask = 0xFF; break;
5039     case X86::VBLENDPDrri:   Mask = 0x03; break;
5040     case X86::VBLENDPSrri:   Mask = 0x0F; break;
5041     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
5042     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
5043     case X86::VPBLENDDrri:   Mask = 0x0F; break;
5044     case X86::VPBLENDWrri:   Mask = 0xFF; break;
5045     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
5046     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
5047     }
5048     // Only the least significant bits of Imm are used.
5049     unsigned Imm = MI.getOperand(3).getImm() & Mask;
5050     auto &WorkingMI = cloneIfNew(MI);
5051     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
5052     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5053                                                    OpIdx1, OpIdx2);
5054   }
5055   case X86::MOVSDrr:
5056   case X86::MOVSSrr:
5057   case X86::VMOVSDrr:
5058   case X86::VMOVSSrr:{
5059     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
5060     if (!Subtarget.hasSSE41())
5061       return nullptr;
5062 
5063     unsigned Mask, Opc;
5064     switch (MI.getOpcode()) {
5065     default: llvm_unreachable("Unreachable!");
5066     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
5067     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
5068     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
5069     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
5070     }
5071 
5072     // MOVSD/MOVSS's 2nd operand is a FR64/FR32 reg class - we need to copy
5073     // this over to a VR128 class like the 1st operand to use a BLENDPD/BLENDPS.
5074     auto &MRI = MI.getParent()->getParent()->getRegInfo();
5075     auto VR128RC = MRI.getRegClass(MI.getOperand(1).getReg());
5076     unsigned VR128 = MRI.createVirtualRegister(VR128RC);
5077     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY),
5078             VR128)
5079         .addReg(MI.getOperand(2).getReg());
5080 
5081     auto &WorkingMI = cloneIfNew(MI);
5082     WorkingMI.setDesc(get(Opc));
5083     WorkingMI.getOperand(2).setReg(VR128);
5084     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
5085     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5086                                                    OpIdx1, OpIdx2);
5087   }
5088   case X86::PCLMULQDQrr:
5089   case X86::VPCLMULQDQrr:{
5090     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
5091     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
5092     unsigned Imm = MI.getOperand(3).getImm();
5093     unsigned Src1Hi = Imm & 0x01;
5094     unsigned Src2Hi = Imm & 0x10;
5095     auto &WorkingMI = cloneIfNew(MI);
5096     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
5097     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5098                                                    OpIdx1, OpIdx2);
5099   }
5100   case X86::CMPSDrr:
5101   case X86::CMPSSrr:
5102   case X86::CMPPDrri:
5103   case X86::CMPPSrri:
5104   case X86::VCMPSDrr:
5105   case X86::VCMPSSrr:
5106   case X86::VCMPPDrri:
5107   case X86::VCMPPSrri:
5108   case X86::VCMPPDYrri:
5109   case X86::VCMPPSYrri:
5110   case X86::VCMPSDZrr:
5111   case X86::VCMPSSZrr:
5112   case X86::VCMPPDZrri:
5113   case X86::VCMPPSZrri:
5114   case X86::VCMPPDZ128rri:
5115   case X86::VCMPPSZ128rri:
5116   case X86::VCMPPDZ256rri:
5117   case X86::VCMPPSZ256rri: {
5118     // Float comparison can be safely commuted for
5119     // Ordered/Unordered/Equal/NotEqual tests
5120     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5121     switch (Imm) {
5122     case 0x00: // EQUAL
5123     case 0x03: // UNORDERED
5124     case 0x04: // NOT EQUAL
5125     case 0x07: // ORDERED
5126       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5127     default:
5128       return nullptr;
5129     }
5130   }
5131   case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
5132   case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
5133   case X86::VPCMPBZrri:    case X86::VPCMPUBZrri:
5134   case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
5135   case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
5136   case X86::VPCMPDZrri:    case X86::VPCMPUDZrri:
5137   case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
5138   case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
5139   case X86::VPCMPQZrri:    case X86::VPCMPUQZrri:
5140   case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
5141   case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
5142   case X86::VPCMPWZrri:    case X86::VPCMPUWZrri: {
5143     // Flip comparison mode immediate (if necessary).
5144     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5145     switch (Imm) {
5146     default: llvm_unreachable("Unreachable!");
5147     case 0x01: Imm = 0x06; break; // LT  -> NLE
5148     case 0x02: Imm = 0x05; break; // LE  -> NLT
5149     case 0x05: Imm = 0x02; break; // NLT -> LE
5150     case 0x06: Imm = 0x01; break; // NLE -> LT
5151     case 0x00: // EQ
5152     case 0x03: // FALSE
5153     case 0x04: // NE
5154     case 0x07: // TRUE
5155       break;
5156     }
5157     auto &WorkingMI = cloneIfNew(MI);
5158     WorkingMI.getOperand(3).setImm(Imm);
5159     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5160                                                    OpIdx1, OpIdx2);
5161   }
5162   case X86::VPCOMBri: case X86::VPCOMUBri:
5163   case X86::VPCOMDri: case X86::VPCOMUDri:
5164   case X86::VPCOMQri: case X86::VPCOMUQri:
5165   case X86::VPCOMWri: case X86::VPCOMUWri: {
5166     // Flip comparison mode immediate (if necessary).
5167     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5168     switch (Imm) {
5169     default: llvm_unreachable("Unreachable!");
5170     case 0x00: Imm = 0x02; break; // LT -> GT
5171     case 0x01: Imm = 0x03; break; // LE -> GE
5172     case 0x02: Imm = 0x00; break; // GT -> LT
5173     case 0x03: Imm = 0x01; break; // GE -> LE
5174     case 0x04: // EQ
5175     case 0x05: // NE
5176     case 0x06: // FALSE
5177     case 0x07: // TRUE
5178       break;
5179     }
5180     auto &WorkingMI = cloneIfNew(MI);
5181     WorkingMI.getOperand(3).setImm(Imm);
5182     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5183                                                    OpIdx1, OpIdx2);
5184   }
5185   case X86::VPERM2F128rr:
5186   case X86::VPERM2I128rr: {
5187     // Flip permute source immediate.
5188     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
5189     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
5190     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
5191     auto &WorkingMI = cloneIfNew(MI);
5192     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
5193     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5194                                                    OpIdx1, OpIdx2);
5195   }
5196   case X86::MOVHLPSrr:
5197   case X86::UNPCKHPDrr: {
5198     if (!Subtarget.hasSSE2())
5199       return nullptr;
5200 
5201     unsigned Opc = MI.getOpcode();
5202     switch (Opc) {
5203       default: llvm_unreachable("Unreachable!");
5204       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
5205       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
5206     }
5207     auto &WorkingMI = cloneIfNew(MI);
5208     WorkingMI.setDesc(get(Opc));
5209     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5210                                                    OpIdx1, OpIdx2);
5211   }
5212   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
5213   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
5214   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
5215   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
5216   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
5217   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
5218   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
5219   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
5220   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
5221   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
5222   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
5223   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
5224   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
5225   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
5226   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
5227   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
5228     unsigned Opc;
5229     switch (MI.getOpcode()) {
5230     default: llvm_unreachable("Unreachable!");
5231     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
5232     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
5233     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
5234     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
5235     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
5236     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
5237     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
5238     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
5239     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
5240     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
5241     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
5242     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
5243     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
5244     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
5245     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
5246     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
5247     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
5248     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
5249     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
5250     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
5251     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
5252     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
5253     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
5254     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
5255     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
5256     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
5257     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
5258     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
5259     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
5260     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
5261     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
5262     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
5263     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
5264     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
5265     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
5266     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
5267     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
5268     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
5269     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
5270     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
5271     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
5272     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
5273     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
5274     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
5275     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
5276     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
5277     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
5278     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
5279     }
5280     auto &WorkingMI = cloneIfNew(MI);
5281     WorkingMI.setDesc(get(Opc));
5282     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5283                                                    OpIdx1, OpIdx2);
5284   }
5285   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5286   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5287   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5288   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5289   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5290   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5291   case X86::VPTERNLOGDZrrik:
5292   case X86::VPTERNLOGDZ128rrik:
5293   case X86::VPTERNLOGDZ256rrik:
5294   case X86::VPTERNLOGQZrrik:
5295   case X86::VPTERNLOGQZ128rrik:
5296   case X86::VPTERNLOGQZ256rrik:
5297   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5298   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5299   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5300   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5301   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5302   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5303   case X86::VPTERNLOGDZ128rmbi:
5304   case X86::VPTERNLOGDZ256rmbi:
5305   case X86::VPTERNLOGDZrmbi:
5306   case X86::VPTERNLOGQZ128rmbi:
5307   case X86::VPTERNLOGQZ256rmbi:
5308   case X86::VPTERNLOGQZrmbi:
5309   case X86::VPTERNLOGDZ128rmbikz:
5310   case X86::VPTERNLOGDZ256rmbikz:
5311   case X86::VPTERNLOGDZrmbikz:
5312   case X86::VPTERNLOGQZ128rmbikz:
5313   case X86::VPTERNLOGQZ256rmbikz:
5314   case X86::VPTERNLOGQZrmbikz: {
5315     auto &WorkingMI = cloneIfNew(MI);
5316     if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
5317       return nullptr;
5318     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5319                                                    OpIdx1, OpIdx2);
5320   }
5321   default: {
5322     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
5323       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
5324       auto &WorkingMI = cloneIfNew(MI);
5325       WorkingMI.setDesc(get(Opc));
5326       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5327                                                      OpIdx1, OpIdx2);
5328     }
5329 
5330     const X86InstrFMA3Group *FMA3Group =
5331         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5332     if (FMA3Group) {
5333       unsigned Opc =
5334         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
5335       if (Opc == 0)
5336         return nullptr;
5337       auto &WorkingMI = cloneIfNew(MI);
5338       WorkingMI.setDesc(get(Opc));
5339       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5340                                                      OpIdx1, OpIdx2);
5341     }
5342 
5343     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5344   }
5345   }
5346 }
5347 
5348 bool X86InstrInfo::findFMA3CommutedOpIndices(
5349     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
5350     const X86InstrFMA3Group &FMA3Group) const {
5351 
5352   if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
5353     return false;
5354 
5355   // Check if we can adjust the opcode to preserve the semantics when
5356   // commute the register operands.
5357   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
5358 }
5359 
5360 bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
5361                                                  unsigned &SrcOpIdx1,
5362                                                  unsigned &SrcOpIdx2) const {
5363   uint64_t TSFlags = MI.getDesc().TSFlags;
5364 
5365   unsigned FirstCommutableVecOp = 1;
5366   unsigned LastCommutableVecOp = 3;
5367   unsigned KMaskOp = 0;
5368   if (X86II::isKMasked(TSFlags)) {
5369     // The k-mask operand has index = 2 for masked and zero-masked operations.
5370     KMaskOp = 2;
5371 
5372     // The operand with index = 1 is used as a source for those elements for
5373     // which the corresponding bit in the k-mask is set to 0.
5374     if (X86II::isKMergeMasked(TSFlags))
5375       FirstCommutableVecOp = 3;
5376 
5377     LastCommutableVecOp++;
5378   }
5379 
5380   if (isMem(MI, LastCommutableVecOp))
5381     LastCommutableVecOp--;
5382 
5383   // Only the first RegOpsNum operands are commutable.
5384   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
5385   // that the operand is not specified/fixed.
5386   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
5387       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
5388        SrcOpIdx1 == KMaskOp))
5389     return false;
5390   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
5391       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
5392        SrcOpIdx2 == KMaskOp))
5393     return false;
5394 
5395   // Look for two different register operands assumed to be commutable
5396   // regardless of the FMA opcode. The FMA opcode is adjusted later.
5397   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
5398       SrcOpIdx2 == CommuteAnyOperandIndex) {
5399     unsigned CommutableOpIdx1 = SrcOpIdx1;
5400     unsigned CommutableOpIdx2 = SrcOpIdx2;
5401 
5402     // At least one of operands to be commuted is not specified and
5403     // this method is free to choose appropriate commutable operands.
5404     if (SrcOpIdx1 == SrcOpIdx2)
5405       // Both of operands are not fixed. By default set one of commutable
5406       // operands to the last register operand of the instruction.
5407       CommutableOpIdx2 = LastCommutableVecOp;
5408     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
5409       // Only one of operands is not fixed.
5410       CommutableOpIdx2 = SrcOpIdx1;
5411 
5412     // CommutableOpIdx2 is well defined now. Let's choose another commutable
5413     // operand and assign its index to CommutableOpIdx1.
5414     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
5415     for (CommutableOpIdx1 = LastCommutableVecOp;
5416          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
5417       // Just ignore and skip the k-mask operand.
5418       if (CommutableOpIdx1 == KMaskOp)
5419         continue;
5420 
5421       // The commuted operands must have different registers.
5422       // Otherwise, the commute transformation does not change anything and
5423       // is useless then.
5424       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
5425         break;
5426     }
5427 
5428     // No appropriate commutable operands were found.
5429     if (CommutableOpIdx1 < FirstCommutableVecOp)
5430       return false;
5431 
5432     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
5433     // to return those values.
5434     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5435                               CommutableOpIdx1, CommutableOpIdx2))
5436       return false;
5437   }
5438 
5439   return true;
5440 }
5441 
5442 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
5443                                          unsigned &SrcOpIdx2) const {
5444   const MCInstrDesc &Desc = MI.getDesc();
5445   if (!Desc.isCommutable())
5446     return false;
5447 
5448   switch (MI.getOpcode()) {
5449   case X86::CMPSDrr:
5450   case X86::CMPSSrr:
5451   case X86::CMPPDrri:
5452   case X86::CMPPSrri:
5453   case X86::VCMPSDrr:
5454   case X86::VCMPSSrr:
5455   case X86::VCMPPDrri:
5456   case X86::VCMPPSrri:
5457   case X86::VCMPPDYrri:
5458   case X86::VCMPPSYrri:
5459   case X86::VCMPSDZrr:
5460   case X86::VCMPSSZrr:
5461   case X86::VCMPPDZrri:
5462   case X86::VCMPPSZrri:
5463   case X86::VCMPPDZ128rri:
5464   case X86::VCMPPSZ128rri:
5465   case X86::VCMPPDZ256rri:
5466   case X86::VCMPPSZ256rri: {
5467     // Float comparison can be safely commuted for
5468     // Ordered/Unordered/Equal/NotEqual tests
5469     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5470     switch (Imm) {
5471     case 0x00: // EQUAL
5472     case 0x03: // UNORDERED
5473     case 0x04: // NOT EQUAL
5474     case 0x07: // ORDERED
5475       // The indices of the commutable operands are 1 and 2.
5476       // Assign them to the returned operand indices here.
5477       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
5478     }
5479     return false;
5480   }
5481   case X86::MOVSDrr:
5482   case X86::MOVSSrr:
5483   case X86::VMOVSDrr:
5484   case X86::VMOVSSrr: {
5485     if (Subtarget.hasSSE41())
5486       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5487     return false;
5488   }
5489   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5490   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5491   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5492   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5493   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5494   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5495   case X86::VPTERNLOGDZrrik:
5496   case X86::VPTERNLOGDZ128rrik:
5497   case X86::VPTERNLOGDZ256rrik:
5498   case X86::VPTERNLOGQZrrik:
5499   case X86::VPTERNLOGQZ128rrik:
5500   case X86::VPTERNLOGQZ256rrik:
5501   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5502   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5503   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5504   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5505   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5506   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5507   case X86::VPTERNLOGDZ128rmbi:
5508   case X86::VPTERNLOGDZ256rmbi:
5509   case X86::VPTERNLOGDZrmbi:
5510   case X86::VPTERNLOGQZ128rmbi:
5511   case X86::VPTERNLOGQZ256rmbi:
5512   case X86::VPTERNLOGQZrmbi:
5513   case X86::VPTERNLOGDZ128rmbikz:
5514   case X86::VPTERNLOGDZ256rmbikz:
5515   case X86::VPTERNLOGDZrmbikz:
5516   case X86::VPTERNLOGQZ128rmbikz:
5517   case X86::VPTERNLOGQZ256rmbikz:
5518   case X86::VPTERNLOGQZrmbikz:
5519     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5520   default:
5521     const X86InstrFMA3Group *FMA3Group =
5522         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5523     if (FMA3Group)
5524       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
5525 
5526     // Handled masked instructions since we need to skip over the mask input
5527     // and the preserved input.
5528     if (Desc.TSFlags & X86II::EVEX_K) {
5529       // First assume that the first input is the mask operand and skip past it.
5530       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
5531       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
5532       // Check if the first input is tied. If there isn't one then we only
5533       // need to skip the mask operand which we did above.
5534       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
5535                                              MCOI::TIED_TO) != -1)) {
5536         // If this is zero masking instruction with a tied operand, we need to
5537         // move the first index back to the first input since this must
5538         // be a 3 input instruction and we want the first two non-mask inputs.
5539         // Otherwise this is a 2 input instruction with a preserved input and
5540         // mask, so we need to move the indices to skip one more input.
5541         if (Desc.TSFlags & X86II::EVEX_Z)
5542           --CommutableOpIdx1;
5543         else {
5544           ++CommutableOpIdx1;
5545           ++CommutableOpIdx2;
5546         }
5547       }
5548 
5549       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5550                                 CommutableOpIdx1, CommutableOpIdx2))
5551         return false;
5552 
5553       if (!MI.getOperand(SrcOpIdx1).isReg() ||
5554           !MI.getOperand(SrcOpIdx2).isReg())
5555         // No idea.
5556         return false;
5557       return true;
5558     }
5559 
5560     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5561   }
5562   return false;
5563 }
5564 
5565 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
5566   switch (BrOpc) {
5567   default: return X86::COND_INVALID;
5568   case X86::JE_1:  return X86::COND_E;
5569   case X86::JNE_1: return X86::COND_NE;
5570   case X86::JL_1:  return X86::COND_L;
5571   case X86::JLE_1: return X86::COND_LE;
5572   case X86::JG_1:  return X86::COND_G;
5573   case X86::JGE_1: return X86::COND_GE;
5574   case X86::JB_1:  return X86::COND_B;
5575   case X86::JBE_1: return X86::COND_BE;
5576   case X86::JA_1:  return X86::COND_A;
5577   case X86::JAE_1: return X86::COND_AE;
5578   case X86::JS_1:  return X86::COND_S;
5579   case X86::JNS_1: return X86::COND_NS;
5580   case X86::JP_1:  return X86::COND_P;
5581   case X86::JNP_1: return X86::COND_NP;
5582   case X86::JO_1:  return X86::COND_O;
5583   case X86::JNO_1: return X86::COND_NO;
5584   }
5585 }
5586 
5587 /// Return condition code of a SET opcode.
5588 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
5589   switch (Opc) {
5590   default: return X86::COND_INVALID;
5591   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
5592   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
5593   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
5594   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
5595   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
5596   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
5597   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
5598   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
5599   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
5600   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
5601   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
5602   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
5603   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
5604   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
5605   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
5606   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
5607   }
5608 }
5609 
5610 /// Return condition code of a CMov opcode.
5611 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
5612   switch (Opc) {
5613   default: return X86::COND_INVALID;
5614   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
5615   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
5616     return X86::COND_A;
5617   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
5618   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
5619     return X86::COND_AE;
5620   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
5621   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
5622     return X86::COND_B;
5623   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
5624   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
5625     return X86::COND_BE;
5626   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
5627   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
5628     return X86::COND_E;
5629   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
5630   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
5631     return X86::COND_G;
5632   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
5633   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
5634     return X86::COND_GE;
5635   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
5636   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
5637     return X86::COND_L;
5638   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
5639   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
5640     return X86::COND_LE;
5641   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
5642   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
5643     return X86::COND_NE;
5644   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
5645   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
5646     return X86::COND_NO;
5647   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
5648   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
5649     return X86::COND_NP;
5650   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
5651   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
5652     return X86::COND_NS;
5653   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
5654   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
5655     return X86::COND_O;
5656   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
5657   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
5658     return X86::COND_P;
5659   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
5660   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
5661     return X86::COND_S;
5662   }
5663 }
5664 
5665 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
5666   switch (CC) {
5667   default: llvm_unreachable("Illegal condition code!");
5668   case X86::COND_E:  return X86::JE_1;
5669   case X86::COND_NE: return X86::JNE_1;
5670   case X86::COND_L:  return X86::JL_1;
5671   case X86::COND_LE: return X86::JLE_1;
5672   case X86::COND_G:  return X86::JG_1;
5673   case X86::COND_GE: return X86::JGE_1;
5674   case X86::COND_B:  return X86::JB_1;
5675   case X86::COND_BE: return X86::JBE_1;
5676   case X86::COND_A:  return X86::JA_1;
5677   case X86::COND_AE: return X86::JAE_1;
5678   case X86::COND_S:  return X86::JS_1;
5679   case X86::COND_NS: return X86::JNS_1;
5680   case X86::COND_P:  return X86::JP_1;
5681   case X86::COND_NP: return X86::JNP_1;
5682   case X86::COND_O:  return X86::JO_1;
5683   case X86::COND_NO: return X86::JNO_1;
5684   }
5685 }
5686 
5687 /// Return the inverse of the specified condition,
5688 /// e.g. turning COND_E to COND_NE.
5689 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
5690   switch (CC) {
5691   default: llvm_unreachable("Illegal condition code!");
5692   case X86::COND_E:  return X86::COND_NE;
5693   case X86::COND_NE: return X86::COND_E;
5694   case X86::COND_L:  return X86::COND_GE;
5695   case X86::COND_LE: return X86::COND_G;
5696   case X86::COND_G:  return X86::COND_LE;
5697   case X86::COND_GE: return X86::COND_L;
5698   case X86::COND_B:  return X86::COND_AE;
5699   case X86::COND_BE: return X86::COND_A;
5700   case X86::COND_A:  return X86::COND_BE;
5701   case X86::COND_AE: return X86::COND_B;
5702   case X86::COND_S:  return X86::COND_NS;
5703   case X86::COND_NS: return X86::COND_S;
5704   case X86::COND_P:  return X86::COND_NP;
5705   case X86::COND_NP: return X86::COND_P;
5706   case X86::COND_O:  return X86::COND_NO;
5707   case X86::COND_NO: return X86::COND_O;
5708   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
5709   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
5710   }
5711 }
5712 
5713 /// Assuming the flags are set by MI(a,b), return the condition code if we
5714 /// modify the instructions such that flags are set by MI(b,a).
5715 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
5716   switch (CC) {
5717   default: return X86::COND_INVALID;
5718   case X86::COND_E:  return X86::COND_E;
5719   case X86::COND_NE: return X86::COND_NE;
5720   case X86::COND_L:  return X86::COND_G;
5721   case X86::COND_LE: return X86::COND_GE;
5722   case X86::COND_G:  return X86::COND_L;
5723   case X86::COND_GE: return X86::COND_LE;
5724   case X86::COND_B:  return X86::COND_A;
5725   case X86::COND_BE: return X86::COND_AE;
5726   case X86::COND_A:  return X86::COND_B;
5727   case X86::COND_AE: return X86::COND_BE;
5728   }
5729 }
5730 
5731 /// Return a set opcode for the given condition and
5732 /// whether it has memory operand.
5733 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
5734   static const uint16_t Opc[16][2] = {
5735     { X86::SETAr,  X86::SETAm  },
5736     { X86::SETAEr, X86::SETAEm },
5737     { X86::SETBr,  X86::SETBm  },
5738     { X86::SETBEr, X86::SETBEm },
5739     { X86::SETEr,  X86::SETEm  },
5740     { X86::SETGr,  X86::SETGm  },
5741     { X86::SETGEr, X86::SETGEm },
5742     { X86::SETLr,  X86::SETLm  },
5743     { X86::SETLEr, X86::SETLEm },
5744     { X86::SETNEr, X86::SETNEm },
5745     { X86::SETNOr, X86::SETNOm },
5746     { X86::SETNPr, X86::SETNPm },
5747     { X86::SETNSr, X86::SETNSm },
5748     { X86::SETOr,  X86::SETOm  },
5749     { X86::SETPr,  X86::SETPm  },
5750     { X86::SETSr,  X86::SETSm  }
5751   };
5752 
5753   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
5754   return Opc[CC][HasMemoryOperand ? 1 : 0];
5755 }
5756 
5757 /// Return a cmov opcode for the given condition,
5758 /// register size in bytes, and operand type.
5759 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
5760                               bool HasMemoryOperand) {
5761   static const uint16_t Opc[32][3] = {
5762     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
5763     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
5764     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
5765     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
5766     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
5767     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
5768     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
5769     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
5770     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
5771     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
5772     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
5773     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
5774     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
5775     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
5776     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
5777     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
5778     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
5779     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
5780     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
5781     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
5782     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
5783     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
5784     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
5785     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
5786     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
5787     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
5788     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
5789     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
5790     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
5791     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
5792     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
5793     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
5794   };
5795 
5796   assert(CC < 16 && "Can only handle standard cond codes");
5797   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
5798   switch(RegBytes) {
5799   default: llvm_unreachable("Illegal register size!");
5800   case 2: return Opc[Idx][0];
5801   case 4: return Opc[Idx][1];
5802   case 8: return Opc[Idx][2];
5803   }
5804 }
5805 
5806 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
5807   if (!MI.isTerminator()) return false;
5808 
5809   // Conditional branch is a special case.
5810   if (MI.isBranch() && !MI.isBarrier())
5811     return true;
5812   if (!MI.isPredicable())
5813     return true;
5814   return !isPredicated(MI);
5815 }
5816 
5817 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
5818   switch (MI.getOpcode()) {
5819   case X86::TCRETURNdi:
5820   case X86::TCRETURNri:
5821   case X86::TCRETURNmi:
5822   case X86::TCRETURNdi64:
5823   case X86::TCRETURNri64:
5824   case X86::TCRETURNmi64:
5825     return true;
5826   default:
5827     return false;
5828   }
5829 }
5830 
5831 bool X86InstrInfo::canMakeTailCallConditional(
5832     SmallVectorImpl<MachineOperand> &BranchCond,
5833     const MachineInstr &TailCall) const {
5834   if (TailCall.getOpcode() != X86::TCRETURNdi &&
5835       TailCall.getOpcode() != X86::TCRETURNdi64) {
5836     // Only direct calls can be done with a conditional branch.
5837     return false;
5838   }
5839 
5840   const MachineFunction *MF = TailCall.getParent()->getParent();
5841   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
5842     // Conditional tail calls confuse the Win64 unwinder.
5843     return false;
5844   }
5845 
5846   assert(BranchCond.size() == 1);
5847   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
5848     // Can't make a conditional tail call with this condition.
5849     return false;
5850   }
5851 
5852   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5853   if (X86FI->getTCReturnAddrDelta() != 0 ||
5854       TailCall.getOperand(1).getImm() != 0) {
5855     // A conditional tail call cannot do any stack adjustment.
5856     return false;
5857   }
5858 
5859   return true;
5860 }
5861 
5862 void X86InstrInfo::replaceBranchWithTailCall(
5863     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
5864     const MachineInstr &TailCall) const {
5865   assert(canMakeTailCallConditional(BranchCond, TailCall));
5866 
5867   MachineBasicBlock::iterator I = MBB.end();
5868   while (I != MBB.begin()) {
5869     --I;
5870     if (I->isDebugValue())
5871       continue;
5872     if (!I->isBranch())
5873       assert(0 && "Can't find the branch to replace!");
5874 
5875     X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
5876     assert(BranchCond.size() == 1);
5877     if (CC != BranchCond[0].getImm())
5878       continue;
5879 
5880     break;
5881   }
5882 
5883   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
5884                                                          : X86::TCRETURNdi64cc;
5885 
5886   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
5887   MIB->addOperand(TailCall.getOperand(0)); // Destination.
5888   MIB.addImm(0); // Stack offset (not used).
5889   MIB->addOperand(BranchCond[0]); // Condition.
5890   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
5891 
5892   // Add implicit uses and defs of all live regs potentially clobbered by the
5893   // call. This way they still appear live across the call.
5894   LivePhysRegs LiveRegs(&getRegisterInfo());
5895   LiveRegs.addLiveOuts(MBB);
5896   SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers;
5897   LiveRegs.stepForward(*MIB, Clobbers);
5898   for (const auto &C : Clobbers) {
5899     MIB.addReg(C.first, RegState::Implicit);
5900     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
5901   }
5902 
5903   I->eraseFromParent();
5904 }
5905 
5906 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
5907 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
5908 // fallthrough MBB cannot be identified.
5909 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
5910                                             MachineBasicBlock *TBB) {
5911   // Look for non-EHPad successors other than TBB. If we find exactly one, it
5912   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
5913   // and fallthrough MBB. If we find more than one, we cannot identify the
5914   // fallthrough MBB and should return nullptr.
5915   MachineBasicBlock *FallthroughBB = nullptr;
5916   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
5917     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
5918       continue;
5919     // Return a nullptr if we found more than one fallthrough successor.
5920     if (FallthroughBB && FallthroughBB != TBB)
5921       return nullptr;
5922     FallthroughBB = *SI;
5923   }
5924   return FallthroughBB;
5925 }
5926 
5927 bool X86InstrInfo::AnalyzeBranchImpl(
5928     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
5929     SmallVectorImpl<MachineOperand> &Cond,
5930     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
5931 
5932   // Start from the bottom of the block and work up, examining the
5933   // terminator instructions.
5934   MachineBasicBlock::iterator I = MBB.end();
5935   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
5936   while (I != MBB.begin()) {
5937     --I;
5938     if (I->isDebugValue())
5939       continue;
5940 
5941     // Working from the bottom, when we see a non-terminator instruction, we're
5942     // done.
5943     if (!isUnpredicatedTerminator(*I))
5944       break;
5945 
5946     // A terminator that isn't a branch can't easily be handled by this
5947     // analysis.
5948     if (!I->isBranch())
5949       return true;
5950 
5951     // Handle unconditional branches.
5952     if (I->getOpcode() == X86::JMP_1) {
5953       UnCondBrIter = I;
5954 
5955       if (!AllowModify) {
5956         TBB = I->getOperand(0).getMBB();
5957         continue;
5958       }
5959 
5960       // If the block has any instructions after a JMP, delete them.
5961       while (std::next(I) != MBB.end())
5962         std::next(I)->eraseFromParent();
5963 
5964       Cond.clear();
5965       FBB = nullptr;
5966 
5967       // Delete the JMP if it's equivalent to a fall-through.
5968       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
5969         TBB = nullptr;
5970         I->eraseFromParent();
5971         I = MBB.end();
5972         UnCondBrIter = MBB.end();
5973         continue;
5974       }
5975 
5976       // TBB is used to indicate the unconditional destination.
5977       TBB = I->getOperand(0).getMBB();
5978       continue;
5979     }
5980 
5981     // Handle conditional branches.
5982     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
5983     if (BranchCode == X86::COND_INVALID)
5984       return true;  // Can't handle indirect branch.
5985 
5986     // Working from the bottom, handle the first conditional branch.
5987     if (Cond.empty()) {
5988       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
5989       if (AllowModify && UnCondBrIter != MBB.end() &&
5990           MBB.isLayoutSuccessor(TargetBB)) {
5991         // If we can modify the code and it ends in something like:
5992         //
5993         //     jCC L1
5994         //     jmp L2
5995         //   L1:
5996         //     ...
5997         //   L2:
5998         //
5999         // Then we can change this to:
6000         //
6001         //     jnCC L2
6002         //   L1:
6003         //     ...
6004         //   L2:
6005         //
6006         // Which is a bit more efficient.
6007         // We conditionally jump to the fall-through block.
6008         BranchCode = GetOppositeBranchCondition(BranchCode);
6009         unsigned JNCC = GetCondBranchFromCond(BranchCode);
6010         MachineBasicBlock::iterator OldInst = I;
6011 
6012         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
6013           .addMBB(UnCondBrIter->getOperand(0).getMBB());
6014         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
6015           .addMBB(TargetBB);
6016 
6017         OldInst->eraseFromParent();
6018         UnCondBrIter->eraseFromParent();
6019 
6020         // Restart the analysis.
6021         UnCondBrIter = MBB.end();
6022         I = MBB.end();
6023         continue;
6024       }
6025 
6026       FBB = TBB;
6027       TBB = I->getOperand(0).getMBB();
6028       Cond.push_back(MachineOperand::CreateImm(BranchCode));
6029       CondBranches.push_back(&*I);
6030       continue;
6031     }
6032 
6033     // Handle subsequent conditional branches. Only handle the case where all
6034     // conditional branches branch to the same destination and their condition
6035     // opcodes fit one of the special multi-branch idioms.
6036     assert(Cond.size() == 1);
6037     assert(TBB);
6038 
6039     // If the conditions are the same, we can leave them alone.
6040     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
6041     auto NewTBB = I->getOperand(0).getMBB();
6042     if (OldBranchCode == BranchCode && TBB == NewTBB)
6043       continue;
6044 
6045     // If they differ, see if they fit one of the known patterns. Theoretically,
6046     // we could handle more patterns here, but we shouldn't expect to see them
6047     // if instruction selection has done a reasonable job.
6048     if (TBB == NewTBB &&
6049                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
6050                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
6051       BranchCode = X86::COND_NE_OR_P;
6052     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
6053                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
6054       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
6055         return true;
6056 
6057       // X86::COND_E_AND_NP usually has two different branch destinations.
6058       //
6059       // JP B1
6060       // JE B2
6061       // JMP B1
6062       // B1:
6063       // B2:
6064       //
6065       // Here this condition branches to B2 only if NP && E. It has another
6066       // equivalent form:
6067       //
6068       // JNE B1
6069       // JNP B2
6070       // JMP B1
6071       // B1:
6072       // B2:
6073       //
6074       // Similarly it branches to B2 only if E && NP. That is why this condition
6075       // is named with COND_E_AND_NP.
6076       BranchCode = X86::COND_E_AND_NP;
6077     } else
6078       return true;
6079 
6080     // Update the MachineOperand.
6081     Cond[0].setImm(BranchCode);
6082     CondBranches.push_back(&*I);
6083   }
6084 
6085   return false;
6086 }
6087 
6088 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
6089                                  MachineBasicBlock *&TBB,
6090                                  MachineBasicBlock *&FBB,
6091                                  SmallVectorImpl<MachineOperand> &Cond,
6092                                  bool AllowModify) const {
6093   SmallVector<MachineInstr *, 4> CondBranches;
6094   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
6095 }
6096 
6097 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
6098                                           MachineBranchPredicate &MBP,
6099                                           bool AllowModify) const {
6100   using namespace std::placeholders;
6101 
6102   SmallVector<MachineOperand, 4> Cond;
6103   SmallVector<MachineInstr *, 4> CondBranches;
6104   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
6105                         AllowModify))
6106     return true;
6107 
6108   if (Cond.size() != 1)
6109     return true;
6110 
6111   assert(MBP.TrueDest && "expected!");
6112 
6113   if (!MBP.FalseDest)
6114     MBP.FalseDest = MBB.getNextNode();
6115 
6116   const TargetRegisterInfo *TRI = &getRegisterInfo();
6117 
6118   MachineInstr *ConditionDef = nullptr;
6119   bool SingleUseCondition = true;
6120 
6121   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
6122     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
6123       ConditionDef = &*I;
6124       break;
6125     }
6126 
6127     if (I->readsRegister(X86::EFLAGS, TRI))
6128       SingleUseCondition = false;
6129   }
6130 
6131   if (!ConditionDef)
6132     return true;
6133 
6134   if (SingleUseCondition) {
6135     for (auto *Succ : MBB.successors())
6136       if (Succ->isLiveIn(X86::EFLAGS))
6137         SingleUseCondition = false;
6138   }
6139 
6140   MBP.ConditionDef = ConditionDef;
6141   MBP.SingleUseCondition = SingleUseCondition;
6142 
6143   // Currently we only recognize the simple pattern:
6144   //
6145   //   test %reg, %reg
6146   //   je %label
6147   //
6148   const unsigned TestOpcode =
6149       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
6150 
6151   if (ConditionDef->getOpcode() == TestOpcode &&
6152       ConditionDef->getNumOperands() == 3 &&
6153       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
6154       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
6155     MBP.LHS = ConditionDef->getOperand(0);
6156     MBP.RHS = MachineOperand::CreateImm(0);
6157     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
6158                         ? MachineBranchPredicate::PRED_NE
6159                         : MachineBranchPredicate::PRED_EQ;
6160     return false;
6161   }
6162 
6163   return true;
6164 }
6165 
6166 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
6167                                     int *BytesRemoved) const {
6168   assert(!BytesRemoved && "code size not handled");
6169 
6170   MachineBasicBlock::iterator I = MBB.end();
6171   unsigned Count = 0;
6172 
6173   while (I != MBB.begin()) {
6174     --I;
6175     if (I->isDebugValue())
6176       continue;
6177     if (I->getOpcode() != X86::JMP_1 &&
6178         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
6179       break;
6180     // Remove the branch.
6181     I->eraseFromParent();
6182     I = MBB.end();
6183     ++Count;
6184   }
6185 
6186   return Count;
6187 }
6188 
6189 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
6190                                     MachineBasicBlock *TBB,
6191                                     MachineBasicBlock *FBB,
6192                                     ArrayRef<MachineOperand> Cond,
6193                                     const DebugLoc &DL,
6194                                     int *BytesAdded) const {
6195   // Shouldn't be a fall through.
6196   assert(TBB && "insertBranch must not be told to insert a fallthrough");
6197   assert((Cond.size() == 1 || Cond.size() == 0) &&
6198          "X86 branch conditions have one component!");
6199   assert(!BytesAdded && "code size not handled");
6200 
6201   if (Cond.empty()) {
6202     // Unconditional branch?
6203     assert(!FBB && "Unconditional branch with multiple successors!");
6204     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
6205     return 1;
6206   }
6207 
6208   // If FBB is null, it is implied to be a fall-through block.
6209   bool FallThru = FBB == nullptr;
6210 
6211   // Conditional branch.
6212   unsigned Count = 0;
6213   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
6214   switch (CC) {
6215   case X86::COND_NE_OR_P:
6216     // Synthesize NE_OR_P with two branches.
6217     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
6218     ++Count;
6219     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
6220     ++Count;
6221     break;
6222   case X86::COND_E_AND_NP:
6223     // Use the next block of MBB as FBB if it is null.
6224     if (FBB == nullptr) {
6225       FBB = getFallThroughMBB(&MBB, TBB);
6226       assert(FBB && "MBB cannot be the last block in function when the false "
6227                     "body is a fall-through.");
6228     }
6229     // Synthesize COND_E_AND_NP with two branches.
6230     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
6231     ++Count;
6232     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
6233     ++Count;
6234     break;
6235   default: {
6236     unsigned Opc = GetCondBranchFromCond(CC);
6237     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
6238     ++Count;
6239   }
6240   }
6241   if (!FallThru) {
6242     // Two-way Conditional branch. Insert the second branch.
6243     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
6244     ++Count;
6245   }
6246   return Count;
6247 }
6248 
6249 bool X86InstrInfo::
6250 canInsertSelect(const MachineBasicBlock &MBB,
6251                 ArrayRef<MachineOperand> Cond,
6252                 unsigned TrueReg, unsigned FalseReg,
6253                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
6254   // Not all subtargets have cmov instructions.
6255   if (!Subtarget.hasCMov())
6256     return false;
6257   if (Cond.size() != 1)
6258     return false;
6259   // We cannot do the composite conditions, at least not in SSA form.
6260   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
6261     return false;
6262 
6263   // Check register classes.
6264   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6265   const TargetRegisterClass *RC =
6266     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
6267   if (!RC)
6268     return false;
6269 
6270   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
6271   if (X86::GR16RegClass.hasSubClassEq(RC) ||
6272       X86::GR32RegClass.hasSubClassEq(RC) ||
6273       X86::GR64RegClass.hasSubClassEq(RC)) {
6274     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
6275     // Bridge. Probably Ivy Bridge as well.
6276     CondCycles = 2;
6277     TrueCycles = 2;
6278     FalseCycles = 2;
6279     return true;
6280   }
6281 
6282   // Can't do vectors.
6283   return false;
6284 }
6285 
6286 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
6287                                 MachineBasicBlock::iterator I,
6288                                 const DebugLoc &DL, unsigned DstReg,
6289                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
6290                                 unsigned FalseReg) const {
6291   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6292   assert(Cond.size() == 1 && "Invalid Cond array");
6293   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
6294                                  MRI.getRegClass(DstReg)->getSize(),
6295                                  false /*HasMemoryOperand*/);
6296   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
6297 }
6298 
6299 /// Test if the given register is a physical h register.
6300 static bool isHReg(unsigned Reg) {
6301   return X86::GR8_ABCD_HRegClass.contains(Reg);
6302 }
6303 
6304 // Try and copy between VR128/VR64 and GR64 registers.
6305 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
6306                                         const X86Subtarget &Subtarget) {
6307   bool HasAVX = Subtarget.hasAVX();
6308   bool HasAVX512 = Subtarget.hasAVX512();
6309 
6310   // SrcReg(MaskReg) -> DestReg(GR64)
6311   // SrcReg(MaskReg) -> DestReg(GR32)
6312   // SrcReg(MaskReg) -> DestReg(GR16)
6313   // SrcReg(MaskReg) -> DestReg(GR8)
6314 
6315   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6316   if (X86::VK16RegClass.contains(SrcReg)) {
6317     if (X86::GR64RegClass.contains(DestReg)) {
6318       assert(Subtarget.hasBWI());
6319       return X86::KMOVQrk;
6320     }
6321     if (X86::GR32RegClass.contains(DestReg))
6322       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
6323     if (X86::GR16RegClass.contains(DestReg)) {
6324       DestReg = getX86SubSuperRegister(DestReg, 32);
6325       return X86::KMOVWrk;
6326     }
6327     if (X86::GR8RegClass.contains(DestReg)) {
6328       DestReg = getX86SubSuperRegister(DestReg, 32);
6329       return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
6330     }
6331   }
6332 
6333   // SrcReg(GR64) -> DestReg(MaskReg)
6334   // SrcReg(GR32) -> DestReg(MaskReg)
6335   // SrcReg(GR16) -> DestReg(MaskReg)
6336   // SrcReg(GR8)  -> DestReg(MaskReg)
6337 
6338   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6339   if (X86::VK16RegClass.contains(DestReg)) {
6340     if (X86::GR64RegClass.contains(SrcReg)) {
6341       assert(Subtarget.hasBWI());
6342       return X86::KMOVQkr;
6343     }
6344     if (X86::GR32RegClass.contains(SrcReg))
6345       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
6346     if (X86::GR16RegClass.contains(SrcReg)) {
6347       SrcReg = getX86SubSuperRegister(SrcReg, 32);
6348       return X86::KMOVWkr;
6349     }
6350     if (X86::GR8RegClass.contains(SrcReg)) {
6351       SrcReg = getX86SubSuperRegister(SrcReg, 32);
6352       return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
6353     }
6354   }
6355 
6356 
6357   // SrcReg(VR128) -> DestReg(GR64)
6358   // SrcReg(VR64)  -> DestReg(GR64)
6359   // SrcReg(GR64)  -> DestReg(VR128)
6360   // SrcReg(GR64)  -> DestReg(VR64)
6361 
6362   if (X86::GR64RegClass.contains(DestReg)) {
6363     if (X86::VR128XRegClass.contains(SrcReg))
6364       // Copy from a VR128 register to a GR64 register.
6365       return HasAVX512 ? X86::VMOVPQIto64Zrr :
6366              HasAVX    ? X86::VMOVPQIto64rr  :
6367                          X86::MOVPQIto64rr;
6368     if (X86::VR64RegClass.contains(SrcReg))
6369       // Copy from a VR64 register to a GR64 register.
6370       return X86::MMX_MOVD64from64rr;
6371   } else if (X86::GR64RegClass.contains(SrcReg)) {
6372     // Copy from a GR64 register to a VR128 register.
6373     if (X86::VR128XRegClass.contains(DestReg))
6374       return HasAVX512 ? X86::VMOV64toPQIZrr :
6375              HasAVX    ? X86::VMOV64toPQIrr  :
6376                          X86::MOV64toPQIrr;
6377     // Copy from a GR64 register to a VR64 register.
6378     if (X86::VR64RegClass.contains(DestReg))
6379       return X86::MMX_MOVD64to64rr;
6380   }
6381 
6382   // SrcReg(FR32) -> DestReg(GR32)
6383   // SrcReg(GR32) -> DestReg(FR32)
6384 
6385   if (X86::GR32RegClass.contains(DestReg) &&
6386       X86::FR32XRegClass.contains(SrcReg))
6387     // Copy from a FR32 register to a GR32 register.
6388     return HasAVX512 ? X86::VMOVSS2DIZrr :
6389            HasAVX    ? X86::VMOVSS2DIrr  :
6390                        X86::MOVSS2DIrr;
6391 
6392   if (X86::FR32XRegClass.contains(DestReg) &&
6393       X86::GR32RegClass.contains(SrcReg))
6394     // Copy from a GR32 register to a FR32 register.
6395     return HasAVX512 ? X86::VMOVDI2SSZrr :
6396            HasAVX    ? X86::VMOVDI2SSrr  :
6397                        X86::MOVDI2SSrr;
6398   return 0;
6399 }
6400 
6401 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
6402                                MachineBasicBlock::iterator MI,
6403                                const DebugLoc &DL, unsigned DestReg,
6404                                unsigned SrcReg, bool KillSrc) const {
6405   // First deal with the normal symmetric copies.
6406   bool HasAVX = Subtarget.hasAVX();
6407   bool HasVLX = Subtarget.hasVLX();
6408   unsigned Opc = 0;
6409   if (X86::GR64RegClass.contains(DestReg, SrcReg))
6410     Opc = X86::MOV64rr;
6411   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
6412     Opc = X86::MOV32rr;
6413   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
6414     Opc = X86::MOV16rr;
6415   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
6416     // Copying to or from a physical H register on x86-64 requires a NOREX
6417     // move.  Otherwise use a normal move.
6418     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
6419         Subtarget.is64Bit()) {
6420       Opc = X86::MOV8rr_NOREX;
6421       // Both operands must be encodable without an REX prefix.
6422       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
6423              "8-bit H register can not be copied outside GR8_NOREX");
6424     } else
6425       Opc = X86::MOV8rr;
6426   }
6427   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
6428     Opc = X86::MMX_MOVQ64rr;
6429   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
6430     if (HasVLX)
6431       Opc = X86::VMOVAPSZ128rr;
6432     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
6433       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
6434     else {
6435       // If this an extended register and we don't have VLX we need to use a
6436       // 512-bit move.
6437       Opc = X86::VMOVAPSZrr;
6438       const TargetRegisterInfo *TRI = &getRegisterInfo();
6439       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
6440                                          &X86::VR512RegClass);
6441       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
6442                                         &X86::VR512RegClass);
6443     }
6444   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
6445     if (HasVLX)
6446       Opc = X86::VMOVAPSZ256rr;
6447     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
6448       Opc = X86::VMOVAPSYrr;
6449     else {
6450       // If this an extended register and we don't have VLX we need to use a
6451       // 512-bit move.
6452       Opc = X86::VMOVAPSZrr;
6453       const TargetRegisterInfo *TRI = &getRegisterInfo();
6454       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
6455                                          &X86::VR512RegClass);
6456       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
6457                                         &X86::VR512RegClass);
6458     }
6459   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
6460     Opc = X86::VMOVAPSZrr;
6461   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6462   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
6463     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
6464   if (!Opc)
6465     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
6466 
6467   if (Opc) {
6468     BuildMI(MBB, MI, DL, get(Opc), DestReg)
6469       .addReg(SrcReg, getKillRegState(KillSrc));
6470     return;
6471   }
6472 
6473   bool FromEFLAGS = SrcReg == X86::EFLAGS;
6474   bool ToEFLAGS = DestReg == X86::EFLAGS;
6475   int Reg = FromEFLAGS ? DestReg : SrcReg;
6476   bool is32 = X86::GR32RegClass.contains(Reg);
6477   bool is64 = X86::GR64RegClass.contains(Reg);
6478 
6479   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
6480     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
6481     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
6482     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
6483     int Pop = is64 ? X86::POP64r : X86::POP32r;
6484     int PopF = is64 ? X86::POPF64 : X86::POPF32;
6485     int AX = is64 ? X86::RAX : X86::EAX;
6486 
6487     if (!Subtarget.hasLAHFSAHF()) {
6488       assert(Subtarget.is64Bit() &&
6489              "Not having LAHF/SAHF only happens on 64-bit.");
6490       // Moving EFLAGS to / from another register requires a push and a pop.
6491       // Notice that we have to adjust the stack if we don't want to clobber the
6492       // first frame index. See X86FrameLowering.cpp - usesTheStack.
6493       if (FromEFLAGS) {
6494         BuildMI(MBB, MI, DL, get(PushF));
6495         BuildMI(MBB, MI, DL, get(Pop), DestReg);
6496       }
6497       if (ToEFLAGS) {
6498         BuildMI(MBB, MI, DL, get(Push))
6499             .addReg(SrcReg, getKillRegState(KillSrc));
6500         BuildMI(MBB, MI, DL, get(PopF));
6501       }
6502       return;
6503     }
6504 
6505     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
6506     // inefficient. Instead:
6507     //   - Save the overflow flag OF into AL using SETO, and restore it using a
6508     //     signed 8-bit addition of AL and INT8_MAX.
6509     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
6510     //     using LAHF/SAHF.
6511     //   - When RAX/EAX is live and isn't the destination register, make sure it
6512     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
6513     //     the flags.
6514     // This approach is ~2.25x faster than using PUSHF/POPF.
6515     //
6516     // This is still somewhat inefficient because we don't know which flags are
6517     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
6518     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
6519     //
6520     // PUSHF/POPF is also potentially incorrect because it affects other flags
6521     // such as TF/IF/DF, which LLVM doesn't model.
6522     //
6523     // Notice that we have to adjust the stack if we don't want to clobber the
6524     // first frame index.
6525     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
6526 
6527     const TargetRegisterInfo *TRI = &getRegisterInfo();
6528     MachineBasicBlock::LivenessQueryResult LQR =
6529         MBB.computeRegisterLiveness(TRI, AX, MI);
6530     // We do not want to save and restore AX if we do not have to.
6531     // Moreover, if we do so whereas AX is dead, we would need to set
6532     // an undef flag on the use of AX, otherwise the verifier will
6533     // complain that we read an undef value.
6534     // We do not want to change the behavior of the machine verifier
6535     // as this is usually wrong to read an undef value.
6536     if (MachineBasicBlock::LQR_Unknown == LQR) {
6537       LivePhysRegs LPR(TRI);
6538       LPR.addLiveOuts(MBB);
6539       MachineBasicBlock::iterator I = MBB.end();
6540       while (I != MI) {
6541         --I;
6542         LPR.stepBackward(*I);
6543       }
6544       // AX contains the top most register in the aliasing hierarchy.
6545       // It may not be live, but one of its aliases may be.
6546       for (MCRegAliasIterator AI(AX, TRI, true);
6547            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
6548         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
6549                                 : MachineBasicBlock::LQR_Dead;
6550     }
6551     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
6552     if (!AXDead)
6553       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
6554     if (FromEFLAGS) {
6555       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
6556       BuildMI(MBB, MI, DL, get(X86::LAHF));
6557       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
6558     }
6559     if (ToEFLAGS) {
6560       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
6561       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
6562           .addReg(X86::AL)
6563           .addImm(INT8_MAX);
6564       BuildMI(MBB, MI, DL, get(X86::SAHF));
6565     }
6566     if (!AXDead)
6567       BuildMI(MBB, MI, DL, get(Pop), AX);
6568     return;
6569   }
6570 
6571   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
6572                << " to " << RI.getName(DestReg) << '\n');
6573   llvm_unreachable("Cannot emit physreg copy instruction");
6574 }
6575 
6576 static unsigned getLoadStoreRegOpcode(unsigned Reg,
6577                                       const TargetRegisterClass *RC,
6578                                       bool isStackAligned,
6579                                       const X86Subtarget &STI,
6580                                       bool load) {
6581   bool HasAVX = STI.hasAVX();
6582   bool HasAVX512 = STI.hasAVX512();
6583   bool HasVLX = STI.hasVLX();
6584 
6585   switch (RC->getSize()) {
6586   default:
6587     llvm_unreachable("Unknown spill size");
6588   case 1:
6589     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
6590     if (STI.is64Bit())
6591       // Copying to or from a physical H register on x86-64 requires a NOREX
6592       // move.  Otherwise use a normal move.
6593       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
6594         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
6595     return load ? X86::MOV8rm : X86::MOV8mr;
6596   case 2:
6597     if (X86::VK16RegClass.hasSubClassEq(RC))
6598       return load ? X86::KMOVWkm : X86::KMOVWmk;
6599     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
6600     return load ? X86::MOV16rm : X86::MOV16mr;
6601   case 4:
6602     if (X86::GR32RegClass.hasSubClassEq(RC))
6603       return load ? X86::MOV32rm : X86::MOV32mr;
6604     if (X86::FR32XRegClass.hasSubClassEq(RC))
6605       return load ?
6606         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
6607         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
6608     if (X86::RFP32RegClass.hasSubClassEq(RC))
6609       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
6610     if (X86::VK32RegClass.hasSubClassEq(RC))
6611       return load ? X86::KMOVDkm : X86::KMOVDmk;
6612     llvm_unreachable("Unknown 4-byte regclass");
6613   case 8:
6614     if (X86::GR64RegClass.hasSubClassEq(RC))
6615       return load ? X86::MOV64rm : X86::MOV64mr;
6616     if (X86::FR64XRegClass.hasSubClassEq(RC))
6617       return load ?
6618         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
6619         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
6620     if (X86::VR64RegClass.hasSubClassEq(RC))
6621       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
6622     if (X86::RFP64RegClass.hasSubClassEq(RC))
6623       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
6624     if (X86::VK64RegClass.hasSubClassEq(RC))
6625       return load ? X86::KMOVQkm : X86::KMOVQmk;
6626     llvm_unreachable("Unknown 8-byte regclass");
6627   case 10:
6628     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
6629     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
6630   case 16: {
6631     assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
6632     // If stack is realigned we can use aligned stores.
6633     if (isStackAligned)
6634       return load ?
6635         (HasVLX    ? X86::VMOVAPSZ128rm :
6636          HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
6637          HasAVX    ? X86::VMOVAPSrm :
6638                      X86::MOVAPSrm):
6639         (HasVLX    ? X86::VMOVAPSZ128mr :
6640          HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
6641          HasAVX    ? X86::VMOVAPSmr :
6642                      X86::MOVAPSmr);
6643     else
6644       return load ?
6645         (HasVLX    ? X86::VMOVUPSZ128rm :
6646          HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
6647          HasAVX    ? X86::VMOVUPSrm :
6648                      X86::MOVUPSrm):
6649         (HasVLX    ? X86::VMOVUPSZ128mr :
6650          HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
6651          HasAVX    ? X86::VMOVUPSmr :
6652                      X86::MOVUPSmr);
6653   }
6654   case 32:
6655     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
6656     // If stack is realigned we can use aligned stores.
6657     if (isStackAligned)
6658       return load ?
6659         (HasVLX    ? X86::VMOVAPSZ256rm :
6660          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
6661                      X86::VMOVAPSYrm) :
6662         (HasVLX    ? X86::VMOVAPSZ256mr :
6663          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
6664                      X86::VMOVAPSYmr);
6665     else
6666       return load ?
6667         (HasVLX    ? X86::VMOVUPSZ256rm :
6668          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
6669                      X86::VMOVUPSYrm) :
6670         (HasVLX    ? X86::VMOVUPSZ256mr :
6671          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
6672                      X86::VMOVUPSYmr);
6673   case 64:
6674     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
6675     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
6676     if (isStackAligned)
6677       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
6678     else
6679       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
6680   }
6681 }
6682 
6683 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
6684                                          int64_t &Offset,
6685                                          const TargetRegisterInfo *TRI) const {
6686   const MCInstrDesc &Desc = MemOp.getDesc();
6687   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
6688   if (MemRefBegin < 0)
6689     return false;
6690 
6691   MemRefBegin += X86II::getOperandBias(Desc);
6692 
6693   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
6694   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
6695     return false;
6696 
6697   BaseReg = BaseMO.getReg();
6698   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
6699     return false;
6700 
6701   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
6702       X86::NoRegister)
6703     return false;
6704 
6705   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
6706 
6707   // Displacement can be symbolic
6708   if (!DispMO.isImm())
6709     return false;
6710 
6711   Offset = DispMO.getImm();
6712 
6713   return true;
6714 }
6715 
6716 static unsigned getStoreRegOpcode(unsigned SrcReg,
6717                                   const TargetRegisterClass *RC,
6718                                   bool isStackAligned,
6719                                   const X86Subtarget &STI) {
6720   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
6721 }
6722 
6723 
6724 static unsigned getLoadRegOpcode(unsigned DestReg,
6725                                  const TargetRegisterClass *RC,
6726                                  bool isStackAligned,
6727                                  const X86Subtarget &STI) {
6728   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
6729 }
6730 
6731 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
6732                                        MachineBasicBlock::iterator MI,
6733                                        unsigned SrcReg, bool isKill, int FrameIdx,
6734                                        const TargetRegisterClass *RC,
6735                                        const TargetRegisterInfo *TRI) const {
6736   const MachineFunction &MF = *MBB.getParent();
6737   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
6738          "Stack slot too small for store");
6739   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6740   bool isAligned =
6741       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6742       RI.canRealignStack(MF);
6743   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6744   DebugLoc DL = MBB.findDebugLoc(MI);
6745   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
6746     .addReg(SrcReg, getKillRegState(isKill));
6747 }
6748 
6749 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
6750                                   bool isKill,
6751                                   SmallVectorImpl<MachineOperand> &Addr,
6752                                   const TargetRegisterClass *RC,
6753                                   MachineInstr::mmo_iterator MMOBegin,
6754                                   MachineInstr::mmo_iterator MMOEnd,
6755                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
6756   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6757   bool isAligned = MMOBegin != MMOEnd &&
6758                    (*MMOBegin)->getAlignment() >= Alignment;
6759   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6760   DebugLoc DL;
6761   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6762   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6763     MIB.add(Addr[i]);
6764   MIB.addReg(SrcReg, getKillRegState(isKill));
6765   (*MIB).setMemRefs(MMOBegin, MMOEnd);
6766   NewMIs.push_back(MIB);
6767 }
6768 
6769 
6770 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
6771                                         MachineBasicBlock::iterator MI,
6772                                         unsigned DestReg, int FrameIdx,
6773                                         const TargetRegisterClass *RC,
6774                                         const TargetRegisterInfo *TRI) const {
6775   const MachineFunction &MF = *MBB.getParent();
6776   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6777   bool isAligned =
6778       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6779       RI.canRealignStack(MF);
6780   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6781   DebugLoc DL = MBB.findDebugLoc(MI);
6782   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
6783 }
6784 
6785 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
6786                                  SmallVectorImpl<MachineOperand> &Addr,
6787                                  const TargetRegisterClass *RC,
6788                                  MachineInstr::mmo_iterator MMOBegin,
6789                                  MachineInstr::mmo_iterator MMOEnd,
6790                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
6791   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6792   bool isAligned = MMOBegin != MMOEnd &&
6793                    (*MMOBegin)->getAlignment() >= Alignment;
6794   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6795   DebugLoc DL;
6796   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
6797   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6798     MIB.add(Addr[i]);
6799   (*MIB).setMemRefs(MMOBegin, MMOEnd);
6800   NewMIs.push_back(MIB);
6801 }
6802 
6803 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
6804                                   unsigned &SrcReg2, int &CmpMask,
6805                                   int &CmpValue) const {
6806   switch (MI.getOpcode()) {
6807   default: break;
6808   case X86::CMP64ri32:
6809   case X86::CMP64ri8:
6810   case X86::CMP32ri:
6811   case X86::CMP32ri8:
6812   case X86::CMP16ri:
6813   case X86::CMP16ri8:
6814   case X86::CMP8ri:
6815     SrcReg = MI.getOperand(0).getReg();
6816     SrcReg2 = 0;
6817     if (MI.getOperand(1).isImm()) {
6818       CmpMask = ~0;
6819       CmpValue = MI.getOperand(1).getImm();
6820     } else {
6821       CmpMask = CmpValue = 0;
6822     }
6823     return true;
6824   // A SUB can be used to perform comparison.
6825   case X86::SUB64rm:
6826   case X86::SUB32rm:
6827   case X86::SUB16rm:
6828   case X86::SUB8rm:
6829     SrcReg = MI.getOperand(1).getReg();
6830     SrcReg2 = 0;
6831     CmpMask = 0;
6832     CmpValue = 0;
6833     return true;
6834   case X86::SUB64rr:
6835   case X86::SUB32rr:
6836   case X86::SUB16rr:
6837   case X86::SUB8rr:
6838     SrcReg = MI.getOperand(1).getReg();
6839     SrcReg2 = MI.getOperand(2).getReg();
6840     CmpMask = 0;
6841     CmpValue = 0;
6842     return true;
6843   case X86::SUB64ri32:
6844   case X86::SUB64ri8:
6845   case X86::SUB32ri:
6846   case X86::SUB32ri8:
6847   case X86::SUB16ri:
6848   case X86::SUB16ri8:
6849   case X86::SUB8ri:
6850     SrcReg = MI.getOperand(1).getReg();
6851     SrcReg2 = 0;
6852     if (MI.getOperand(2).isImm()) {
6853       CmpMask = ~0;
6854       CmpValue = MI.getOperand(2).getImm();
6855     } else {
6856       CmpMask = CmpValue = 0;
6857     }
6858     return true;
6859   case X86::CMP64rr:
6860   case X86::CMP32rr:
6861   case X86::CMP16rr:
6862   case X86::CMP8rr:
6863     SrcReg = MI.getOperand(0).getReg();
6864     SrcReg2 = MI.getOperand(1).getReg();
6865     CmpMask = 0;
6866     CmpValue = 0;
6867     return true;
6868   case X86::TEST8rr:
6869   case X86::TEST16rr:
6870   case X86::TEST32rr:
6871   case X86::TEST64rr:
6872     SrcReg = MI.getOperand(0).getReg();
6873     if (MI.getOperand(1).getReg() != SrcReg)
6874       return false;
6875     // Compare against zero.
6876     SrcReg2 = 0;
6877     CmpMask = ~0;
6878     CmpValue = 0;
6879     return true;
6880   }
6881   return false;
6882 }
6883 
6884 /// Check whether the first instruction, whose only
6885 /// purpose is to update flags, can be made redundant.
6886 /// CMPrr can be made redundant by SUBrr if the operands are the same.
6887 /// This function can be extended later on.
6888 /// SrcReg, SrcRegs: register operands for FlagI.
6889 /// ImmValue: immediate for FlagI if it takes an immediate.
6890 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
6891                                         unsigned SrcReg2, int ImmMask,
6892                                         int ImmValue, MachineInstr &OI) {
6893   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
6894        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
6895        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
6896        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
6897       ((OI.getOperand(1).getReg() == SrcReg &&
6898         OI.getOperand(2).getReg() == SrcReg2) ||
6899        (OI.getOperand(1).getReg() == SrcReg2 &&
6900         OI.getOperand(2).getReg() == SrcReg)))
6901     return true;
6902 
6903   if (ImmMask != 0 &&
6904       ((FlagI.getOpcode() == X86::CMP64ri32 &&
6905         OI.getOpcode() == X86::SUB64ri32) ||
6906        (FlagI.getOpcode() == X86::CMP64ri8 &&
6907         OI.getOpcode() == X86::SUB64ri8) ||
6908        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
6909        (FlagI.getOpcode() == X86::CMP32ri8 &&
6910         OI.getOpcode() == X86::SUB32ri8) ||
6911        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
6912        (FlagI.getOpcode() == X86::CMP16ri8 &&
6913         OI.getOpcode() == X86::SUB16ri8) ||
6914        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
6915       OI.getOperand(1).getReg() == SrcReg &&
6916       OI.getOperand(2).getImm() == ImmValue)
6917     return true;
6918   return false;
6919 }
6920 
6921 /// Check whether the definition can be converted
6922 /// to remove a comparison against zero.
6923 inline static bool isDefConvertible(MachineInstr &MI) {
6924   switch (MI.getOpcode()) {
6925   default: return false;
6926 
6927   // The shift instructions only modify ZF if their shift count is non-zero.
6928   // N.B.: The processor truncates the shift count depending on the encoding.
6929   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
6930   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
6931      return getTruncatedShiftCount(MI, 2) != 0;
6932 
6933   // Some left shift instructions can be turned into LEA instructions but only
6934   // if their flags aren't used. Avoid transforming such instructions.
6935   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
6936     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
6937     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
6938     return ShAmt != 0;
6939   }
6940 
6941   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
6942   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
6943      return getTruncatedShiftCount(MI, 3) != 0;
6944 
6945   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
6946   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
6947   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
6948   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
6949   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
6950   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
6951   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
6952   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
6953   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
6954   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
6955   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
6956   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
6957   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
6958   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
6959   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
6960   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
6961   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
6962   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
6963   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
6964   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
6965   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
6966   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
6967   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
6968   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
6969   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
6970   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
6971   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
6972   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
6973   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
6974   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
6975   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
6976   case X86::ADC32ri:   case X86::ADC32ri8:
6977   case X86::ADC32rr:   case X86::ADC64ri32:
6978   case X86::ADC64ri8:  case X86::ADC64rr:
6979   case X86::SBB32ri:   case X86::SBB32ri8:
6980   case X86::SBB32rr:   case X86::SBB64ri32:
6981   case X86::SBB64ri8:  case X86::SBB64rr:
6982   case X86::ANDN32rr:  case X86::ANDN32rm:
6983   case X86::ANDN64rr:  case X86::ANDN64rm:
6984   case X86::BEXTR32rr: case X86::BEXTR64rr:
6985   case X86::BEXTR32rm: case X86::BEXTR64rm:
6986   case X86::BLSI32rr:  case X86::BLSI32rm:
6987   case X86::BLSI64rr:  case X86::BLSI64rm:
6988   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
6989   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
6990   case X86::BLSR32rr:  case X86::BLSR32rm:
6991   case X86::BLSR64rr:  case X86::BLSR64rm:
6992   case X86::BZHI32rr:  case X86::BZHI32rm:
6993   case X86::BZHI64rr:  case X86::BZHI64rm:
6994   case X86::LZCNT16rr: case X86::LZCNT16rm:
6995   case X86::LZCNT32rr: case X86::LZCNT32rm:
6996   case X86::LZCNT64rr: case X86::LZCNT64rm:
6997   case X86::POPCNT16rr:case X86::POPCNT16rm:
6998   case X86::POPCNT32rr:case X86::POPCNT32rm:
6999   case X86::POPCNT64rr:case X86::POPCNT64rm:
7000   case X86::TZCNT16rr: case X86::TZCNT16rm:
7001   case X86::TZCNT32rr: case X86::TZCNT32rm:
7002   case X86::TZCNT64rr: case X86::TZCNT64rm:
7003     return true;
7004   }
7005 }
7006 
7007 /// Check whether the use can be converted to remove a comparison against zero.
7008 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
7009   switch (MI.getOpcode()) {
7010   default: return X86::COND_INVALID;
7011   case X86::LZCNT16rr: case X86::LZCNT16rm:
7012   case X86::LZCNT32rr: case X86::LZCNT32rm:
7013   case X86::LZCNT64rr: case X86::LZCNT64rm:
7014     return X86::COND_B;
7015   case X86::POPCNT16rr:case X86::POPCNT16rm:
7016   case X86::POPCNT32rr:case X86::POPCNT32rm:
7017   case X86::POPCNT64rr:case X86::POPCNT64rm:
7018     return X86::COND_E;
7019   case X86::TZCNT16rr: case X86::TZCNT16rm:
7020   case X86::TZCNT32rr: case X86::TZCNT32rm:
7021   case X86::TZCNT64rr: case X86::TZCNT64rm:
7022     return X86::COND_B;
7023   }
7024 }
7025 
7026 /// Check if there exists an earlier instruction that
7027 /// operates on the same source operands and sets flags in the same way as
7028 /// Compare; remove Compare if possible.
7029 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
7030                                         unsigned SrcReg2, int CmpMask,
7031                                         int CmpValue,
7032                                         const MachineRegisterInfo *MRI) const {
7033   // Check whether we can replace SUB with CMP.
7034   unsigned NewOpcode = 0;
7035   switch (CmpInstr.getOpcode()) {
7036   default: break;
7037   case X86::SUB64ri32:
7038   case X86::SUB64ri8:
7039   case X86::SUB32ri:
7040   case X86::SUB32ri8:
7041   case X86::SUB16ri:
7042   case X86::SUB16ri8:
7043   case X86::SUB8ri:
7044   case X86::SUB64rm:
7045   case X86::SUB32rm:
7046   case X86::SUB16rm:
7047   case X86::SUB8rm:
7048   case X86::SUB64rr:
7049   case X86::SUB32rr:
7050   case X86::SUB16rr:
7051   case X86::SUB8rr: {
7052     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
7053       return false;
7054     // There is no use of the destination register, we can replace SUB with CMP.
7055     switch (CmpInstr.getOpcode()) {
7056     default: llvm_unreachable("Unreachable!");
7057     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
7058     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
7059     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
7060     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
7061     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
7062     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
7063     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
7064     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
7065     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
7066     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
7067     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
7068     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
7069     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
7070     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
7071     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
7072     }
7073     CmpInstr.setDesc(get(NewOpcode));
7074     CmpInstr.RemoveOperand(0);
7075     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
7076     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
7077         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
7078       return false;
7079   }
7080   }
7081 
7082   // Get the unique definition of SrcReg.
7083   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
7084   if (!MI) return false;
7085 
7086   // CmpInstr is the first instruction of the BB.
7087   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
7088 
7089   // If we are comparing against zero, check whether we can use MI to update
7090   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
7091   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
7092   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
7093     return false;
7094 
7095   // If we have a use of the source register between the def and our compare
7096   // instruction we can eliminate the compare iff the use sets EFLAGS in the
7097   // right way.
7098   bool ShouldUpdateCC = false;
7099   X86::CondCode NewCC = X86::COND_INVALID;
7100   if (IsCmpZero && !isDefConvertible(*MI)) {
7101     // Scan forward from the use until we hit the use we're looking for or the
7102     // compare instruction.
7103     for (MachineBasicBlock::iterator J = MI;; ++J) {
7104       // Do we have a convertible instruction?
7105       NewCC = isUseDefConvertible(*J);
7106       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
7107           J->getOperand(1).getReg() == SrcReg) {
7108         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
7109         ShouldUpdateCC = true; // Update CC later on.
7110         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
7111         // with the new def.
7112         Def = J;
7113         MI = &*Def;
7114         break;
7115       }
7116 
7117       if (J == I)
7118         return false;
7119     }
7120   }
7121 
7122   // We are searching for an earlier instruction that can make CmpInstr
7123   // redundant and that instruction will be saved in Sub.
7124   MachineInstr *Sub = nullptr;
7125   const TargetRegisterInfo *TRI = &getRegisterInfo();
7126 
7127   // We iterate backward, starting from the instruction before CmpInstr and
7128   // stop when reaching the definition of a source register or done with the BB.
7129   // RI points to the instruction before CmpInstr.
7130   // If the definition is in this basic block, RE points to the definition;
7131   // otherwise, RE is the rend of the basic block.
7132   MachineBasicBlock::reverse_iterator
7133       RI = ++I.getReverse(),
7134       RE = CmpInstr.getParent() == MI->getParent()
7135                ? Def.getReverse() /* points to MI */
7136                : CmpInstr.getParent()->rend();
7137   MachineInstr *Movr0Inst = nullptr;
7138   for (; RI != RE; ++RI) {
7139     MachineInstr &Instr = *RI;
7140     // Check whether CmpInstr can be made redundant by the current instruction.
7141     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
7142                                            CmpValue, Instr)) {
7143       Sub = &Instr;
7144       break;
7145     }
7146 
7147     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
7148         Instr.readsRegister(X86::EFLAGS, TRI)) {
7149       // This instruction modifies or uses EFLAGS.
7150 
7151       // MOV32r0 etc. are implemented with xor which clobbers condition code.
7152       // They are safe to move up, if the definition to EFLAGS is dead and
7153       // earlier instructions do not read or write EFLAGS.
7154       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
7155           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
7156         Movr0Inst = &Instr;
7157         continue;
7158       }
7159 
7160       // We can't remove CmpInstr.
7161       return false;
7162     }
7163   }
7164 
7165   // Return false if no candidates exist.
7166   if (!IsCmpZero && !Sub)
7167     return false;
7168 
7169   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
7170                     Sub->getOperand(2).getReg() == SrcReg);
7171 
7172   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
7173   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
7174   // If we are done with the basic block, we need to check whether EFLAGS is
7175   // live-out.
7176   bool IsSafe = false;
7177   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
7178   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
7179   for (++I; I != E; ++I) {
7180     const MachineInstr &Instr = *I;
7181     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
7182     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
7183     // We should check the usage if this instruction uses and updates EFLAGS.
7184     if (!UseEFLAGS && ModifyEFLAGS) {
7185       // It is safe to remove CmpInstr if EFLAGS is updated again.
7186       IsSafe = true;
7187       break;
7188     }
7189     if (!UseEFLAGS && !ModifyEFLAGS)
7190       continue;
7191 
7192     // EFLAGS is used by this instruction.
7193     X86::CondCode OldCC = X86::COND_INVALID;
7194     bool OpcIsSET = false;
7195     if (IsCmpZero || IsSwapped) {
7196       // We decode the condition code from opcode.
7197       if (Instr.isBranch())
7198         OldCC = getCondFromBranchOpc(Instr.getOpcode());
7199       else {
7200         OldCC = getCondFromSETOpc(Instr.getOpcode());
7201         if (OldCC != X86::COND_INVALID)
7202           OpcIsSET = true;
7203         else
7204           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
7205       }
7206       if (OldCC == X86::COND_INVALID) return false;
7207     }
7208     if (IsCmpZero) {
7209       switch (OldCC) {
7210       default: break;
7211       case X86::COND_A: case X86::COND_AE:
7212       case X86::COND_B: case X86::COND_BE:
7213       case X86::COND_G: case X86::COND_GE:
7214       case X86::COND_L: case X86::COND_LE:
7215       case X86::COND_O: case X86::COND_NO:
7216         // CF and OF are used, we can't perform this optimization.
7217         return false;
7218       }
7219 
7220       // If we're updating the condition code check if we have to reverse the
7221       // condition.
7222       if (ShouldUpdateCC)
7223         switch (OldCC) {
7224         default:
7225           return false;
7226         case X86::COND_E:
7227           break;
7228         case X86::COND_NE:
7229           NewCC = GetOppositeBranchCondition(NewCC);
7230           break;
7231         }
7232     } else if (IsSwapped) {
7233       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
7234       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
7235       // We swap the condition code and synthesize the new opcode.
7236       NewCC = getSwappedCondition(OldCC);
7237       if (NewCC == X86::COND_INVALID) return false;
7238     }
7239 
7240     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
7241       // Synthesize the new opcode.
7242       bool HasMemoryOperand = Instr.hasOneMemOperand();
7243       unsigned NewOpc;
7244       if (Instr.isBranch())
7245         NewOpc = GetCondBranchFromCond(NewCC);
7246       else if(OpcIsSET)
7247         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
7248       else {
7249         unsigned DstReg = Instr.getOperand(0).getReg();
7250         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
7251                                  HasMemoryOperand);
7252       }
7253 
7254       // Push the MachineInstr to OpsToUpdate.
7255       // If it is safe to remove CmpInstr, the condition code of these
7256       // instructions will be modified.
7257       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
7258     }
7259     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
7260       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
7261       IsSafe = true;
7262       break;
7263     }
7264   }
7265 
7266   // If EFLAGS is not killed nor re-defined, we should check whether it is
7267   // live-out. If it is live-out, do not optimize.
7268   if ((IsCmpZero || IsSwapped) && !IsSafe) {
7269     MachineBasicBlock *MBB = CmpInstr.getParent();
7270     for (MachineBasicBlock *Successor : MBB->successors())
7271       if (Successor->isLiveIn(X86::EFLAGS))
7272         return false;
7273   }
7274 
7275   // The instruction to be updated is either Sub or MI.
7276   Sub = IsCmpZero ? MI : Sub;
7277   // Move Movr0Inst to the appropriate place before Sub.
7278   if (Movr0Inst) {
7279     // Look backwards until we find a def that doesn't use the current EFLAGS.
7280     Def = Sub;
7281     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
7282                                         InsertE = Sub->getParent()->rend();
7283     for (; InsertI != InsertE; ++InsertI) {
7284       MachineInstr *Instr = &*InsertI;
7285       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
7286           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
7287         Sub->getParent()->remove(Movr0Inst);
7288         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
7289                                    Movr0Inst);
7290         break;
7291       }
7292     }
7293     if (InsertI == InsertE)
7294       return false;
7295   }
7296 
7297   // Make sure Sub instruction defines EFLAGS and mark the def live.
7298   unsigned i = 0, e = Sub->getNumOperands();
7299   for (; i != e; ++i) {
7300     MachineOperand &MO = Sub->getOperand(i);
7301     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
7302       MO.setIsDead(false);
7303       break;
7304     }
7305   }
7306   assert(i != e && "Unable to locate a def EFLAGS operand");
7307 
7308   CmpInstr.eraseFromParent();
7309 
7310   // Modify the condition code of instructions in OpsToUpdate.
7311   for (auto &Op : OpsToUpdate)
7312     Op.first->setDesc(get(Op.second));
7313   return true;
7314 }
7315 
7316 /// Try to remove the load by folding it to a register
7317 /// operand at the use. We fold the load instructions if load defines a virtual
7318 /// register, the virtual register is used once in the same BB, and the
7319 /// instructions in-between do not load or store, and have no side effects.
7320 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
7321                                               const MachineRegisterInfo *MRI,
7322                                               unsigned &FoldAsLoadDefReg,
7323                                               MachineInstr *&DefMI) const {
7324   // Check whether we can move DefMI here.
7325   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
7326   assert(DefMI);
7327   bool SawStore = false;
7328   if (!DefMI->isSafeToMove(nullptr, SawStore))
7329     return nullptr;
7330 
7331   // Collect information about virtual register operands of MI.
7332   SmallVector<unsigned, 1> SrcOperandIds;
7333   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7334     MachineOperand &MO = MI.getOperand(i);
7335     if (!MO.isReg())
7336       continue;
7337     unsigned Reg = MO.getReg();
7338     if (Reg != FoldAsLoadDefReg)
7339       continue;
7340     // Do not fold if we have a subreg use or a def.
7341     if (MO.getSubReg() || MO.isDef())
7342       return nullptr;
7343     SrcOperandIds.push_back(i);
7344   }
7345   if (SrcOperandIds.empty())
7346     return nullptr;
7347 
7348   // Check whether we can fold the def into SrcOperandId.
7349   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
7350     FoldAsLoadDefReg = 0;
7351     return FoldMI;
7352   }
7353 
7354   return nullptr;
7355 }
7356 
7357 /// Expand a single-def pseudo instruction to a two-addr
7358 /// instruction with two undef reads of the register being defined.
7359 /// This is used for mapping:
7360 ///   %xmm4 = V_SET0
7361 /// to:
7362 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
7363 ///
7364 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
7365                              const MCInstrDesc &Desc) {
7366   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7367   unsigned Reg = MIB->getOperand(0).getReg();
7368   MIB->setDesc(Desc);
7369 
7370   // MachineInstr::addOperand() will insert explicit operands before any
7371   // implicit operands.
7372   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7373   // But we don't trust that.
7374   assert(MIB->getOperand(1).getReg() == Reg &&
7375          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
7376   return true;
7377 }
7378 
7379 /// Expand a single-def pseudo instruction to a two-addr
7380 /// instruction with two %k0 reads.
7381 /// This is used for mapping:
7382 ///   %k4 = K_SET1
7383 /// to:
7384 ///   %k4 = KXNORrr %k0, %k0
7385 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
7386                             const MCInstrDesc &Desc, unsigned Reg) {
7387   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7388   MIB->setDesc(Desc);
7389   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7390   return true;
7391 }
7392 
7393 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
7394                           bool MinusOne) {
7395   MachineBasicBlock &MBB = *MIB->getParent();
7396   DebugLoc DL = MIB->getDebugLoc();
7397   unsigned Reg = MIB->getOperand(0).getReg();
7398 
7399   // Insert the XOR.
7400   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
7401       .addReg(Reg, RegState::Undef)
7402       .addReg(Reg, RegState::Undef);
7403 
7404   // Turn the pseudo into an INC or DEC.
7405   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
7406   MIB.addReg(Reg);
7407 
7408   return true;
7409 }
7410 
7411 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
7412                                const TargetInstrInfo &TII,
7413                                const X86Subtarget &Subtarget) {
7414   MachineBasicBlock &MBB = *MIB->getParent();
7415   DebugLoc DL = MIB->getDebugLoc();
7416   int64_t Imm = MIB->getOperand(1).getImm();
7417   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
7418   MachineBasicBlock::iterator I = MIB.getInstr();
7419 
7420   int StackAdjustment;
7421 
7422   if (Subtarget.is64Bit()) {
7423     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
7424            MIB->getOpcode() == X86::MOV32ImmSExti8);
7425 
7426     // Can't use push/pop lowering if the function might write to the red zone.
7427     X86MachineFunctionInfo *X86FI =
7428         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
7429     if (X86FI->getUsesRedZone()) {
7430       MIB->setDesc(TII.get(MIB->getOpcode() ==
7431                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
7432       return true;
7433     }
7434 
7435     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
7436     // widen the register if necessary.
7437     StackAdjustment = 8;
7438     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
7439     MIB->setDesc(TII.get(X86::POP64r));
7440     MIB->getOperand(0)
7441         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
7442   } else {
7443     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
7444     StackAdjustment = 4;
7445     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
7446     MIB->setDesc(TII.get(X86::POP32r));
7447   }
7448 
7449   // Build CFI if necessary.
7450   MachineFunction &MF = *MBB.getParent();
7451   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
7452   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
7453   bool NeedsDwarfCFI =
7454       !IsWin64Prologue &&
7455       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
7456   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
7457   if (EmitCFI) {
7458     TFL->BuildCFI(MBB, I, DL,
7459         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
7460     TFL->BuildCFI(MBB, std::next(I), DL,
7461         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
7462   }
7463 
7464   return true;
7465 }
7466 
7467 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
7468 // code sequence is needed for other targets.
7469 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
7470                                  const TargetInstrInfo &TII) {
7471   MachineBasicBlock &MBB = *MIB->getParent();
7472   DebugLoc DL = MIB->getDebugLoc();
7473   unsigned Reg = MIB->getOperand(0).getReg();
7474   const GlobalValue *GV =
7475       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
7476   auto Flags = MachineMemOperand::MOLoad |
7477                MachineMemOperand::MODereferenceable |
7478                MachineMemOperand::MOInvariant;
7479   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
7480       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
7481   MachineBasicBlock::iterator I = MIB.getInstr();
7482 
7483   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
7484       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
7485       .addMemOperand(MMO);
7486   MIB->setDebugLoc(DL);
7487   MIB->setDesc(TII.get(X86::MOV64rm));
7488   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
7489 }
7490 
7491 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7492 // but not VLX. If it uses an extended register we need to use an instruction
7493 // that loads the lower 128/256-bit, but is available with only AVX512F.
7494 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
7495                             const TargetRegisterInfo *TRI,
7496                             const MCInstrDesc &LoadDesc,
7497                             const MCInstrDesc &BroadcastDesc,
7498                             unsigned SubIdx) {
7499   unsigned DestReg = MIB->getOperand(0).getReg();
7500   // Check if DestReg is XMM16-31 or YMM16-31.
7501   if (TRI->getEncodingValue(DestReg) < 16) {
7502     // We can use a normal VEX encoded load.
7503     MIB->setDesc(LoadDesc);
7504   } else {
7505     // Use a 128/256-bit VBROADCAST instruction.
7506     MIB->setDesc(BroadcastDesc);
7507     // Change the destination to a 512-bit register.
7508     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
7509     MIB->getOperand(0).setReg(DestReg);
7510   }
7511   return true;
7512 }
7513 
7514 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7515 // but not VLX. If it uses an extended register we need to use an instruction
7516 // that stores the lower 128/256-bit, but is available with only AVX512F.
7517 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
7518                              const TargetRegisterInfo *TRI,
7519                              const MCInstrDesc &StoreDesc,
7520                              const MCInstrDesc &ExtractDesc,
7521                              unsigned SubIdx) {
7522   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
7523   // Check if DestReg is XMM16-31 or YMM16-31.
7524   if (TRI->getEncodingValue(SrcReg) < 16) {
7525     // We can use a normal VEX encoded store.
7526     MIB->setDesc(StoreDesc);
7527   } else {
7528     // Use a VEXTRACTF instruction.
7529     MIB->setDesc(ExtractDesc);
7530     // Change the destination to a 512-bit register.
7531     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
7532     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
7533     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
7534   }
7535 
7536   return true;
7537 }
7538 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
7539   bool HasAVX = Subtarget.hasAVX();
7540   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
7541   switch (MI.getOpcode()) {
7542   case X86::MOV32r0:
7543     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
7544   case X86::MOV32r1:
7545     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
7546   case X86::MOV32r_1:
7547     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
7548   case X86::MOV32ImmSExti8:
7549   case X86::MOV64ImmSExti8:
7550     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
7551   case X86::SETB_C8r:
7552     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
7553   case X86::SETB_C16r:
7554     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
7555   case X86::SETB_C32r:
7556     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
7557   case X86::SETB_C64r:
7558     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
7559   case X86::V_SET0:
7560   case X86::FsFLD0SS:
7561   case X86::FsFLD0SD:
7562     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
7563   case X86::AVX_SET0:
7564     assert(HasAVX && "AVX not supported");
7565     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
7566   case X86::AVX512_128_SET0:
7567   case X86::AVX512_FsFLD0SS:
7568   case X86::AVX512_FsFLD0SD: {
7569     bool HasVLX = Subtarget.hasVLX();
7570     unsigned SrcReg = MIB->getOperand(0).getReg();
7571     const TargetRegisterInfo *TRI = &getRegisterInfo();
7572     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7573       return Expand2AddrUndef(MIB,
7574                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7575     // Extended register without VLX. Use a larger XOR.
7576     SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
7577     MIB->getOperand(0).setReg(SrcReg);
7578     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7579   }
7580   case X86::AVX512_256_SET0: {
7581     bool HasVLX = Subtarget.hasVLX();
7582     unsigned SrcReg = MIB->getOperand(0).getReg();
7583     const TargetRegisterInfo *TRI = &getRegisterInfo();
7584     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7585       return Expand2AddrUndef(MIB,
7586                               get(HasVLX ? X86::VPXORDZ256rr : X86::VXORPSYrr));
7587     // Extended register without VLX. Use a larger XOR.
7588     SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
7589     MIB->getOperand(0).setReg(SrcReg);
7590     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7591   }
7592   case X86::AVX512_512_SET0:
7593     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7594   case X86::V_SETALLONES:
7595     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
7596   case X86::AVX2_SETALLONES:
7597     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
7598   case X86::AVX512_512_SETALLONES: {
7599     unsigned Reg = MIB->getOperand(0).getReg();
7600     MIB->setDesc(get(X86::VPTERNLOGDZrri));
7601     // VPTERNLOGD needs 3 register inputs and an immediate.
7602     // 0xff will return 1s for any input.
7603     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
7604        .addReg(Reg, RegState::Undef).addImm(0xff);
7605     return true;
7606   }
7607   case X86::AVX512_512_SEXT_MASK_32:
7608   case X86::AVX512_512_SEXT_MASK_64: {
7609     unsigned Reg = MIB->getOperand(0).getReg();
7610     unsigned MaskReg = MIB->getOperand(1).getReg();
7611     unsigned MaskState = getRegState(MIB->getOperand(1));
7612     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
7613                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
7614     MI.RemoveOperand(1);
7615     MIB->setDesc(get(Opc));
7616     // VPTERNLOG needs 3 register inputs and an immediate.
7617     // 0xff will return 1s for any input.
7618     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
7619        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
7620     return true;
7621   }
7622   case X86::VMOVAPSZ128rm_NOVLX:
7623     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
7624                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7625   case X86::VMOVUPSZ128rm_NOVLX:
7626     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
7627                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7628   case X86::VMOVAPSZ256rm_NOVLX:
7629     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
7630                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7631   case X86::VMOVUPSZ256rm_NOVLX:
7632     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
7633                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7634   case X86::VMOVAPSZ128mr_NOVLX:
7635     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
7636                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7637   case X86::VMOVUPSZ128mr_NOVLX:
7638     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
7639                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7640   case X86::VMOVAPSZ256mr_NOVLX:
7641     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
7642                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7643   case X86::VMOVUPSZ256mr_NOVLX:
7644     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
7645                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7646   case X86::TEST8ri_NOREX:
7647     MI.setDesc(get(X86::TEST8ri));
7648     return true;
7649   case X86::MOV32ri64:
7650     MI.setDesc(get(X86::MOV32ri));
7651     return true;
7652 
7653   // KNL does not recognize dependency-breaking idioms for mask registers,
7654   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
7655   // Using %k0 as the undef input register is a performance heuristic based
7656   // on the assumption that %k0 is used less frequently than the other mask
7657   // registers, since it is not usable as a write mask.
7658   // FIXME: A more advanced approach would be to choose the best input mask
7659   // register based on context.
7660   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
7661   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
7662   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
7663   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
7664   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
7665   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
7666   case TargetOpcode::LOAD_STACK_GUARD:
7667     expandLoadStackGuard(MIB, *this);
7668     return true;
7669   }
7670   return false;
7671 }
7672 
7673 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7674                         int PtrOffset = 0) {
7675   unsigned NumAddrOps = MOs.size();
7676 
7677   if (NumAddrOps < 4) {
7678     // FrameIndex only - add an immediate offset (whether its zero or not).
7679     for (unsigned i = 0; i != NumAddrOps; ++i)
7680       MIB.add(MOs[i]);
7681     addOffset(MIB, PtrOffset);
7682   } else {
7683     // General Memory Addressing - we need to add any offset to an existing
7684     // offset.
7685     assert(MOs.size() == 5 && "Unexpected memory operand list length");
7686     for (unsigned i = 0; i != NumAddrOps; ++i) {
7687       const MachineOperand &MO = MOs[i];
7688       if (i == 3 && PtrOffset != 0) {
7689         MIB.addDisp(MO, PtrOffset);
7690       } else {
7691         MIB.add(MO);
7692       }
7693     }
7694   }
7695 }
7696 
7697 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
7698                                      ArrayRef<MachineOperand> MOs,
7699                                      MachineBasicBlock::iterator InsertPt,
7700                                      MachineInstr &MI,
7701                                      const TargetInstrInfo &TII) {
7702   // Create the base instruction with the memory operand as the first part.
7703   // Omit the implicit operands, something BuildMI can't do.
7704   MachineInstr *NewMI =
7705       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
7706   MachineInstrBuilder MIB(MF, NewMI);
7707   addOperands(MIB, MOs);
7708 
7709   // Loop over the rest of the ri operands, converting them over.
7710   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
7711   for (unsigned i = 0; i != NumOps; ++i) {
7712     MachineOperand &MO = MI.getOperand(i + 2);
7713     MIB.add(MO);
7714   }
7715   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
7716     MachineOperand &MO = MI.getOperand(i);
7717     MIB.add(MO);
7718   }
7719 
7720   MachineBasicBlock *MBB = InsertPt->getParent();
7721   MBB->insert(InsertPt, NewMI);
7722 
7723   return MIB;
7724 }
7725 
7726 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
7727                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
7728                               MachineBasicBlock::iterator InsertPt,
7729                               MachineInstr &MI, const TargetInstrInfo &TII,
7730                               int PtrOffset = 0) {
7731   // Omit the implicit operands, something BuildMI can't do.
7732   MachineInstr *NewMI =
7733       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
7734   MachineInstrBuilder MIB(MF, NewMI);
7735 
7736   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7737     MachineOperand &MO = MI.getOperand(i);
7738     if (i == OpNo) {
7739       assert(MO.isReg() && "Expected to fold into reg operand!");
7740       addOperands(MIB, MOs, PtrOffset);
7741     } else {
7742       MIB.add(MO);
7743     }
7744   }
7745 
7746   MachineBasicBlock *MBB = InsertPt->getParent();
7747   MBB->insert(InsertPt, NewMI);
7748 
7749   return MIB;
7750 }
7751 
7752 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
7753                                 ArrayRef<MachineOperand> MOs,
7754                                 MachineBasicBlock::iterator InsertPt,
7755                                 MachineInstr &MI) {
7756   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
7757                                     MI.getDebugLoc(), TII.get(Opcode));
7758   addOperands(MIB, MOs);
7759   return MIB.addImm(0);
7760 }
7761 
7762 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
7763     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7764     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7765     unsigned Size, unsigned Align) const {
7766   switch (MI.getOpcode()) {
7767   case X86::INSERTPSrr:
7768   case X86::VINSERTPSrr:
7769   case X86::VINSERTPSZrr:
7770     // Attempt to convert the load of inserted vector into a fold load
7771     // of a single float.
7772     if (OpNum == 2) {
7773       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
7774       unsigned ZMask = Imm & 15;
7775       unsigned DstIdx = (Imm >> 4) & 3;
7776       unsigned SrcIdx = (Imm >> 6) & 3;
7777 
7778       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7779       if (Size <= RCSize && 4 <= Align) {
7780         int PtrOffset = SrcIdx * 4;
7781         unsigned NewImm = (DstIdx << 4) | ZMask;
7782         unsigned NewOpCode =
7783             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
7784             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
7785                                                     X86::INSERTPSrm;
7786         MachineInstr *NewMI =
7787             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
7788         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
7789         return NewMI;
7790       }
7791     }
7792     break;
7793   case X86::MOVHLPSrr:
7794   case X86::VMOVHLPSrr:
7795   case X86::VMOVHLPSZrr:
7796     // Move the upper 64-bits of the second operand to the lower 64-bits.
7797     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
7798     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
7799     if (OpNum == 2) {
7800       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7801       if (Size <= RCSize && 8 <= Align) {
7802         unsigned NewOpCode =
7803             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
7804             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
7805                                                    X86::MOVLPSrm;
7806         MachineInstr *NewMI =
7807             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
7808         return NewMI;
7809       }
7810     }
7811     break;
7812   };
7813 
7814   return nullptr;
7815 }
7816 
7817 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7818     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7819     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7820     unsigned Size, unsigned Align, bool AllowCommute) const {
7821   const DenseMap<unsigned,
7822                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
7823   bool isCallRegIndirect = Subtarget.callRegIndirect();
7824   bool isTwoAddrFold = false;
7825 
7826   // For CPUs that favor the register form of a call or push,
7827   // do not fold loads into calls or pushes, unless optimizing for size
7828   // aggressively.
7829   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
7830       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
7831        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
7832        MI.getOpcode() == X86::PUSH64r))
7833     return nullptr;
7834 
7835   unsigned NumOps = MI.getDesc().getNumOperands();
7836   bool isTwoAddr =
7837       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
7838 
7839   // FIXME: AsmPrinter doesn't know how to handle
7840   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
7841   if (MI.getOpcode() == X86::ADD32ri &&
7842       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
7843     return nullptr;
7844 
7845   MachineInstr *NewMI = nullptr;
7846 
7847   // Attempt to fold any custom cases we have.
7848   if (MachineInstr *CustomMI =
7849           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
7850     return CustomMI;
7851 
7852   // Folding a memory location into the two-address part of a two-address
7853   // instruction is different than folding it other places.  It requires
7854   // replacing the *two* registers with the memory location.
7855   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
7856       MI.getOperand(1).isReg() &&
7857       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
7858     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
7859     isTwoAddrFold = true;
7860   } else if (OpNum == 0) {
7861     if (MI.getOpcode() == X86::MOV32r0) {
7862       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
7863       if (NewMI)
7864         return NewMI;
7865     }
7866 
7867     OpcodeTablePtr = &RegOp2MemOpTable0;
7868   } else if (OpNum == 1) {
7869     OpcodeTablePtr = &RegOp2MemOpTable1;
7870   } else if (OpNum == 2) {
7871     OpcodeTablePtr = &RegOp2MemOpTable2;
7872   } else if (OpNum == 3) {
7873     OpcodeTablePtr = &RegOp2MemOpTable3;
7874   } else if (OpNum == 4) {
7875     OpcodeTablePtr = &RegOp2MemOpTable4;
7876   }
7877 
7878   // If table selected...
7879   if (OpcodeTablePtr) {
7880     // Find the Opcode to fuse
7881     auto I = OpcodeTablePtr->find(MI.getOpcode());
7882     if (I != OpcodeTablePtr->end()) {
7883       unsigned Opcode = I->second.first;
7884       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
7885       if (Align < MinAlign)
7886         return nullptr;
7887       bool NarrowToMOV32rm = false;
7888       if (Size) {
7889         unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7890         if (Size < RCSize) {
7891           // Check if it's safe to fold the load. If the size of the object is
7892           // narrower than the load width, then it's not.
7893           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7894             return nullptr;
7895           // If this is a 64-bit load, but the spill slot is 32, then we can do
7896           // a 32-bit load which is implicitly zero-extended. This likely is
7897           // due to live interval analysis remat'ing a load from stack slot.
7898           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
7899             return nullptr;
7900           Opcode = X86::MOV32rm;
7901           NarrowToMOV32rm = true;
7902         }
7903       }
7904 
7905       if (isTwoAddrFold)
7906         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
7907       else
7908         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
7909 
7910       if (NarrowToMOV32rm) {
7911         // If this is the special case where we use a MOV32rm to load a 32-bit
7912         // value and zero-extend the top bits. Change the destination register
7913         // to a 32-bit one.
7914         unsigned DstReg = NewMI->getOperand(0).getReg();
7915         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
7916           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
7917         else
7918           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
7919       }
7920       return NewMI;
7921     }
7922   }
7923 
7924   // If the instruction and target operand are commutable, commute the
7925   // instruction and try again.
7926   if (AllowCommute) {
7927     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
7928     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
7929       bool HasDef = MI.getDesc().getNumDefs();
7930       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
7931       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
7932       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
7933       bool Tied1 =
7934           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
7935       bool Tied2 =
7936           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
7937 
7938       // If either of the commutable operands are tied to the destination
7939       // then we can not commute + fold.
7940       if ((HasDef && Reg0 == Reg1 && Tied1) ||
7941           (HasDef && Reg0 == Reg2 && Tied2))
7942         return nullptr;
7943 
7944       MachineInstr *CommutedMI =
7945           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
7946       if (!CommutedMI) {
7947         // Unable to commute.
7948         return nullptr;
7949       }
7950       if (CommutedMI != &MI) {
7951         // New instruction. We can't fold from this.
7952         CommutedMI->eraseFromParent();
7953         return nullptr;
7954       }
7955 
7956       // Attempt to fold with the commuted version of the instruction.
7957       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
7958                                     Size, Align, /*AllowCommute=*/false);
7959       if (NewMI)
7960         return NewMI;
7961 
7962       // Folding failed again - undo the commute before returning.
7963       MachineInstr *UncommutedMI =
7964           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
7965       if (!UncommutedMI) {
7966         // Unable to commute.
7967         return nullptr;
7968       }
7969       if (UncommutedMI != &MI) {
7970         // New instruction. It doesn't need to be kept.
7971         UncommutedMI->eraseFromParent();
7972         return nullptr;
7973       }
7974 
7975       // Return here to prevent duplicate fuse failure report.
7976       return nullptr;
7977     }
7978   }
7979 
7980   // No fusion
7981   if (PrintFailedFusing && !MI.isCopy())
7982     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
7983   return nullptr;
7984 }
7985 
7986 /// Return true for all instructions that only update
7987 /// the first 32 or 64-bits of the destination register and leave the rest
7988 /// unmodified. This can be used to avoid folding loads if the instructions
7989 /// only update part of the destination register, and the non-updated part is
7990 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
7991 /// instructions breaks the partial register dependency and it can improve
7992 /// performance. e.g.:
7993 ///
7994 ///   movss (%rdi), %xmm0
7995 ///   cvtss2sd %xmm0, %xmm0
7996 ///
7997 /// Instead of
7998 ///   cvtss2sd (%rdi), %xmm0
7999 ///
8000 /// FIXME: This should be turned into a TSFlags.
8001 ///
8002 static bool hasPartialRegUpdate(unsigned Opcode) {
8003   switch (Opcode) {
8004   case X86::CVTSI2SSrr:
8005   case X86::CVTSI2SSrm:
8006   case X86::CVTSI2SS64rr:
8007   case X86::CVTSI2SS64rm:
8008   case X86::CVTSI2SDrr:
8009   case X86::CVTSI2SDrm:
8010   case X86::CVTSI2SD64rr:
8011   case X86::CVTSI2SD64rm:
8012   case X86::CVTSD2SSrr:
8013   case X86::CVTSD2SSrm:
8014   case X86::CVTSS2SDrr:
8015   case X86::CVTSS2SDrm:
8016   case X86::MOVHPDrm:
8017   case X86::MOVHPSrm:
8018   case X86::MOVLPDrm:
8019   case X86::MOVLPSrm:
8020   case X86::RCPSSr:
8021   case X86::RCPSSm:
8022   case X86::RCPSSr_Int:
8023   case X86::RCPSSm_Int:
8024   case X86::ROUNDSDr:
8025   case X86::ROUNDSDm:
8026   case X86::ROUNDSSr:
8027   case X86::ROUNDSSm:
8028   case X86::RSQRTSSr:
8029   case X86::RSQRTSSm:
8030   case X86::RSQRTSSr_Int:
8031   case X86::RSQRTSSm_Int:
8032   case X86::SQRTSSr:
8033   case X86::SQRTSSm:
8034   case X86::SQRTSSr_Int:
8035   case X86::SQRTSSm_Int:
8036   case X86::SQRTSDr:
8037   case X86::SQRTSDm:
8038   case X86::SQRTSDr_Int:
8039   case X86::SQRTSDm_Int:
8040     return true;
8041   }
8042 
8043   return false;
8044 }
8045 
8046 /// Inform the ExeDepsFix pass how many idle
8047 /// instructions we would like before a partial register update.
8048 unsigned X86InstrInfo::getPartialRegUpdateClearance(
8049     const MachineInstr &MI, unsigned OpNum,
8050     const TargetRegisterInfo *TRI) const {
8051   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
8052     return 0;
8053 
8054   // If MI is marked as reading Reg, the partial register update is wanted.
8055   const MachineOperand &MO = MI.getOperand(0);
8056   unsigned Reg = MO.getReg();
8057   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
8058     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
8059       return 0;
8060   } else {
8061     if (MI.readsRegister(Reg, TRI))
8062       return 0;
8063   }
8064 
8065   // If any instructions in the clearance range are reading Reg, insert a
8066   // dependency breaking instruction, which is inexpensive and is likely to
8067   // be hidden in other instruction's cycles.
8068   return PartialRegUpdateClearance;
8069 }
8070 
8071 // Return true for any instruction the copies the high bits of the first source
8072 // operand into the unused high bits of the destination operand.
8073 static bool hasUndefRegUpdate(unsigned Opcode) {
8074   switch (Opcode) {
8075   case X86::VCVTSI2SSrr:
8076   case X86::VCVTSI2SSrm:
8077   case X86::Int_VCVTSI2SSrr:
8078   case X86::Int_VCVTSI2SSrm:
8079   case X86::VCVTSI2SS64rr:
8080   case X86::VCVTSI2SS64rm:
8081   case X86::Int_VCVTSI2SS64rr:
8082   case X86::Int_VCVTSI2SS64rm:
8083   case X86::VCVTSI2SDrr:
8084   case X86::VCVTSI2SDrm:
8085   case X86::Int_VCVTSI2SDrr:
8086   case X86::Int_VCVTSI2SDrm:
8087   case X86::VCVTSI2SD64rr:
8088   case X86::VCVTSI2SD64rm:
8089   case X86::Int_VCVTSI2SD64rr:
8090   case X86::Int_VCVTSI2SD64rm:
8091   case X86::VCVTSD2SSrr:
8092   case X86::VCVTSD2SSrm:
8093   case X86::Int_VCVTSD2SSrr:
8094   case X86::Int_VCVTSD2SSrm:
8095   case X86::VCVTSS2SDrr:
8096   case X86::VCVTSS2SDrm:
8097   case X86::Int_VCVTSS2SDrr:
8098   case X86::Int_VCVTSS2SDrm:
8099   case X86::VRCPSSr:
8100   case X86::VRCPSSr_Int:
8101   case X86::VRCPSSm:
8102   case X86::VRCPSSm_Int:
8103   case X86::VROUNDSDr:
8104   case X86::VROUNDSDm:
8105   case X86::VROUNDSDr_Int:
8106   case X86::VROUNDSDm_Int:
8107   case X86::VROUNDSSr:
8108   case X86::VROUNDSSm:
8109   case X86::VROUNDSSr_Int:
8110   case X86::VROUNDSSm_Int:
8111   case X86::VRSQRTSSr:
8112   case X86::VRSQRTSSr_Int:
8113   case X86::VRSQRTSSm:
8114   case X86::VRSQRTSSm_Int:
8115   case X86::VSQRTSSr:
8116   case X86::VSQRTSSr_Int:
8117   case X86::VSQRTSSm:
8118   case X86::VSQRTSSm_Int:
8119   case X86::VSQRTSDr:
8120   case X86::VSQRTSDr_Int:
8121   case X86::VSQRTSDm:
8122   case X86::VSQRTSDm_Int:
8123   // AVX-512
8124   case X86::VCVTSI2SSZrr:
8125   case X86::VCVTSI2SSZrm:
8126   case X86::VCVTSI2SSZrr_Int:
8127   case X86::VCVTSI2SSZrrb_Int:
8128   case X86::VCVTSI2SSZrm_Int:
8129   case X86::VCVTSI642SSZrr:
8130   case X86::VCVTSI642SSZrm:
8131   case X86::VCVTSI642SSZrr_Int:
8132   case X86::VCVTSI642SSZrrb_Int:
8133   case X86::VCVTSI642SSZrm_Int:
8134   case X86::VCVTSI2SDZrr:
8135   case X86::VCVTSI2SDZrm:
8136   case X86::VCVTSI2SDZrr_Int:
8137   case X86::VCVTSI2SDZrrb_Int:
8138   case X86::VCVTSI2SDZrm_Int:
8139   case X86::VCVTSI642SDZrr:
8140   case X86::VCVTSI642SDZrm:
8141   case X86::VCVTSI642SDZrr_Int:
8142   case X86::VCVTSI642SDZrrb_Int:
8143   case X86::VCVTSI642SDZrm_Int:
8144   case X86::VCVTUSI2SSZrr:
8145   case X86::VCVTUSI2SSZrm:
8146   case X86::VCVTUSI2SSZrr_Int:
8147   case X86::VCVTUSI2SSZrrb_Int:
8148   case X86::VCVTUSI2SSZrm_Int:
8149   case X86::VCVTUSI642SSZrr:
8150   case X86::VCVTUSI642SSZrm:
8151   case X86::VCVTUSI642SSZrr_Int:
8152   case X86::VCVTUSI642SSZrrb_Int:
8153   case X86::VCVTUSI642SSZrm_Int:
8154   case X86::VCVTUSI2SDZrr:
8155   case X86::VCVTUSI2SDZrm:
8156   case X86::VCVTUSI2SDZrr_Int:
8157   case X86::VCVTUSI2SDZrm_Int:
8158   case X86::VCVTUSI642SDZrr:
8159   case X86::VCVTUSI642SDZrm:
8160   case X86::VCVTUSI642SDZrr_Int:
8161   case X86::VCVTUSI642SDZrrb_Int:
8162   case X86::VCVTUSI642SDZrm_Int:
8163   case X86::VCVTSD2SSZrr:
8164   case X86::VCVTSD2SSZrr_Int:
8165   case X86::VCVTSD2SSZrrb_Int:
8166   case X86::VCVTSD2SSZrm:
8167   case X86::VCVTSD2SSZrm_Int:
8168   case X86::VCVTSS2SDZrr:
8169   case X86::VCVTSS2SDZrr_Int:
8170   case X86::VCVTSS2SDZrrb_Int:
8171   case X86::VCVTSS2SDZrm:
8172   case X86::VCVTSS2SDZrm_Int:
8173   case X86::VRNDSCALESDr:
8174   case X86::VRNDSCALESDrb:
8175   case X86::VRNDSCALESDm:
8176   case X86::VRNDSCALESSr:
8177   case X86::VRNDSCALESSrb:
8178   case X86::VRNDSCALESSm:
8179   case X86::VRCP14SSrr:
8180   case X86::VRCP14SSrm:
8181   case X86::VRSQRT14SSrr:
8182   case X86::VRSQRT14SSrm:
8183   case X86::VSQRTSSZr:
8184   case X86::VSQRTSSZr_Int:
8185   case X86::VSQRTSSZrb_Int:
8186   case X86::VSQRTSSZm:
8187   case X86::VSQRTSSZm_Int:
8188   case X86::VSQRTSDZr:
8189   case X86::VSQRTSDZr_Int:
8190   case X86::VSQRTSDZrb_Int:
8191   case X86::VSQRTSDZm:
8192   case X86::VSQRTSDZm_Int:
8193     return true;
8194   }
8195 
8196   return false;
8197 }
8198 
8199 /// Inform the ExeDepsFix pass how many idle instructions we would like before
8200 /// certain undef register reads.
8201 ///
8202 /// This catches the VCVTSI2SD family of instructions:
8203 ///
8204 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
8205 ///
8206 /// We should to be careful *not* to catch VXOR idioms which are presumably
8207 /// handled specially in the pipeline:
8208 ///
8209 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
8210 ///
8211 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
8212 /// high bits that are passed-through are not live.
8213 unsigned
8214 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
8215                                    const TargetRegisterInfo *TRI) const {
8216   if (!hasUndefRegUpdate(MI.getOpcode()))
8217     return 0;
8218 
8219   // Set the OpNum parameter to the first source operand.
8220   OpNum = 1;
8221 
8222   const MachineOperand &MO = MI.getOperand(OpNum);
8223   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
8224     return UndefRegClearance;
8225   }
8226   return 0;
8227 }
8228 
8229 void X86InstrInfo::breakPartialRegDependency(
8230     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
8231   unsigned Reg = MI.getOperand(OpNum).getReg();
8232   // If MI kills this register, the false dependence is already broken.
8233   if (MI.killsRegister(Reg, TRI))
8234     return;
8235 
8236   if (X86::VR128RegClass.contains(Reg)) {
8237     // These instructions are all floating point domain, so xorps is the best
8238     // choice.
8239     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
8240     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
8241         .addReg(Reg, RegState::Undef)
8242         .addReg(Reg, RegState::Undef);
8243     MI.addRegisterKilled(Reg, TRI, true);
8244   } else if (X86::VR256RegClass.contains(Reg)) {
8245     // Use vxorps to clear the full ymm register.
8246     // It wants to read and write the xmm sub-register.
8247     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
8248     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
8249         .addReg(XReg, RegState::Undef)
8250         .addReg(XReg, RegState::Undef)
8251         .addReg(Reg, RegState::ImplicitDefine);
8252     MI.addRegisterKilled(Reg, TRI, true);
8253   }
8254 }
8255 
8256 MachineInstr *
8257 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
8258                                     ArrayRef<unsigned> Ops,
8259                                     MachineBasicBlock::iterator InsertPt,
8260                                     int FrameIndex, LiveIntervals *LIS) const {
8261   // Check switch flag
8262   if (NoFusing)
8263     return nullptr;
8264 
8265   // Unless optimizing for size, don't fold to avoid partial
8266   // register update stalls
8267   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
8268     return nullptr;
8269 
8270   // Don't fold subreg spills, or reloads that use a high subreg.
8271   for (auto Op : Ops) {
8272     MachineOperand &MO = MI.getOperand(Op);
8273     auto SubReg = MO.getSubReg();
8274     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
8275       return nullptr;
8276   }
8277 
8278   const MachineFrameInfo &MFI = MF.getFrameInfo();
8279   unsigned Size = MFI.getObjectSize(FrameIndex);
8280   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
8281   // If the function stack isn't realigned we don't want to fold instructions
8282   // that need increased alignment.
8283   if (!RI.needsStackRealignment(MF))
8284     Alignment =
8285         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
8286   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8287     unsigned NewOpc = 0;
8288     unsigned RCSize = 0;
8289     switch (MI.getOpcode()) {
8290     default: return nullptr;
8291     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
8292     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
8293     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
8294     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
8295     }
8296     // Check if it's safe to fold the load. If the size of the object is
8297     // narrower than the load width, then it's not.
8298     if (Size < RCSize)
8299       return nullptr;
8300     // Change to CMPXXri r, 0 first.
8301     MI.setDesc(get(NewOpc));
8302     MI.getOperand(1).ChangeToImmediate(0);
8303   } else if (Ops.size() != 1)
8304     return nullptr;
8305 
8306   return foldMemoryOperandImpl(MF, MI, Ops[0],
8307                                MachineOperand::CreateFI(FrameIndex), InsertPt,
8308                                Size, Alignment, /*AllowCommute=*/true);
8309 }
8310 
8311 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
8312 /// because the latter uses contents that wouldn't be defined in the folded
8313 /// version.  For instance, this transformation isn't legal:
8314 ///   movss (%rdi), %xmm0
8315 ///   addps %xmm0, %xmm0
8316 /// ->
8317 ///   addps (%rdi), %xmm0
8318 ///
8319 /// But this one is:
8320 ///   movss (%rdi), %xmm0
8321 ///   addss %xmm0, %xmm0
8322 /// ->
8323 ///   addss (%rdi), %xmm0
8324 ///
8325 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
8326                                              const MachineInstr &UserMI,
8327                                              const MachineFunction &MF) {
8328   unsigned Opc = LoadMI.getOpcode();
8329   unsigned UserOpc = UserMI.getOpcode();
8330   unsigned RegSize =
8331       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
8332 
8333   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
8334       RegSize > 4) {
8335     // These instructions only load 32 bits, we can't fold them if the
8336     // destination register is wider than 32 bits (4 bytes), and its user
8337     // instruction isn't scalar (SS).
8338     switch (UserOpc) {
8339     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
8340     case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
8341     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
8342     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
8343     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
8344     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
8345     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
8346     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
8347     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
8348     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
8349     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
8350     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
8351     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
8352     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
8353     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
8354     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
8355     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
8356     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
8357     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
8358     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
8359     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
8360     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
8361     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
8362     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
8363     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
8364     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
8365     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
8366     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
8367     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
8368     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
8369     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
8370     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
8371     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
8372     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
8373     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
8374     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
8375     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
8376     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
8377     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
8378       return false;
8379     default:
8380       return true;
8381     }
8382   }
8383 
8384   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
8385       RegSize > 8) {
8386     // These instructions only load 64 bits, we can't fold them if the
8387     // destination register is wider than 64 bits (8 bytes), and its user
8388     // instruction isn't scalar (SD).
8389     switch (UserOpc) {
8390     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
8391     case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
8392     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
8393     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
8394     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
8395     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
8396     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
8397     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
8398     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
8399     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
8400     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
8401     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
8402     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
8403     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
8404     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
8405     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
8406     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
8407     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
8408     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
8409     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
8410     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
8411     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
8412     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
8413     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
8414     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
8415     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
8416     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
8417     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
8418     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
8419     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
8420     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
8421     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
8422     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
8423     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
8424     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
8425     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
8426     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
8427     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
8428     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
8429       return false;
8430     default:
8431       return true;
8432     }
8433   }
8434 
8435   return false;
8436 }
8437 
8438 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8439     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
8440     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
8441     LiveIntervals *LIS) const {
8442 
8443   // TODO: Support the case where LoadMI loads a wide register, but MI
8444   // only uses a subreg.
8445   for (auto Op : Ops) {
8446     if (MI.getOperand(Op).getSubReg())
8447       return nullptr;
8448   }
8449 
8450   // If loading from a FrameIndex, fold directly from the FrameIndex.
8451   unsigned NumOps = LoadMI.getDesc().getNumOperands();
8452   int FrameIndex;
8453   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
8454     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8455       return nullptr;
8456     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
8457   }
8458 
8459   // Check switch flag
8460   if (NoFusing) return nullptr;
8461 
8462   // Avoid partial register update stalls unless optimizing for size.
8463   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
8464     return nullptr;
8465 
8466   // Determine the alignment of the load.
8467   unsigned Alignment = 0;
8468   if (LoadMI.hasOneMemOperand())
8469     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
8470   else
8471     switch (LoadMI.getOpcode()) {
8472     case X86::AVX512_512_SET0:
8473     case X86::AVX512_512_SETALLONES:
8474       Alignment = 64;
8475       break;
8476     case X86::AVX2_SETALLONES:
8477     case X86::AVX_SET0:
8478     case X86::AVX512_256_SET0:
8479       Alignment = 32;
8480       break;
8481     case X86::V_SET0:
8482     case X86::V_SETALLONES:
8483     case X86::AVX512_128_SET0:
8484       Alignment = 16;
8485       break;
8486     case X86::FsFLD0SD:
8487     case X86::AVX512_FsFLD0SD:
8488       Alignment = 8;
8489       break;
8490     case X86::FsFLD0SS:
8491     case X86::AVX512_FsFLD0SS:
8492       Alignment = 4;
8493       break;
8494     default:
8495       return nullptr;
8496     }
8497   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8498     unsigned NewOpc = 0;
8499     switch (MI.getOpcode()) {
8500     default: return nullptr;
8501     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
8502     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
8503     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
8504     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
8505     }
8506     // Change to CMPXXri r, 0 first.
8507     MI.setDesc(get(NewOpc));
8508     MI.getOperand(1).ChangeToImmediate(0);
8509   } else if (Ops.size() != 1)
8510     return nullptr;
8511 
8512   // Make sure the subregisters match.
8513   // Otherwise we risk changing the size of the load.
8514   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
8515     return nullptr;
8516 
8517   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
8518   switch (LoadMI.getOpcode()) {
8519   case X86::V_SET0:
8520   case X86::V_SETALLONES:
8521   case X86::AVX2_SETALLONES:
8522   case X86::AVX_SET0:
8523   case X86::AVX512_128_SET0:
8524   case X86::AVX512_256_SET0:
8525   case X86::AVX512_512_SET0:
8526   case X86::AVX512_512_SETALLONES:
8527   case X86::FsFLD0SD:
8528   case X86::AVX512_FsFLD0SD:
8529   case X86::FsFLD0SS:
8530   case X86::AVX512_FsFLD0SS: {
8531     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8532     // Create a constant-pool entry and operands to load from it.
8533 
8534     // Medium and large mode can't fold loads this way.
8535     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
8536         MF.getTarget().getCodeModel() != CodeModel::Kernel)
8537       return nullptr;
8538 
8539     // x86-32 PIC requires a PIC base register for constant pools.
8540     unsigned PICBase = 0;
8541     if (MF.getTarget().isPositionIndependent()) {
8542       if (Subtarget.is64Bit())
8543         PICBase = X86::RIP;
8544       else
8545         // FIXME: PICBase = getGlobalBaseReg(&MF);
8546         // This doesn't work for several reasons.
8547         // 1. GlobalBaseReg may have been spilled.
8548         // 2. It may not be live at MI.
8549         return nullptr;
8550     }
8551 
8552     // Create a constant-pool entry.
8553     MachineConstantPool &MCP = *MF.getConstantPool();
8554     Type *Ty;
8555     unsigned Opc = LoadMI.getOpcode();
8556     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
8557       Ty = Type::getFloatTy(MF.getFunction()->getContext());
8558     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
8559       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
8560     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
8561       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
8562     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
8563              Opc == X86::AVX512_256_SET0)
8564       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
8565     else
8566       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
8567 
8568     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
8569                       Opc == X86::AVX512_512_SETALLONES);
8570     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
8571                                     Constant::getNullValue(Ty);
8572     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
8573 
8574     // Create operands to load from the constant pool entry.
8575     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
8576     MOs.push_back(MachineOperand::CreateImm(1));
8577     MOs.push_back(MachineOperand::CreateReg(0, false));
8578     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
8579     MOs.push_back(MachineOperand::CreateReg(0, false));
8580     break;
8581   }
8582   default: {
8583     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8584       return nullptr;
8585 
8586     // Folding a normal load. Just copy the load's address operands.
8587     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
8588                LoadMI.operands_begin() + NumOps);
8589     break;
8590   }
8591   }
8592   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
8593                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
8594 }
8595 
8596 bool X86InstrInfo::unfoldMemoryOperand(
8597     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
8598     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
8599   auto I = MemOp2RegOpTable.find(MI.getOpcode());
8600   if (I == MemOp2RegOpTable.end())
8601     return false;
8602   unsigned Opc = I->second.first;
8603   unsigned Index = I->second.second & TB_INDEX_MASK;
8604   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8605   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8606   if (UnfoldLoad && !FoldedLoad)
8607     return false;
8608   UnfoldLoad &= FoldedLoad;
8609   if (UnfoldStore && !FoldedStore)
8610     return false;
8611   UnfoldStore &= FoldedStore;
8612 
8613   const MCInstrDesc &MCID = get(Opc);
8614   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
8615   // TODO: Check if 32-byte or greater accesses are slow too?
8616   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8617       Subtarget.isUnalignedMem16Slow())
8618     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
8619     // conservatively assume the address is unaligned. That's bad for
8620     // performance.
8621     return false;
8622   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
8623   SmallVector<MachineOperand,2> BeforeOps;
8624   SmallVector<MachineOperand,2> AfterOps;
8625   SmallVector<MachineOperand,4> ImpOps;
8626   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8627     MachineOperand &Op = MI.getOperand(i);
8628     if (i >= Index && i < Index + X86::AddrNumOperands)
8629       AddrOps.push_back(Op);
8630     else if (Op.isReg() && Op.isImplicit())
8631       ImpOps.push_back(Op);
8632     else if (i < Index)
8633       BeforeOps.push_back(Op);
8634     else if (i > Index)
8635       AfterOps.push_back(Op);
8636   }
8637 
8638   // Emit the load instruction.
8639   if (UnfoldLoad) {
8640     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
8641         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
8642     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
8643     if (UnfoldStore) {
8644       // Address operands cannot be marked isKill.
8645       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
8646         MachineOperand &MO = NewMIs[0]->getOperand(i);
8647         if (MO.isReg())
8648           MO.setIsKill(false);
8649       }
8650     }
8651   }
8652 
8653   // Emit the data processing instruction.
8654   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
8655   MachineInstrBuilder MIB(MF, DataMI);
8656 
8657   if (FoldedStore)
8658     MIB.addReg(Reg, RegState::Define);
8659   for (MachineOperand &BeforeOp : BeforeOps)
8660     MIB.add(BeforeOp);
8661   if (FoldedLoad)
8662     MIB.addReg(Reg);
8663   for (MachineOperand &AfterOp : AfterOps)
8664     MIB.add(AfterOp);
8665   for (MachineOperand &ImpOp : ImpOps) {
8666     MIB.addReg(ImpOp.getReg(),
8667                getDefRegState(ImpOp.isDef()) |
8668                RegState::Implicit |
8669                getKillRegState(ImpOp.isKill()) |
8670                getDeadRegState(ImpOp.isDead()) |
8671                getUndefRegState(ImpOp.isUndef()));
8672   }
8673   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8674   switch (DataMI->getOpcode()) {
8675   default: break;
8676   case X86::CMP64ri32:
8677   case X86::CMP64ri8:
8678   case X86::CMP32ri:
8679   case X86::CMP32ri8:
8680   case X86::CMP16ri:
8681   case X86::CMP16ri8:
8682   case X86::CMP8ri: {
8683     MachineOperand &MO0 = DataMI->getOperand(0);
8684     MachineOperand &MO1 = DataMI->getOperand(1);
8685     if (MO1.getImm() == 0) {
8686       unsigned NewOpc;
8687       switch (DataMI->getOpcode()) {
8688       default: llvm_unreachable("Unreachable!");
8689       case X86::CMP64ri8:
8690       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
8691       case X86::CMP32ri8:
8692       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
8693       case X86::CMP16ri8:
8694       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
8695       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
8696       }
8697       DataMI->setDesc(get(NewOpc));
8698       MO1.ChangeToRegister(MO0.getReg(), false);
8699     }
8700   }
8701   }
8702   NewMIs.push_back(DataMI);
8703 
8704   // Emit the store instruction.
8705   if (UnfoldStore) {
8706     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
8707     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
8708         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
8709     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
8710   }
8711 
8712   return true;
8713 }
8714 
8715 bool
8716 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
8717                                   SmallVectorImpl<SDNode*> &NewNodes) const {
8718   if (!N->isMachineOpcode())
8719     return false;
8720 
8721   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
8722   if (I == MemOp2RegOpTable.end())
8723     return false;
8724   unsigned Opc = I->second.first;
8725   unsigned Index = I->second.second & TB_INDEX_MASK;
8726   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8727   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8728   const MCInstrDesc &MCID = get(Opc);
8729   MachineFunction &MF = DAG.getMachineFunction();
8730   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
8731   unsigned NumDefs = MCID.NumDefs;
8732   std::vector<SDValue> AddrOps;
8733   std::vector<SDValue> BeforeOps;
8734   std::vector<SDValue> AfterOps;
8735   SDLoc dl(N);
8736   unsigned NumOps = N->getNumOperands();
8737   for (unsigned i = 0; i != NumOps-1; ++i) {
8738     SDValue Op = N->getOperand(i);
8739     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
8740       AddrOps.push_back(Op);
8741     else if (i < Index-NumDefs)
8742       BeforeOps.push_back(Op);
8743     else if (i > Index-NumDefs)
8744       AfterOps.push_back(Op);
8745   }
8746   SDValue Chain = N->getOperand(NumOps-1);
8747   AddrOps.push_back(Chain);
8748 
8749   // Emit the load instruction.
8750   SDNode *Load = nullptr;
8751   if (FoldedLoad) {
8752     EVT VT = *RC->vt_begin();
8753     std::pair<MachineInstr::mmo_iterator,
8754               MachineInstr::mmo_iterator> MMOs =
8755       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
8756                             cast<MachineSDNode>(N)->memoperands_end());
8757     if (!(*MMOs.first) &&
8758         RC == &X86::VR128RegClass &&
8759         Subtarget.isUnalignedMem16Slow())
8760       // Do not introduce a slow unaligned load.
8761       return false;
8762     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8763     // memory access is slow above.
8764     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
8765     bool isAligned = (*MMOs.first) &&
8766                      (*MMOs.first)->getAlignment() >= Alignment;
8767     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
8768                               VT, MVT::Other, AddrOps);
8769     NewNodes.push_back(Load);
8770 
8771     // Preserve memory reference information.
8772     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
8773   }
8774 
8775   // Emit the data processing instruction.
8776   std::vector<EVT> VTs;
8777   const TargetRegisterClass *DstRC = nullptr;
8778   if (MCID.getNumDefs() > 0) {
8779     DstRC = getRegClass(MCID, 0, &RI, MF);
8780     VTs.push_back(*DstRC->vt_begin());
8781   }
8782   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
8783     EVT VT = N->getValueType(i);
8784     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
8785       VTs.push_back(VT);
8786   }
8787   if (Load)
8788     BeforeOps.push_back(SDValue(Load, 0));
8789   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
8790   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
8791   NewNodes.push_back(NewNode);
8792 
8793   // Emit the store instruction.
8794   if (FoldedStore) {
8795     AddrOps.pop_back();
8796     AddrOps.push_back(SDValue(NewNode, 0));
8797     AddrOps.push_back(Chain);
8798     std::pair<MachineInstr::mmo_iterator,
8799               MachineInstr::mmo_iterator> MMOs =
8800       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
8801                              cast<MachineSDNode>(N)->memoperands_end());
8802     if (!(*MMOs.first) &&
8803         RC == &X86::VR128RegClass &&
8804         Subtarget.isUnalignedMem16Slow())
8805       // Do not introduce a slow unaligned store.
8806       return false;
8807     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8808     // memory access is slow above.
8809     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
8810     bool isAligned = (*MMOs.first) &&
8811                      (*MMOs.first)->getAlignment() >= Alignment;
8812     SDNode *Store =
8813         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
8814                            dl, MVT::Other, AddrOps);
8815     NewNodes.push_back(Store);
8816 
8817     // Preserve memory reference information.
8818     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
8819   }
8820 
8821   return true;
8822 }
8823 
8824 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
8825                                       bool UnfoldLoad, bool UnfoldStore,
8826                                       unsigned *LoadRegIndex) const {
8827   auto I = MemOp2RegOpTable.find(Opc);
8828   if (I == MemOp2RegOpTable.end())
8829     return 0;
8830   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8831   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8832   if (UnfoldLoad && !FoldedLoad)
8833     return 0;
8834   if (UnfoldStore && !FoldedStore)
8835     return 0;
8836   if (LoadRegIndex)
8837     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
8838   return I->second.first;
8839 }
8840 
8841 bool
8842 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
8843                                      int64_t &Offset1, int64_t &Offset2) const {
8844   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
8845     return false;
8846   unsigned Opc1 = Load1->getMachineOpcode();
8847   unsigned Opc2 = Load2->getMachineOpcode();
8848   switch (Opc1) {
8849   default: return false;
8850   case X86::MOV8rm:
8851   case X86::MOV16rm:
8852   case X86::MOV32rm:
8853   case X86::MOV64rm:
8854   case X86::LD_Fp32m:
8855   case X86::LD_Fp64m:
8856   case X86::LD_Fp80m:
8857   case X86::MOVSSrm:
8858   case X86::MOVSDrm:
8859   case X86::MMX_MOVD64rm:
8860   case X86::MMX_MOVQ64rm:
8861   case X86::MOVAPSrm:
8862   case X86::MOVUPSrm:
8863   case X86::MOVAPDrm:
8864   case X86::MOVUPDrm:
8865   case X86::MOVDQArm:
8866   case X86::MOVDQUrm:
8867   // AVX load instructions
8868   case X86::VMOVSSrm:
8869   case X86::VMOVSDrm:
8870   case X86::VMOVAPSrm:
8871   case X86::VMOVUPSrm:
8872   case X86::VMOVAPDrm:
8873   case X86::VMOVUPDrm:
8874   case X86::VMOVDQArm:
8875   case X86::VMOVDQUrm:
8876   case X86::VMOVAPSYrm:
8877   case X86::VMOVUPSYrm:
8878   case X86::VMOVAPDYrm:
8879   case X86::VMOVUPDYrm:
8880   case X86::VMOVDQAYrm:
8881   case X86::VMOVDQUYrm:
8882   // AVX512 load instructions
8883   case X86::VMOVSSZrm:
8884   case X86::VMOVSDZrm:
8885   case X86::VMOVAPSZ128rm:
8886   case X86::VMOVUPSZ128rm:
8887   case X86::VMOVAPSZ128rm_NOVLX:
8888   case X86::VMOVUPSZ128rm_NOVLX:
8889   case X86::VMOVAPDZ128rm:
8890   case X86::VMOVUPDZ128rm:
8891   case X86::VMOVDQU8Z128rm:
8892   case X86::VMOVDQU16Z128rm:
8893   case X86::VMOVDQA32Z128rm:
8894   case X86::VMOVDQU32Z128rm:
8895   case X86::VMOVDQA64Z128rm:
8896   case X86::VMOVDQU64Z128rm:
8897   case X86::VMOVAPSZ256rm:
8898   case X86::VMOVUPSZ256rm:
8899   case X86::VMOVAPSZ256rm_NOVLX:
8900   case X86::VMOVUPSZ256rm_NOVLX:
8901   case X86::VMOVAPDZ256rm:
8902   case X86::VMOVUPDZ256rm:
8903   case X86::VMOVDQU8Z256rm:
8904   case X86::VMOVDQU16Z256rm:
8905   case X86::VMOVDQA32Z256rm:
8906   case X86::VMOVDQU32Z256rm:
8907   case X86::VMOVDQA64Z256rm:
8908   case X86::VMOVDQU64Z256rm:
8909   case X86::VMOVAPSZrm:
8910   case X86::VMOVUPSZrm:
8911   case X86::VMOVAPDZrm:
8912   case X86::VMOVUPDZrm:
8913   case X86::VMOVDQU8Zrm:
8914   case X86::VMOVDQU16Zrm:
8915   case X86::VMOVDQA32Zrm:
8916   case X86::VMOVDQU32Zrm:
8917   case X86::VMOVDQA64Zrm:
8918   case X86::VMOVDQU64Zrm:
8919   case X86::KMOVBkm:
8920   case X86::KMOVWkm:
8921   case X86::KMOVDkm:
8922   case X86::KMOVQkm:
8923     break;
8924   }
8925   switch (Opc2) {
8926   default: return false;
8927   case X86::MOV8rm:
8928   case X86::MOV16rm:
8929   case X86::MOV32rm:
8930   case X86::MOV64rm:
8931   case X86::LD_Fp32m:
8932   case X86::LD_Fp64m:
8933   case X86::LD_Fp80m:
8934   case X86::MOVSSrm:
8935   case X86::MOVSDrm:
8936   case X86::MMX_MOVD64rm:
8937   case X86::MMX_MOVQ64rm:
8938   case X86::MOVAPSrm:
8939   case X86::MOVUPSrm:
8940   case X86::MOVAPDrm:
8941   case X86::MOVUPDrm:
8942   case X86::MOVDQArm:
8943   case X86::MOVDQUrm:
8944   // AVX load instructions
8945   case X86::VMOVSSrm:
8946   case X86::VMOVSDrm:
8947   case X86::VMOVAPSrm:
8948   case X86::VMOVUPSrm:
8949   case X86::VMOVAPDrm:
8950   case X86::VMOVUPDrm:
8951   case X86::VMOVDQArm:
8952   case X86::VMOVDQUrm:
8953   case X86::VMOVAPSYrm:
8954   case X86::VMOVUPSYrm:
8955   case X86::VMOVAPDYrm:
8956   case X86::VMOVUPDYrm:
8957   case X86::VMOVDQAYrm:
8958   case X86::VMOVDQUYrm:
8959   // AVX512 load instructions
8960   case X86::VMOVSSZrm:
8961   case X86::VMOVSDZrm:
8962   case X86::VMOVAPSZ128rm:
8963   case X86::VMOVUPSZ128rm:
8964   case X86::VMOVAPSZ128rm_NOVLX:
8965   case X86::VMOVUPSZ128rm_NOVLX:
8966   case X86::VMOVAPDZ128rm:
8967   case X86::VMOVUPDZ128rm:
8968   case X86::VMOVDQU8Z128rm:
8969   case X86::VMOVDQU16Z128rm:
8970   case X86::VMOVDQA32Z128rm:
8971   case X86::VMOVDQU32Z128rm:
8972   case X86::VMOVDQA64Z128rm:
8973   case X86::VMOVDQU64Z128rm:
8974   case X86::VMOVAPSZ256rm:
8975   case X86::VMOVUPSZ256rm:
8976   case X86::VMOVAPSZ256rm_NOVLX:
8977   case X86::VMOVUPSZ256rm_NOVLX:
8978   case X86::VMOVAPDZ256rm:
8979   case X86::VMOVUPDZ256rm:
8980   case X86::VMOVDQU8Z256rm:
8981   case X86::VMOVDQU16Z256rm:
8982   case X86::VMOVDQA32Z256rm:
8983   case X86::VMOVDQU32Z256rm:
8984   case X86::VMOVDQA64Z256rm:
8985   case X86::VMOVDQU64Z256rm:
8986   case X86::VMOVAPSZrm:
8987   case X86::VMOVUPSZrm:
8988   case X86::VMOVAPDZrm:
8989   case X86::VMOVUPDZrm:
8990   case X86::VMOVDQU8Zrm:
8991   case X86::VMOVDQU16Zrm:
8992   case X86::VMOVDQA32Zrm:
8993   case X86::VMOVDQU32Zrm:
8994   case X86::VMOVDQA64Zrm:
8995   case X86::VMOVDQU64Zrm:
8996   case X86::KMOVBkm:
8997   case X86::KMOVWkm:
8998   case X86::KMOVDkm:
8999   case X86::KMOVQkm:
9000     break;
9001   }
9002 
9003   // Check if chain operands and base addresses match.
9004   if (Load1->getOperand(0) != Load2->getOperand(0) ||
9005       Load1->getOperand(5) != Load2->getOperand(5))
9006     return false;
9007   // Segment operands should match as well.
9008   if (Load1->getOperand(4) != Load2->getOperand(4))
9009     return false;
9010   // Scale should be 1, Index should be Reg0.
9011   if (Load1->getOperand(1) == Load2->getOperand(1) &&
9012       Load1->getOperand(2) == Load2->getOperand(2)) {
9013     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
9014       return false;
9015 
9016     // Now let's examine the displacements.
9017     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
9018         isa<ConstantSDNode>(Load2->getOperand(3))) {
9019       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
9020       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
9021       return true;
9022     }
9023   }
9024   return false;
9025 }
9026 
9027 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
9028                                            int64_t Offset1, int64_t Offset2,
9029                                            unsigned NumLoads) const {
9030   assert(Offset2 > Offset1);
9031   if ((Offset2 - Offset1) / 8 > 64)
9032     return false;
9033 
9034   unsigned Opc1 = Load1->getMachineOpcode();
9035   unsigned Opc2 = Load2->getMachineOpcode();
9036   if (Opc1 != Opc2)
9037     return false;  // FIXME: overly conservative?
9038 
9039   switch (Opc1) {
9040   default: break;
9041   case X86::LD_Fp32m:
9042   case X86::LD_Fp64m:
9043   case X86::LD_Fp80m:
9044   case X86::MMX_MOVD64rm:
9045   case X86::MMX_MOVQ64rm:
9046     return false;
9047   }
9048 
9049   EVT VT = Load1->getValueType(0);
9050   switch (VT.getSimpleVT().SimpleTy) {
9051   default:
9052     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
9053     // have 16 of them to play with.
9054     if (Subtarget.is64Bit()) {
9055       if (NumLoads >= 3)
9056         return false;
9057     } else if (NumLoads) {
9058       return false;
9059     }
9060     break;
9061   case MVT::i8:
9062   case MVT::i16:
9063   case MVT::i32:
9064   case MVT::i64:
9065   case MVT::f32:
9066   case MVT::f64:
9067     if (NumLoads)
9068       return false;
9069     break;
9070   }
9071 
9072   return true;
9073 }
9074 
9075 bool X86InstrInfo::
9076 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
9077   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
9078   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
9079   Cond[0].setImm(GetOppositeBranchCondition(CC));
9080   return false;
9081 }
9082 
9083 bool X86InstrInfo::
9084 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
9085   // FIXME: Return false for x87 stack register classes for now. We can't
9086   // allow any loads of these registers before FpGet_ST0_80.
9087   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
9088            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
9089 }
9090 
9091 /// Return a virtual register initialized with the
9092 /// the global base register value. Output instructions required to
9093 /// initialize the register in the function entry block, if necessary.
9094 ///
9095 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
9096 ///
9097 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
9098   assert(!Subtarget.is64Bit() &&
9099          "X86-64 PIC uses RIP relative addressing");
9100 
9101   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
9102   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
9103   if (GlobalBaseReg != 0)
9104     return GlobalBaseReg;
9105 
9106   // Create the register. The code to initialize it is inserted
9107   // later, by the CGBR pass (below).
9108   MachineRegisterInfo &RegInfo = MF->getRegInfo();
9109   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
9110   X86FI->setGlobalBaseReg(GlobalBaseReg);
9111   return GlobalBaseReg;
9112 }
9113 
9114 // These are the replaceable SSE instructions. Some of these have Int variants
9115 // that we don't include here. We don't want to replace instructions selected
9116 // by intrinsics.
9117 static const uint16_t ReplaceableInstrs[][3] = {
9118   //PackedSingle     PackedDouble    PackedInt
9119   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
9120   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
9121   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
9122   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
9123   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
9124   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
9125   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
9126   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
9127   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
9128   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
9129   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
9130   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
9131   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
9132   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
9133   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
9134   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
9135   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
9136   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
9137   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
9138   // AVX 128-bit support
9139   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
9140   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
9141   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
9142   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
9143   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
9144   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
9145   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
9146   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
9147   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
9148   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
9149   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
9150   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
9151   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
9152   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
9153   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
9154   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
9155   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
9156   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
9157   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
9158   // AVX 256-bit support
9159   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
9160   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
9161   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
9162   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
9163   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
9164   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
9165   // AVX512 support
9166   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
9167   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
9168   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
9169   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
9170   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
9171   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
9172   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
9173   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
9174   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
9175   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
9176   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
9177   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
9178   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
9179   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
9180   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
9181   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
9182   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
9183   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
9184 };
9185 
9186 static const uint16_t ReplaceableInstrsAVX2[][3] = {
9187   //PackedSingle       PackedDouble       PackedInt
9188   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
9189   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
9190   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
9191   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
9192   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
9193   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
9194   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
9195   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
9196   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
9197   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
9198   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
9199   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
9200   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
9201   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
9202   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
9203   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
9204   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
9205 };
9206 
9207 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
9208   //PackedSingle       PackedDouble       PackedInt
9209   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
9210   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
9211   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
9212   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
9213 };
9214 
9215 static const uint16_t ReplaceableInstrsAVX512[][4] = {
9216   // Two integer columns for 64-bit and 32-bit elements.
9217   //PackedSingle        PackedDouble        PackedInt             PackedInt
9218   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
9219   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
9220   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
9221   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
9222   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
9223   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
9224   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
9225   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
9226   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
9227   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
9228   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
9229   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
9230   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
9231   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
9232   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
9233 };
9234 
9235 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
9236   // Two integer columns for 64-bit and 32-bit elements.
9237   //PackedSingle        PackedDouble        PackedInt           PackedInt
9238   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
9239   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
9240   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
9241   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
9242   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
9243   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
9244   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
9245   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
9246   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
9247   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
9248   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
9249   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
9250   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
9251   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
9252   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
9253   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
9254   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
9255   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
9256   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
9257   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
9258   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
9259   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
9260   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
9261   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
9262 };
9263 
9264 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
9265   // Two integer columns for 64-bit and 32-bit elements.
9266   //PackedSingle          PackedDouble
9267   //PackedInt             PackedInt
9268   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
9269     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
9270   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
9271     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
9272   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
9273     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
9274   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
9275     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
9276   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
9277     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
9278   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
9279     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
9280   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
9281     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
9282   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
9283     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
9284   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
9285     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
9286   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
9287     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
9288   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
9289     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
9290   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
9291     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
9292   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
9293     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
9294   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
9295     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
9296   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
9297     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
9298   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
9299     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
9300   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
9301     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
9302   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
9303     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
9304   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
9305     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
9306   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
9307     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
9308   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
9309     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
9310   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
9311     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
9312   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
9313     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
9314   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
9315     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
9316   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
9317     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
9318   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
9319     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
9320   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
9321     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
9322   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
9323     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
9324   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
9325     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
9326   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
9327     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
9328   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
9329     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
9330   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
9331     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
9332   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
9333     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
9334   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
9335     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
9336   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
9337     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
9338   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
9339     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
9340   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
9341     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
9342   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
9343     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
9344   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
9345     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
9346   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
9347     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
9348   { X86::VORPSZrmk,       X86::VORPDZrmk,
9349     X86::VPORQZrmk,       X86::VPORDZrmk       },
9350   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
9351     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
9352   { X86::VORPSZrrk,       X86::VORPDZrrk,
9353     X86::VPORQZrrk,       X86::VPORDZrrk       },
9354   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
9355     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
9356   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
9357     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
9358   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
9359     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
9360   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
9361     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
9362   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
9363     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
9364   // Broadcast loads can be handled the same as masked operations to avoid
9365   // changing element size.
9366   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
9367     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
9368   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
9369     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
9370   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
9371     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
9372   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
9373     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
9374   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
9375     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
9376   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
9377     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
9378   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
9379     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
9380   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
9381     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
9382   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
9383     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
9384   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9385     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9386   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9387     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9388   { X86::VORPSZrmb,       X86::VORPDZrmb,
9389     X86::VPORQZrmb,       X86::VPORDZrmb       },
9390   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
9391     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
9392   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
9393     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
9394   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
9395     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
9396   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
9397     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
9398   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
9399     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
9400   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
9401     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
9402   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
9403     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
9404   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
9405     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
9406   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
9407     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
9408   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
9409     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
9410   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9411     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9412   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9413     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9414   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
9415     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
9416   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
9417     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
9418   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
9419     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
9420   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
9421     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
9422   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
9423     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
9424   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
9425     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
9426   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
9427     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
9428   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
9429     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
9430   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
9431     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
9432   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
9433     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
9434   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
9435     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
9436   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
9437     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
9438   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
9439     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
9440   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
9441     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
9442   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
9443     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
9444 };
9445 
9446 // FIXME: Some shuffle and unpack instructions have equivalents in different
9447 // domains, but they require a bit more work than just switching opcodes.
9448 
9449 static const uint16_t *lookup(unsigned opcode, unsigned domain,
9450                               ArrayRef<uint16_t[3]> Table) {
9451   for (const uint16_t (&Row)[3] : Table)
9452     if (Row[domain-1] == opcode)
9453       return Row;
9454   return nullptr;
9455 }
9456 
9457 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
9458                                     ArrayRef<uint16_t[4]> Table) {
9459   // If this is the integer domain make sure to check both integer columns.
9460   for (const uint16_t (&Row)[4] : Table)
9461     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
9462       return Row;
9463   return nullptr;
9464 }
9465 
9466 std::pair<uint16_t, uint16_t>
9467 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
9468   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9469   unsigned opcode = MI.getOpcode();
9470   uint16_t validDomains = 0;
9471   if (domain) {
9472     if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
9473       validDomains = 0xe;
9474     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
9475       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
9476     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
9477       // Insert/extract instructions should only effect domain if AVX2
9478       // is enabled.
9479       if (!Subtarget.hasAVX2())
9480         return std::make_pair(0, 0);
9481       validDomains = 0xe;
9482     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
9483       validDomains = 0xe;
9484     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
9485                                                   ReplaceableInstrsAVX512DQ)) {
9486       validDomains = 0xe;
9487     } else if (Subtarget.hasDQI()) {
9488       if (const uint16_t *table = lookupAVX512(opcode, domain,
9489                                              ReplaceableInstrsAVX512DQMasked)) {
9490         if (domain == 1 || (domain == 3 && table[3] == opcode))
9491           validDomains = 0xa;
9492         else
9493           validDomains = 0xc;
9494       }
9495     }
9496   }
9497   return std::make_pair(domain, validDomains);
9498 }
9499 
9500 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
9501   assert(Domain>0 && Domain<4 && "Invalid execution domain");
9502   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9503   assert(dom && "Not an SSE instruction");
9504   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
9505   if (!table) { // try the other table
9506     assert((Subtarget.hasAVX2() || Domain < 3) &&
9507            "256-bit vector operations only available in AVX2");
9508     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
9509   }
9510   if (!table) { // try the other table
9511     assert(Subtarget.hasAVX2() &&
9512            "256-bit insert/extract only available in AVX2");
9513     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
9514   }
9515   if (!table) { // try the AVX512 table
9516     assert(Subtarget.hasAVX512() && "Requires AVX-512");
9517     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
9518     // Don't change integer Q instructions to D instructions.
9519     if (table && Domain == 3 && table[3] == MI.getOpcode())
9520       Domain = 4;
9521   }
9522   if (!table) { // try the AVX512DQ table
9523     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9524     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
9525     // Don't change integer Q instructions to D instructions and
9526     // use D intructions if we started with a PS instruction.
9527     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9528       Domain = 4;
9529   }
9530   if (!table) { // try the AVX512DQMasked table
9531     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9532     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
9533     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9534       Domain = 4;
9535   }
9536   assert(table && "Cannot change domain");
9537   MI.setDesc(get(table[Domain - 1]));
9538 }
9539 
9540 /// Return the noop instruction to use for a noop.
9541 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
9542   NopInst.setOpcode(X86::NOOP);
9543 }
9544 
9545 bool X86InstrInfo::isHighLatencyDef(int opc) const {
9546   switch (opc) {
9547   default: return false;
9548   case X86::DIVPDrm:
9549   case X86::DIVPDrr:
9550   case X86::DIVPSrm:
9551   case X86::DIVPSrr:
9552   case X86::DIVSDrm:
9553   case X86::DIVSDrm_Int:
9554   case X86::DIVSDrr:
9555   case X86::DIVSDrr_Int:
9556   case X86::DIVSSrm:
9557   case X86::DIVSSrm_Int:
9558   case X86::DIVSSrr:
9559   case X86::DIVSSrr_Int:
9560   case X86::SQRTPDm:
9561   case X86::SQRTPDr:
9562   case X86::SQRTPSm:
9563   case X86::SQRTPSr:
9564   case X86::SQRTSDm:
9565   case X86::SQRTSDm_Int:
9566   case X86::SQRTSDr:
9567   case X86::SQRTSDr_Int:
9568   case X86::SQRTSSm:
9569   case X86::SQRTSSm_Int:
9570   case X86::SQRTSSr:
9571   case X86::SQRTSSr_Int:
9572   // AVX instructions with high latency
9573   case X86::VDIVPDrm:
9574   case X86::VDIVPDrr:
9575   case X86::VDIVPDYrm:
9576   case X86::VDIVPDYrr:
9577   case X86::VDIVPSrm:
9578   case X86::VDIVPSrr:
9579   case X86::VDIVPSYrm:
9580   case X86::VDIVPSYrr:
9581   case X86::VDIVSDrm:
9582   case X86::VDIVSDrm_Int:
9583   case X86::VDIVSDrr:
9584   case X86::VDIVSDrr_Int:
9585   case X86::VDIVSSrm:
9586   case X86::VDIVSSrm_Int:
9587   case X86::VDIVSSrr:
9588   case X86::VDIVSSrr_Int:
9589   case X86::VSQRTPDm:
9590   case X86::VSQRTPDr:
9591   case X86::VSQRTPDYm:
9592   case X86::VSQRTPDYr:
9593   case X86::VSQRTPSm:
9594   case X86::VSQRTPSr:
9595   case X86::VSQRTPSYm:
9596   case X86::VSQRTPSYr:
9597   case X86::VSQRTSDm:
9598   case X86::VSQRTSDm_Int:
9599   case X86::VSQRTSDr:
9600   case X86::VSQRTSDr_Int:
9601   case X86::VSQRTSSm:
9602   case X86::VSQRTSSm_Int:
9603   case X86::VSQRTSSr:
9604   case X86::VSQRTSSr_Int:
9605   // AVX512 instructions with high latency
9606   case X86::VDIVPDZ128rm:
9607   case X86::VDIVPDZ128rmb:
9608   case X86::VDIVPDZ128rmbk:
9609   case X86::VDIVPDZ128rmbkz:
9610   case X86::VDIVPDZ128rmk:
9611   case X86::VDIVPDZ128rmkz:
9612   case X86::VDIVPDZ128rr:
9613   case X86::VDIVPDZ128rrk:
9614   case X86::VDIVPDZ128rrkz:
9615   case X86::VDIVPDZ256rm:
9616   case X86::VDIVPDZ256rmb:
9617   case X86::VDIVPDZ256rmbk:
9618   case X86::VDIVPDZ256rmbkz:
9619   case X86::VDIVPDZ256rmk:
9620   case X86::VDIVPDZ256rmkz:
9621   case X86::VDIVPDZ256rr:
9622   case X86::VDIVPDZ256rrk:
9623   case X86::VDIVPDZ256rrkz:
9624   case X86::VDIVPDZrb:
9625   case X86::VDIVPDZrbk:
9626   case X86::VDIVPDZrbkz:
9627   case X86::VDIVPDZrm:
9628   case X86::VDIVPDZrmb:
9629   case X86::VDIVPDZrmbk:
9630   case X86::VDIVPDZrmbkz:
9631   case X86::VDIVPDZrmk:
9632   case X86::VDIVPDZrmkz:
9633   case X86::VDIVPDZrr:
9634   case X86::VDIVPDZrrk:
9635   case X86::VDIVPDZrrkz:
9636   case X86::VDIVPSZ128rm:
9637   case X86::VDIVPSZ128rmb:
9638   case X86::VDIVPSZ128rmbk:
9639   case X86::VDIVPSZ128rmbkz:
9640   case X86::VDIVPSZ128rmk:
9641   case X86::VDIVPSZ128rmkz:
9642   case X86::VDIVPSZ128rr:
9643   case X86::VDIVPSZ128rrk:
9644   case X86::VDIVPSZ128rrkz:
9645   case X86::VDIVPSZ256rm:
9646   case X86::VDIVPSZ256rmb:
9647   case X86::VDIVPSZ256rmbk:
9648   case X86::VDIVPSZ256rmbkz:
9649   case X86::VDIVPSZ256rmk:
9650   case X86::VDIVPSZ256rmkz:
9651   case X86::VDIVPSZ256rr:
9652   case X86::VDIVPSZ256rrk:
9653   case X86::VDIVPSZ256rrkz:
9654   case X86::VDIVPSZrb:
9655   case X86::VDIVPSZrbk:
9656   case X86::VDIVPSZrbkz:
9657   case X86::VDIVPSZrm:
9658   case X86::VDIVPSZrmb:
9659   case X86::VDIVPSZrmbk:
9660   case X86::VDIVPSZrmbkz:
9661   case X86::VDIVPSZrmk:
9662   case X86::VDIVPSZrmkz:
9663   case X86::VDIVPSZrr:
9664   case X86::VDIVPSZrrk:
9665   case X86::VDIVPSZrrkz:
9666   case X86::VDIVSDZrm:
9667   case X86::VDIVSDZrr:
9668   case X86::VDIVSDZrm_Int:
9669   case X86::VDIVSDZrm_Intk:
9670   case X86::VDIVSDZrm_Intkz:
9671   case X86::VDIVSDZrr_Int:
9672   case X86::VDIVSDZrr_Intk:
9673   case X86::VDIVSDZrr_Intkz:
9674   case X86::VDIVSDZrrb:
9675   case X86::VDIVSDZrrbk:
9676   case X86::VDIVSDZrrbkz:
9677   case X86::VDIVSSZrm:
9678   case X86::VDIVSSZrr:
9679   case X86::VDIVSSZrm_Int:
9680   case X86::VDIVSSZrm_Intk:
9681   case X86::VDIVSSZrm_Intkz:
9682   case X86::VDIVSSZrr_Int:
9683   case X86::VDIVSSZrr_Intk:
9684   case X86::VDIVSSZrr_Intkz:
9685   case X86::VDIVSSZrrb:
9686   case X86::VDIVSSZrrbk:
9687   case X86::VDIVSSZrrbkz:
9688   case X86::VSQRTPDZ128m:
9689   case X86::VSQRTPDZ128mb:
9690   case X86::VSQRTPDZ128mbk:
9691   case X86::VSQRTPDZ128mbkz:
9692   case X86::VSQRTPDZ128mk:
9693   case X86::VSQRTPDZ128mkz:
9694   case X86::VSQRTPDZ128r:
9695   case X86::VSQRTPDZ128rk:
9696   case X86::VSQRTPDZ128rkz:
9697   case X86::VSQRTPDZ256m:
9698   case X86::VSQRTPDZ256mb:
9699   case X86::VSQRTPDZ256mbk:
9700   case X86::VSQRTPDZ256mbkz:
9701   case X86::VSQRTPDZ256mk:
9702   case X86::VSQRTPDZ256mkz:
9703   case X86::VSQRTPDZ256r:
9704   case X86::VSQRTPDZ256rk:
9705   case X86::VSQRTPDZ256rkz:
9706   case X86::VSQRTPDZm:
9707   case X86::VSQRTPDZmb:
9708   case X86::VSQRTPDZmbk:
9709   case X86::VSQRTPDZmbkz:
9710   case X86::VSQRTPDZmk:
9711   case X86::VSQRTPDZmkz:
9712   case X86::VSQRTPDZr:
9713   case X86::VSQRTPDZrb:
9714   case X86::VSQRTPDZrbk:
9715   case X86::VSQRTPDZrbkz:
9716   case X86::VSQRTPDZrk:
9717   case X86::VSQRTPDZrkz:
9718   case X86::VSQRTPSZ128m:
9719   case X86::VSQRTPSZ128mb:
9720   case X86::VSQRTPSZ128mbk:
9721   case X86::VSQRTPSZ128mbkz:
9722   case X86::VSQRTPSZ128mk:
9723   case X86::VSQRTPSZ128mkz:
9724   case X86::VSQRTPSZ128r:
9725   case X86::VSQRTPSZ128rk:
9726   case X86::VSQRTPSZ128rkz:
9727   case X86::VSQRTPSZ256m:
9728   case X86::VSQRTPSZ256mb:
9729   case X86::VSQRTPSZ256mbk:
9730   case X86::VSQRTPSZ256mbkz:
9731   case X86::VSQRTPSZ256mk:
9732   case X86::VSQRTPSZ256mkz:
9733   case X86::VSQRTPSZ256r:
9734   case X86::VSQRTPSZ256rk:
9735   case X86::VSQRTPSZ256rkz:
9736   case X86::VSQRTPSZm:
9737   case X86::VSQRTPSZmb:
9738   case X86::VSQRTPSZmbk:
9739   case X86::VSQRTPSZmbkz:
9740   case X86::VSQRTPSZmk:
9741   case X86::VSQRTPSZmkz:
9742   case X86::VSQRTPSZr:
9743   case X86::VSQRTPSZrb:
9744   case X86::VSQRTPSZrbk:
9745   case X86::VSQRTPSZrbkz:
9746   case X86::VSQRTPSZrk:
9747   case X86::VSQRTPSZrkz:
9748   case X86::VSQRTSDZm:
9749   case X86::VSQRTSDZm_Int:
9750   case X86::VSQRTSDZm_Intk:
9751   case X86::VSQRTSDZm_Intkz:
9752   case X86::VSQRTSDZr:
9753   case X86::VSQRTSDZr_Int:
9754   case X86::VSQRTSDZr_Intk:
9755   case X86::VSQRTSDZr_Intkz:
9756   case X86::VSQRTSDZrb_Int:
9757   case X86::VSQRTSDZrb_Intk:
9758   case X86::VSQRTSDZrb_Intkz:
9759   case X86::VSQRTSSZm:
9760   case X86::VSQRTSSZm_Int:
9761   case X86::VSQRTSSZm_Intk:
9762   case X86::VSQRTSSZm_Intkz:
9763   case X86::VSQRTSSZr:
9764   case X86::VSQRTSSZr_Int:
9765   case X86::VSQRTSSZr_Intk:
9766   case X86::VSQRTSSZr_Intkz:
9767   case X86::VSQRTSSZrb_Int:
9768   case X86::VSQRTSSZrb_Intk:
9769   case X86::VSQRTSSZrb_Intkz:
9770 
9771   case X86::VGATHERDPDYrm:
9772   case X86::VGATHERDPDZ128rm:
9773   case X86::VGATHERDPDZ256rm:
9774   case X86::VGATHERDPDZrm:
9775   case X86::VGATHERDPDrm:
9776   case X86::VGATHERDPSYrm:
9777   case X86::VGATHERDPSZ128rm:
9778   case X86::VGATHERDPSZ256rm:
9779   case X86::VGATHERDPSZrm:
9780   case X86::VGATHERDPSrm:
9781   case X86::VGATHERPF0DPDm:
9782   case X86::VGATHERPF0DPSm:
9783   case X86::VGATHERPF0QPDm:
9784   case X86::VGATHERPF0QPSm:
9785   case X86::VGATHERPF1DPDm:
9786   case X86::VGATHERPF1DPSm:
9787   case X86::VGATHERPF1QPDm:
9788   case X86::VGATHERPF1QPSm:
9789   case X86::VGATHERQPDYrm:
9790   case X86::VGATHERQPDZ128rm:
9791   case X86::VGATHERQPDZ256rm:
9792   case X86::VGATHERQPDZrm:
9793   case X86::VGATHERQPDrm:
9794   case X86::VGATHERQPSYrm:
9795   case X86::VGATHERQPSZ128rm:
9796   case X86::VGATHERQPSZ256rm:
9797   case X86::VGATHERQPSZrm:
9798   case X86::VGATHERQPSrm:
9799   case X86::VPGATHERDDYrm:
9800   case X86::VPGATHERDDZ128rm:
9801   case X86::VPGATHERDDZ256rm:
9802   case X86::VPGATHERDDZrm:
9803   case X86::VPGATHERDDrm:
9804   case X86::VPGATHERDQYrm:
9805   case X86::VPGATHERDQZ128rm:
9806   case X86::VPGATHERDQZ256rm:
9807   case X86::VPGATHERDQZrm:
9808   case X86::VPGATHERDQrm:
9809   case X86::VPGATHERQDYrm:
9810   case X86::VPGATHERQDZ128rm:
9811   case X86::VPGATHERQDZ256rm:
9812   case X86::VPGATHERQDZrm:
9813   case X86::VPGATHERQDrm:
9814   case X86::VPGATHERQQYrm:
9815   case X86::VPGATHERQQZ128rm:
9816   case X86::VPGATHERQQZ256rm:
9817   case X86::VPGATHERQQZrm:
9818   case X86::VPGATHERQQrm:
9819   case X86::VSCATTERDPDZ128mr:
9820   case X86::VSCATTERDPDZ256mr:
9821   case X86::VSCATTERDPDZmr:
9822   case X86::VSCATTERDPSZ128mr:
9823   case X86::VSCATTERDPSZ256mr:
9824   case X86::VSCATTERDPSZmr:
9825   case X86::VSCATTERPF0DPDm:
9826   case X86::VSCATTERPF0DPSm:
9827   case X86::VSCATTERPF0QPDm:
9828   case X86::VSCATTERPF0QPSm:
9829   case X86::VSCATTERPF1DPDm:
9830   case X86::VSCATTERPF1DPSm:
9831   case X86::VSCATTERPF1QPDm:
9832   case X86::VSCATTERPF1QPSm:
9833   case X86::VSCATTERQPDZ128mr:
9834   case X86::VSCATTERQPDZ256mr:
9835   case X86::VSCATTERQPDZmr:
9836   case X86::VSCATTERQPSZ128mr:
9837   case X86::VSCATTERQPSZ256mr:
9838   case X86::VSCATTERQPSZmr:
9839   case X86::VPSCATTERDDZ128mr:
9840   case X86::VPSCATTERDDZ256mr:
9841   case X86::VPSCATTERDDZmr:
9842   case X86::VPSCATTERDQZ128mr:
9843   case X86::VPSCATTERDQZ256mr:
9844   case X86::VPSCATTERDQZmr:
9845   case X86::VPSCATTERQDZ128mr:
9846   case X86::VPSCATTERQDZ256mr:
9847   case X86::VPSCATTERQDZmr:
9848   case X86::VPSCATTERQQZ128mr:
9849   case X86::VPSCATTERQQZ256mr:
9850   case X86::VPSCATTERQQZmr:
9851     return true;
9852   }
9853 }
9854 
9855 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
9856                                          const MachineRegisterInfo *MRI,
9857                                          const MachineInstr &DefMI,
9858                                          unsigned DefIdx,
9859                                          const MachineInstr &UseMI,
9860                                          unsigned UseIdx) const {
9861   return isHighLatencyDef(DefMI.getOpcode());
9862 }
9863 
9864 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
9865                                            const MachineBasicBlock *MBB) const {
9866   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
9867          "Reassociation needs binary operators");
9868 
9869   // Integer binary math/logic instructions have a third source operand:
9870   // the EFLAGS register. That operand must be both defined here and never
9871   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
9872   // not change anything because rearranging the operands could affect other
9873   // instructions that depend on the exact status flags (zero, sign, etc.)
9874   // that are set by using these particular operands with this operation.
9875   if (Inst.getNumOperands() == 4) {
9876     assert(Inst.getOperand(3).isReg() &&
9877            Inst.getOperand(3).getReg() == X86::EFLAGS &&
9878            "Unexpected operand in reassociable instruction");
9879     if (!Inst.getOperand(3).isDead())
9880       return false;
9881   }
9882 
9883   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
9884 }
9885 
9886 // TODO: There are many more machine instruction opcodes to match:
9887 //       1. Other data types (integer, vectors)
9888 //       2. Other math / logic operations (xor, or)
9889 //       3. Other forms of the same operation (intrinsics and other variants)
9890 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
9891   switch (Inst.getOpcode()) {
9892   case X86::AND8rr:
9893   case X86::AND16rr:
9894   case X86::AND32rr:
9895   case X86::AND64rr:
9896   case X86::OR8rr:
9897   case X86::OR16rr:
9898   case X86::OR32rr:
9899   case X86::OR64rr:
9900   case X86::XOR8rr:
9901   case X86::XOR16rr:
9902   case X86::XOR32rr:
9903   case X86::XOR64rr:
9904   case X86::IMUL16rr:
9905   case X86::IMUL32rr:
9906   case X86::IMUL64rr:
9907   case X86::PANDrr:
9908   case X86::PORrr:
9909   case X86::PXORrr:
9910   case X86::ANDPDrr:
9911   case X86::ANDPSrr:
9912   case X86::ORPDrr:
9913   case X86::ORPSrr:
9914   case X86::XORPDrr:
9915   case X86::XORPSrr:
9916   case X86::PADDBrr:
9917   case X86::PADDWrr:
9918   case X86::PADDDrr:
9919   case X86::PADDQrr:
9920   case X86::VPANDrr:
9921   case X86::VPANDYrr:
9922   case X86::VPANDDZ128rr:
9923   case X86::VPANDDZ256rr:
9924   case X86::VPANDDZrr:
9925   case X86::VPANDQZ128rr:
9926   case X86::VPANDQZ256rr:
9927   case X86::VPANDQZrr:
9928   case X86::VPORrr:
9929   case X86::VPORYrr:
9930   case X86::VPORDZ128rr:
9931   case X86::VPORDZ256rr:
9932   case X86::VPORDZrr:
9933   case X86::VPORQZ128rr:
9934   case X86::VPORQZ256rr:
9935   case X86::VPORQZrr:
9936   case X86::VPXORrr:
9937   case X86::VPXORYrr:
9938   case X86::VPXORDZ128rr:
9939   case X86::VPXORDZ256rr:
9940   case X86::VPXORDZrr:
9941   case X86::VPXORQZ128rr:
9942   case X86::VPXORQZ256rr:
9943   case X86::VPXORQZrr:
9944   case X86::VANDPDrr:
9945   case X86::VANDPSrr:
9946   case X86::VANDPDYrr:
9947   case X86::VANDPSYrr:
9948   case X86::VANDPDZ128rr:
9949   case X86::VANDPSZ128rr:
9950   case X86::VANDPDZ256rr:
9951   case X86::VANDPSZ256rr:
9952   case X86::VANDPDZrr:
9953   case X86::VANDPSZrr:
9954   case X86::VORPDrr:
9955   case X86::VORPSrr:
9956   case X86::VORPDYrr:
9957   case X86::VORPSYrr:
9958   case X86::VORPDZ128rr:
9959   case X86::VORPSZ128rr:
9960   case X86::VORPDZ256rr:
9961   case X86::VORPSZ256rr:
9962   case X86::VORPDZrr:
9963   case X86::VORPSZrr:
9964   case X86::VXORPDrr:
9965   case X86::VXORPSrr:
9966   case X86::VXORPDYrr:
9967   case X86::VXORPSYrr:
9968   case X86::VXORPDZ128rr:
9969   case X86::VXORPSZ128rr:
9970   case X86::VXORPDZ256rr:
9971   case X86::VXORPSZ256rr:
9972   case X86::VXORPDZrr:
9973   case X86::VXORPSZrr:
9974   case X86::KADDBrr:
9975   case X86::KADDWrr:
9976   case X86::KADDDrr:
9977   case X86::KADDQrr:
9978   case X86::KANDBrr:
9979   case X86::KANDWrr:
9980   case X86::KANDDrr:
9981   case X86::KANDQrr:
9982   case X86::KORBrr:
9983   case X86::KORWrr:
9984   case X86::KORDrr:
9985   case X86::KORQrr:
9986   case X86::KXORBrr:
9987   case X86::KXORWrr:
9988   case X86::KXORDrr:
9989   case X86::KXORQrr:
9990   case X86::VPADDBrr:
9991   case X86::VPADDWrr:
9992   case X86::VPADDDrr:
9993   case X86::VPADDQrr:
9994   case X86::VPADDBYrr:
9995   case X86::VPADDWYrr:
9996   case X86::VPADDDYrr:
9997   case X86::VPADDQYrr:
9998   case X86::VPADDBZ128rr:
9999   case X86::VPADDWZ128rr:
10000   case X86::VPADDDZ128rr:
10001   case X86::VPADDQZ128rr:
10002   case X86::VPADDBZ256rr:
10003   case X86::VPADDWZ256rr:
10004   case X86::VPADDDZ256rr:
10005   case X86::VPADDQZ256rr:
10006   case X86::VPADDBZrr:
10007   case X86::VPADDWZrr:
10008   case X86::VPADDDZrr:
10009   case X86::VPADDQZrr:
10010   case X86::VPMULLWrr:
10011   case X86::VPMULLWYrr:
10012   case X86::VPMULLWZ128rr:
10013   case X86::VPMULLWZ256rr:
10014   case X86::VPMULLWZrr:
10015   case X86::VPMULLDrr:
10016   case X86::VPMULLDYrr:
10017   case X86::VPMULLDZ128rr:
10018   case X86::VPMULLDZ256rr:
10019   case X86::VPMULLDZrr:
10020   case X86::VPMULLQZ128rr:
10021   case X86::VPMULLQZ256rr:
10022   case X86::VPMULLQZrr:
10023   // Normal min/max instructions are not commutative because of NaN and signed
10024   // zero semantics, but these are. Thus, there's no need to check for global
10025   // relaxed math; the instructions themselves have the properties we need.
10026   case X86::MAXCPDrr:
10027   case X86::MAXCPSrr:
10028   case X86::MAXCSDrr:
10029   case X86::MAXCSSrr:
10030   case X86::MINCPDrr:
10031   case X86::MINCPSrr:
10032   case X86::MINCSDrr:
10033   case X86::MINCSSrr:
10034   case X86::VMAXCPDrr:
10035   case X86::VMAXCPSrr:
10036   case X86::VMAXCPDYrr:
10037   case X86::VMAXCPSYrr:
10038   case X86::VMAXCPDZ128rr:
10039   case X86::VMAXCPSZ128rr:
10040   case X86::VMAXCPDZ256rr:
10041   case X86::VMAXCPSZ256rr:
10042   case X86::VMAXCPDZrr:
10043   case X86::VMAXCPSZrr:
10044   case X86::VMAXCSDrr:
10045   case X86::VMAXCSSrr:
10046   case X86::VMAXCSDZrr:
10047   case X86::VMAXCSSZrr:
10048   case X86::VMINCPDrr:
10049   case X86::VMINCPSrr:
10050   case X86::VMINCPDYrr:
10051   case X86::VMINCPSYrr:
10052   case X86::VMINCPDZ128rr:
10053   case X86::VMINCPSZ128rr:
10054   case X86::VMINCPDZ256rr:
10055   case X86::VMINCPSZ256rr:
10056   case X86::VMINCPDZrr:
10057   case X86::VMINCPSZrr:
10058   case X86::VMINCSDrr:
10059   case X86::VMINCSSrr:
10060   case X86::VMINCSDZrr:
10061   case X86::VMINCSSZrr:
10062     return true;
10063   case X86::ADDPDrr:
10064   case X86::ADDPSrr:
10065   case X86::ADDSDrr:
10066   case X86::ADDSSrr:
10067   case X86::MULPDrr:
10068   case X86::MULPSrr:
10069   case X86::MULSDrr:
10070   case X86::MULSSrr:
10071   case X86::VADDPDrr:
10072   case X86::VADDPSrr:
10073   case X86::VADDPDYrr:
10074   case X86::VADDPSYrr:
10075   case X86::VADDPDZ128rr:
10076   case X86::VADDPSZ128rr:
10077   case X86::VADDPDZ256rr:
10078   case X86::VADDPSZ256rr:
10079   case X86::VADDPDZrr:
10080   case X86::VADDPSZrr:
10081   case X86::VADDSDrr:
10082   case X86::VADDSSrr:
10083   case X86::VADDSDZrr:
10084   case X86::VADDSSZrr:
10085   case X86::VMULPDrr:
10086   case X86::VMULPSrr:
10087   case X86::VMULPDYrr:
10088   case X86::VMULPSYrr:
10089   case X86::VMULPDZ128rr:
10090   case X86::VMULPSZ128rr:
10091   case X86::VMULPDZ256rr:
10092   case X86::VMULPSZ256rr:
10093   case X86::VMULPDZrr:
10094   case X86::VMULPSZrr:
10095   case X86::VMULSDrr:
10096   case X86::VMULSSrr:
10097   case X86::VMULSDZrr:
10098   case X86::VMULSSZrr:
10099     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
10100   default:
10101     return false;
10102   }
10103 }
10104 
10105 /// This is an architecture-specific helper function of reassociateOps.
10106 /// Set special operand attributes for new instructions after reassociation.
10107 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
10108                                          MachineInstr &OldMI2,
10109                                          MachineInstr &NewMI1,
10110                                          MachineInstr &NewMI2) const {
10111   // Integer instructions define an implicit EFLAGS source register operand as
10112   // the third source (fourth total) operand.
10113   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
10114     return;
10115 
10116   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
10117          "Unexpected instruction type for reassociation");
10118 
10119   MachineOperand &OldOp1 = OldMI1.getOperand(3);
10120   MachineOperand &OldOp2 = OldMI2.getOperand(3);
10121   MachineOperand &NewOp1 = NewMI1.getOperand(3);
10122   MachineOperand &NewOp2 = NewMI2.getOperand(3);
10123 
10124   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
10125          "Must have dead EFLAGS operand in reassociable instruction");
10126   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
10127          "Must have dead EFLAGS operand in reassociable instruction");
10128 
10129   (void)OldOp1;
10130   (void)OldOp2;
10131 
10132   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
10133          "Unexpected operand in reassociable instruction");
10134   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
10135          "Unexpected operand in reassociable instruction");
10136 
10137   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10138   // of this pass or other passes. The EFLAGS operands must be dead in these new
10139   // instructions because the EFLAGS operands in the original instructions must
10140   // be dead in order for reassociation to occur.
10141   NewOp1.setIsDead();
10142   NewOp2.setIsDead();
10143 }
10144 
10145 std::pair<unsigned, unsigned>
10146 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10147   return std::make_pair(TF, 0u);
10148 }
10149 
10150 ArrayRef<std::pair<unsigned, const char *>>
10151 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10152   using namespace X86II;
10153   static const std::pair<unsigned, const char *> TargetFlags[] = {
10154       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10155       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10156       {MO_GOT, "x86-got"},
10157       {MO_GOTOFF, "x86-gotoff"},
10158       {MO_GOTPCREL, "x86-gotpcrel"},
10159       {MO_PLT, "x86-plt"},
10160       {MO_TLSGD, "x86-tlsgd"},
10161       {MO_TLSLD, "x86-tlsld"},
10162       {MO_TLSLDM, "x86-tlsldm"},
10163       {MO_GOTTPOFF, "x86-gottpoff"},
10164       {MO_INDNTPOFF, "x86-indntpoff"},
10165       {MO_TPOFF, "x86-tpoff"},
10166       {MO_DTPOFF, "x86-dtpoff"},
10167       {MO_NTPOFF, "x86-ntpoff"},
10168       {MO_GOTNTPOFF, "x86-gotntpoff"},
10169       {MO_DLLIMPORT, "x86-dllimport"},
10170       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10171       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10172       {MO_TLVP, "x86-tlvp"},
10173       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10174       {MO_SECREL, "x86-secrel"}};
10175   return makeArrayRef(TargetFlags);
10176 }
10177 
10178 bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
10179   switch (Inst.getOpcode()) {
10180     case X86::TCRETURNdi:
10181     case X86::TCRETURNmi:
10182     case X86::TCRETURNri:
10183     case X86::TCRETURNdi64:
10184     case X86::TCRETURNmi64:
10185     case X86::TCRETURNri64:
10186     case X86::TAILJMPd:
10187     case X86::TAILJMPm:
10188     case X86::TAILJMPr:
10189     case X86::TAILJMPd64:
10190     case X86::TAILJMPm64:
10191     case X86::TAILJMPr64:
10192     case X86::TAILJMPm64_REX:
10193     case X86::TAILJMPr64_REX:
10194       return true;
10195     default:
10196       return false;
10197   }
10198 }
10199 
10200 namespace {
10201   /// Create Global Base Reg pass. This initializes the PIC
10202   /// global base register for x86-32.
10203   struct CGBR : public MachineFunctionPass {
10204     static char ID;
10205     CGBR() : MachineFunctionPass(ID) {}
10206 
10207     bool runOnMachineFunction(MachineFunction &MF) override {
10208       const X86TargetMachine *TM =
10209         static_cast<const X86TargetMachine *>(&MF.getTarget());
10210       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
10211 
10212       // Don't do anything if this is 64-bit as 64-bit PIC
10213       // uses RIP relative addressing.
10214       if (STI.is64Bit())
10215         return false;
10216 
10217       // Only emit a global base reg in PIC mode.
10218       if (!TM->isPositionIndependent())
10219         return false;
10220 
10221       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10222       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
10223 
10224       // If we didn't need a GlobalBaseReg, don't insert code.
10225       if (GlobalBaseReg == 0)
10226         return false;
10227 
10228       // Insert the set of GlobalBaseReg into the first MBB of the function
10229       MachineBasicBlock &FirstMBB = MF.front();
10230       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
10231       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
10232       MachineRegisterInfo &RegInfo = MF.getRegInfo();
10233       const X86InstrInfo *TII = STI.getInstrInfo();
10234 
10235       unsigned PC;
10236       if (STI.isPICStyleGOT())
10237         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
10238       else
10239         PC = GlobalBaseReg;
10240 
10241       // Operand of MovePCtoStack is completely ignored by asm printer. It's
10242       // only used in JIT code emission as displacement to pc.
10243       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
10244 
10245       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
10246       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
10247       if (STI.isPICStyleGOT()) {
10248         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
10249         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
10250           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
10251                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
10252       }
10253 
10254       return true;
10255     }
10256 
10257     StringRef getPassName() const override {
10258       return "X86 PIC Global Base Reg Initialization";
10259     }
10260 
10261     void getAnalysisUsage(AnalysisUsage &AU) const override {
10262       AU.setPreservesCFG();
10263       MachineFunctionPass::getAnalysisUsage(AU);
10264     }
10265   };
10266 }
10267 
10268 char CGBR::ID = 0;
10269 FunctionPass*
10270 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
10271 
10272 namespace {
10273   struct LDTLSCleanup : public MachineFunctionPass {
10274     static char ID;
10275     LDTLSCleanup() : MachineFunctionPass(ID) {}
10276 
10277     bool runOnMachineFunction(MachineFunction &MF) override {
10278       if (skipFunction(*MF.getFunction()))
10279         return false;
10280 
10281       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
10282       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
10283         // No point folding accesses if there isn't at least two.
10284         return false;
10285       }
10286 
10287       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
10288       return VisitNode(DT->getRootNode(), 0);
10289     }
10290 
10291     // Visit the dominator subtree rooted at Node in pre-order.
10292     // If TLSBaseAddrReg is non-null, then use that to replace any
10293     // TLS_base_addr instructions. Otherwise, create the register
10294     // when the first such instruction is seen, and then use it
10295     // as we encounter more instructions.
10296     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
10297       MachineBasicBlock *BB = Node->getBlock();
10298       bool Changed = false;
10299 
10300       // Traverse the current block.
10301       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
10302            ++I) {
10303         switch (I->getOpcode()) {
10304           case X86::TLS_base_addr32:
10305           case X86::TLS_base_addr64:
10306             if (TLSBaseAddrReg)
10307               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
10308             else
10309               I = SetRegister(*I, &TLSBaseAddrReg);
10310             Changed = true;
10311             break;
10312           default:
10313             break;
10314         }
10315       }
10316 
10317       // Visit the children of this block in the dominator tree.
10318       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
10319            I != E; ++I) {
10320         Changed |= VisitNode(*I, TLSBaseAddrReg);
10321       }
10322 
10323       return Changed;
10324     }
10325 
10326     // Replace the TLS_base_addr instruction I with a copy from
10327     // TLSBaseAddrReg, returning the new instruction.
10328     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
10329                                          unsigned TLSBaseAddrReg) {
10330       MachineFunction *MF = I.getParent()->getParent();
10331       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
10332       const bool is64Bit = STI.is64Bit();
10333       const X86InstrInfo *TII = STI.getInstrInfo();
10334 
10335       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
10336       MachineInstr *Copy =
10337           BuildMI(*I.getParent(), I, I.getDebugLoc(),
10338                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
10339               .addReg(TLSBaseAddrReg);
10340 
10341       // Erase the TLS_base_addr instruction.
10342       I.eraseFromParent();
10343 
10344       return Copy;
10345     }
10346 
10347     // Create a virtal register in *TLSBaseAddrReg, and populate it by
10348     // inserting a copy instruction after I. Returns the new instruction.
10349     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
10350       MachineFunction *MF = I.getParent()->getParent();
10351       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
10352       const bool is64Bit = STI.is64Bit();
10353       const X86InstrInfo *TII = STI.getInstrInfo();
10354 
10355       // Create a virtual register for the TLS base address.
10356       MachineRegisterInfo &RegInfo = MF->getRegInfo();
10357       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
10358                                                       ? &X86::GR64RegClass
10359                                                       : &X86::GR32RegClass);
10360 
10361       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
10362       MachineInstr *Next = I.getNextNode();
10363       MachineInstr *Copy =
10364           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
10365                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
10366               .addReg(is64Bit ? X86::RAX : X86::EAX);
10367 
10368       return Copy;
10369     }
10370 
10371     StringRef getPassName() const override {
10372       return "Local Dynamic TLS Access Clean-up";
10373     }
10374 
10375     void getAnalysisUsage(AnalysisUsage &AU) const override {
10376       AU.setPreservesCFG();
10377       AU.addRequired<MachineDominatorTree>();
10378       MachineFunctionPass::getAnalysisUsage(AU);
10379     }
10380   };
10381 }
10382 
10383 char LDTLSCleanup::ID = 0;
10384 FunctionPass*
10385 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
10386