1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/DebugInfoMetadata.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     Register &SrcReg, Register &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139   switch (MI.getOpcode()) {
140   default:
141     // By default, assume that the instruction is not data invariant.
142     return false;
143 
144     // Some target-independent operations that trivially lower to data-invariant
145     // instructions.
146   case TargetOpcode::COPY:
147   case TargetOpcode::INSERT_SUBREG:
148   case TargetOpcode::SUBREG_TO_REG:
149     return true;
150 
151   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152   // However, they set flags and are perhaps the most surprisingly constant
153   // time operations so we call them out here separately.
154   case X86::IMUL16rr:
155   case X86::IMUL16rri8:
156   case X86::IMUL16rri:
157   case X86::IMUL32rr:
158   case X86::IMUL32rri8:
159   case X86::IMUL32rri:
160   case X86::IMUL64rr:
161   case X86::IMUL64rri32:
162   case X86::IMUL64rri8:
163 
164   // Bit scanning and counting instructions that are somewhat surprisingly
165   // constant time as they scan across bits and do other fairly complex
166   // operations like popcnt, but are believed to be constant time on x86.
167   // However, these set flags.
168   case X86::BSF16rr:
169   case X86::BSF32rr:
170   case X86::BSF64rr:
171   case X86::BSR16rr:
172   case X86::BSR32rr:
173   case X86::BSR64rr:
174   case X86::LZCNT16rr:
175   case X86::LZCNT32rr:
176   case X86::LZCNT64rr:
177   case X86::POPCNT16rr:
178   case X86::POPCNT32rr:
179   case X86::POPCNT64rr:
180   case X86::TZCNT16rr:
181   case X86::TZCNT32rr:
182   case X86::TZCNT64rr:
183 
184   // Bit manipulation instructions are effectively combinations of basic
185   // arithmetic ops, and should still execute in constant time. These also
186   // set flags.
187   case X86::BLCFILL32rr:
188   case X86::BLCFILL64rr:
189   case X86::BLCI32rr:
190   case X86::BLCI64rr:
191   case X86::BLCIC32rr:
192   case X86::BLCIC64rr:
193   case X86::BLCMSK32rr:
194   case X86::BLCMSK64rr:
195   case X86::BLCS32rr:
196   case X86::BLCS64rr:
197   case X86::BLSFILL32rr:
198   case X86::BLSFILL64rr:
199   case X86::BLSI32rr:
200   case X86::BLSI64rr:
201   case X86::BLSIC32rr:
202   case X86::BLSIC64rr:
203   case X86::BLSMSK32rr:
204   case X86::BLSMSK64rr:
205   case X86::BLSR32rr:
206   case X86::BLSR64rr:
207   case X86::TZMSK32rr:
208   case X86::TZMSK64rr:
209 
210   // Bit extracting and clearing instructions should execute in constant time,
211   // and set flags.
212   case X86::BEXTR32rr:
213   case X86::BEXTR64rr:
214   case X86::BEXTRI32ri:
215   case X86::BEXTRI64ri:
216   case X86::BZHI32rr:
217   case X86::BZHI64rr:
218 
219   // Shift and rotate.
220   case X86::ROL8r1:
221   case X86::ROL16r1:
222   case X86::ROL32r1:
223   case X86::ROL64r1:
224   case X86::ROL8rCL:
225   case X86::ROL16rCL:
226   case X86::ROL32rCL:
227   case X86::ROL64rCL:
228   case X86::ROL8ri:
229   case X86::ROL16ri:
230   case X86::ROL32ri:
231   case X86::ROL64ri:
232   case X86::ROR8r1:
233   case X86::ROR16r1:
234   case X86::ROR32r1:
235   case X86::ROR64r1:
236   case X86::ROR8rCL:
237   case X86::ROR16rCL:
238   case X86::ROR32rCL:
239   case X86::ROR64rCL:
240   case X86::ROR8ri:
241   case X86::ROR16ri:
242   case X86::ROR32ri:
243   case X86::ROR64ri:
244   case X86::SAR8r1:
245   case X86::SAR16r1:
246   case X86::SAR32r1:
247   case X86::SAR64r1:
248   case X86::SAR8rCL:
249   case X86::SAR16rCL:
250   case X86::SAR32rCL:
251   case X86::SAR64rCL:
252   case X86::SAR8ri:
253   case X86::SAR16ri:
254   case X86::SAR32ri:
255   case X86::SAR64ri:
256   case X86::SHL8r1:
257   case X86::SHL16r1:
258   case X86::SHL32r1:
259   case X86::SHL64r1:
260   case X86::SHL8rCL:
261   case X86::SHL16rCL:
262   case X86::SHL32rCL:
263   case X86::SHL64rCL:
264   case X86::SHL8ri:
265   case X86::SHL16ri:
266   case X86::SHL32ri:
267   case X86::SHL64ri:
268   case X86::SHR8r1:
269   case X86::SHR16r1:
270   case X86::SHR32r1:
271   case X86::SHR64r1:
272   case X86::SHR8rCL:
273   case X86::SHR16rCL:
274   case X86::SHR32rCL:
275   case X86::SHR64rCL:
276   case X86::SHR8ri:
277   case X86::SHR16ri:
278   case X86::SHR32ri:
279   case X86::SHR64ri:
280   case X86::SHLD16rrCL:
281   case X86::SHLD32rrCL:
282   case X86::SHLD64rrCL:
283   case X86::SHLD16rri8:
284   case X86::SHLD32rri8:
285   case X86::SHLD64rri8:
286   case X86::SHRD16rrCL:
287   case X86::SHRD32rrCL:
288   case X86::SHRD64rrCL:
289   case X86::SHRD16rri8:
290   case X86::SHRD32rri8:
291   case X86::SHRD64rri8:
292 
293   // Basic arithmetic is constant time on the input but does set flags.
294   case X86::ADC8rr:
295   case X86::ADC8ri:
296   case X86::ADC16rr:
297   case X86::ADC16ri:
298   case X86::ADC16ri8:
299   case X86::ADC32rr:
300   case X86::ADC32ri:
301   case X86::ADC32ri8:
302   case X86::ADC64rr:
303   case X86::ADC64ri8:
304   case X86::ADC64ri32:
305   case X86::ADD8rr:
306   case X86::ADD8ri:
307   case X86::ADD16rr:
308   case X86::ADD16ri:
309   case X86::ADD16ri8:
310   case X86::ADD32rr:
311   case X86::ADD32ri:
312   case X86::ADD32ri8:
313   case X86::ADD64rr:
314   case X86::ADD64ri8:
315   case X86::ADD64ri32:
316   case X86::AND8rr:
317   case X86::AND8ri:
318   case X86::AND16rr:
319   case X86::AND16ri:
320   case X86::AND16ri8:
321   case X86::AND32rr:
322   case X86::AND32ri:
323   case X86::AND32ri8:
324   case X86::AND64rr:
325   case X86::AND64ri8:
326   case X86::AND64ri32:
327   case X86::OR8rr:
328   case X86::OR8ri:
329   case X86::OR16rr:
330   case X86::OR16ri:
331   case X86::OR16ri8:
332   case X86::OR32rr:
333   case X86::OR32ri:
334   case X86::OR32ri8:
335   case X86::OR64rr:
336   case X86::OR64ri8:
337   case X86::OR64ri32:
338   case X86::SBB8rr:
339   case X86::SBB8ri:
340   case X86::SBB16rr:
341   case X86::SBB16ri:
342   case X86::SBB16ri8:
343   case X86::SBB32rr:
344   case X86::SBB32ri:
345   case X86::SBB32ri8:
346   case X86::SBB64rr:
347   case X86::SBB64ri8:
348   case X86::SBB64ri32:
349   case X86::SUB8rr:
350   case X86::SUB8ri:
351   case X86::SUB16rr:
352   case X86::SUB16ri:
353   case X86::SUB16ri8:
354   case X86::SUB32rr:
355   case X86::SUB32ri:
356   case X86::SUB32ri8:
357   case X86::SUB64rr:
358   case X86::SUB64ri8:
359   case X86::SUB64ri32:
360   case X86::XOR8rr:
361   case X86::XOR8ri:
362   case X86::XOR16rr:
363   case X86::XOR16ri:
364   case X86::XOR16ri8:
365   case X86::XOR32rr:
366   case X86::XOR32ri:
367   case X86::XOR32ri8:
368   case X86::XOR64rr:
369   case X86::XOR64ri8:
370   case X86::XOR64ri32:
371   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372   case X86::ADCX32rr:
373   case X86::ADCX64rr:
374   case X86::ADOX32rr:
375   case X86::ADOX64rr:
376   case X86::ANDN32rr:
377   case X86::ANDN64rr:
378   // Unary arithmetic operations.
379   case X86::DEC8r:
380   case X86::DEC16r:
381   case X86::DEC32r:
382   case X86::DEC64r:
383   case X86::INC8r:
384   case X86::INC16r:
385   case X86::INC32r:
386   case X86::INC64r:
387   case X86::NEG8r:
388   case X86::NEG16r:
389   case X86::NEG32r:
390   case X86::NEG64r:
391 
392   // Unlike other arithmetic, NOT doesn't set EFLAGS.
393   case X86::NOT8r:
394   case X86::NOT16r:
395   case X86::NOT32r:
396   case X86::NOT64r:
397 
398   // Various move instructions used to zero or sign extend things. Note that we
399   // intentionally don't support the _NOREX variants as we can't handle that
400   // register constraint anyways.
401   case X86::MOVSX16rr8:
402   case X86::MOVSX32rr8:
403   case X86::MOVSX32rr16:
404   case X86::MOVSX64rr8:
405   case X86::MOVSX64rr16:
406   case X86::MOVSX64rr32:
407   case X86::MOVZX16rr8:
408   case X86::MOVZX32rr8:
409   case X86::MOVZX32rr16:
410   case X86::MOVZX64rr8:
411   case X86::MOVZX64rr16:
412   case X86::MOV32rr:
413 
414   // Arithmetic instructions that are both constant time and don't set flags.
415   case X86::RORX32ri:
416   case X86::RORX64ri:
417   case X86::SARX32rr:
418   case X86::SARX64rr:
419   case X86::SHLX32rr:
420   case X86::SHLX64rr:
421   case X86::SHRX32rr:
422   case X86::SHRX64rr:
423 
424   // LEA doesn't actually access memory, and its arithmetic is constant time.
425   case X86::LEA16r:
426   case X86::LEA32r:
427   case X86::LEA64_32r:
428   case X86::LEA64r:
429     return true;
430   }
431 }
432 
433 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434   switch (MI.getOpcode()) {
435   default:
436     // By default, assume that the load will immediately leak.
437     return false;
438 
439   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440   // However, they set flags and are perhaps the most surprisingly constant
441   // time operations so we call them out here separately.
442   case X86::IMUL16rm:
443   case X86::IMUL16rmi8:
444   case X86::IMUL16rmi:
445   case X86::IMUL32rm:
446   case X86::IMUL32rmi8:
447   case X86::IMUL32rmi:
448   case X86::IMUL64rm:
449   case X86::IMUL64rmi32:
450   case X86::IMUL64rmi8:
451 
452   // Bit scanning and counting instructions that are somewhat surprisingly
453   // constant time as they scan across bits and do other fairly complex
454   // operations like popcnt, but are believed to be constant time on x86.
455   // However, these set flags.
456   case X86::BSF16rm:
457   case X86::BSF32rm:
458   case X86::BSF64rm:
459   case X86::BSR16rm:
460   case X86::BSR32rm:
461   case X86::BSR64rm:
462   case X86::LZCNT16rm:
463   case X86::LZCNT32rm:
464   case X86::LZCNT64rm:
465   case X86::POPCNT16rm:
466   case X86::POPCNT32rm:
467   case X86::POPCNT64rm:
468   case X86::TZCNT16rm:
469   case X86::TZCNT32rm:
470   case X86::TZCNT64rm:
471 
472   // Bit manipulation instructions are effectively combinations of basic
473   // arithmetic ops, and should still execute in constant time. These also
474   // set flags.
475   case X86::BLCFILL32rm:
476   case X86::BLCFILL64rm:
477   case X86::BLCI32rm:
478   case X86::BLCI64rm:
479   case X86::BLCIC32rm:
480   case X86::BLCIC64rm:
481   case X86::BLCMSK32rm:
482   case X86::BLCMSK64rm:
483   case X86::BLCS32rm:
484   case X86::BLCS64rm:
485   case X86::BLSFILL32rm:
486   case X86::BLSFILL64rm:
487   case X86::BLSI32rm:
488   case X86::BLSI64rm:
489   case X86::BLSIC32rm:
490   case X86::BLSIC64rm:
491   case X86::BLSMSK32rm:
492   case X86::BLSMSK64rm:
493   case X86::BLSR32rm:
494   case X86::BLSR64rm:
495   case X86::TZMSK32rm:
496   case X86::TZMSK64rm:
497 
498   // Bit extracting and clearing instructions should execute in constant time,
499   // and set flags.
500   case X86::BEXTR32rm:
501   case X86::BEXTR64rm:
502   case X86::BEXTRI32mi:
503   case X86::BEXTRI64mi:
504   case X86::BZHI32rm:
505   case X86::BZHI64rm:
506 
507   // Basic arithmetic is constant time on the input but does set flags.
508   case X86::ADC8rm:
509   case X86::ADC16rm:
510   case X86::ADC32rm:
511   case X86::ADC64rm:
512   case X86::ADCX32rm:
513   case X86::ADCX64rm:
514   case X86::ADD8rm:
515   case X86::ADD16rm:
516   case X86::ADD32rm:
517   case X86::ADD64rm:
518   case X86::ADOX32rm:
519   case X86::ADOX64rm:
520   case X86::AND8rm:
521   case X86::AND16rm:
522   case X86::AND32rm:
523   case X86::AND64rm:
524   case X86::ANDN32rm:
525   case X86::ANDN64rm:
526   case X86::OR8rm:
527   case X86::OR16rm:
528   case X86::OR32rm:
529   case X86::OR64rm:
530   case X86::SBB8rm:
531   case X86::SBB16rm:
532   case X86::SBB32rm:
533   case X86::SBB64rm:
534   case X86::SUB8rm:
535   case X86::SUB16rm:
536   case X86::SUB32rm:
537   case X86::SUB64rm:
538   case X86::XOR8rm:
539   case X86::XOR16rm:
540   case X86::XOR32rm:
541   case X86::XOR64rm:
542 
543   // Integer multiply w/o affecting flags is still believed to be constant
544   // time on x86. Called out separately as this is among the most surprising
545   // instructions to exhibit that behavior.
546   case X86::MULX32rm:
547   case X86::MULX64rm:
548 
549   // Arithmetic instructions that are both constant time and don't set flags.
550   case X86::RORX32mi:
551   case X86::RORX64mi:
552   case X86::SARX32rm:
553   case X86::SARX64rm:
554   case X86::SHLX32rm:
555   case X86::SHLX64rm:
556   case X86::SHRX32rm:
557   case X86::SHRX64rm:
558 
559   // Conversions are believed to be constant time and don't set flags.
560   case X86::CVTTSD2SI64rm:
561   case X86::VCVTTSD2SI64rm:
562   case X86::VCVTTSD2SI64Zrm:
563   case X86::CVTTSD2SIrm:
564   case X86::VCVTTSD2SIrm:
565   case X86::VCVTTSD2SIZrm:
566   case X86::CVTTSS2SI64rm:
567   case X86::VCVTTSS2SI64rm:
568   case X86::VCVTTSS2SI64Zrm:
569   case X86::CVTTSS2SIrm:
570   case X86::VCVTTSS2SIrm:
571   case X86::VCVTTSS2SIZrm:
572   case X86::CVTSI2SDrm:
573   case X86::VCVTSI2SDrm:
574   case X86::VCVTSI2SDZrm:
575   case X86::CVTSI2SSrm:
576   case X86::VCVTSI2SSrm:
577   case X86::VCVTSI2SSZrm:
578   case X86::CVTSI642SDrm:
579   case X86::VCVTSI642SDrm:
580   case X86::VCVTSI642SDZrm:
581   case X86::CVTSI642SSrm:
582   case X86::VCVTSI642SSrm:
583   case X86::VCVTSI642SSZrm:
584   case X86::CVTSS2SDrm:
585   case X86::VCVTSS2SDrm:
586   case X86::VCVTSS2SDZrm:
587   case X86::CVTSD2SSrm:
588   case X86::VCVTSD2SSrm:
589   case X86::VCVTSD2SSZrm:
590   // AVX512 added unsigned integer conversions.
591   case X86::VCVTTSD2USI64Zrm:
592   case X86::VCVTTSD2USIZrm:
593   case X86::VCVTTSS2USI64Zrm:
594   case X86::VCVTTSS2USIZrm:
595   case X86::VCVTUSI2SDZrm:
596   case X86::VCVTUSI642SDZrm:
597   case X86::VCVTUSI2SSZrm:
598   case X86::VCVTUSI642SSZrm:
599 
600   // Loads to register don't set flags.
601   case X86::MOV8rm:
602   case X86::MOV8rm_NOREX:
603   case X86::MOV16rm:
604   case X86::MOV32rm:
605   case X86::MOV64rm:
606   case X86::MOVSX16rm8:
607   case X86::MOVSX32rm16:
608   case X86::MOVSX32rm8:
609   case X86::MOVSX32rm8_NOREX:
610   case X86::MOVSX64rm16:
611   case X86::MOVSX64rm32:
612   case X86::MOVSX64rm8:
613   case X86::MOVZX16rm8:
614   case X86::MOVZX32rm16:
615   case X86::MOVZX32rm8:
616   case X86::MOVZX32rm8_NOREX:
617   case X86::MOVZX64rm16:
618   case X86::MOVZX64rm8:
619     return true;
620   }
621 }
622 
623 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624   const MachineFunction *MF = MI.getParent()->getParent();
625   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626 
627   if (isFrameInstr(MI)) {
628     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629     SPAdj -= getFrameAdjustment(MI);
630     if (!isFrameSetup(MI))
631       SPAdj = -SPAdj;
632     return SPAdj;
633   }
634 
635   // To know whether a call adjusts the stack, we need information
636   // that is bound to the following ADJCALLSTACKUP pseudo.
637   // Look for the next ADJCALLSTACKUP that follows the call.
638   if (MI.isCall()) {
639     const MachineBasicBlock *MBB = MI.getParent();
640     auto I = ++MachineBasicBlock::const_iterator(MI);
641     for (auto E = MBB->end(); I != E; ++I) {
642       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643           I->isCall())
644         break;
645     }
646 
647     // If we could not find a frame destroy opcode, then it has already
648     // been simplified, so we don't care.
649     if (I->getOpcode() != getCallFrameDestroyOpcode())
650       return 0;
651 
652     return -(I->getOperand(1).getImm());
653   }
654 
655   // Currently handle only PUSHes we can reasonably expect to see
656   // in call sequences
657   switch (MI.getOpcode()) {
658   default:
659     return 0;
660   case X86::PUSH32i8:
661   case X86::PUSH32r:
662   case X86::PUSH32rmm:
663   case X86::PUSH32rmr:
664   case X86::PUSHi32:
665     return 4;
666   case X86::PUSH64i8:
667   case X86::PUSH64r:
668   case X86::PUSH64rmm:
669   case X86::PUSH64rmr:
670   case X86::PUSH64i32:
671     return 8;
672   }
673 }
674 
675 /// Return true and the FrameIndex if the specified
676 /// operand and follow operands form a reference to the stack frame.
677 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678                                   int &FrameIndex) const {
679   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682       MI.getOperand(Op + X86::AddrDisp).isImm() &&
683       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687     return true;
688   }
689   return false;
690 }
691 
692 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693   switch (Opcode) {
694   default:
695     return false;
696   case X86::MOV8rm:
697   case X86::KMOVBkm:
698     MemBytes = 1;
699     return true;
700   case X86::MOV16rm:
701   case X86::KMOVWkm:
702     MemBytes = 2;
703     return true;
704   case X86::MOV32rm:
705   case X86::MOVSSrm:
706   case X86::MOVSSrm_alt:
707   case X86::VMOVSSrm:
708   case X86::VMOVSSrm_alt:
709   case X86::VMOVSSZrm:
710   case X86::VMOVSSZrm_alt:
711   case X86::KMOVDkm:
712     MemBytes = 4;
713     return true;
714   case X86::MOV64rm:
715   case X86::LD_Fp64m:
716   case X86::MOVSDrm:
717   case X86::MOVSDrm_alt:
718   case X86::VMOVSDrm:
719   case X86::VMOVSDrm_alt:
720   case X86::VMOVSDZrm:
721   case X86::VMOVSDZrm_alt:
722   case X86::MMX_MOVD64rm:
723   case X86::MMX_MOVQ64rm:
724   case X86::KMOVQkm:
725     MemBytes = 8;
726     return true;
727   case X86::MOVAPSrm:
728   case X86::MOVUPSrm:
729   case X86::MOVAPDrm:
730   case X86::MOVUPDrm:
731   case X86::MOVDQArm:
732   case X86::MOVDQUrm:
733   case X86::VMOVAPSrm:
734   case X86::VMOVUPSrm:
735   case X86::VMOVAPDrm:
736   case X86::VMOVUPDrm:
737   case X86::VMOVDQArm:
738   case X86::VMOVDQUrm:
739   case X86::VMOVAPSZ128rm:
740   case X86::VMOVUPSZ128rm:
741   case X86::VMOVAPSZ128rm_NOVLX:
742   case X86::VMOVUPSZ128rm_NOVLX:
743   case X86::VMOVAPDZ128rm:
744   case X86::VMOVUPDZ128rm:
745   case X86::VMOVDQU8Z128rm:
746   case X86::VMOVDQU16Z128rm:
747   case X86::VMOVDQA32Z128rm:
748   case X86::VMOVDQU32Z128rm:
749   case X86::VMOVDQA64Z128rm:
750   case X86::VMOVDQU64Z128rm:
751     MemBytes = 16;
752     return true;
753   case X86::VMOVAPSYrm:
754   case X86::VMOVUPSYrm:
755   case X86::VMOVAPDYrm:
756   case X86::VMOVUPDYrm:
757   case X86::VMOVDQAYrm:
758   case X86::VMOVDQUYrm:
759   case X86::VMOVAPSZ256rm:
760   case X86::VMOVUPSZ256rm:
761   case X86::VMOVAPSZ256rm_NOVLX:
762   case X86::VMOVUPSZ256rm_NOVLX:
763   case X86::VMOVAPDZ256rm:
764   case X86::VMOVUPDZ256rm:
765   case X86::VMOVDQU8Z256rm:
766   case X86::VMOVDQU16Z256rm:
767   case X86::VMOVDQA32Z256rm:
768   case X86::VMOVDQU32Z256rm:
769   case X86::VMOVDQA64Z256rm:
770   case X86::VMOVDQU64Z256rm:
771     MemBytes = 32;
772     return true;
773   case X86::VMOVAPSZrm:
774   case X86::VMOVUPSZrm:
775   case X86::VMOVAPDZrm:
776   case X86::VMOVUPDZrm:
777   case X86::VMOVDQU8Zrm:
778   case X86::VMOVDQU16Zrm:
779   case X86::VMOVDQA32Zrm:
780   case X86::VMOVDQU32Zrm:
781   case X86::VMOVDQA64Zrm:
782   case X86::VMOVDQU64Zrm:
783     MemBytes = 64;
784     return true;
785   }
786 }
787 
788 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
789   switch (Opcode) {
790   default:
791     return false;
792   case X86::MOV8mr:
793   case X86::KMOVBmk:
794     MemBytes = 1;
795     return true;
796   case X86::MOV16mr:
797   case X86::KMOVWmk:
798     MemBytes = 2;
799     return true;
800   case X86::MOV32mr:
801   case X86::MOVSSmr:
802   case X86::VMOVSSmr:
803   case X86::VMOVSSZmr:
804   case X86::KMOVDmk:
805     MemBytes = 4;
806     return true;
807   case X86::MOV64mr:
808   case X86::ST_FpP64m:
809   case X86::MOVSDmr:
810   case X86::VMOVSDmr:
811   case X86::VMOVSDZmr:
812   case X86::MMX_MOVD64mr:
813   case X86::MMX_MOVQ64mr:
814   case X86::MMX_MOVNTQmr:
815   case X86::KMOVQmk:
816     MemBytes = 8;
817     return true;
818   case X86::MOVAPSmr:
819   case X86::MOVUPSmr:
820   case X86::MOVAPDmr:
821   case X86::MOVUPDmr:
822   case X86::MOVDQAmr:
823   case X86::MOVDQUmr:
824   case X86::VMOVAPSmr:
825   case X86::VMOVUPSmr:
826   case X86::VMOVAPDmr:
827   case X86::VMOVUPDmr:
828   case X86::VMOVDQAmr:
829   case X86::VMOVDQUmr:
830   case X86::VMOVUPSZ128mr:
831   case X86::VMOVAPSZ128mr:
832   case X86::VMOVUPSZ128mr_NOVLX:
833   case X86::VMOVAPSZ128mr_NOVLX:
834   case X86::VMOVUPDZ128mr:
835   case X86::VMOVAPDZ128mr:
836   case X86::VMOVDQA32Z128mr:
837   case X86::VMOVDQU32Z128mr:
838   case X86::VMOVDQA64Z128mr:
839   case X86::VMOVDQU64Z128mr:
840   case X86::VMOVDQU8Z128mr:
841   case X86::VMOVDQU16Z128mr:
842     MemBytes = 16;
843     return true;
844   case X86::VMOVUPSYmr:
845   case X86::VMOVAPSYmr:
846   case X86::VMOVUPDYmr:
847   case X86::VMOVAPDYmr:
848   case X86::VMOVDQUYmr:
849   case X86::VMOVDQAYmr:
850   case X86::VMOVUPSZ256mr:
851   case X86::VMOVAPSZ256mr:
852   case X86::VMOVUPSZ256mr_NOVLX:
853   case X86::VMOVAPSZ256mr_NOVLX:
854   case X86::VMOVUPDZ256mr:
855   case X86::VMOVAPDZ256mr:
856   case X86::VMOVDQU8Z256mr:
857   case X86::VMOVDQU16Z256mr:
858   case X86::VMOVDQA32Z256mr:
859   case X86::VMOVDQU32Z256mr:
860   case X86::VMOVDQA64Z256mr:
861   case X86::VMOVDQU64Z256mr:
862     MemBytes = 32;
863     return true;
864   case X86::VMOVUPSZmr:
865   case X86::VMOVAPSZmr:
866   case X86::VMOVUPDZmr:
867   case X86::VMOVAPDZmr:
868   case X86::VMOVDQU8Zmr:
869   case X86::VMOVDQU16Zmr:
870   case X86::VMOVDQA32Zmr:
871   case X86::VMOVDQU32Zmr:
872   case X86::VMOVDQA64Zmr:
873   case X86::VMOVDQU64Zmr:
874     MemBytes = 64;
875     return true;
876   }
877   return false;
878 }
879 
880 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
881                                            int &FrameIndex) const {
882   unsigned Dummy;
883   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
884 }
885 
886 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
887                                            int &FrameIndex,
888                                            unsigned &MemBytes) const {
889   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
890     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
891       return MI.getOperand(0).getReg();
892   return 0;
893 }
894 
895 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
896                                                  int &FrameIndex) const {
897   unsigned Dummy;
898   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
899     unsigned Reg;
900     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
901       return Reg;
902     // Check for post-frame index elimination operations
903     SmallVector<const MachineMemOperand *, 1> Accesses;
904     if (hasLoadFromStackSlot(MI, Accesses)) {
905       FrameIndex =
906           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
907               ->getFrameIndex();
908       return 1;
909     }
910   }
911   return 0;
912 }
913 
914 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
915                                           int &FrameIndex) const {
916   unsigned Dummy;
917   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
918 }
919 
920 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
921                                           int &FrameIndex,
922                                           unsigned &MemBytes) const {
923   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
924     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
925         isFrameOperand(MI, 0, FrameIndex))
926       return MI.getOperand(X86::AddrNumOperands).getReg();
927   return 0;
928 }
929 
930 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
931                                                 int &FrameIndex) const {
932   unsigned Dummy;
933   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
934     unsigned Reg;
935     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
936       return Reg;
937     // Check for post-frame index elimination operations
938     SmallVector<const MachineMemOperand *, 1> Accesses;
939     if (hasStoreToStackSlot(MI, Accesses)) {
940       FrameIndex =
941           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
942               ->getFrameIndex();
943       return 1;
944     }
945   }
946   return 0;
947 }
948 
949 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
950 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
951   // Don't waste compile time scanning use-def chains of physregs.
952   if (!Register::isVirtualRegister(BaseReg))
953     return false;
954   bool isPICBase = false;
955   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
956          E = MRI.def_instr_end(); I != E; ++I) {
957     MachineInstr *DefMI = &*I;
958     if (DefMI->getOpcode() != X86::MOVPC32r)
959       return false;
960     assert(!isPICBase && "More than one PIC base?");
961     isPICBase = true;
962   }
963   return isPICBase;
964 }
965 
966 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
967                                                      AAResults *AA) const {
968   switch (MI.getOpcode()) {
969   default:
970     // This function should only be called for opcodes with the ReMaterializable
971     // flag set.
972     llvm_unreachable("Unknown rematerializable operation!");
973     break;
974 
975   case X86::LOAD_STACK_GUARD:
976   case X86::AVX1_SETALLONES:
977   case X86::AVX2_SETALLONES:
978   case X86::AVX512_128_SET0:
979   case X86::AVX512_256_SET0:
980   case X86::AVX512_512_SET0:
981   case X86::AVX512_512_SETALLONES:
982   case X86::AVX512_FsFLD0SD:
983   case X86::AVX512_FsFLD0SS:
984   case X86::AVX512_FsFLD0F128:
985   case X86::AVX_SET0:
986   case X86::FsFLD0SD:
987   case X86::FsFLD0SS:
988   case X86::FsFLD0F128:
989   case X86::KSET0D:
990   case X86::KSET0Q:
991   case X86::KSET0W:
992   case X86::KSET1D:
993   case X86::KSET1Q:
994   case X86::KSET1W:
995   case X86::MMX_SET0:
996   case X86::MOV32ImmSExti8:
997   case X86::MOV32r0:
998   case X86::MOV32r1:
999   case X86::MOV32r_1:
1000   case X86::MOV32ri64:
1001   case X86::MOV64ImmSExti8:
1002   case X86::V_SET0:
1003   case X86::V_SETALLONES:
1004   case X86::MOV16ri:
1005   case X86::MOV32ri:
1006   case X86::MOV64ri:
1007   case X86::MOV64ri32:
1008   case X86::MOV8ri:
1009     return true;
1010 
1011   case X86::MOV8rm:
1012   case X86::MOV8rm_NOREX:
1013   case X86::MOV16rm:
1014   case X86::MOV32rm:
1015   case X86::MOV64rm:
1016   case X86::MOVSSrm:
1017   case X86::MOVSSrm_alt:
1018   case X86::MOVSDrm:
1019   case X86::MOVSDrm_alt:
1020   case X86::MOVAPSrm:
1021   case X86::MOVUPSrm:
1022   case X86::MOVAPDrm:
1023   case X86::MOVUPDrm:
1024   case X86::MOVDQArm:
1025   case X86::MOVDQUrm:
1026   case X86::VMOVSSrm:
1027   case X86::VMOVSSrm_alt:
1028   case X86::VMOVSDrm:
1029   case X86::VMOVSDrm_alt:
1030   case X86::VMOVAPSrm:
1031   case X86::VMOVUPSrm:
1032   case X86::VMOVAPDrm:
1033   case X86::VMOVUPDrm:
1034   case X86::VMOVDQArm:
1035   case X86::VMOVDQUrm:
1036   case X86::VMOVAPSYrm:
1037   case X86::VMOVUPSYrm:
1038   case X86::VMOVAPDYrm:
1039   case X86::VMOVUPDYrm:
1040   case X86::VMOVDQAYrm:
1041   case X86::VMOVDQUYrm:
1042   case X86::MMX_MOVD64rm:
1043   case X86::MMX_MOVQ64rm:
1044   // AVX-512
1045   case X86::VMOVSSZrm:
1046   case X86::VMOVSSZrm_alt:
1047   case X86::VMOVSDZrm:
1048   case X86::VMOVSDZrm_alt:
1049   case X86::VMOVAPDZ128rm:
1050   case X86::VMOVAPDZ256rm:
1051   case X86::VMOVAPDZrm:
1052   case X86::VMOVAPSZ128rm:
1053   case X86::VMOVAPSZ256rm:
1054   case X86::VMOVAPSZ128rm_NOVLX:
1055   case X86::VMOVAPSZ256rm_NOVLX:
1056   case X86::VMOVAPSZrm:
1057   case X86::VMOVDQA32Z128rm:
1058   case X86::VMOVDQA32Z256rm:
1059   case X86::VMOVDQA32Zrm:
1060   case X86::VMOVDQA64Z128rm:
1061   case X86::VMOVDQA64Z256rm:
1062   case X86::VMOVDQA64Zrm:
1063   case X86::VMOVDQU16Z128rm:
1064   case X86::VMOVDQU16Z256rm:
1065   case X86::VMOVDQU16Zrm:
1066   case X86::VMOVDQU32Z128rm:
1067   case X86::VMOVDQU32Z256rm:
1068   case X86::VMOVDQU32Zrm:
1069   case X86::VMOVDQU64Z128rm:
1070   case X86::VMOVDQU64Z256rm:
1071   case X86::VMOVDQU64Zrm:
1072   case X86::VMOVDQU8Z128rm:
1073   case X86::VMOVDQU8Z256rm:
1074   case X86::VMOVDQU8Zrm:
1075   case X86::VMOVUPDZ128rm:
1076   case X86::VMOVUPDZ256rm:
1077   case X86::VMOVUPDZrm:
1078   case X86::VMOVUPSZ128rm:
1079   case X86::VMOVUPSZ256rm:
1080   case X86::VMOVUPSZ128rm_NOVLX:
1081   case X86::VMOVUPSZ256rm_NOVLX:
1082   case X86::VMOVUPSZrm: {
1083     // Loads from constant pools are trivially rematerializable.
1084     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1085         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1086         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1087         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1088         MI.isDereferenceableInvariantLoad(AA)) {
1089       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1090       if (BaseReg == 0 || BaseReg == X86::RIP)
1091         return true;
1092       // Allow re-materialization of PIC load.
1093       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1094         return false;
1095       const MachineFunction &MF = *MI.getParent()->getParent();
1096       const MachineRegisterInfo &MRI = MF.getRegInfo();
1097       return regIsPICBase(BaseReg, MRI);
1098     }
1099     return false;
1100   }
1101 
1102   case X86::LEA32r:
1103   case X86::LEA64r: {
1104     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1105         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1106         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1107         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1108       // lea fi#, lea GV, etc. are all rematerializable.
1109       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1110         return true;
1111       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1112       if (BaseReg == 0)
1113         return true;
1114       // Allow re-materialization of lea PICBase + x.
1115       const MachineFunction &MF = *MI.getParent()->getParent();
1116       const MachineRegisterInfo &MRI = MF.getRegInfo();
1117       return regIsPICBase(BaseReg, MRI);
1118     }
1119     return false;
1120   }
1121   }
1122 }
1123 
1124 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1125                                  MachineBasicBlock::iterator I,
1126                                  Register DestReg, unsigned SubIdx,
1127                                  const MachineInstr &Orig,
1128                                  const TargetRegisterInfo &TRI) const {
1129   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1130   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
1131     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1132     // effects.
1133     int Value;
1134     switch (Orig.getOpcode()) {
1135     case X86::MOV32r0:  Value = 0; break;
1136     case X86::MOV32r1:  Value = 1; break;
1137     case X86::MOV32r_1: Value = -1; break;
1138     default:
1139       llvm_unreachable("Unexpected instruction!");
1140     }
1141 
1142     const DebugLoc &DL = Orig.getDebugLoc();
1143     BuildMI(MBB, I, DL, get(X86::MOV32ri))
1144         .add(Orig.getOperand(0))
1145         .addImm(Value);
1146   } else {
1147     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1148     MBB.insert(I, MI);
1149   }
1150 
1151   MachineInstr &NewMI = *std::prev(I);
1152   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1153 }
1154 
1155 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1156 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1157   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1158     MachineOperand &MO = MI.getOperand(i);
1159     if (MO.isReg() && MO.isDef() &&
1160         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1161       return true;
1162     }
1163   }
1164   return false;
1165 }
1166 
1167 /// Check whether the shift count for a machine operand is non-zero.
1168 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1169                                               unsigned ShiftAmtOperandIdx) {
1170   // The shift count is six bits with the REX.W prefix and five bits without.
1171   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1172   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1173   return Imm & ShiftCountMask;
1174 }
1175 
1176 /// Check whether the given shift count is appropriate
1177 /// can be represented by a LEA instruction.
1178 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1179   // Left shift instructions can be transformed into load-effective-address
1180   // instructions if we can encode them appropriately.
1181   // A LEA instruction utilizes a SIB byte to encode its scale factor.
1182   // The SIB.scale field is two bits wide which means that we can encode any
1183   // shift amount less than 4.
1184   return ShAmt < 4 && ShAmt > 0;
1185 }
1186 
1187 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1188                                   unsigned Opc, bool AllowSP, Register &NewSrc,
1189                                   bool &isKill, MachineOperand &ImplicitOp,
1190                                   LiveVariables *LV) const {
1191   MachineFunction &MF = *MI.getParent()->getParent();
1192   const TargetRegisterClass *RC;
1193   if (AllowSP) {
1194     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1195   } else {
1196     RC = Opc != X86::LEA32r ?
1197       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1198   }
1199   Register SrcReg = Src.getReg();
1200 
1201   // For both LEA64 and LEA32 the register already has essentially the right
1202   // type (32-bit or 64-bit) we may just need to forbid SP.
1203   if (Opc != X86::LEA64_32r) {
1204     NewSrc = SrcReg;
1205     isKill = Src.isKill();
1206     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1207 
1208     if (Register::isVirtualRegister(NewSrc) &&
1209         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1210       return false;
1211 
1212     return true;
1213   }
1214 
1215   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1216   // another we need to add 64-bit registers to the final MI.
1217   if (Register::isPhysicalRegister(SrcReg)) {
1218     ImplicitOp = Src;
1219     ImplicitOp.setImplicit();
1220 
1221     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1222     isKill = Src.isKill();
1223     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1224   } else {
1225     // Virtual register of the wrong class, we have to create a temporary 64-bit
1226     // vreg to feed into the LEA.
1227     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1228     MachineInstr *Copy =
1229         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1230             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1231             .add(Src);
1232 
1233     // Which is obviously going to be dead after we're done with it.
1234     isKill = true;
1235 
1236     if (LV)
1237       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1238   }
1239 
1240   // We've set all the parameters without issue.
1241   return true;
1242 }
1243 
1244 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
1245     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
1246     LiveVariables *LV, bool Is8BitOp) const {
1247   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1248   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1249   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1250               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1251          "Unexpected type for LEA transform");
1252 
1253   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1254   // something like this:
1255   //   Opcode = X86::LEA32r;
1256   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1257   //   OutRegLEA =
1258   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1259   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1260   if (!Subtarget.is64Bit())
1261     return nullptr;
1262 
1263   unsigned Opcode = X86::LEA64_32r;
1264   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1265   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1266 
1267   // Build and insert into an implicit UNDEF value. This is OK because
1268   // we will be shifting and then extracting the lower 8/16-bits.
1269   // This has the potential to cause partial register stall. e.g.
1270   //   movw    (%rbp,%rcx,2), %dx
1271   //   leal    -65(%rdx), %esi
1272   // But testing has shown this *does* help performance in 64-bit mode (at
1273   // least on modern x86 machines).
1274   MachineBasicBlock::iterator MBBI = MI.getIterator();
1275   Register Dest = MI.getOperand(0).getReg();
1276   Register Src = MI.getOperand(1).getReg();
1277   bool IsDead = MI.getOperand(0).isDead();
1278   bool IsKill = MI.getOperand(1).isKill();
1279   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1280   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1281   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1282   MachineInstr *InsMI =
1283       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1284           .addReg(InRegLEA, RegState::Define, SubReg)
1285           .addReg(Src, getKillRegState(IsKill));
1286 
1287   MachineInstrBuilder MIB =
1288       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1289   switch (MIOpc) {
1290   default: llvm_unreachable("Unreachable!");
1291   case X86::SHL8ri:
1292   case X86::SHL16ri: {
1293     unsigned ShAmt = MI.getOperand(2).getImm();
1294     MIB.addReg(0).addImm(1ULL << ShAmt)
1295        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1296     break;
1297   }
1298   case X86::INC8r:
1299   case X86::INC16r:
1300     addRegOffset(MIB, InRegLEA, true, 1);
1301     break;
1302   case X86::DEC8r:
1303   case X86::DEC16r:
1304     addRegOffset(MIB, InRegLEA, true, -1);
1305     break;
1306   case X86::ADD8ri:
1307   case X86::ADD8ri_DB:
1308   case X86::ADD16ri:
1309   case X86::ADD16ri8:
1310   case X86::ADD16ri_DB:
1311   case X86::ADD16ri8_DB:
1312     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1313     break;
1314   case X86::ADD8rr:
1315   case X86::ADD8rr_DB:
1316   case X86::ADD16rr:
1317   case X86::ADD16rr_DB: {
1318     Register Src2 = MI.getOperand(2).getReg();
1319     bool IsKill2 = MI.getOperand(2).isKill();
1320     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1321     unsigned InRegLEA2 = 0;
1322     MachineInstr *InsMI2 = nullptr;
1323     if (Src == Src2) {
1324       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1325       // just a single insert_subreg.
1326       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1327     } else {
1328       if (Subtarget.is64Bit())
1329         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1330       else
1331         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1332       // Build and insert into an implicit UNDEF value. This is OK because
1333       // we will be shifting and then extracting the lower 8/16-bits.
1334       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1335       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1336                    .addReg(InRegLEA2, RegState::Define, SubReg)
1337                    .addReg(Src2, getKillRegState(IsKill2));
1338       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1339     }
1340     if (LV && IsKill2 && InsMI2)
1341       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1342     break;
1343   }
1344   }
1345 
1346   MachineInstr *NewMI = MIB;
1347   MachineInstr *ExtMI =
1348       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1349           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1350           .addReg(OutRegLEA, RegState::Kill, SubReg);
1351 
1352   if (LV) {
1353     // Update live variables.
1354     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1355     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1356     if (IsKill)
1357       LV->replaceKillInstruction(Src, MI, *InsMI);
1358     if (IsDead)
1359       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1360   }
1361 
1362   return ExtMI;
1363 }
1364 
1365 /// This method must be implemented by targets that
1366 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1367 /// may be able to convert a two-address instruction into a true
1368 /// three-address instruction on demand.  This allows the X86 target (for
1369 /// example) to convert ADD and SHL instructions into LEA instructions if they
1370 /// would require register copies due to two-addressness.
1371 ///
1372 /// This method returns a null pointer if the transformation cannot be
1373 /// performed, otherwise it returns the new instruction.
1374 ///
1375 MachineInstr *
1376 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1377                                     MachineInstr &MI, LiveVariables *LV) const {
1378   // The following opcodes also sets the condition code register(s). Only
1379   // convert them to equivalent lea if the condition code register def's
1380   // are dead!
1381   if (hasLiveCondCodeDef(MI))
1382     return nullptr;
1383 
1384   MachineFunction &MF = *MI.getParent()->getParent();
1385   // All instructions input are two-addr instructions.  Get the known operands.
1386   const MachineOperand &Dest = MI.getOperand(0);
1387   const MachineOperand &Src = MI.getOperand(1);
1388 
1389   // Ideally, operations with undef should be folded before we get here, but we
1390   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1391   // Without this, we have to forward undef state to new register operands to
1392   // avoid machine verifier errors.
1393   if (Src.isUndef())
1394     return nullptr;
1395   if (MI.getNumOperands() > 2)
1396     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1397       return nullptr;
1398 
1399   MachineInstr *NewMI = nullptr;
1400   bool Is64Bit = Subtarget.is64Bit();
1401 
1402   bool Is8BitOp = false;
1403   unsigned MIOpc = MI.getOpcode();
1404   switch (MIOpc) {
1405   default: llvm_unreachable("Unreachable!");
1406   case X86::SHL64ri: {
1407     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1408     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1409     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1410 
1411     // LEA can't handle RSP.
1412     if (Register::isVirtualRegister(Src.getReg()) &&
1413         !MF.getRegInfo().constrainRegClass(Src.getReg(),
1414                                            &X86::GR64_NOSPRegClass))
1415       return nullptr;
1416 
1417     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1418                 .add(Dest)
1419                 .addReg(0)
1420                 .addImm(1ULL << ShAmt)
1421                 .add(Src)
1422                 .addImm(0)
1423                 .addReg(0);
1424     break;
1425   }
1426   case X86::SHL32ri: {
1427     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1428     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1429     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1430 
1431     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1432 
1433     // LEA can't handle ESP.
1434     bool isKill;
1435     Register SrcReg;
1436     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1437     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1438                         SrcReg, isKill, ImplicitOp, LV))
1439       return nullptr;
1440 
1441     MachineInstrBuilder MIB =
1442         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1443             .add(Dest)
1444             .addReg(0)
1445             .addImm(1ULL << ShAmt)
1446             .addReg(SrcReg, getKillRegState(isKill))
1447             .addImm(0)
1448             .addReg(0);
1449     if (ImplicitOp.getReg() != 0)
1450       MIB.add(ImplicitOp);
1451     NewMI = MIB;
1452 
1453     break;
1454   }
1455   case X86::SHL8ri:
1456     Is8BitOp = true;
1457     LLVM_FALLTHROUGH;
1458   case X86::SHL16ri: {
1459     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1460     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1461     if (!isTruncatedShiftCountForLEA(ShAmt))
1462       return nullptr;
1463     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1464   }
1465   case X86::INC64r:
1466   case X86::INC32r: {
1467     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1468     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1469         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1470     bool isKill;
1471     Register SrcReg;
1472     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1473     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1474                         ImplicitOp, LV))
1475       return nullptr;
1476 
1477     MachineInstrBuilder MIB =
1478         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1479             .add(Dest)
1480             .addReg(SrcReg, getKillRegState(isKill));
1481     if (ImplicitOp.getReg() != 0)
1482       MIB.add(ImplicitOp);
1483 
1484     NewMI = addOffset(MIB, 1);
1485     break;
1486   }
1487   case X86::DEC64r:
1488   case X86::DEC32r: {
1489     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1490     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1491         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1492 
1493     bool isKill;
1494     Register SrcReg;
1495     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1496     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1497                         ImplicitOp, LV))
1498       return nullptr;
1499 
1500     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1501                                   .add(Dest)
1502                                   .addReg(SrcReg, getKillRegState(isKill));
1503     if (ImplicitOp.getReg() != 0)
1504       MIB.add(ImplicitOp);
1505 
1506     NewMI = addOffset(MIB, -1);
1507 
1508     break;
1509   }
1510   case X86::DEC8r:
1511   case X86::INC8r:
1512     Is8BitOp = true;
1513     LLVM_FALLTHROUGH;
1514   case X86::DEC16r:
1515   case X86::INC16r:
1516     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1517   case X86::ADD64rr:
1518   case X86::ADD64rr_DB:
1519   case X86::ADD32rr:
1520   case X86::ADD32rr_DB: {
1521     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1522     unsigned Opc;
1523     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1524       Opc = X86::LEA64r;
1525     else
1526       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1527 
1528     bool isKill;
1529     Register SrcReg;
1530     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1531     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1532                         SrcReg, isKill, ImplicitOp, LV))
1533       return nullptr;
1534 
1535     const MachineOperand &Src2 = MI.getOperand(2);
1536     bool isKill2;
1537     Register SrcReg2;
1538     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1539     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1540                         SrcReg2, isKill2, ImplicitOp2, LV))
1541       return nullptr;
1542 
1543     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1544     if (ImplicitOp.getReg() != 0)
1545       MIB.add(ImplicitOp);
1546     if (ImplicitOp2.getReg() != 0)
1547       MIB.add(ImplicitOp2);
1548 
1549     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1550     if (LV && Src2.isKill())
1551       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1552     break;
1553   }
1554   case X86::ADD8rr:
1555   case X86::ADD8rr_DB:
1556     Is8BitOp = true;
1557     LLVM_FALLTHROUGH;
1558   case X86::ADD16rr:
1559   case X86::ADD16rr_DB:
1560     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1561   case X86::ADD64ri32:
1562   case X86::ADD64ri8:
1563   case X86::ADD64ri32_DB:
1564   case X86::ADD64ri8_DB:
1565     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1566     NewMI = addOffset(
1567         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1568         MI.getOperand(2));
1569     break;
1570   case X86::ADD32ri:
1571   case X86::ADD32ri8:
1572   case X86::ADD32ri_DB:
1573   case X86::ADD32ri8_DB: {
1574     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1575     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1576 
1577     bool isKill;
1578     Register SrcReg;
1579     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1580     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1581                         SrcReg, isKill, ImplicitOp, LV))
1582       return nullptr;
1583 
1584     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1585                                   .add(Dest)
1586                                   .addReg(SrcReg, getKillRegState(isKill));
1587     if (ImplicitOp.getReg() != 0)
1588       MIB.add(ImplicitOp);
1589 
1590     NewMI = addOffset(MIB, MI.getOperand(2));
1591     break;
1592   }
1593   case X86::ADD8ri:
1594   case X86::ADD8ri_DB:
1595     Is8BitOp = true;
1596     LLVM_FALLTHROUGH;
1597   case X86::ADD16ri:
1598   case X86::ADD16ri8:
1599   case X86::ADD16ri_DB:
1600   case X86::ADD16ri8_DB:
1601     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1602   case X86::SUB8ri:
1603   case X86::SUB16ri8:
1604   case X86::SUB16ri:
1605     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1606     return nullptr;
1607   case X86::SUB32ri8:
1608   case X86::SUB32ri: {
1609     if (!MI.getOperand(2).isImm())
1610       return nullptr;
1611     int64_t Imm = MI.getOperand(2).getImm();
1612     if (!isInt<32>(-Imm))
1613       return nullptr;
1614 
1615     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1616     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1617 
1618     bool isKill;
1619     Register SrcReg;
1620     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1621     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1622                         SrcReg, isKill, ImplicitOp, LV))
1623       return nullptr;
1624 
1625     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1626                                   .add(Dest)
1627                                   .addReg(SrcReg, getKillRegState(isKill));
1628     if (ImplicitOp.getReg() != 0)
1629       MIB.add(ImplicitOp);
1630 
1631     NewMI = addOffset(MIB, -Imm);
1632     break;
1633   }
1634 
1635   case X86::SUB64ri8:
1636   case X86::SUB64ri32: {
1637     if (!MI.getOperand(2).isImm())
1638       return nullptr;
1639     int64_t Imm = MI.getOperand(2).getImm();
1640     if (!isInt<32>(-Imm))
1641       return nullptr;
1642 
1643     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1644 
1645     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1646                                       get(X86::LEA64r)).add(Dest).add(Src);
1647     NewMI = addOffset(MIB, -Imm);
1648     break;
1649   }
1650 
1651   case X86::VMOVDQU8Z128rmk:
1652   case X86::VMOVDQU8Z256rmk:
1653   case X86::VMOVDQU8Zrmk:
1654   case X86::VMOVDQU16Z128rmk:
1655   case X86::VMOVDQU16Z256rmk:
1656   case X86::VMOVDQU16Zrmk:
1657   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1658   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1659   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1660   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1661   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1662   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1663   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1664   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1665   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1666   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1667   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1668   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1669   case X86::VBROADCASTSDZ256rmk:
1670   case X86::VBROADCASTSDZrmk:
1671   case X86::VBROADCASTSSZ128rmk:
1672   case X86::VBROADCASTSSZ256rmk:
1673   case X86::VBROADCASTSSZrmk:
1674   case X86::VPBROADCASTDZ128rmk:
1675   case X86::VPBROADCASTDZ256rmk:
1676   case X86::VPBROADCASTDZrmk:
1677   case X86::VPBROADCASTQZ128rmk:
1678   case X86::VPBROADCASTQZ256rmk:
1679   case X86::VPBROADCASTQZrmk: {
1680     unsigned Opc;
1681     switch (MIOpc) {
1682     default: llvm_unreachable("Unreachable!");
1683     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1684     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1685     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1686     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1687     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1688     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1689     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1690     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1691     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1692     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1693     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1694     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1695     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1696     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1697     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1698     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1699     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1700     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1701     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1702     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1703     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1704     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1705     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1706     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1707     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1708     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1709     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1710     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1711     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1712     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1713     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1714     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1715     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1716     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1717     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1718     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1719     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1720     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1721     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1722     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1723     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1724     }
1725 
1726     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1727               .add(Dest)
1728               .add(MI.getOperand(2))
1729               .add(Src)
1730               .add(MI.getOperand(3))
1731               .add(MI.getOperand(4))
1732               .add(MI.getOperand(5))
1733               .add(MI.getOperand(6))
1734               .add(MI.getOperand(7));
1735     break;
1736   }
1737 
1738   case X86::VMOVDQU8Z128rrk:
1739   case X86::VMOVDQU8Z256rrk:
1740   case X86::VMOVDQU8Zrrk:
1741   case X86::VMOVDQU16Z128rrk:
1742   case X86::VMOVDQU16Z256rrk:
1743   case X86::VMOVDQU16Zrrk:
1744   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1745   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1746   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1747   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1748   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1749   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1750   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1751   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1752   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1753   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1754   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1755   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1756     unsigned Opc;
1757     switch (MIOpc) {
1758     default: llvm_unreachable("Unreachable!");
1759     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1760     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1761     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1762     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1763     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1764     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1765     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1766     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1767     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1768     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1769     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1770     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1771     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1772     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1773     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1774     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1775     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1776     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1777     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1778     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1779     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1780     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1781     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1782     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1783     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1784     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1785     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1786     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1787     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1788     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1789     }
1790 
1791     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1792               .add(Dest)
1793               .add(MI.getOperand(2))
1794               .add(Src)
1795               .add(MI.getOperand(3));
1796     break;
1797   }
1798   }
1799 
1800   if (!NewMI) return nullptr;
1801 
1802   if (LV) {  // Update live variables
1803     if (Src.isKill())
1804       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1805     if (Dest.isDead())
1806       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1807   }
1808 
1809   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1810   return NewMI;
1811 }
1812 
1813 /// This determines which of three possible cases of a three source commute
1814 /// the source indexes correspond to taking into account any mask operands.
1815 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1816 /// possible.
1817 /// Case 0 - Possible to commute the first and second operands.
1818 /// Case 1 - Possible to commute the first and third operands.
1819 /// Case 2 - Possible to commute the second and third operands.
1820 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1821                                        unsigned SrcOpIdx2) {
1822   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1823   if (SrcOpIdx1 > SrcOpIdx2)
1824     std::swap(SrcOpIdx1, SrcOpIdx2);
1825 
1826   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1827   if (X86II::isKMasked(TSFlags)) {
1828     Op2++;
1829     Op3++;
1830   }
1831 
1832   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1833     return 0;
1834   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1835     return 1;
1836   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1837     return 2;
1838   llvm_unreachable("Unknown three src commute case.");
1839 }
1840 
1841 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1842     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1843     const X86InstrFMA3Group &FMA3Group) const {
1844 
1845   unsigned Opc = MI.getOpcode();
1846 
1847   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1848   // analysis. The commute optimization is legal only if all users of FMA*_Int
1849   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1850   // not implemented yet. So, just return 0 in that case.
1851   // When such analysis are available this place will be the right place for
1852   // calling it.
1853   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1854          "Intrinsic instructions can't commute operand 1");
1855 
1856   // Determine which case this commute is or if it can't be done.
1857   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1858                                          SrcOpIdx2);
1859   assert(Case < 3 && "Unexpected case number!");
1860 
1861   // Define the FMA forms mapping array that helps to map input FMA form
1862   // to output FMA form to preserve the operation semantics after
1863   // commuting the operands.
1864   const unsigned Form132Index = 0;
1865   const unsigned Form213Index = 1;
1866   const unsigned Form231Index = 2;
1867   static const unsigned FormMapping[][3] = {
1868     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1869     // FMA132 A, C, b; ==> FMA231 C, A, b;
1870     // FMA213 B, A, c; ==> FMA213 A, B, c;
1871     // FMA231 C, A, b; ==> FMA132 A, C, b;
1872     { Form231Index, Form213Index, Form132Index },
1873     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1874     // FMA132 A, c, B; ==> FMA132 B, c, A;
1875     // FMA213 B, a, C; ==> FMA231 C, a, B;
1876     // FMA231 C, a, B; ==> FMA213 B, a, C;
1877     { Form132Index, Form231Index, Form213Index },
1878     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1879     // FMA132 a, C, B; ==> FMA213 a, B, C;
1880     // FMA213 b, A, C; ==> FMA132 b, C, A;
1881     // FMA231 c, A, B; ==> FMA231 c, B, A;
1882     { Form213Index, Form132Index, Form231Index }
1883   };
1884 
1885   unsigned FMAForms[3];
1886   FMAForms[0] = FMA3Group.get132Opcode();
1887   FMAForms[1] = FMA3Group.get213Opcode();
1888   FMAForms[2] = FMA3Group.get231Opcode();
1889   unsigned FormIndex;
1890   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1891     if (Opc == FMAForms[FormIndex])
1892       break;
1893 
1894   // Everything is ready, just adjust the FMA opcode and return it.
1895   FormIndex = FormMapping[Case][FormIndex];
1896   return FMAForms[FormIndex];
1897 }
1898 
1899 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1900                              unsigned SrcOpIdx2) {
1901   // Determine which case this commute is or if it can't be done.
1902   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1903                                          SrcOpIdx2);
1904   assert(Case < 3 && "Unexpected case value!");
1905 
1906   // For each case we need to swap two pairs of bits in the final immediate.
1907   static const uint8_t SwapMasks[3][4] = {
1908     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1909     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1910     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1911   };
1912 
1913   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1914   // Clear out the bits we are swapping.
1915   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1916                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1917   // If the immediate had a bit of the pair set, then set the opposite bit.
1918   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1919   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1920   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1921   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1922   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1923 }
1924 
1925 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1926 // commuted.
1927 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1928 #define VPERM_CASES(Suffix) \
1929   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1930   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1931   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1932   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1933   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1934   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1935   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1936   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1937   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1938   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1939   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1940   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1941 
1942 #define VPERM_CASES_BROADCAST(Suffix) \
1943   VPERM_CASES(Suffix) \
1944   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1945   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1946   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1947   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1948   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1949   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1950 
1951   switch (Opcode) {
1952   default: return false;
1953   VPERM_CASES(B)
1954   VPERM_CASES_BROADCAST(D)
1955   VPERM_CASES_BROADCAST(PD)
1956   VPERM_CASES_BROADCAST(PS)
1957   VPERM_CASES_BROADCAST(Q)
1958   VPERM_CASES(W)
1959     return true;
1960   }
1961 #undef VPERM_CASES_BROADCAST
1962 #undef VPERM_CASES
1963 }
1964 
1965 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1966 // from the I opcode to the T opcode and vice versa.
1967 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1968 #define VPERM_CASES(Orig, New) \
1969   case X86::Orig##128rr:    return X86::New##128rr;   \
1970   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1971   case X86::Orig##128rm:    return X86::New##128rm;   \
1972   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1973   case X86::Orig##256rr:    return X86::New##256rr;   \
1974   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1975   case X86::Orig##256rm:    return X86::New##256rm;   \
1976   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1977   case X86::Orig##rr:       return X86::New##rr;      \
1978   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1979   case X86::Orig##rm:       return X86::New##rm;      \
1980   case X86::Orig##rmkz:     return X86::New##rmkz;
1981 
1982 #define VPERM_CASES_BROADCAST(Orig, New) \
1983   VPERM_CASES(Orig, New) \
1984   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1985   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1986   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1987   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1988   case X86::Orig##rmb:      return X86::New##rmb;      \
1989   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1990 
1991   switch (Opcode) {
1992   VPERM_CASES(VPERMI2B, VPERMT2B)
1993   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1994   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1995   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1996   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1997   VPERM_CASES(VPERMI2W, VPERMT2W)
1998   VPERM_CASES(VPERMT2B, VPERMI2B)
1999   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
2000   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2001   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2002   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
2003   VPERM_CASES(VPERMT2W, VPERMI2W)
2004   }
2005 
2006   llvm_unreachable("Unreachable!");
2007 #undef VPERM_CASES_BROADCAST
2008 #undef VPERM_CASES
2009 }
2010 
2011 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2012                                                    unsigned OpIdx1,
2013                                                    unsigned OpIdx2) const {
2014   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2015     if (NewMI)
2016       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2017     return MI;
2018   };
2019 
2020   switch (MI.getOpcode()) {
2021   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2022   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2023   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2024   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2025   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2026   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2027     unsigned Opc;
2028     unsigned Size;
2029     switch (MI.getOpcode()) {
2030     default: llvm_unreachable("Unreachable!");
2031     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2032     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2033     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2034     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2035     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2036     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2037     }
2038     unsigned Amt = MI.getOperand(3).getImm();
2039     auto &WorkingMI = cloneIfNew(MI);
2040     WorkingMI.setDesc(get(Opc));
2041     WorkingMI.getOperand(3).setImm(Size - Amt);
2042     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2043                                                    OpIdx1, OpIdx2);
2044   }
2045   case X86::PFSUBrr:
2046   case X86::PFSUBRrr: {
2047     // PFSUB  x, y: x = x - y
2048     // PFSUBR x, y: x = y - x
2049     unsigned Opc =
2050         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2051     auto &WorkingMI = cloneIfNew(MI);
2052     WorkingMI.setDesc(get(Opc));
2053     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2054                                                    OpIdx1, OpIdx2);
2055   }
2056   case X86::BLENDPDrri:
2057   case X86::BLENDPSrri:
2058   case X86::VBLENDPDrri:
2059   case X86::VBLENDPSrri:
2060     // If we're optimizing for size, try to use MOVSD/MOVSS.
2061     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2062       unsigned Mask, Opc;
2063       switch (MI.getOpcode()) {
2064       default: llvm_unreachable("Unreachable!");
2065       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
2066       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
2067       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2068       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2069       }
2070       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2071         auto &WorkingMI = cloneIfNew(MI);
2072         WorkingMI.setDesc(get(Opc));
2073         WorkingMI.RemoveOperand(3);
2074         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2075                                                        /*NewMI=*/false,
2076                                                        OpIdx1, OpIdx2);
2077       }
2078     }
2079     LLVM_FALLTHROUGH;
2080   case X86::PBLENDWrri:
2081   case X86::VBLENDPDYrri:
2082   case X86::VBLENDPSYrri:
2083   case X86::VPBLENDDrri:
2084   case X86::VPBLENDWrri:
2085   case X86::VPBLENDDYrri:
2086   case X86::VPBLENDWYrri:{
2087     int8_t Mask;
2088     switch (MI.getOpcode()) {
2089     default: llvm_unreachable("Unreachable!");
2090     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
2091     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
2092     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
2093     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
2094     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
2095     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
2096     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
2097     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
2098     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
2099     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
2100     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
2101     }
2102     // Only the least significant bits of Imm are used.
2103     // Using int8_t to ensure it will be sign extended to the int64_t that
2104     // setImm takes in order to match isel behavior.
2105     int8_t Imm = MI.getOperand(3).getImm() & Mask;
2106     auto &WorkingMI = cloneIfNew(MI);
2107     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2108     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2109                                                    OpIdx1, OpIdx2);
2110   }
2111   case X86::INSERTPSrr:
2112   case X86::VINSERTPSrr:
2113   case X86::VINSERTPSZrr: {
2114     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2115     unsigned ZMask = Imm & 15;
2116     unsigned DstIdx = (Imm >> 4) & 3;
2117     unsigned SrcIdx = (Imm >> 6) & 3;
2118 
2119     // We can commute insertps if we zero 2 of the elements, the insertion is
2120     // "inline" and we don't override the insertion with a zero.
2121     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2122         countPopulation(ZMask) == 2) {
2123       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2124       assert(AltIdx < 4 && "Illegal insertion index");
2125       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2126       auto &WorkingMI = cloneIfNew(MI);
2127       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2128       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2129                                                      OpIdx1, OpIdx2);
2130     }
2131     return nullptr;
2132   }
2133   case X86::MOVSDrr:
2134   case X86::MOVSSrr:
2135   case X86::VMOVSDrr:
2136   case X86::VMOVSSrr:{
2137     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2138     if (Subtarget.hasSSE41()) {
2139       unsigned Mask, Opc;
2140       switch (MI.getOpcode()) {
2141       default: llvm_unreachable("Unreachable!");
2142       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
2143       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
2144       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2145       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2146       }
2147 
2148       auto &WorkingMI = cloneIfNew(MI);
2149       WorkingMI.setDesc(get(Opc));
2150       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2151       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2152                                                      OpIdx1, OpIdx2);
2153     }
2154 
2155     // Convert to SHUFPD.
2156     assert(MI.getOpcode() == X86::MOVSDrr &&
2157            "Can only commute MOVSDrr without SSE4.1");
2158 
2159     auto &WorkingMI = cloneIfNew(MI);
2160     WorkingMI.setDesc(get(X86::SHUFPDrri));
2161     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2162     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2163                                                    OpIdx1, OpIdx2);
2164   }
2165   case X86::SHUFPDrri: {
2166     // Commute to MOVSD.
2167     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2168     auto &WorkingMI = cloneIfNew(MI);
2169     WorkingMI.setDesc(get(X86::MOVSDrr));
2170     WorkingMI.RemoveOperand(3);
2171     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2172                                                    OpIdx1, OpIdx2);
2173   }
2174   case X86::PCLMULQDQrr:
2175   case X86::VPCLMULQDQrr:
2176   case X86::VPCLMULQDQYrr:
2177   case X86::VPCLMULQDQZrr:
2178   case X86::VPCLMULQDQZ128rr:
2179   case X86::VPCLMULQDQZ256rr: {
2180     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2181     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2182     unsigned Imm = MI.getOperand(3).getImm();
2183     unsigned Src1Hi = Imm & 0x01;
2184     unsigned Src2Hi = Imm & 0x10;
2185     auto &WorkingMI = cloneIfNew(MI);
2186     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2187     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2188                                                    OpIdx1, OpIdx2);
2189   }
2190   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2191   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2192   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2193   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2194   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2195   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2196   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2197   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2198   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2199   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2200   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2201   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2202   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2203   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2204   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2205   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2206   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2207   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2208   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2209   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2210   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2211   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2212   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2213   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2214     // Flip comparison mode immediate (if necessary).
2215     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2216     Imm = X86::getSwappedVPCMPImm(Imm);
2217     auto &WorkingMI = cloneIfNew(MI);
2218     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2219     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2220                                                    OpIdx1, OpIdx2);
2221   }
2222   case X86::VPCOMBri: case X86::VPCOMUBri:
2223   case X86::VPCOMDri: case X86::VPCOMUDri:
2224   case X86::VPCOMQri: case X86::VPCOMUQri:
2225   case X86::VPCOMWri: case X86::VPCOMUWri: {
2226     // Flip comparison mode immediate (if necessary).
2227     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2228     Imm = X86::getSwappedVPCOMImm(Imm);
2229     auto &WorkingMI = cloneIfNew(MI);
2230     WorkingMI.getOperand(3).setImm(Imm);
2231     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2232                                                    OpIdx1, OpIdx2);
2233   }
2234   case X86::VCMPSDZrr:
2235   case X86::VCMPSSZrr:
2236   case X86::VCMPPDZrri:
2237   case X86::VCMPPSZrri:
2238   case X86::VCMPPDZ128rri:
2239   case X86::VCMPPSZ128rri:
2240   case X86::VCMPPDZ256rri:
2241   case X86::VCMPPSZ256rri:
2242   case X86::VCMPPDZrrik:
2243   case X86::VCMPPSZrrik:
2244   case X86::VCMPPDZ128rrik:
2245   case X86::VCMPPSZ128rrik:
2246   case X86::VCMPPDZ256rrik:
2247   case X86::VCMPPSZ256rrik: {
2248     unsigned Imm =
2249                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2250     Imm = X86::getSwappedVCMPImm(Imm);
2251     auto &WorkingMI = cloneIfNew(MI);
2252     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2253     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2254                                                    OpIdx1, OpIdx2);
2255   }
2256   case X86::VPERM2F128rr:
2257   case X86::VPERM2I128rr: {
2258     // Flip permute source immediate.
2259     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2260     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2261     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2262     auto &WorkingMI = cloneIfNew(MI);
2263     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2264     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2265                                                    OpIdx1, OpIdx2);
2266   }
2267   case X86::MOVHLPSrr:
2268   case X86::UNPCKHPDrr:
2269   case X86::VMOVHLPSrr:
2270   case X86::VUNPCKHPDrr:
2271   case X86::VMOVHLPSZrr:
2272   case X86::VUNPCKHPDZ128rr: {
2273     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2274 
2275     unsigned Opc = MI.getOpcode();
2276     switch (Opc) {
2277     default: llvm_unreachable("Unreachable!");
2278     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2279     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2280     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2281     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2282     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2283     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2284     }
2285     auto &WorkingMI = cloneIfNew(MI);
2286     WorkingMI.setDesc(get(Opc));
2287     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2288                                                    OpIdx1, OpIdx2);
2289   }
2290   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2291     auto &WorkingMI = cloneIfNew(MI);
2292     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2293     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2294     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2295     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2296                                                    OpIdx1, OpIdx2);
2297   }
2298   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2299   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2300   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2301   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2302   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2303   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2304   case X86::VPTERNLOGDZrrik:
2305   case X86::VPTERNLOGDZ128rrik:
2306   case X86::VPTERNLOGDZ256rrik:
2307   case X86::VPTERNLOGQZrrik:
2308   case X86::VPTERNLOGQZ128rrik:
2309   case X86::VPTERNLOGQZ256rrik:
2310   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2311   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2312   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2313   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2314   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2315   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2316   case X86::VPTERNLOGDZ128rmbi:
2317   case X86::VPTERNLOGDZ256rmbi:
2318   case X86::VPTERNLOGDZrmbi:
2319   case X86::VPTERNLOGQZ128rmbi:
2320   case X86::VPTERNLOGQZ256rmbi:
2321   case X86::VPTERNLOGQZrmbi:
2322   case X86::VPTERNLOGDZ128rmbikz:
2323   case X86::VPTERNLOGDZ256rmbikz:
2324   case X86::VPTERNLOGDZrmbikz:
2325   case X86::VPTERNLOGQZ128rmbikz:
2326   case X86::VPTERNLOGQZ256rmbikz:
2327   case X86::VPTERNLOGQZrmbikz: {
2328     auto &WorkingMI = cloneIfNew(MI);
2329     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2330     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2331                                                    OpIdx1, OpIdx2);
2332   }
2333   default: {
2334     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2335       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2336       auto &WorkingMI = cloneIfNew(MI);
2337       WorkingMI.setDesc(get(Opc));
2338       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2339                                                      OpIdx1, OpIdx2);
2340     }
2341 
2342     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2343                                                       MI.getDesc().TSFlags);
2344     if (FMA3Group) {
2345       unsigned Opc =
2346         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2347       auto &WorkingMI = cloneIfNew(MI);
2348       WorkingMI.setDesc(get(Opc));
2349       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2350                                                      OpIdx1, OpIdx2);
2351     }
2352 
2353     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2354   }
2355   }
2356 }
2357 
2358 bool
2359 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2360                                             unsigned &SrcOpIdx1,
2361                                             unsigned &SrcOpIdx2,
2362                                             bool IsIntrinsic) const {
2363   uint64_t TSFlags = MI.getDesc().TSFlags;
2364 
2365   unsigned FirstCommutableVecOp = 1;
2366   unsigned LastCommutableVecOp = 3;
2367   unsigned KMaskOp = -1U;
2368   if (X86II::isKMasked(TSFlags)) {
2369     // For k-zero-masked operations it is Ok to commute the first vector
2370     // operand. Unless this is an intrinsic instruction.
2371     // For regular k-masked operations a conservative choice is done as the
2372     // elements of the first vector operand, for which the corresponding bit
2373     // in the k-mask operand is set to 0, are copied to the result of the
2374     // instruction.
2375     // TODO/FIXME: The commute still may be legal if it is known that the
2376     // k-mask operand is set to either all ones or all zeroes.
2377     // It is also Ok to commute the 1st operand if all users of MI use only
2378     // the elements enabled by the k-mask operand. For example,
2379     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2380     //                                                     : v1[i];
2381     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2382     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2383 
2384     // The k-mask operand has index = 2 for masked and zero-masked operations.
2385     KMaskOp = 2;
2386 
2387     // The operand with index = 1 is used as a source for those elements for
2388     // which the corresponding bit in the k-mask is set to 0.
2389     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2390       FirstCommutableVecOp = 3;
2391 
2392     LastCommutableVecOp++;
2393   } else if (IsIntrinsic) {
2394     // Commuting the first operand of an intrinsic instruction isn't possible
2395     // unless we can prove that only the lowest element of the result is used.
2396     FirstCommutableVecOp = 2;
2397   }
2398 
2399   if (isMem(MI, LastCommutableVecOp))
2400     LastCommutableVecOp--;
2401 
2402   // Only the first RegOpsNum operands are commutable.
2403   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2404   // that the operand is not specified/fixed.
2405   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2406       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2407        SrcOpIdx1 == KMaskOp))
2408     return false;
2409   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2410       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2411        SrcOpIdx2 == KMaskOp))
2412     return false;
2413 
2414   // Look for two different register operands assumed to be commutable
2415   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2416   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2417       SrcOpIdx2 == CommuteAnyOperandIndex) {
2418     unsigned CommutableOpIdx2 = SrcOpIdx2;
2419 
2420     // At least one of operands to be commuted is not specified and
2421     // this method is free to choose appropriate commutable operands.
2422     if (SrcOpIdx1 == SrcOpIdx2)
2423       // Both of operands are not fixed. By default set one of commutable
2424       // operands to the last register operand of the instruction.
2425       CommutableOpIdx2 = LastCommutableVecOp;
2426     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2427       // Only one of operands is not fixed.
2428       CommutableOpIdx2 = SrcOpIdx1;
2429 
2430     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2431     // operand and assign its index to CommutableOpIdx1.
2432     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2433 
2434     unsigned CommutableOpIdx1;
2435     for (CommutableOpIdx1 = LastCommutableVecOp;
2436          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2437       // Just ignore and skip the k-mask operand.
2438       if (CommutableOpIdx1 == KMaskOp)
2439         continue;
2440 
2441       // The commuted operands must have different registers.
2442       // Otherwise, the commute transformation does not change anything and
2443       // is useless then.
2444       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2445         break;
2446     }
2447 
2448     // No appropriate commutable operands were found.
2449     if (CommutableOpIdx1 < FirstCommutableVecOp)
2450       return false;
2451 
2452     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2453     // to return those values.
2454     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2455                               CommutableOpIdx1, CommutableOpIdx2))
2456       return false;
2457   }
2458 
2459   return true;
2460 }
2461 
2462 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2463                                          unsigned &SrcOpIdx1,
2464                                          unsigned &SrcOpIdx2) const {
2465   const MCInstrDesc &Desc = MI.getDesc();
2466   if (!Desc.isCommutable())
2467     return false;
2468 
2469   switch (MI.getOpcode()) {
2470   case X86::CMPSDrr:
2471   case X86::CMPSSrr:
2472   case X86::CMPPDrri:
2473   case X86::CMPPSrri:
2474   case X86::VCMPSDrr:
2475   case X86::VCMPSSrr:
2476   case X86::VCMPPDrri:
2477   case X86::VCMPPSrri:
2478   case X86::VCMPPDYrri:
2479   case X86::VCMPPSYrri:
2480   case X86::VCMPSDZrr:
2481   case X86::VCMPSSZrr:
2482   case X86::VCMPPDZrri:
2483   case X86::VCMPPSZrri:
2484   case X86::VCMPPDZ128rri:
2485   case X86::VCMPPSZ128rri:
2486   case X86::VCMPPDZ256rri:
2487   case X86::VCMPPSZ256rri:
2488   case X86::VCMPPDZrrik:
2489   case X86::VCMPPSZrrik:
2490   case X86::VCMPPDZ128rrik:
2491   case X86::VCMPPSZ128rrik:
2492   case X86::VCMPPDZ256rrik:
2493   case X86::VCMPPSZ256rrik: {
2494     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2495 
2496     // Float comparison can be safely commuted for
2497     // Ordered/Unordered/Equal/NotEqual tests
2498     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2499     switch (Imm) {
2500     default:
2501       // EVEX versions can be commuted.
2502       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2503         break;
2504       return false;
2505     case 0x00: // EQUAL
2506     case 0x03: // UNORDERED
2507     case 0x04: // NOT EQUAL
2508     case 0x07: // ORDERED
2509       break;
2510     }
2511 
2512     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2513     // when masked).
2514     // Assign them to the returned operand indices here.
2515     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2516                                 2 + OpOffset);
2517   }
2518   case X86::MOVSSrr:
2519     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2520     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2521     // AVX implies sse4.1.
2522     if (Subtarget.hasSSE41())
2523       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2524     return false;
2525   case X86::SHUFPDrri:
2526     // We can commute this to MOVSD.
2527     if (MI.getOperand(3).getImm() == 0x02)
2528       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2529     return false;
2530   case X86::MOVHLPSrr:
2531   case X86::UNPCKHPDrr:
2532   case X86::VMOVHLPSrr:
2533   case X86::VUNPCKHPDrr:
2534   case X86::VMOVHLPSZrr:
2535   case X86::VUNPCKHPDZ128rr:
2536     if (Subtarget.hasSSE2())
2537       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2538     return false;
2539   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2540   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2541   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2542   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2543   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2544   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2545   case X86::VPTERNLOGDZrrik:
2546   case X86::VPTERNLOGDZ128rrik:
2547   case X86::VPTERNLOGDZ256rrik:
2548   case X86::VPTERNLOGQZrrik:
2549   case X86::VPTERNLOGQZ128rrik:
2550   case X86::VPTERNLOGQZ256rrik:
2551   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2552   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2553   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2554   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2555   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2556   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2557   case X86::VPTERNLOGDZ128rmbi:
2558   case X86::VPTERNLOGDZ256rmbi:
2559   case X86::VPTERNLOGDZrmbi:
2560   case X86::VPTERNLOGQZ128rmbi:
2561   case X86::VPTERNLOGQZ256rmbi:
2562   case X86::VPTERNLOGQZrmbi:
2563   case X86::VPTERNLOGDZ128rmbikz:
2564   case X86::VPTERNLOGDZ256rmbikz:
2565   case X86::VPTERNLOGDZrmbikz:
2566   case X86::VPTERNLOGQZ128rmbikz:
2567   case X86::VPTERNLOGQZ256rmbikz:
2568   case X86::VPTERNLOGQZrmbikz:
2569     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2570   case X86::VPDPWSSDZ128r:
2571   case X86::VPDPWSSDZ128rk:
2572   case X86::VPDPWSSDZ128rkz:
2573   case X86::VPDPWSSDZ256r:
2574   case X86::VPDPWSSDZ256rk:
2575   case X86::VPDPWSSDZ256rkz:
2576   case X86::VPDPWSSDZr:
2577   case X86::VPDPWSSDZrk:
2578   case X86::VPDPWSSDZrkz:
2579   case X86::VPDPWSSDSZ128r:
2580   case X86::VPDPWSSDSZ128rk:
2581   case X86::VPDPWSSDSZ128rkz:
2582   case X86::VPDPWSSDSZ256r:
2583   case X86::VPDPWSSDSZ256rk:
2584   case X86::VPDPWSSDSZ256rkz:
2585   case X86::VPDPWSSDSZr:
2586   case X86::VPDPWSSDSZrk:
2587   case X86::VPDPWSSDSZrkz:
2588   case X86::VPMADD52HUQZ128r:
2589   case X86::VPMADD52HUQZ128rk:
2590   case X86::VPMADD52HUQZ128rkz:
2591   case X86::VPMADD52HUQZ256r:
2592   case X86::VPMADD52HUQZ256rk:
2593   case X86::VPMADD52HUQZ256rkz:
2594   case X86::VPMADD52HUQZr:
2595   case X86::VPMADD52HUQZrk:
2596   case X86::VPMADD52HUQZrkz:
2597   case X86::VPMADD52LUQZ128r:
2598   case X86::VPMADD52LUQZ128rk:
2599   case X86::VPMADD52LUQZ128rkz:
2600   case X86::VPMADD52LUQZ256r:
2601   case X86::VPMADD52LUQZ256rk:
2602   case X86::VPMADD52LUQZ256rkz:
2603   case X86::VPMADD52LUQZr:
2604   case X86::VPMADD52LUQZrk:
2605   case X86::VPMADD52LUQZrkz: {
2606     unsigned CommutableOpIdx1 = 2;
2607     unsigned CommutableOpIdx2 = 3;
2608     if (X86II::isKMasked(Desc.TSFlags)) {
2609       // Skip the mask register.
2610       ++CommutableOpIdx1;
2611       ++CommutableOpIdx2;
2612     }
2613     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2614                               CommutableOpIdx1, CommutableOpIdx2))
2615       return false;
2616     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2617         !MI.getOperand(SrcOpIdx2).isReg())
2618       // No idea.
2619       return false;
2620     return true;
2621   }
2622 
2623   default:
2624     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2625                                                       MI.getDesc().TSFlags);
2626     if (FMA3Group)
2627       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2628                                            FMA3Group->isIntrinsic());
2629 
2630     // Handled masked instructions since we need to skip over the mask input
2631     // and the preserved input.
2632     if (X86II::isKMasked(Desc.TSFlags)) {
2633       // First assume that the first input is the mask operand and skip past it.
2634       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2635       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2636       // Check if the first input is tied. If there isn't one then we only
2637       // need to skip the mask operand which we did above.
2638       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2639                                              MCOI::TIED_TO) != -1)) {
2640         // If this is zero masking instruction with a tied operand, we need to
2641         // move the first index back to the first input since this must
2642         // be a 3 input instruction and we want the first two non-mask inputs.
2643         // Otherwise this is a 2 input instruction with a preserved input and
2644         // mask, so we need to move the indices to skip one more input.
2645         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2646           ++CommutableOpIdx1;
2647           ++CommutableOpIdx2;
2648         } else {
2649           --CommutableOpIdx1;
2650         }
2651       }
2652 
2653       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2654                                 CommutableOpIdx1, CommutableOpIdx2))
2655         return false;
2656 
2657       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2658           !MI.getOperand(SrcOpIdx2).isReg())
2659         // No idea.
2660         return false;
2661       return true;
2662     }
2663 
2664     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2665   }
2666   return false;
2667 }
2668 
2669 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2670   switch (MI.getOpcode()) {
2671   default: return X86::COND_INVALID;
2672   case X86::JCC_1:
2673     return static_cast<X86::CondCode>(
2674         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2675   }
2676 }
2677 
2678 /// Return condition code of a SETCC opcode.
2679 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2680   switch (MI.getOpcode()) {
2681   default: return X86::COND_INVALID;
2682   case X86::SETCCr: case X86::SETCCm:
2683     return static_cast<X86::CondCode>(
2684         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2685   }
2686 }
2687 
2688 /// Return condition code of a CMov opcode.
2689 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2690   switch (MI.getOpcode()) {
2691   default: return X86::COND_INVALID;
2692   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2693   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2694     return static_cast<X86::CondCode>(
2695         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2696   }
2697 }
2698 
2699 /// Return the inverse of the specified condition,
2700 /// e.g. turning COND_E to COND_NE.
2701 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2702   switch (CC) {
2703   default: llvm_unreachable("Illegal condition code!");
2704   case X86::COND_E:  return X86::COND_NE;
2705   case X86::COND_NE: return X86::COND_E;
2706   case X86::COND_L:  return X86::COND_GE;
2707   case X86::COND_LE: return X86::COND_G;
2708   case X86::COND_G:  return X86::COND_LE;
2709   case X86::COND_GE: return X86::COND_L;
2710   case X86::COND_B:  return X86::COND_AE;
2711   case X86::COND_BE: return X86::COND_A;
2712   case X86::COND_A:  return X86::COND_BE;
2713   case X86::COND_AE: return X86::COND_B;
2714   case X86::COND_S:  return X86::COND_NS;
2715   case X86::COND_NS: return X86::COND_S;
2716   case X86::COND_P:  return X86::COND_NP;
2717   case X86::COND_NP: return X86::COND_P;
2718   case X86::COND_O:  return X86::COND_NO;
2719   case X86::COND_NO: return X86::COND_O;
2720   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2721   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2722   }
2723 }
2724 
2725 /// Assuming the flags are set by MI(a,b), return the condition code if we
2726 /// modify the instructions such that flags are set by MI(b,a).
2727 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2728   switch (CC) {
2729   default: return X86::COND_INVALID;
2730   case X86::COND_E:  return X86::COND_E;
2731   case X86::COND_NE: return X86::COND_NE;
2732   case X86::COND_L:  return X86::COND_G;
2733   case X86::COND_LE: return X86::COND_GE;
2734   case X86::COND_G:  return X86::COND_L;
2735   case X86::COND_GE: return X86::COND_LE;
2736   case X86::COND_B:  return X86::COND_A;
2737   case X86::COND_BE: return X86::COND_AE;
2738   case X86::COND_A:  return X86::COND_B;
2739   case X86::COND_AE: return X86::COND_BE;
2740   }
2741 }
2742 
2743 std::pair<X86::CondCode, bool>
2744 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2745   X86::CondCode CC = X86::COND_INVALID;
2746   bool NeedSwap = false;
2747   switch (Predicate) {
2748   default: break;
2749   // Floating-point Predicates
2750   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2751   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2752   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2753   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2754   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2755   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2756   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2757   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2758   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2759   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2760   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2761   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2762   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2763   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2764 
2765   // Integer Predicates
2766   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2767   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2768   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2769   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2770   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2771   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2772   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2773   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2774   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2775   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2776   }
2777 
2778   return std::make_pair(CC, NeedSwap);
2779 }
2780 
2781 /// Return a setcc opcode based on whether it has memory operand.
2782 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2783   return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2784 }
2785 
2786 /// Return a cmov opcode for the given register size in bytes, and operand type.
2787 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2788   switch(RegBytes) {
2789   default: llvm_unreachable("Illegal register size!");
2790   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2791   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2792   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2793   }
2794 }
2795 
2796 /// Get the VPCMP immediate for the given condition.
2797 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2798   switch (CC) {
2799   default: llvm_unreachable("Unexpected SETCC condition");
2800   case ISD::SETNE:  return 4;
2801   case ISD::SETEQ:  return 0;
2802   case ISD::SETULT:
2803   case ISD::SETLT: return 1;
2804   case ISD::SETUGT:
2805   case ISD::SETGT: return 6;
2806   case ISD::SETUGE:
2807   case ISD::SETGE: return 5;
2808   case ISD::SETULE:
2809   case ISD::SETLE: return 2;
2810   }
2811 }
2812 
2813 /// Get the VPCMP immediate if the operands are swapped.
2814 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2815   switch (Imm) {
2816   default: llvm_unreachable("Unreachable!");
2817   case 0x01: Imm = 0x06; break; // LT  -> NLE
2818   case 0x02: Imm = 0x05; break; // LE  -> NLT
2819   case 0x05: Imm = 0x02; break; // NLT -> LE
2820   case 0x06: Imm = 0x01; break; // NLE -> LT
2821   case 0x00: // EQ
2822   case 0x03: // FALSE
2823   case 0x04: // NE
2824   case 0x07: // TRUE
2825     break;
2826   }
2827 
2828   return Imm;
2829 }
2830 
2831 /// Get the VPCOM immediate if the operands are swapped.
2832 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2833   switch (Imm) {
2834   default: llvm_unreachable("Unreachable!");
2835   case 0x00: Imm = 0x02; break; // LT -> GT
2836   case 0x01: Imm = 0x03; break; // LE -> GE
2837   case 0x02: Imm = 0x00; break; // GT -> LT
2838   case 0x03: Imm = 0x01; break; // GE -> LE
2839   case 0x04: // EQ
2840   case 0x05: // NE
2841   case 0x06: // FALSE
2842   case 0x07: // TRUE
2843     break;
2844   }
2845 
2846   return Imm;
2847 }
2848 
2849 /// Get the VCMP immediate if the operands are swapped.
2850 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2851   // Only need the lower 2 bits to distinquish.
2852   switch (Imm & 0x3) {
2853   default: llvm_unreachable("Unreachable!");
2854   case 0x00: case 0x03:
2855     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2856     break;
2857   case 0x01: case 0x02:
2858     // Need to toggle bits 3:0. Bit 4 stays the same.
2859     Imm ^= 0xf;
2860     break;
2861   }
2862 
2863   return Imm;
2864 }
2865 
2866 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2867   if (!MI.isTerminator()) return false;
2868 
2869   // Conditional branch is a special case.
2870   if (MI.isBranch() && !MI.isBarrier())
2871     return true;
2872   if (!MI.isPredicable())
2873     return true;
2874   return !isPredicated(MI);
2875 }
2876 
2877 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2878   switch (MI.getOpcode()) {
2879   case X86::TCRETURNdi:
2880   case X86::TCRETURNri:
2881   case X86::TCRETURNmi:
2882   case X86::TCRETURNdi64:
2883   case X86::TCRETURNri64:
2884   case X86::TCRETURNmi64:
2885     return true;
2886   default:
2887     return false;
2888   }
2889 }
2890 
2891 bool X86InstrInfo::canMakeTailCallConditional(
2892     SmallVectorImpl<MachineOperand> &BranchCond,
2893     const MachineInstr &TailCall) const {
2894   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2895       TailCall.getOpcode() != X86::TCRETURNdi64) {
2896     // Only direct calls can be done with a conditional branch.
2897     return false;
2898   }
2899 
2900   const MachineFunction *MF = TailCall.getParent()->getParent();
2901   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2902     // Conditional tail calls confuse the Win64 unwinder.
2903     return false;
2904   }
2905 
2906   assert(BranchCond.size() == 1);
2907   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2908     // Can't make a conditional tail call with this condition.
2909     return false;
2910   }
2911 
2912   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2913   if (X86FI->getTCReturnAddrDelta() != 0 ||
2914       TailCall.getOperand(1).getImm() != 0) {
2915     // A conditional tail call cannot do any stack adjustment.
2916     return false;
2917   }
2918 
2919   return true;
2920 }
2921 
2922 void X86InstrInfo::replaceBranchWithTailCall(
2923     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2924     const MachineInstr &TailCall) const {
2925   assert(canMakeTailCallConditional(BranchCond, TailCall));
2926 
2927   MachineBasicBlock::iterator I = MBB.end();
2928   while (I != MBB.begin()) {
2929     --I;
2930     if (I->isDebugInstr())
2931       continue;
2932     if (!I->isBranch())
2933       assert(0 && "Can't find the branch to replace!");
2934 
2935     X86::CondCode CC = X86::getCondFromBranch(*I);
2936     assert(BranchCond.size() == 1);
2937     if (CC != BranchCond[0].getImm())
2938       continue;
2939 
2940     break;
2941   }
2942 
2943   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2944                                                          : X86::TCRETURNdi64cc;
2945 
2946   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2947   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2948   MIB.addImm(0); // Stack offset (not used).
2949   MIB->addOperand(BranchCond[0]); // Condition.
2950   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2951 
2952   // Add implicit uses and defs of all live regs potentially clobbered by the
2953   // call. This way they still appear live across the call.
2954   LivePhysRegs LiveRegs(getRegisterInfo());
2955   LiveRegs.addLiveOuts(MBB);
2956   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2957   LiveRegs.stepForward(*MIB, Clobbers);
2958   for (const auto &C : Clobbers) {
2959     MIB.addReg(C.first, RegState::Implicit);
2960     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2961   }
2962 
2963   I->eraseFromParent();
2964 }
2965 
2966 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2967 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2968 // fallthrough MBB cannot be identified.
2969 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2970                                             MachineBasicBlock *TBB) {
2971   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2972   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2973   // and fallthrough MBB. If we find more than one, we cannot identify the
2974   // fallthrough MBB and should return nullptr.
2975   MachineBasicBlock *FallthroughBB = nullptr;
2976   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2977     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2978       continue;
2979     // Return a nullptr if we found more than one fallthrough successor.
2980     if (FallthroughBB && FallthroughBB != TBB)
2981       return nullptr;
2982     FallthroughBB = *SI;
2983   }
2984   return FallthroughBB;
2985 }
2986 
2987 bool X86InstrInfo::AnalyzeBranchImpl(
2988     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2989     SmallVectorImpl<MachineOperand> &Cond,
2990     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2991 
2992   // Start from the bottom of the block and work up, examining the
2993   // terminator instructions.
2994   MachineBasicBlock::iterator I = MBB.end();
2995   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2996   while (I != MBB.begin()) {
2997     --I;
2998     if (I->isDebugInstr())
2999       continue;
3000 
3001     // Working from the bottom, when we see a non-terminator instruction, we're
3002     // done.
3003     if (!isUnpredicatedTerminator(*I))
3004       break;
3005 
3006     // A terminator that isn't a branch can't easily be handled by this
3007     // analysis.
3008     if (!I->isBranch())
3009       return true;
3010 
3011     // Handle unconditional branches.
3012     if (I->getOpcode() == X86::JMP_1) {
3013       UnCondBrIter = I;
3014 
3015       if (!AllowModify) {
3016         TBB = I->getOperand(0).getMBB();
3017         continue;
3018       }
3019 
3020       // If the block has any instructions after a JMP, delete them.
3021       while (std::next(I) != MBB.end())
3022         std::next(I)->eraseFromParent();
3023 
3024       Cond.clear();
3025       FBB = nullptr;
3026 
3027       // Delete the JMP if it's equivalent to a fall-through.
3028       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3029         TBB = nullptr;
3030         I->eraseFromParent();
3031         I = MBB.end();
3032         UnCondBrIter = MBB.end();
3033         continue;
3034       }
3035 
3036       // TBB is used to indicate the unconditional destination.
3037       TBB = I->getOperand(0).getMBB();
3038       continue;
3039     }
3040 
3041     // Handle conditional branches.
3042     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3043     if (BranchCode == X86::COND_INVALID)
3044       return true;  // Can't handle indirect branch.
3045 
3046     // In practice we should never have an undef eflags operand, if we do
3047     // abort here as we are not prepared to preserve the flag.
3048     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3049       return true;
3050 
3051     // Working from the bottom, handle the first conditional branch.
3052     if (Cond.empty()) {
3053       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3054       if (AllowModify && UnCondBrIter != MBB.end() &&
3055           MBB.isLayoutSuccessor(TargetBB)) {
3056         // If we can modify the code and it ends in something like:
3057         //
3058         //     jCC L1
3059         //     jmp L2
3060         //   L1:
3061         //     ...
3062         //   L2:
3063         //
3064         // Then we can change this to:
3065         //
3066         //     jnCC L2
3067         //   L1:
3068         //     ...
3069         //   L2:
3070         //
3071         // Which is a bit more efficient.
3072         // We conditionally jump to the fall-through block.
3073         BranchCode = GetOppositeBranchCondition(BranchCode);
3074         MachineBasicBlock::iterator OldInst = I;
3075 
3076         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3077           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3078           .addImm(BranchCode);
3079         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3080           .addMBB(TargetBB);
3081 
3082         OldInst->eraseFromParent();
3083         UnCondBrIter->eraseFromParent();
3084 
3085         // Restart the analysis.
3086         UnCondBrIter = MBB.end();
3087         I = MBB.end();
3088         continue;
3089       }
3090 
3091       FBB = TBB;
3092       TBB = I->getOperand(0).getMBB();
3093       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3094       CondBranches.push_back(&*I);
3095       continue;
3096     }
3097 
3098     // Handle subsequent conditional branches. Only handle the case where all
3099     // conditional branches branch to the same destination and their condition
3100     // opcodes fit one of the special multi-branch idioms.
3101     assert(Cond.size() == 1);
3102     assert(TBB);
3103 
3104     // If the conditions are the same, we can leave them alone.
3105     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3106     auto NewTBB = I->getOperand(0).getMBB();
3107     if (OldBranchCode == BranchCode && TBB == NewTBB)
3108       continue;
3109 
3110     // If they differ, see if they fit one of the known patterns. Theoretically,
3111     // we could handle more patterns here, but we shouldn't expect to see them
3112     // if instruction selection has done a reasonable job.
3113     if (TBB == NewTBB &&
3114                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3115                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3116       BranchCode = X86::COND_NE_OR_P;
3117     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3118                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3119       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3120         return true;
3121 
3122       // X86::COND_E_AND_NP usually has two different branch destinations.
3123       //
3124       // JP B1
3125       // JE B2
3126       // JMP B1
3127       // B1:
3128       // B2:
3129       //
3130       // Here this condition branches to B2 only if NP && E. It has another
3131       // equivalent form:
3132       //
3133       // JNE B1
3134       // JNP B2
3135       // JMP B1
3136       // B1:
3137       // B2:
3138       //
3139       // Similarly it branches to B2 only if E && NP. That is why this condition
3140       // is named with COND_E_AND_NP.
3141       BranchCode = X86::COND_E_AND_NP;
3142     } else
3143       return true;
3144 
3145     // Update the MachineOperand.
3146     Cond[0].setImm(BranchCode);
3147     CondBranches.push_back(&*I);
3148   }
3149 
3150   return false;
3151 }
3152 
3153 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3154                                  MachineBasicBlock *&TBB,
3155                                  MachineBasicBlock *&FBB,
3156                                  SmallVectorImpl<MachineOperand> &Cond,
3157                                  bool AllowModify) const {
3158   SmallVector<MachineInstr *, 4> CondBranches;
3159   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3160 }
3161 
3162 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3163                                           MachineBranchPredicate &MBP,
3164                                           bool AllowModify) const {
3165   using namespace std::placeholders;
3166 
3167   SmallVector<MachineOperand, 4> Cond;
3168   SmallVector<MachineInstr *, 4> CondBranches;
3169   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3170                         AllowModify))
3171     return true;
3172 
3173   if (Cond.size() != 1)
3174     return true;
3175 
3176   assert(MBP.TrueDest && "expected!");
3177 
3178   if (!MBP.FalseDest)
3179     MBP.FalseDest = MBB.getNextNode();
3180 
3181   const TargetRegisterInfo *TRI = &getRegisterInfo();
3182 
3183   MachineInstr *ConditionDef = nullptr;
3184   bool SingleUseCondition = true;
3185 
3186   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3187     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3188       ConditionDef = &*I;
3189       break;
3190     }
3191 
3192     if (I->readsRegister(X86::EFLAGS, TRI))
3193       SingleUseCondition = false;
3194   }
3195 
3196   if (!ConditionDef)
3197     return true;
3198 
3199   if (SingleUseCondition) {
3200     for (auto *Succ : MBB.successors())
3201       if (Succ->isLiveIn(X86::EFLAGS))
3202         SingleUseCondition = false;
3203   }
3204 
3205   MBP.ConditionDef = ConditionDef;
3206   MBP.SingleUseCondition = SingleUseCondition;
3207 
3208   // Currently we only recognize the simple pattern:
3209   //
3210   //   test %reg, %reg
3211   //   je %label
3212   //
3213   const unsigned TestOpcode =
3214       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3215 
3216   if (ConditionDef->getOpcode() == TestOpcode &&
3217       ConditionDef->getNumOperands() == 3 &&
3218       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3219       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3220     MBP.LHS = ConditionDef->getOperand(0);
3221     MBP.RHS = MachineOperand::CreateImm(0);
3222     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3223                         ? MachineBranchPredicate::PRED_NE
3224                         : MachineBranchPredicate::PRED_EQ;
3225     return false;
3226   }
3227 
3228   return true;
3229 }
3230 
3231 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3232                                     int *BytesRemoved) const {
3233   assert(!BytesRemoved && "code size not handled");
3234 
3235   MachineBasicBlock::iterator I = MBB.end();
3236   unsigned Count = 0;
3237 
3238   while (I != MBB.begin()) {
3239     --I;
3240     if (I->isDebugInstr())
3241       continue;
3242     if (I->getOpcode() != X86::JMP_1 &&
3243         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3244       break;
3245     // Remove the branch.
3246     I->eraseFromParent();
3247     I = MBB.end();
3248     ++Count;
3249   }
3250 
3251   return Count;
3252 }
3253 
3254 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3255                                     MachineBasicBlock *TBB,
3256                                     MachineBasicBlock *FBB,
3257                                     ArrayRef<MachineOperand> Cond,
3258                                     const DebugLoc &DL,
3259                                     int *BytesAdded) const {
3260   // Shouldn't be a fall through.
3261   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3262   assert((Cond.size() == 1 || Cond.size() == 0) &&
3263          "X86 branch conditions have one component!");
3264   assert(!BytesAdded && "code size not handled");
3265 
3266   if (Cond.empty()) {
3267     // Unconditional branch?
3268     assert(!FBB && "Unconditional branch with multiple successors!");
3269     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3270     return 1;
3271   }
3272 
3273   // If FBB is null, it is implied to be a fall-through block.
3274   bool FallThru = FBB == nullptr;
3275 
3276   // Conditional branch.
3277   unsigned Count = 0;
3278   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3279   switch (CC) {
3280   case X86::COND_NE_OR_P:
3281     // Synthesize NE_OR_P with two branches.
3282     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3283     ++Count;
3284     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3285     ++Count;
3286     break;
3287   case X86::COND_E_AND_NP:
3288     // Use the next block of MBB as FBB if it is null.
3289     if (FBB == nullptr) {
3290       FBB = getFallThroughMBB(&MBB, TBB);
3291       assert(FBB && "MBB cannot be the last block in function when the false "
3292                     "body is a fall-through.");
3293     }
3294     // Synthesize COND_E_AND_NP with two branches.
3295     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3296     ++Count;
3297     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3298     ++Count;
3299     break;
3300   default: {
3301     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3302     ++Count;
3303   }
3304   }
3305   if (!FallThru) {
3306     // Two-way Conditional branch. Insert the second branch.
3307     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3308     ++Count;
3309   }
3310   return Count;
3311 }
3312 
3313 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3314                                    ArrayRef<MachineOperand> Cond,
3315                                    Register DstReg, Register TrueReg,
3316                                    Register FalseReg, int &CondCycles,
3317                                    int &TrueCycles, int &FalseCycles) const {
3318   // Not all subtargets have cmov instructions.
3319   if (!Subtarget.hasCMov())
3320     return false;
3321   if (Cond.size() != 1)
3322     return false;
3323   // We cannot do the composite conditions, at least not in SSA form.
3324   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3325     return false;
3326 
3327   // Check register classes.
3328   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3329   const TargetRegisterClass *RC =
3330     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3331   if (!RC)
3332     return false;
3333 
3334   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3335   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3336       X86::GR32RegClass.hasSubClassEq(RC) ||
3337       X86::GR64RegClass.hasSubClassEq(RC)) {
3338     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3339     // Bridge. Probably Ivy Bridge as well.
3340     CondCycles = 2;
3341     TrueCycles = 2;
3342     FalseCycles = 2;
3343     return true;
3344   }
3345 
3346   // Can't do vectors.
3347   return false;
3348 }
3349 
3350 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3351                                 MachineBasicBlock::iterator I,
3352                                 const DebugLoc &DL, Register DstReg,
3353                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3354                                 Register FalseReg) const {
3355   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3356   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3357   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3358   assert(Cond.size() == 1 && "Invalid Cond array");
3359   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3360                                     false /*HasMemoryOperand*/);
3361   BuildMI(MBB, I, DL, get(Opc), DstReg)
3362       .addReg(FalseReg)
3363       .addReg(TrueReg)
3364       .addImm(Cond[0].getImm());
3365 }
3366 
3367 /// Test if the given register is a physical h register.
3368 static bool isHReg(unsigned Reg) {
3369   return X86::GR8_ABCD_HRegClass.contains(Reg);
3370 }
3371 
3372 // Try and copy between VR128/VR64 and GR64 registers.
3373 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3374                                         const X86Subtarget &Subtarget) {
3375   bool HasAVX = Subtarget.hasAVX();
3376   bool HasAVX512 = Subtarget.hasAVX512();
3377 
3378   // SrcReg(MaskReg) -> DestReg(GR64)
3379   // SrcReg(MaskReg) -> DestReg(GR32)
3380 
3381   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3382   if (X86::VK16RegClass.contains(SrcReg)) {
3383     if (X86::GR64RegClass.contains(DestReg)) {
3384       assert(Subtarget.hasBWI());
3385       return X86::KMOVQrk;
3386     }
3387     if (X86::GR32RegClass.contains(DestReg))
3388       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3389   }
3390 
3391   // SrcReg(GR64) -> DestReg(MaskReg)
3392   // SrcReg(GR32) -> DestReg(MaskReg)
3393 
3394   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3395   if (X86::VK16RegClass.contains(DestReg)) {
3396     if (X86::GR64RegClass.contains(SrcReg)) {
3397       assert(Subtarget.hasBWI());
3398       return X86::KMOVQkr;
3399     }
3400     if (X86::GR32RegClass.contains(SrcReg))
3401       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3402   }
3403 
3404 
3405   // SrcReg(VR128) -> DestReg(GR64)
3406   // SrcReg(VR64)  -> DestReg(GR64)
3407   // SrcReg(GR64)  -> DestReg(VR128)
3408   // SrcReg(GR64)  -> DestReg(VR64)
3409 
3410   if (X86::GR64RegClass.contains(DestReg)) {
3411     if (X86::VR128XRegClass.contains(SrcReg))
3412       // Copy from a VR128 register to a GR64 register.
3413       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3414              HasAVX    ? X86::VMOVPQIto64rr  :
3415                          X86::MOVPQIto64rr;
3416     if (X86::VR64RegClass.contains(SrcReg))
3417       // Copy from a VR64 register to a GR64 register.
3418       return X86::MMX_MOVD64from64rr;
3419   } else if (X86::GR64RegClass.contains(SrcReg)) {
3420     // Copy from a GR64 register to a VR128 register.
3421     if (X86::VR128XRegClass.contains(DestReg))
3422       return HasAVX512 ? X86::VMOV64toPQIZrr :
3423              HasAVX    ? X86::VMOV64toPQIrr  :
3424                          X86::MOV64toPQIrr;
3425     // Copy from a GR64 register to a VR64 register.
3426     if (X86::VR64RegClass.contains(DestReg))
3427       return X86::MMX_MOVD64to64rr;
3428   }
3429 
3430   // SrcReg(VR128) -> DestReg(GR32)
3431   // SrcReg(GR32)  -> DestReg(VR128)
3432 
3433   if (X86::GR32RegClass.contains(DestReg) &&
3434       X86::VR128XRegClass.contains(SrcReg))
3435     // Copy from a VR128 register to a GR32 register.
3436     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3437            HasAVX    ? X86::VMOVPDI2DIrr  :
3438                        X86::MOVPDI2DIrr;
3439 
3440   if (X86::VR128XRegClass.contains(DestReg) &&
3441       X86::GR32RegClass.contains(SrcReg))
3442     // Copy from a VR128 register to a VR128 register.
3443     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3444            HasAVX    ? X86::VMOVDI2PDIrr  :
3445                        X86::MOVDI2PDIrr;
3446   return 0;
3447 }
3448 
3449 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3450                                MachineBasicBlock::iterator MI,
3451                                const DebugLoc &DL, MCRegister DestReg,
3452                                MCRegister SrcReg, bool KillSrc) const {
3453   // First deal with the normal symmetric copies.
3454   bool HasAVX = Subtarget.hasAVX();
3455   bool HasVLX = Subtarget.hasVLX();
3456   unsigned Opc = 0;
3457   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3458     Opc = X86::MOV64rr;
3459   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3460     Opc = X86::MOV32rr;
3461   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3462     Opc = X86::MOV16rr;
3463   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3464     // Copying to or from a physical H register on x86-64 requires a NOREX
3465     // move.  Otherwise use a normal move.
3466     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3467         Subtarget.is64Bit()) {
3468       Opc = X86::MOV8rr_NOREX;
3469       // Both operands must be encodable without an REX prefix.
3470       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3471              "8-bit H register can not be copied outside GR8_NOREX");
3472     } else
3473       Opc = X86::MOV8rr;
3474   }
3475   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3476     Opc = X86::MMX_MOVQ64rr;
3477   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3478     if (HasVLX)
3479       Opc = X86::VMOVAPSZ128rr;
3480     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3481       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3482     else {
3483       // If this an extended register and we don't have VLX we need to use a
3484       // 512-bit move.
3485       Opc = X86::VMOVAPSZrr;
3486       const TargetRegisterInfo *TRI = &getRegisterInfo();
3487       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3488                                          &X86::VR512RegClass);
3489       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3490                                         &X86::VR512RegClass);
3491     }
3492   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3493     if (HasVLX)
3494       Opc = X86::VMOVAPSZ256rr;
3495     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3496       Opc = X86::VMOVAPSYrr;
3497     else {
3498       // If this an extended register and we don't have VLX we need to use a
3499       // 512-bit move.
3500       Opc = X86::VMOVAPSZrr;
3501       const TargetRegisterInfo *TRI = &getRegisterInfo();
3502       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3503                                          &X86::VR512RegClass);
3504       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3505                                         &X86::VR512RegClass);
3506     }
3507   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3508     Opc = X86::VMOVAPSZrr;
3509   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3510   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3511     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3512   if (!Opc)
3513     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3514 
3515   if (Opc) {
3516     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3517       .addReg(SrcReg, getKillRegState(KillSrc));
3518     return;
3519   }
3520 
3521   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3522     // FIXME: We use a fatal error here because historically LLVM has tried
3523     // lower some of these physreg copies and we want to ensure we get
3524     // reasonable bug reports if someone encounters a case no other testing
3525     // found. This path should be removed after the LLVM 7 release.
3526     report_fatal_error("Unable to copy EFLAGS physical register!");
3527   }
3528 
3529   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3530                     << RI.getName(DestReg) << '\n');
3531   report_fatal_error("Cannot emit physreg copy instruction");
3532 }
3533 
3534 Optional<DestSourcePair>
3535 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3536   if (MI.isMoveReg())
3537     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3538   return None;
3539 }
3540 
3541 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3542                                       const TargetRegisterClass *RC,
3543                                       bool isStackAligned,
3544                                       const X86Subtarget &STI,
3545                                       bool load) {
3546   bool HasAVX = STI.hasAVX();
3547   bool HasAVX512 = STI.hasAVX512();
3548   bool HasVLX = STI.hasVLX();
3549 
3550   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3551   default:
3552     llvm_unreachable("Unknown spill size");
3553   case 1:
3554     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3555     if (STI.is64Bit())
3556       // Copying to or from a physical H register on x86-64 requires a NOREX
3557       // move.  Otherwise use a normal move.
3558       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3559         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3560     return load ? X86::MOV8rm : X86::MOV8mr;
3561   case 2:
3562     if (X86::VK16RegClass.hasSubClassEq(RC))
3563       return load ? X86::KMOVWkm : X86::KMOVWmk;
3564     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3565     return load ? X86::MOV16rm : X86::MOV16mr;
3566   case 4:
3567     if (X86::GR32RegClass.hasSubClassEq(RC))
3568       return load ? X86::MOV32rm : X86::MOV32mr;
3569     if (X86::FR32XRegClass.hasSubClassEq(RC))
3570       return load ?
3571         (HasAVX512 ? X86::VMOVSSZrm_alt :
3572          HasAVX    ? X86::VMOVSSrm_alt :
3573                      X86::MOVSSrm_alt) :
3574         (HasAVX512 ? X86::VMOVSSZmr :
3575          HasAVX    ? X86::VMOVSSmr :
3576                      X86::MOVSSmr);
3577     if (X86::RFP32RegClass.hasSubClassEq(RC))
3578       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3579     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3580       assert(STI.hasBWI() && "KMOVD requires BWI");
3581       return load ? X86::KMOVDkm : X86::KMOVDmk;
3582     }
3583     // All of these mask pair classes have the same spill size, the same kind
3584     // of kmov instructions can be used with all of them.
3585     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3586         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3587         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3588         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3589         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3590       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3591     llvm_unreachable("Unknown 4-byte regclass");
3592   case 8:
3593     if (X86::GR64RegClass.hasSubClassEq(RC))
3594       return load ? X86::MOV64rm : X86::MOV64mr;
3595     if (X86::FR64XRegClass.hasSubClassEq(RC))
3596       return load ?
3597         (HasAVX512 ? X86::VMOVSDZrm_alt :
3598          HasAVX    ? X86::VMOVSDrm_alt :
3599                      X86::MOVSDrm_alt) :
3600         (HasAVX512 ? X86::VMOVSDZmr :
3601          HasAVX    ? X86::VMOVSDmr :
3602                      X86::MOVSDmr);
3603     if (X86::VR64RegClass.hasSubClassEq(RC))
3604       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3605     if (X86::RFP64RegClass.hasSubClassEq(RC))
3606       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3607     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3608       assert(STI.hasBWI() && "KMOVQ requires BWI");
3609       return load ? X86::KMOVQkm : X86::KMOVQmk;
3610     }
3611     llvm_unreachable("Unknown 8-byte regclass");
3612   case 10:
3613     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3614     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3615   case 16: {
3616     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3617       // If stack is realigned we can use aligned stores.
3618       if (isStackAligned)
3619         return load ?
3620           (HasVLX    ? X86::VMOVAPSZ128rm :
3621            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3622            HasAVX    ? X86::VMOVAPSrm :
3623                        X86::MOVAPSrm):
3624           (HasVLX    ? X86::VMOVAPSZ128mr :
3625            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3626            HasAVX    ? X86::VMOVAPSmr :
3627                        X86::MOVAPSmr);
3628       else
3629         return load ?
3630           (HasVLX    ? X86::VMOVUPSZ128rm :
3631            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3632            HasAVX    ? X86::VMOVUPSrm :
3633                        X86::MOVUPSrm):
3634           (HasVLX    ? X86::VMOVUPSZ128mr :
3635            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3636            HasAVX    ? X86::VMOVUPSmr :
3637                        X86::MOVUPSmr);
3638     }
3639     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3640       if (STI.is64Bit())
3641         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3642       else
3643         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3644     }
3645     llvm_unreachable("Unknown 16-byte regclass");
3646   }
3647   case 32:
3648     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3649     // If stack is realigned we can use aligned stores.
3650     if (isStackAligned)
3651       return load ?
3652         (HasVLX    ? X86::VMOVAPSZ256rm :
3653          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3654                      X86::VMOVAPSYrm) :
3655         (HasVLX    ? X86::VMOVAPSZ256mr :
3656          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3657                      X86::VMOVAPSYmr);
3658     else
3659       return load ?
3660         (HasVLX    ? X86::VMOVUPSZ256rm :
3661          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3662                      X86::VMOVUPSYrm) :
3663         (HasVLX    ? X86::VMOVUPSZ256mr :
3664          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3665                      X86::VMOVUPSYmr);
3666   case 64:
3667     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3668     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3669     if (isStackAligned)
3670       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3671     else
3672       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3673   }
3674 }
3675 
3676 bool X86InstrInfo::getMemOperandsWithOffset(
3677     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3678     int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
3679   const MCInstrDesc &Desc = MemOp.getDesc();
3680   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3681   if (MemRefBegin < 0)
3682     return false;
3683 
3684   MemRefBegin += X86II::getOperandBias(Desc);
3685 
3686   const MachineOperand *BaseOp =
3687       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3688   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3689     return false;
3690 
3691   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3692     return false;
3693 
3694   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3695       X86::NoRegister)
3696     return false;
3697 
3698   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3699 
3700   // Displacement can be symbolic
3701   if (!DispMO.isImm())
3702     return false;
3703 
3704   Offset = DispMO.getImm();
3705 
3706   if (!BaseOp->isReg())
3707     return false;
3708 
3709   OffsetIsScalable = false;
3710   BaseOps.push_back(BaseOp);
3711   return true;
3712 }
3713 
3714 static unsigned getStoreRegOpcode(unsigned SrcReg,
3715                                   const TargetRegisterClass *RC,
3716                                   bool isStackAligned,
3717                                   const X86Subtarget &STI) {
3718   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3719 }
3720 
3721 
3722 static unsigned getLoadRegOpcode(unsigned DestReg,
3723                                  const TargetRegisterClass *RC,
3724                                  bool isStackAligned,
3725                                  const X86Subtarget &STI) {
3726   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3727 }
3728 
3729 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3730                                        MachineBasicBlock::iterator MI,
3731                                        Register SrcReg, bool isKill, int FrameIdx,
3732                                        const TargetRegisterClass *RC,
3733                                        const TargetRegisterInfo *TRI) const {
3734   const MachineFunction &MF = *MBB.getParent();
3735   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3736          "Stack slot too small for store");
3737   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3738   bool isAligned =
3739       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3740       RI.canRealignStack(MF);
3741   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3742   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3743     .addReg(SrcReg, getKillRegState(isKill));
3744 }
3745 
3746 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3747                                         MachineBasicBlock::iterator MI,
3748                                         Register DestReg, int FrameIdx,
3749                                         const TargetRegisterClass *RC,
3750                                         const TargetRegisterInfo *TRI) const {
3751   const MachineFunction &MF = *MBB.getParent();
3752   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3753   bool isAligned =
3754       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3755       RI.canRealignStack(MF);
3756   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3757   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3758 }
3759 
3760 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3761                                   Register &SrcReg2, int &CmpMask,
3762                                   int &CmpValue) const {
3763   switch (MI.getOpcode()) {
3764   default: break;
3765   case X86::CMP64ri32:
3766   case X86::CMP64ri8:
3767   case X86::CMP32ri:
3768   case X86::CMP32ri8:
3769   case X86::CMP16ri:
3770   case X86::CMP16ri8:
3771   case X86::CMP8ri:
3772     SrcReg = MI.getOperand(0).getReg();
3773     SrcReg2 = 0;
3774     if (MI.getOperand(1).isImm()) {
3775       CmpMask = ~0;
3776       CmpValue = MI.getOperand(1).getImm();
3777     } else {
3778       CmpMask = CmpValue = 0;
3779     }
3780     return true;
3781   // A SUB can be used to perform comparison.
3782   case X86::SUB64rm:
3783   case X86::SUB32rm:
3784   case X86::SUB16rm:
3785   case X86::SUB8rm:
3786     SrcReg = MI.getOperand(1).getReg();
3787     SrcReg2 = 0;
3788     CmpMask = 0;
3789     CmpValue = 0;
3790     return true;
3791   case X86::SUB64rr:
3792   case X86::SUB32rr:
3793   case X86::SUB16rr:
3794   case X86::SUB8rr:
3795     SrcReg = MI.getOperand(1).getReg();
3796     SrcReg2 = MI.getOperand(2).getReg();
3797     CmpMask = 0;
3798     CmpValue = 0;
3799     return true;
3800   case X86::SUB64ri32:
3801   case X86::SUB64ri8:
3802   case X86::SUB32ri:
3803   case X86::SUB32ri8:
3804   case X86::SUB16ri:
3805   case X86::SUB16ri8:
3806   case X86::SUB8ri:
3807     SrcReg = MI.getOperand(1).getReg();
3808     SrcReg2 = 0;
3809     if (MI.getOperand(2).isImm()) {
3810       CmpMask = ~0;
3811       CmpValue = MI.getOperand(2).getImm();
3812     } else {
3813       CmpMask = CmpValue = 0;
3814     }
3815     return true;
3816   case X86::CMP64rr:
3817   case X86::CMP32rr:
3818   case X86::CMP16rr:
3819   case X86::CMP8rr:
3820     SrcReg = MI.getOperand(0).getReg();
3821     SrcReg2 = MI.getOperand(1).getReg();
3822     CmpMask = 0;
3823     CmpValue = 0;
3824     return true;
3825   case X86::TEST8rr:
3826   case X86::TEST16rr:
3827   case X86::TEST32rr:
3828   case X86::TEST64rr:
3829     SrcReg = MI.getOperand(0).getReg();
3830     if (MI.getOperand(1).getReg() != SrcReg)
3831       return false;
3832     // Compare against zero.
3833     SrcReg2 = 0;
3834     CmpMask = ~0;
3835     CmpValue = 0;
3836     return true;
3837   }
3838   return false;
3839 }
3840 
3841 /// Check whether the first instruction, whose only
3842 /// purpose is to update flags, can be made redundant.
3843 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3844 /// This function can be extended later on.
3845 /// SrcReg, SrcRegs: register operands for FlagI.
3846 /// ImmValue: immediate for FlagI if it takes an immediate.
3847 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3848                                         Register SrcReg, Register SrcReg2,
3849                                         int ImmMask, int ImmValue,
3850                                         const MachineInstr &OI) {
3851   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3852        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3853        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3854        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3855       ((OI.getOperand(1).getReg() == SrcReg &&
3856         OI.getOperand(2).getReg() == SrcReg2) ||
3857        (OI.getOperand(1).getReg() == SrcReg2 &&
3858         OI.getOperand(2).getReg() == SrcReg)))
3859     return true;
3860 
3861   if (ImmMask != 0 &&
3862       ((FlagI.getOpcode() == X86::CMP64ri32 &&
3863         OI.getOpcode() == X86::SUB64ri32) ||
3864        (FlagI.getOpcode() == X86::CMP64ri8 &&
3865         OI.getOpcode() == X86::SUB64ri8) ||
3866        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3867        (FlagI.getOpcode() == X86::CMP32ri8 &&
3868         OI.getOpcode() == X86::SUB32ri8) ||
3869        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3870        (FlagI.getOpcode() == X86::CMP16ri8 &&
3871         OI.getOpcode() == X86::SUB16ri8) ||
3872        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3873       OI.getOperand(1).getReg() == SrcReg &&
3874       OI.getOperand(2).getImm() == ImmValue)
3875     return true;
3876   return false;
3877 }
3878 
3879 /// Check whether the definition can be converted
3880 /// to remove a comparison against zero.
3881 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3882   NoSignFlag = false;
3883 
3884   switch (MI.getOpcode()) {
3885   default: return false;
3886 
3887   // The shift instructions only modify ZF if their shift count is non-zero.
3888   // N.B.: The processor truncates the shift count depending on the encoding.
3889   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3890   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3891      return getTruncatedShiftCount(MI, 2) != 0;
3892 
3893   // Some left shift instructions can be turned into LEA instructions but only
3894   // if their flags aren't used. Avoid transforming such instructions.
3895   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3896     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3897     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3898     return ShAmt != 0;
3899   }
3900 
3901   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3902   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3903      return getTruncatedShiftCount(MI, 3) != 0;
3904 
3905   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3906   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3907   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3908   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3909   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3910   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3911   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3912   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3913   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3914   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3915   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3916   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3917   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3918   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3919   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3920   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3921   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3922   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3923   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3924   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3925   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3926   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3927   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3928   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3929   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3930   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3931   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3932   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3933   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3934   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3935   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3936   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
3937   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3938   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
3939   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
3940   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
3941   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
3942   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3943   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3944   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3945   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3946   case X86::ANDN32rr:  case X86::ANDN32rm:
3947   case X86::ANDN64rr:  case X86::ANDN64rm:
3948   case X86::BLSI32rr:  case X86::BLSI32rm:
3949   case X86::BLSI64rr:  case X86::BLSI64rm:
3950   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3951   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3952   case X86::BLSR32rr:  case X86::BLSR32rm:
3953   case X86::BLSR64rr:  case X86::BLSR64rm:
3954   case X86::BZHI32rr:  case X86::BZHI32rm:
3955   case X86::BZHI64rr:  case X86::BZHI64rm:
3956   case X86::LZCNT16rr: case X86::LZCNT16rm:
3957   case X86::LZCNT32rr: case X86::LZCNT32rm:
3958   case X86::LZCNT64rr: case X86::LZCNT64rm:
3959   case X86::POPCNT16rr:case X86::POPCNT16rm:
3960   case X86::POPCNT32rr:case X86::POPCNT32rm:
3961   case X86::POPCNT64rr:case X86::POPCNT64rm:
3962   case X86::TZCNT16rr: case X86::TZCNT16rm:
3963   case X86::TZCNT32rr: case X86::TZCNT32rm:
3964   case X86::TZCNT64rr: case X86::TZCNT64rm:
3965   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3966   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3967   case X86::BLCI32rr:    case X86::BLCI32rm:
3968   case X86::BLCI64rr:    case X86::BLCI64rm:
3969   case X86::BLCIC32rr:   case X86::BLCIC32rm:
3970   case X86::BLCIC64rr:   case X86::BLCIC64rm:
3971   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
3972   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
3973   case X86::BLCS32rr:    case X86::BLCS32rm:
3974   case X86::BLCS64rr:    case X86::BLCS64rm:
3975   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3976   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3977   case X86::BLSIC32rr:   case X86::BLSIC32rm:
3978   case X86::BLSIC64rr:   case X86::BLSIC64rm:
3979   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
3980   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
3981   case X86::TZMSK32rr:   case X86::TZMSK32rm:
3982   case X86::TZMSK64rr:   case X86::TZMSK64rm:
3983     return true;
3984   case X86::BEXTR32rr:   case X86::BEXTR64rr:
3985   case X86::BEXTR32rm:   case X86::BEXTR64rm:
3986   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
3987   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
3988     // BEXTR doesn't update the sign flag so we can't use it.
3989     NoSignFlag = true;
3990     return true;
3991   }
3992 }
3993 
3994 /// Check whether the use can be converted to remove a comparison against zero.
3995 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3996   switch (MI.getOpcode()) {
3997   default: return X86::COND_INVALID;
3998   case X86::NEG8r:
3999   case X86::NEG16r:
4000   case X86::NEG32r:
4001   case X86::NEG64r:
4002     return X86::COND_AE;
4003   case X86::LZCNT16rr:
4004   case X86::LZCNT32rr:
4005   case X86::LZCNT64rr:
4006     return X86::COND_B;
4007   case X86::POPCNT16rr:
4008   case X86::POPCNT32rr:
4009   case X86::POPCNT64rr:
4010     return X86::COND_E;
4011   case X86::TZCNT16rr:
4012   case X86::TZCNT32rr:
4013   case X86::TZCNT64rr:
4014     return X86::COND_B;
4015   case X86::BSF16rr:
4016   case X86::BSF32rr:
4017   case X86::BSF64rr:
4018   case X86::BSR16rr:
4019   case X86::BSR32rr:
4020   case X86::BSR64rr:
4021     return X86::COND_E;
4022   case X86::BLSI32rr:
4023   case X86::BLSI64rr:
4024     return X86::COND_AE;
4025   case X86::BLSR32rr:
4026   case X86::BLSR64rr:
4027   case X86::BLSMSK32rr:
4028   case X86::BLSMSK64rr:
4029     return X86::COND_B;
4030   // TODO: TBM instructions.
4031   }
4032 }
4033 
4034 /// Check if there exists an earlier instruction that
4035 /// operates on the same source operands and sets flags in the same way as
4036 /// Compare; remove Compare if possible.
4037 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4038                                         Register SrcReg2, int CmpMask,
4039                                         int CmpValue,
4040                                         const MachineRegisterInfo *MRI) const {
4041   // Check whether we can replace SUB with CMP.
4042   switch (CmpInstr.getOpcode()) {
4043   default: break;
4044   case X86::SUB64ri32:
4045   case X86::SUB64ri8:
4046   case X86::SUB32ri:
4047   case X86::SUB32ri8:
4048   case X86::SUB16ri:
4049   case X86::SUB16ri8:
4050   case X86::SUB8ri:
4051   case X86::SUB64rm:
4052   case X86::SUB32rm:
4053   case X86::SUB16rm:
4054   case X86::SUB8rm:
4055   case X86::SUB64rr:
4056   case X86::SUB32rr:
4057   case X86::SUB16rr:
4058   case X86::SUB8rr: {
4059     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4060       return false;
4061     // There is no use of the destination register, we can replace SUB with CMP.
4062     unsigned NewOpcode = 0;
4063     switch (CmpInstr.getOpcode()) {
4064     default: llvm_unreachable("Unreachable!");
4065     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4066     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4067     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4068     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4069     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4070     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4071     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4072     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4073     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4074     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4075     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4076     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4077     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4078     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4079     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4080     }
4081     CmpInstr.setDesc(get(NewOpcode));
4082     CmpInstr.RemoveOperand(0);
4083     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4084     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4085         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4086       return false;
4087   }
4088   }
4089 
4090   // Get the unique definition of SrcReg.
4091   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4092   if (!MI) return false;
4093 
4094   // CmpInstr is the first instruction of the BB.
4095   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4096 
4097   // If we are comparing against zero, check whether we can use MI to update
4098   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4099   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4100   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4101     return false;
4102 
4103   // If we have a use of the source register between the def and our compare
4104   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4105   // right way.
4106   bool ShouldUpdateCC = false;
4107   bool NoSignFlag = false;
4108   X86::CondCode NewCC = X86::COND_INVALID;
4109   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
4110     // Scan forward from the use until we hit the use we're looking for or the
4111     // compare instruction.
4112     for (MachineBasicBlock::iterator J = MI;; ++J) {
4113       // Do we have a convertible instruction?
4114       NewCC = isUseDefConvertible(*J);
4115       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4116           J->getOperand(1).getReg() == SrcReg) {
4117         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4118         ShouldUpdateCC = true; // Update CC later on.
4119         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4120         // with the new def.
4121         Def = J;
4122         MI = &*Def;
4123         break;
4124       }
4125 
4126       if (J == I)
4127         return false;
4128     }
4129   }
4130 
4131   // We are searching for an earlier instruction that can make CmpInstr
4132   // redundant and that instruction will be saved in Sub.
4133   MachineInstr *Sub = nullptr;
4134   const TargetRegisterInfo *TRI = &getRegisterInfo();
4135 
4136   // We iterate backward, starting from the instruction before CmpInstr and
4137   // stop when reaching the definition of a source register or done with the BB.
4138   // RI points to the instruction before CmpInstr.
4139   // If the definition is in this basic block, RE points to the definition;
4140   // otherwise, RE is the rend of the basic block.
4141   MachineBasicBlock::reverse_iterator
4142       RI = ++I.getReverse(),
4143       RE = CmpInstr.getParent() == MI->getParent()
4144                ? Def.getReverse() /* points to MI */
4145                : CmpInstr.getParent()->rend();
4146   MachineInstr *Movr0Inst = nullptr;
4147   for (; RI != RE; ++RI) {
4148     MachineInstr &Instr = *RI;
4149     // Check whether CmpInstr can be made redundant by the current instruction.
4150     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4151                                            CmpValue, Instr)) {
4152       Sub = &Instr;
4153       break;
4154     }
4155 
4156     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4157         Instr.readsRegister(X86::EFLAGS, TRI)) {
4158       // This instruction modifies or uses EFLAGS.
4159 
4160       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4161       // They are safe to move up, if the definition to EFLAGS is dead and
4162       // earlier instructions do not read or write EFLAGS.
4163       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4164           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4165         Movr0Inst = &Instr;
4166         continue;
4167       }
4168 
4169       // We can't remove CmpInstr.
4170       return false;
4171     }
4172   }
4173 
4174   // Return false if no candidates exist.
4175   if (!IsCmpZero && !Sub)
4176     return false;
4177 
4178   bool IsSwapped =
4179       (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4180        Sub->getOperand(2).getReg() == SrcReg);
4181 
4182   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4183   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4184   // If we are done with the basic block, we need to check whether EFLAGS is
4185   // live-out.
4186   bool IsSafe = false;
4187   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4188   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4189   for (++I; I != E; ++I) {
4190     const MachineInstr &Instr = *I;
4191     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4192     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4193     // We should check the usage if this instruction uses and updates EFLAGS.
4194     if (!UseEFLAGS && ModifyEFLAGS) {
4195       // It is safe to remove CmpInstr if EFLAGS is updated again.
4196       IsSafe = true;
4197       break;
4198     }
4199     if (!UseEFLAGS && !ModifyEFLAGS)
4200       continue;
4201 
4202     // EFLAGS is used by this instruction.
4203     X86::CondCode OldCC = X86::COND_INVALID;
4204     if (IsCmpZero || IsSwapped) {
4205       // We decode the condition code from opcode.
4206       if (Instr.isBranch())
4207         OldCC = X86::getCondFromBranch(Instr);
4208       else {
4209         OldCC = X86::getCondFromSETCC(Instr);
4210         if (OldCC == X86::COND_INVALID)
4211           OldCC = X86::getCondFromCMov(Instr);
4212       }
4213       if (OldCC == X86::COND_INVALID) return false;
4214     }
4215     X86::CondCode ReplacementCC = X86::COND_INVALID;
4216     if (IsCmpZero) {
4217       switch (OldCC) {
4218       default: break;
4219       case X86::COND_A: case X86::COND_AE:
4220       case X86::COND_B: case X86::COND_BE:
4221       case X86::COND_G: case X86::COND_GE:
4222       case X86::COND_L: case X86::COND_LE:
4223       case X86::COND_O: case X86::COND_NO:
4224         // CF and OF are used, we can't perform this optimization.
4225         return false;
4226       case X86::COND_S: case X86::COND_NS:
4227         // If SF is used, but the instruction doesn't update the SF, then we
4228         // can't do the optimization.
4229         if (NoSignFlag)
4230           return false;
4231         break;
4232       }
4233 
4234       // If we're updating the condition code check if we have to reverse the
4235       // condition.
4236       if (ShouldUpdateCC)
4237         switch (OldCC) {
4238         default:
4239           return false;
4240         case X86::COND_E:
4241           ReplacementCC = NewCC;
4242           break;
4243         case X86::COND_NE:
4244           ReplacementCC = GetOppositeBranchCondition(NewCC);
4245           break;
4246         }
4247     } else if (IsSwapped) {
4248       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4249       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4250       // We swap the condition code and synthesize the new opcode.
4251       ReplacementCC = getSwappedCondition(OldCC);
4252       if (ReplacementCC == X86::COND_INVALID) return false;
4253     }
4254 
4255     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4256       // Push the MachineInstr to OpsToUpdate.
4257       // If it is safe to remove CmpInstr, the condition code of these
4258       // instructions will be modified.
4259       OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4260     }
4261     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4262       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4263       IsSafe = true;
4264       break;
4265     }
4266   }
4267 
4268   // If EFLAGS is not killed nor re-defined, we should check whether it is
4269   // live-out. If it is live-out, do not optimize.
4270   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4271     MachineBasicBlock *MBB = CmpInstr.getParent();
4272     for (MachineBasicBlock *Successor : MBB->successors())
4273       if (Successor->isLiveIn(X86::EFLAGS))
4274         return false;
4275   }
4276 
4277   // The instruction to be updated is either Sub or MI.
4278   Sub = IsCmpZero ? MI : Sub;
4279   // Move Movr0Inst to the appropriate place before Sub.
4280   if (Movr0Inst) {
4281     // Look backwards until we find a def that doesn't use the current EFLAGS.
4282     Def = Sub;
4283     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4284                                         InsertE = Sub->getParent()->rend();
4285     for (; InsertI != InsertE; ++InsertI) {
4286       MachineInstr *Instr = &*InsertI;
4287       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4288           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4289         Sub->getParent()->remove(Movr0Inst);
4290         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4291                                    Movr0Inst);
4292         break;
4293       }
4294     }
4295     if (InsertI == InsertE)
4296       return false;
4297   }
4298 
4299   // Make sure Sub instruction defines EFLAGS and mark the def live.
4300   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4301   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4302   FlagDef->setIsDead(false);
4303 
4304   CmpInstr.eraseFromParent();
4305 
4306   // Modify the condition code of instructions in OpsToUpdate.
4307   for (auto &Op : OpsToUpdate) {
4308     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4309         .setImm(Op.second);
4310   }
4311   return true;
4312 }
4313 
4314 /// Try to remove the load by folding it to a register
4315 /// operand at the use. We fold the load instructions if load defines a virtual
4316 /// register, the virtual register is used once in the same BB, and the
4317 /// instructions in-between do not load or store, and have no side effects.
4318 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4319                                               const MachineRegisterInfo *MRI,
4320                                               unsigned &FoldAsLoadDefReg,
4321                                               MachineInstr *&DefMI) const {
4322   // Check whether we can move DefMI here.
4323   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4324   assert(DefMI);
4325   bool SawStore = false;
4326   if (!DefMI->isSafeToMove(nullptr, SawStore))
4327     return nullptr;
4328 
4329   // Collect information about virtual register operands of MI.
4330   SmallVector<unsigned, 1> SrcOperandIds;
4331   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4332     MachineOperand &MO = MI.getOperand(i);
4333     if (!MO.isReg())
4334       continue;
4335     Register Reg = MO.getReg();
4336     if (Reg != FoldAsLoadDefReg)
4337       continue;
4338     // Do not fold if we have a subreg use or a def.
4339     if (MO.getSubReg() || MO.isDef())
4340       return nullptr;
4341     SrcOperandIds.push_back(i);
4342   }
4343   if (SrcOperandIds.empty())
4344     return nullptr;
4345 
4346   // Check whether we can fold the def into SrcOperandId.
4347   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4348     FoldAsLoadDefReg = 0;
4349     return FoldMI;
4350   }
4351 
4352   return nullptr;
4353 }
4354 
4355 /// Expand a single-def pseudo instruction to a two-addr
4356 /// instruction with two undef reads of the register being defined.
4357 /// This is used for mapping:
4358 ///   %xmm4 = V_SET0
4359 /// to:
4360 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4361 ///
4362 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4363                              const MCInstrDesc &Desc) {
4364   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4365   Register Reg = MIB.getReg(0);
4366   MIB->setDesc(Desc);
4367 
4368   // MachineInstr::addOperand() will insert explicit operands before any
4369   // implicit operands.
4370   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4371   // But we don't trust that.
4372   assert(MIB.getReg(1) == Reg &&
4373          MIB.getReg(2) == Reg && "Misplaced operand");
4374   return true;
4375 }
4376 
4377 /// Expand a single-def pseudo instruction to a two-addr
4378 /// instruction with two %k0 reads.
4379 /// This is used for mapping:
4380 ///   %k4 = K_SET1
4381 /// to:
4382 ///   %k4 = KXNORrr %k0, %k0
4383 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
4384                             const MCInstrDesc &Desc, unsigned Reg) {
4385   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4386   MIB->setDesc(Desc);
4387   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4388   return true;
4389 }
4390 
4391 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4392                           bool MinusOne) {
4393   MachineBasicBlock &MBB = *MIB->getParent();
4394   DebugLoc DL = MIB->getDebugLoc();
4395   Register Reg = MIB.getReg(0);
4396 
4397   // Insert the XOR.
4398   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4399       .addReg(Reg, RegState::Undef)
4400       .addReg(Reg, RegState::Undef);
4401 
4402   // Turn the pseudo into an INC or DEC.
4403   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4404   MIB.addReg(Reg);
4405 
4406   return true;
4407 }
4408 
4409 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4410                                const TargetInstrInfo &TII,
4411                                const X86Subtarget &Subtarget) {
4412   MachineBasicBlock &MBB = *MIB->getParent();
4413   DebugLoc DL = MIB->getDebugLoc();
4414   int64_t Imm = MIB->getOperand(1).getImm();
4415   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4416   MachineBasicBlock::iterator I = MIB.getInstr();
4417 
4418   int StackAdjustment;
4419 
4420   if (Subtarget.is64Bit()) {
4421     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4422            MIB->getOpcode() == X86::MOV32ImmSExti8);
4423 
4424     // Can't use push/pop lowering if the function might write to the red zone.
4425     X86MachineFunctionInfo *X86FI =
4426         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4427     if (X86FI->getUsesRedZone()) {
4428       MIB->setDesc(TII.get(MIB->getOpcode() ==
4429                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4430       return true;
4431     }
4432 
4433     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4434     // widen the register if necessary.
4435     StackAdjustment = 8;
4436     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4437     MIB->setDesc(TII.get(X86::POP64r));
4438     MIB->getOperand(0)
4439         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4440   } else {
4441     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4442     StackAdjustment = 4;
4443     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4444     MIB->setDesc(TII.get(X86::POP32r));
4445   }
4446   MIB->RemoveOperand(1);
4447   MIB->addImplicitDefUseOperands(*MBB.getParent());
4448 
4449   // Build CFI if necessary.
4450   MachineFunction &MF = *MBB.getParent();
4451   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4452   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4453   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4454   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4455   if (EmitCFI) {
4456     TFL->BuildCFI(MBB, I, DL,
4457         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4458     TFL->BuildCFI(MBB, std::next(I), DL,
4459         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4460   }
4461 
4462   return true;
4463 }
4464 
4465 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4466 // code sequence is needed for other targets.
4467 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4468                                  const TargetInstrInfo &TII) {
4469   MachineBasicBlock &MBB = *MIB->getParent();
4470   DebugLoc DL = MIB->getDebugLoc();
4471   Register Reg = MIB.getReg(0);
4472   const GlobalValue *GV =
4473       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4474   auto Flags = MachineMemOperand::MOLoad |
4475                MachineMemOperand::MODereferenceable |
4476                MachineMemOperand::MOInvariant;
4477   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4478       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4479   MachineBasicBlock::iterator I = MIB.getInstr();
4480 
4481   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4482       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4483       .addMemOperand(MMO);
4484   MIB->setDebugLoc(DL);
4485   MIB->setDesc(TII.get(X86::MOV64rm));
4486   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4487 }
4488 
4489 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4490   MachineBasicBlock &MBB = *MIB->getParent();
4491   MachineFunction &MF = *MBB.getParent();
4492   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4493   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4494   unsigned XorOp =
4495       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4496   MIB->setDesc(TII.get(XorOp));
4497   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4498   return true;
4499 }
4500 
4501 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4502 // but not VLX. If it uses an extended register we need to use an instruction
4503 // that loads the lower 128/256-bit, but is available with only AVX512F.
4504 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4505                             const TargetRegisterInfo *TRI,
4506                             const MCInstrDesc &LoadDesc,
4507                             const MCInstrDesc &BroadcastDesc,
4508                             unsigned SubIdx) {
4509   Register DestReg = MIB.getReg(0);
4510   // Check if DestReg is XMM16-31 or YMM16-31.
4511   if (TRI->getEncodingValue(DestReg) < 16) {
4512     // We can use a normal VEX encoded load.
4513     MIB->setDesc(LoadDesc);
4514   } else {
4515     // Use a 128/256-bit VBROADCAST instruction.
4516     MIB->setDesc(BroadcastDesc);
4517     // Change the destination to a 512-bit register.
4518     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4519     MIB->getOperand(0).setReg(DestReg);
4520   }
4521   return true;
4522 }
4523 
4524 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4525 // but not VLX. If it uses an extended register we need to use an instruction
4526 // that stores the lower 128/256-bit, but is available with only AVX512F.
4527 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4528                              const TargetRegisterInfo *TRI,
4529                              const MCInstrDesc &StoreDesc,
4530                              const MCInstrDesc &ExtractDesc,
4531                              unsigned SubIdx) {
4532   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4533   // Check if DestReg is XMM16-31 or YMM16-31.
4534   if (TRI->getEncodingValue(SrcReg) < 16) {
4535     // We can use a normal VEX encoded store.
4536     MIB->setDesc(StoreDesc);
4537   } else {
4538     // Use a VEXTRACTF instruction.
4539     MIB->setDesc(ExtractDesc);
4540     // Change the destination to a 512-bit register.
4541     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4542     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4543     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4544   }
4545 
4546   return true;
4547 }
4548 
4549 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4550   MIB->setDesc(Desc);
4551   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4552   // Temporarily remove the immediate so we can add another source register.
4553   MIB->RemoveOperand(2);
4554   // Add the register. Don't copy the kill flag if there is one.
4555   MIB.addReg(MIB.getReg(1),
4556              getUndefRegState(MIB->getOperand(1).isUndef()));
4557   // Add back the immediate.
4558   MIB.addImm(ShiftAmt);
4559   return true;
4560 }
4561 
4562 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4563   bool HasAVX = Subtarget.hasAVX();
4564   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4565   switch (MI.getOpcode()) {
4566   case X86::MOV32r0:
4567     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4568   case X86::MOV32r1:
4569     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4570   case X86::MOV32r_1:
4571     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4572   case X86::MOV32ImmSExti8:
4573   case X86::MOV64ImmSExti8:
4574     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4575   case X86::SETB_C32r:
4576     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4577   case X86::SETB_C64r:
4578     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4579   case X86::MMX_SET0:
4580     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4581   case X86::V_SET0:
4582   case X86::FsFLD0SS:
4583   case X86::FsFLD0SD:
4584   case X86::FsFLD0F128:
4585     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4586   case X86::AVX_SET0: {
4587     assert(HasAVX && "AVX not supported");
4588     const TargetRegisterInfo *TRI = &getRegisterInfo();
4589     Register SrcReg = MIB.getReg(0);
4590     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4591     MIB->getOperand(0).setReg(XReg);
4592     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4593     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4594     return true;
4595   }
4596   case X86::AVX512_128_SET0:
4597   case X86::AVX512_FsFLD0SS:
4598   case X86::AVX512_FsFLD0SD:
4599   case X86::AVX512_FsFLD0F128: {
4600     bool HasVLX = Subtarget.hasVLX();
4601     Register SrcReg = MIB.getReg(0);
4602     const TargetRegisterInfo *TRI = &getRegisterInfo();
4603     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4604       return Expand2AddrUndef(MIB,
4605                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4606     // Extended register without VLX. Use a larger XOR.
4607     SrcReg =
4608         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4609     MIB->getOperand(0).setReg(SrcReg);
4610     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4611   }
4612   case X86::AVX512_256_SET0:
4613   case X86::AVX512_512_SET0: {
4614     bool HasVLX = Subtarget.hasVLX();
4615     Register SrcReg = MIB.getReg(0);
4616     const TargetRegisterInfo *TRI = &getRegisterInfo();
4617     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4618       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4619       MIB->getOperand(0).setReg(XReg);
4620       Expand2AddrUndef(MIB,
4621                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4622       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4623       return true;
4624     }
4625     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4626       // No VLX so we must reference a zmm.
4627       unsigned ZReg =
4628         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4629       MIB->getOperand(0).setReg(ZReg);
4630     }
4631     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4632   }
4633   case X86::V_SETALLONES:
4634     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4635   case X86::AVX2_SETALLONES:
4636     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4637   case X86::AVX1_SETALLONES: {
4638     Register Reg = MIB.getReg(0);
4639     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4640     MIB->setDesc(get(X86::VCMPPSYrri));
4641     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4642     return true;
4643   }
4644   case X86::AVX512_512_SETALLONES: {
4645     Register Reg = MIB.getReg(0);
4646     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4647     // VPTERNLOGD needs 3 register inputs and an immediate.
4648     // 0xff will return 1s for any input.
4649     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4650        .addReg(Reg, RegState::Undef).addImm(0xff);
4651     return true;
4652   }
4653   case X86::AVX512_512_SEXT_MASK_32:
4654   case X86::AVX512_512_SEXT_MASK_64: {
4655     Register Reg = MIB.getReg(0);
4656     Register MaskReg = MIB.getReg(1);
4657     unsigned MaskState = getRegState(MIB->getOperand(1));
4658     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4659                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4660     MI.RemoveOperand(1);
4661     MIB->setDesc(get(Opc));
4662     // VPTERNLOG needs 3 register inputs and an immediate.
4663     // 0xff will return 1s for any input.
4664     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4665        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4666     return true;
4667   }
4668   case X86::VMOVAPSZ128rm_NOVLX:
4669     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4670                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4671   case X86::VMOVUPSZ128rm_NOVLX:
4672     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4673                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4674   case X86::VMOVAPSZ256rm_NOVLX:
4675     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4676                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4677   case X86::VMOVUPSZ256rm_NOVLX:
4678     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4679                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4680   case X86::VMOVAPSZ128mr_NOVLX:
4681     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4682                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4683   case X86::VMOVUPSZ128mr_NOVLX:
4684     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4685                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4686   case X86::VMOVAPSZ256mr_NOVLX:
4687     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4688                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4689   case X86::VMOVUPSZ256mr_NOVLX:
4690     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4691                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4692   case X86::MOV32ri64: {
4693     Register Reg = MIB.getReg(0);
4694     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4695     MI.setDesc(get(X86::MOV32ri));
4696     MIB->getOperand(0).setReg(Reg32);
4697     MIB.addReg(Reg, RegState::ImplicitDefine);
4698     return true;
4699   }
4700 
4701   // KNL does not recognize dependency-breaking idioms for mask registers,
4702   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4703   // Using %k0 as the undef input register is a performance heuristic based
4704   // on the assumption that %k0 is used less frequently than the other mask
4705   // registers, since it is not usable as a write mask.
4706   // FIXME: A more advanced approach would be to choose the best input mask
4707   // register based on context.
4708   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4709   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4710   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4711   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4712   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4713   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4714   case TargetOpcode::LOAD_STACK_GUARD:
4715     expandLoadStackGuard(MIB, *this);
4716     return true;
4717   case X86::XOR64_FP:
4718   case X86::XOR32_FP:
4719     return expandXorFP(MIB, *this);
4720   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4721   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4722   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4723   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4724   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4725   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4726   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4727   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4728   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4729   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4730   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4731   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4732   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4733   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4734   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4735   }
4736   return false;
4737 }
4738 
4739 /// Return true for all instructions that only update
4740 /// the first 32 or 64-bits of the destination register and leave the rest
4741 /// unmodified. This can be used to avoid folding loads if the instructions
4742 /// only update part of the destination register, and the non-updated part is
4743 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4744 /// instructions breaks the partial register dependency and it can improve
4745 /// performance. e.g.:
4746 ///
4747 ///   movss (%rdi), %xmm0
4748 ///   cvtss2sd %xmm0, %xmm0
4749 ///
4750 /// Instead of
4751 ///   cvtss2sd (%rdi), %xmm0
4752 ///
4753 /// FIXME: This should be turned into a TSFlags.
4754 ///
4755 static bool hasPartialRegUpdate(unsigned Opcode,
4756                                 const X86Subtarget &Subtarget,
4757                                 bool ForLoadFold = false) {
4758   switch (Opcode) {
4759   case X86::CVTSI2SSrr:
4760   case X86::CVTSI2SSrm:
4761   case X86::CVTSI642SSrr:
4762   case X86::CVTSI642SSrm:
4763   case X86::CVTSI2SDrr:
4764   case X86::CVTSI2SDrm:
4765   case X86::CVTSI642SDrr:
4766   case X86::CVTSI642SDrm:
4767     // Load folding won't effect the undef register update since the input is
4768     // a GPR.
4769     return !ForLoadFold;
4770   case X86::CVTSD2SSrr:
4771   case X86::CVTSD2SSrm:
4772   case X86::CVTSS2SDrr:
4773   case X86::CVTSS2SDrm:
4774   case X86::MOVHPDrm:
4775   case X86::MOVHPSrm:
4776   case X86::MOVLPDrm:
4777   case X86::MOVLPSrm:
4778   case X86::RCPSSr:
4779   case X86::RCPSSm:
4780   case X86::RCPSSr_Int:
4781   case X86::RCPSSm_Int:
4782   case X86::ROUNDSDr:
4783   case X86::ROUNDSDm:
4784   case X86::ROUNDSSr:
4785   case X86::ROUNDSSm:
4786   case X86::RSQRTSSr:
4787   case X86::RSQRTSSm:
4788   case X86::RSQRTSSr_Int:
4789   case X86::RSQRTSSm_Int:
4790   case X86::SQRTSSr:
4791   case X86::SQRTSSm:
4792   case X86::SQRTSSr_Int:
4793   case X86::SQRTSSm_Int:
4794   case X86::SQRTSDr:
4795   case X86::SQRTSDm:
4796   case X86::SQRTSDr_Int:
4797   case X86::SQRTSDm_Int:
4798     return true;
4799   // GPR
4800   case X86::POPCNT32rm:
4801   case X86::POPCNT32rr:
4802   case X86::POPCNT64rm:
4803   case X86::POPCNT64rr:
4804     return Subtarget.hasPOPCNTFalseDeps();
4805   case X86::LZCNT32rm:
4806   case X86::LZCNT32rr:
4807   case X86::LZCNT64rm:
4808   case X86::LZCNT64rr:
4809   case X86::TZCNT32rm:
4810   case X86::TZCNT32rr:
4811   case X86::TZCNT64rm:
4812   case X86::TZCNT64rr:
4813     return Subtarget.hasLZCNTFalseDeps();
4814   }
4815 
4816   return false;
4817 }
4818 
4819 /// Inform the BreakFalseDeps pass how many idle
4820 /// instructions we would like before a partial register update.
4821 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4822     const MachineInstr &MI, unsigned OpNum,
4823     const TargetRegisterInfo *TRI) const {
4824   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4825     return 0;
4826 
4827   // If MI is marked as reading Reg, the partial register update is wanted.
4828   const MachineOperand &MO = MI.getOperand(0);
4829   Register Reg = MO.getReg();
4830   if (Register::isVirtualRegister(Reg)) {
4831     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4832       return 0;
4833   } else {
4834     if (MI.readsRegister(Reg, TRI))
4835       return 0;
4836   }
4837 
4838   // If any instructions in the clearance range are reading Reg, insert a
4839   // dependency breaking instruction, which is inexpensive and is likely to
4840   // be hidden in other instruction's cycles.
4841   return PartialRegUpdateClearance;
4842 }
4843 
4844 // Return true for any instruction the copies the high bits of the first source
4845 // operand into the unused high bits of the destination operand.
4846 static bool hasUndefRegUpdate(unsigned Opcode, unsigned &OpNum,
4847                               bool ForLoadFold = false) {
4848   // Set the OpNum parameter to the first source operand.
4849   OpNum = 1;
4850   switch (Opcode) {
4851   case X86::VCVTSI2SSrr:
4852   case X86::VCVTSI2SSrm:
4853   case X86::VCVTSI2SSrr_Int:
4854   case X86::VCVTSI2SSrm_Int:
4855   case X86::VCVTSI642SSrr:
4856   case X86::VCVTSI642SSrm:
4857   case X86::VCVTSI642SSrr_Int:
4858   case X86::VCVTSI642SSrm_Int:
4859   case X86::VCVTSI2SDrr:
4860   case X86::VCVTSI2SDrm:
4861   case X86::VCVTSI2SDrr_Int:
4862   case X86::VCVTSI2SDrm_Int:
4863   case X86::VCVTSI642SDrr:
4864   case X86::VCVTSI642SDrm:
4865   case X86::VCVTSI642SDrr_Int:
4866   case X86::VCVTSI642SDrm_Int:
4867   // AVX-512
4868   case X86::VCVTSI2SSZrr:
4869   case X86::VCVTSI2SSZrm:
4870   case X86::VCVTSI2SSZrr_Int:
4871   case X86::VCVTSI2SSZrrb_Int:
4872   case X86::VCVTSI2SSZrm_Int:
4873   case X86::VCVTSI642SSZrr:
4874   case X86::VCVTSI642SSZrm:
4875   case X86::VCVTSI642SSZrr_Int:
4876   case X86::VCVTSI642SSZrrb_Int:
4877   case X86::VCVTSI642SSZrm_Int:
4878   case X86::VCVTSI2SDZrr:
4879   case X86::VCVTSI2SDZrm:
4880   case X86::VCVTSI2SDZrr_Int:
4881   case X86::VCVTSI2SDZrm_Int:
4882   case X86::VCVTSI642SDZrr:
4883   case X86::VCVTSI642SDZrm:
4884   case X86::VCVTSI642SDZrr_Int:
4885   case X86::VCVTSI642SDZrrb_Int:
4886   case X86::VCVTSI642SDZrm_Int:
4887   case X86::VCVTUSI2SSZrr:
4888   case X86::VCVTUSI2SSZrm:
4889   case X86::VCVTUSI2SSZrr_Int:
4890   case X86::VCVTUSI2SSZrrb_Int:
4891   case X86::VCVTUSI2SSZrm_Int:
4892   case X86::VCVTUSI642SSZrr:
4893   case X86::VCVTUSI642SSZrm:
4894   case X86::VCVTUSI642SSZrr_Int:
4895   case X86::VCVTUSI642SSZrrb_Int:
4896   case X86::VCVTUSI642SSZrm_Int:
4897   case X86::VCVTUSI2SDZrr:
4898   case X86::VCVTUSI2SDZrm:
4899   case X86::VCVTUSI2SDZrr_Int:
4900   case X86::VCVTUSI2SDZrm_Int:
4901   case X86::VCVTUSI642SDZrr:
4902   case X86::VCVTUSI642SDZrm:
4903   case X86::VCVTUSI642SDZrr_Int:
4904   case X86::VCVTUSI642SDZrrb_Int:
4905   case X86::VCVTUSI642SDZrm_Int:
4906     // Load folding won't effect the undef register update since the input is
4907     // a GPR.
4908     return !ForLoadFold;
4909   case X86::VCVTSD2SSrr:
4910   case X86::VCVTSD2SSrm:
4911   case X86::VCVTSD2SSrr_Int:
4912   case X86::VCVTSD2SSrm_Int:
4913   case X86::VCVTSS2SDrr:
4914   case X86::VCVTSS2SDrm:
4915   case X86::VCVTSS2SDrr_Int:
4916   case X86::VCVTSS2SDrm_Int:
4917   case X86::VRCPSSr:
4918   case X86::VRCPSSr_Int:
4919   case X86::VRCPSSm:
4920   case X86::VRCPSSm_Int:
4921   case X86::VROUNDSDr:
4922   case X86::VROUNDSDm:
4923   case X86::VROUNDSDr_Int:
4924   case X86::VROUNDSDm_Int:
4925   case X86::VROUNDSSr:
4926   case X86::VROUNDSSm:
4927   case X86::VROUNDSSr_Int:
4928   case X86::VROUNDSSm_Int:
4929   case X86::VRSQRTSSr:
4930   case X86::VRSQRTSSr_Int:
4931   case X86::VRSQRTSSm:
4932   case X86::VRSQRTSSm_Int:
4933   case X86::VSQRTSSr:
4934   case X86::VSQRTSSr_Int:
4935   case X86::VSQRTSSm:
4936   case X86::VSQRTSSm_Int:
4937   case X86::VSQRTSDr:
4938   case X86::VSQRTSDr_Int:
4939   case X86::VSQRTSDm:
4940   case X86::VSQRTSDm_Int:
4941   // AVX-512
4942   case X86::VCVTSD2SSZrr:
4943   case X86::VCVTSD2SSZrr_Int:
4944   case X86::VCVTSD2SSZrrb_Int:
4945   case X86::VCVTSD2SSZrm:
4946   case X86::VCVTSD2SSZrm_Int:
4947   case X86::VCVTSS2SDZrr:
4948   case X86::VCVTSS2SDZrr_Int:
4949   case X86::VCVTSS2SDZrrb_Int:
4950   case X86::VCVTSS2SDZrm:
4951   case X86::VCVTSS2SDZrm_Int:
4952   case X86::VGETEXPSDZr:
4953   case X86::VGETEXPSDZrb:
4954   case X86::VGETEXPSDZm:
4955   case X86::VGETEXPSSZr:
4956   case X86::VGETEXPSSZrb:
4957   case X86::VGETEXPSSZm:
4958   case X86::VGETMANTSDZrri:
4959   case X86::VGETMANTSDZrrib:
4960   case X86::VGETMANTSDZrmi:
4961   case X86::VGETMANTSSZrri:
4962   case X86::VGETMANTSSZrrib:
4963   case X86::VGETMANTSSZrmi:
4964   case X86::VRNDSCALESDZr:
4965   case X86::VRNDSCALESDZr_Int:
4966   case X86::VRNDSCALESDZrb_Int:
4967   case X86::VRNDSCALESDZm:
4968   case X86::VRNDSCALESDZm_Int:
4969   case X86::VRNDSCALESSZr:
4970   case X86::VRNDSCALESSZr_Int:
4971   case X86::VRNDSCALESSZrb_Int:
4972   case X86::VRNDSCALESSZm:
4973   case X86::VRNDSCALESSZm_Int:
4974   case X86::VRCP14SDZrr:
4975   case X86::VRCP14SDZrm:
4976   case X86::VRCP14SSZrr:
4977   case X86::VRCP14SSZrm:
4978   case X86::VRCP28SDZr:
4979   case X86::VRCP28SDZrb:
4980   case X86::VRCP28SDZm:
4981   case X86::VRCP28SSZr:
4982   case X86::VRCP28SSZrb:
4983   case X86::VRCP28SSZm:
4984   case X86::VREDUCESSZrmi:
4985   case X86::VREDUCESSZrri:
4986   case X86::VREDUCESSZrrib:
4987   case X86::VRSQRT14SDZrr:
4988   case X86::VRSQRT14SDZrm:
4989   case X86::VRSQRT14SSZrr:
4990   case X86::VRSQRT14SSZrm:
4991   case X86::VRSQRT28SDZr:
4992   case X86::VRSQRT28SDZrb:
4993   case X86::VRSQRT28SDZm:
4994   case X86::VRSQRT28SSZr:
4995   case X86::VRSQRT28SSZrb:
4996   case X86::VRSQRT28SSZm:
4997   case X86::VSQRTSSZr:
4998   case X86::VSQRTSSZr_Int:
4999   case X86::VSQRTSSZrb_Int:
5000   case X86::VSQRTSSZm:
5001   case X86::VSQRTSSZm_Int:
5002   case X86::VSQRTSDZr:
5003   case X86::VSQRTSDZr_Int:
5004   case X86::VSQRTSDZrb_Int:
5005   case X86::VSQRTSDZm:
5006   case X86::VSQRTSDZm_Int:
5007     return true;
5008   case X86::VMOVSSZrrk:
5009   case X86::VMOVSDZrrk:
5010     OpNum = 3;
5011     return true;
5012   case X86::VMOVSSZrrkz:
5013   case X86::VMOVSDZrrkz:
5014     OpNum = 2;
5015     return true;
5016   }
5017 
5018   return false;
5019 }
5020 
5021 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5022 /// before certain undef register reads.
5023 ///
5024 /// This catches the VCVTSI2SD family of instructions:
5025 ///
5026 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5027 ///
5028 /// We should to be careful *not* to catch VXOR idioms which are presumably
5029 /// handled specially in the pipeline:
5030 ///
5031 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5032 ///
5033 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5034 /// high bits that are passed-through are not live.
5035 unsigned
5036 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
5037                                    const TargetRegisterInfo *TRI) const {
5038   if (!hasUndefRegUpdate(MI.getOpcode(), OpNum))
5039     return 0;
5040 
5041   const MachineOperand &MO = MI.getOperand(OpNum);
5042   if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
5043     return UndefRegClearance;
5044   }
5045   return 0;
5046 }
5047 
5048 void X86InstrInfo::breakPartialRegDependency(
5049     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5050   Register Reg = MI.getOperand(OpNum).getReg();
5051   // If MI kills this register, the false dependence is already broken.
5052   if (MI.killsRegister(Reg, TRI))
5053     return;
5054 
5055   if (X86::VR128RegClass.contains(Reg)) {
5056     // These instructions are all floating point domain, so xorps is the best
5057     // choice.
5058     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5059     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5060         .addReg(Reg, RegState::Undef)
5061         .addReg(Reg, RegState::Undef);
5062     MI.addRegisterKilled(Reg, TRI, true);
5063   } else if (X86::VR256RegClass.contains(Reg)) {
5064     // Use vxorps to clear the full ymm register.
5065     // It wants to read and write the xmm sub-register.
5066     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5067     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5068         .addReg(XReg, RegState::Undef)
5069         .addReg(XReg, RegState::Undef)
5070         .addReg(Reg, RegState::ImplicitDefine);
5071     MI.addRegisterKilled(Reg, TRI, true);
5072   } else if (X86::GR64RegClass.contains(Reg)) {
5073     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5074     // as well.
5075     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5076     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5077         .addReg(XReg, RegState::Undef)
5078         .addReg(XReg, RegState::Undef)
5079         .addReg(Reg, RegState::ImplicitDefine);
5080     MI.addRegisterKilled(Reg, TRI, true);
5081   } else if (X86::GR32RegClass.contains(Reg)) {
5082     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5083         .addReg(Reg, RegState::Undef)
5084         .addReg(Reg, RegState::Undef);
5085     MI.addRegisterKilled(Reg, TRI, true);
5086   }
5087 }
5088 
5089 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5090                         int PtrOffset = 0) {
5091   unsigned NumAddrOps = MOs.size();
5092 
5093   if (NumAddrOps < 4) {
5094     // FrameIndex only - add an immediate offset (whether its zero or not).
5095     for (unsigned i = 0; i != NumAddrOps; ++i)
5096       MIB.add(MOs[i]);
5097     addOffset(MIB, PtrOffset);
5098   } else {
5099     // General Memory Addressing - we need to add any offset to an existing
5100     // offset.
5101     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5102     for (unsigned i = 0; i != NumAddrOps; ++i) {
5103       const MachineOperand &MO = MOs[i];
5104       if (i == 3 && PtrOffset != 0) {
5105         MIB.addDisp(MO, PtrOffset);
5106       } else {
5107         MIB.add(MO);
5108       }
5109     }
5110   }
5111 }
5112 
5113 static void updateOperandRegConstraints(MachineFunction &MF,
5114                                         MachineInstr &NewMI,
5115                                         const TargetInstrInfo &TII) {
5116   MachineRegisterInfo &MRI = MF.getRegInfo();
5117   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5118 
5119   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5120     MachineOperand &MO = NewMI.getOperand(Idx);
5121     // We only need to update constraints on virtual register operands.
5122     if (!MO.isReg())
5123       continue;
5124     Register Reg = MO.getReg();
5125     if (!Register::isVirtualRegister(Reg))
5126       continue;
5127 
5128     auto *NewRC = MRI.constrainRegClass(
5129         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5130     if (!NewRC) {
5131       LLVM_DEBUG(
5132           dbgs() << "WARNING: Unable to update register constraint for operand "
5133                  << Idx << " of instruction:\n";
5134           NewMI.dump(); dbgs() << "\n");
5135     }
5136   }
5137 }
5138 
5139 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5140                                      ArrayRef<MachineOperand> MOs,
5141                                      MachineBasicBlock::iterator InsertPt,
5142                                      MachineInstr &MI,
5143                                      const TargetInstrInfo &TII) {
5144   // Create the base instruction with the memory operand as the first part.
5145   // Omit the implicit operands, something BuildMI can't do.
5146   MachineInstr *NewMI =
5147       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5148   MachineInstrBuilder MIB(MF, NewMI);
5149   addOperands(MIB, MOs);
5150 
5151   // Loop over the rest of the ri operands, converting them over.
5152   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5153   for (unsigned i = 0; i != NumOps; ++i) {
5154     MachineOperand &MO = MI.getOperand(i + 2);
5155     MIB.add(MO);
5156   }
5157   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5158     MachineOperand &MO = MI.getOperand(i);
5159     MIB.add(MO);
5160   }
5161 
5162   updateOperandRegConstraints(MF, *NewMI, TII);
5163 
5164   MachineBasicBlock *MBB = InsertPt->getParent();
5165   MBB->insert(InsertPt, NewMI);
5166 
5167   return MIB;
5168 }
5169 
5170 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5171                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5172                               MachineBasicBlock::iterator InsertPt,
5173                               MachineInstr &MI, const TargetInstrInfo &TII,
5174                               int PtrOffset = 0) {
5175   // Omit the implicit operands, something BuildMI can't do.
5176   MachineInstr *NewMI =
5177       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5178   MachineInstrBuilder MIB(MF, NewMI);
5179 
5180   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5181     MachineOperand &MO = MI.getOperand(i);
5182     if (i == OpNo) {
5183       assert(MO.isReg() && "Expected to fold into reg operand!");
5184       addOperands(MIB, MOs, PtrOffset);
5185     } else {
5186       MIB.add(MO);
5187     }
5188   }
5189 
5190   updateOperandRegConstraints(MF, *NewMI, TII);
5191 
5192   // Copy the NoFPExcept flag from the instruction we're fusing.
5193   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5194     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5195 
5196   MachineBasicBlock *MBB = InsertPt->getParent();
5197   MBB->insert(InsertPt, NewMI);
5198 
5199   return MIB;
5200 }
5201 
5202 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5203                                 ArrayRef<MachineOperand> MOs,
5204                                 MachineBasicBlock::iterator InsertPt,
5205                                 MachineInstr &MI) {
5206   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5207                                     MI.getDebugLoc(), TII.get(Opcode));
5208   addOperands(MIB, MOs);
5209   return MIB.addImm(0);
5210 }
5211 
5212 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5213     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5214     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5215     unsigned Size, Align Alignment) const {
5216   switch (MI.getOpcode()) {
5217   case X86::INSERTPSrr:
5218   case X86::VINSERTPSrr:
5219   case X86::VINSERTPSZrr:
5220     // Attempt to convert the load of inserted vector into a fold load
5221     // of a single float.
5222     if (OpNum == 2) {
5223       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5224       unsigned ZMask = Imm & 15;
5225       unsigned DstIdx = (Imm >> 4) & 3;
5226       unsigned SrcIdx = (Imm >> 6) & 3;
5227 
5228       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5229       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5230       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5231       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5232         int PtrOffset = SrcIdx * 4;
5233         unsigned NewImm = (DstIdx << 4) | ZMask;
5234         unsigned NewOpCode =
5235             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5236             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5237                                                     X86::INSERTPSrm;
5238         MachineInstr *NewMI =
5239             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5240         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5241         return NewMI;
5242       }
5243     }
5244     break;
5245   case X86::MOVHLPSrr:
5246   case X86::VMOVHLPSrr:
5247   case X86::VMOVHLPSZrr:
5248     // Move the upper 64-bits of the second operand to the lower 64-bits.
5249     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5250     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5251     if (OpNum == 2) {
5252       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5253       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5254       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5255       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5256         unsigned NewOpCode =
5257             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5258             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5259                                                    X86::MOVLPSrm;
5260         MachineInstr *NewMI =
5261             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5262         return NewMI;
5263       }
5264     }
5265     break;
5266   case X86::UNPCKLPDrr:
5267     // If we won't be able to fold this to the memory form of UNPCKL, use
5268     // MOVHPD instead. Done as custom because we can't have this in the load
5269     // table twice.
5270     if (OpNum == 2) {
5271       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5272       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5273       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5274       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5275         MachineInstr *NewMI =
5276             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5277         return NewMI;
5278       }
5279     }
5280     break;
5281   }
5282 
5283   return nullptr;
5284 }
5285 
5286 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5287                                                MachineInstr &MI) {
5288   unsigned Ignored;
5289   if (!hasUndefRegUpdate(MI.getOpcode(), Ignored, /*ForLoadFold*/true) ||
5290       !MI.getOperand(1).isReg())
5291     return false;
5292 
5293   // The are two cases we need to handle depending on where in the pipeline
5294   // the folding attempt is being made.
5295   // -Register has the undef flag set.
5296   // -Register is produced by the IMPLICIT_DEF instruction.
5297 
5298   if (MI.getOperand(1).isUndef())
5299     return true;
5300 
5301   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5302   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5303   return VRegDef && VRegDef->isImplicitDef();
5304 }
5305 
5306 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5307     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5308     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5309     unsigned Size, Align Alignment, bool AllowCommute) const {
5310   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5311   bool isTwoAddrFold = false;
5312 
5313   // For CPUs that favor the register form of a call or push,
5314   // do not fold loads into calls or pushes, unless optimizing for size
5315   // aggressively.
5316   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5317       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5318        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5319        MI.getOpcode() == X86::PUSH64r))
5320     return nullptr;
5321 
5322   // Avoid partial and undef register update stalls unless optimizing for size.
5323   if (!MF.getFunction().hasOptSize() &&
5324       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5325        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5326     return nullptr;
5327 
5328   unsigned NumOps = MI.getDesc().getNumOperands();
5329   bool isTwoAddr =
5330       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5331 
5332   // FIXME: AsmPrinter doesn't know how to handle
5333   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5334   if (MI.getOpcode() == X86::ADD32ri &&
5335       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5336     return nullptr;
5337 
5338   // GOTTPOFF relocation loads can only be folded into add instructions.
5339   // FIXME: Need to exclude other relocations that only support specific
5340   // instructions.
5341   if (MOs.size() == X86::AddrNumOperands &&
5342       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5343       MI.getOpcode() != X86::ADD64rr)
5344     return nullptr;
5345 
5346   MachineInstr *NewMI = nullptr;
5347 
5348   // Attempt to fold any custom cases we have.
5349   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5350           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5351     return CustomMI;
5352 
5353   const X86MemoryFoldTableEntry *I = nullptr;
5354 
5355   // Folding a memory location into the two-address part of a two-address
5356   // instruction is different than folding it other places.  It requires
5357   // replacing the *two* registers with the memory location.
5358   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5359       MI.getOperand(1).isReg() &&
5360       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5361     I = lookupTwoAddrFoldTable(MI.getOpcode());
5362     isTwoAddrFold = true;
5363   } else {
5364     if (OpNum == 0) {
5365       if (MI.getOpcode() == X86::MOV32r0) {
5366         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5367         if (NewMI)
5368           return NewMI;
5369       }
5370     }
5371 
5372     I = lookupFoldTable(MI.getOpcode(), OpNum);
5373   }
5374 
5375   if (I != nullptr) {
5376     unsigned Opcode = I->DstOp;
5377     MaybeAlign MinAlign =
5378         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5379     if (MinAlign && Alignment < *MinAlign)
5380       return nullptr;
5381     bool NarrowToMOV32rm = false;
5382     if (Size) {
5383       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5384       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5385                                                   &RI, MF);
5386       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5387       if (Size < RCSize) {
5388         // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5389         // Check if it's safe to fold the load. If the size of the object is
5390         // narrower than the load width, then it's not.
5391         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5392           return nullptr;
5393         // If this is a 64-bit load, but the spill slot is 32, then we can do
5394         // a 32-bit load which is implicitly zero-extended. This likely is
5395         // due to live interval analysis remat'ing a load from stack slot.
5396         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5397           return nullptr;
5398         Opcode = X86::MOV32rm;
5399         NarrowToMOV32rm = true;
5400       }
5401     }
5402 
5403     if (isTwoAddrFold)
5404       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5405     else
5406       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5407 
5408     if (NarrowToMOV32rm) {
5409       // If this is the special case where we use a MOV32rm to load a 32-bit
5410       // value and zero-extend the top bits. Change the destination register
5411       // to a 32-bit one.
5412       Register DstReg = NewMI->getOperand(0).getReg();
5413       if (Register::isPhysicalRegister(DstReg))
5414         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5415       else
5416         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5417     }
5418     return NewMI;
5419   }
5420 
5421   // If the instruction and target operand are commutable, commute the
5422   // instruction and try again.
5423   if (AllowCommute) {
5424     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5425     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5426       bool HasDef = MI.getDesc().getNumDefs();
5427       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5428       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5429       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5430       bool Tied1 =
5431           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5432       bool Tied2 =
5433           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5434 
5435       // If either of the commutable operands are tied to the destination
5436       // then we can not commute + fold.
5437       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5438           (HasDef && Reg0 == Reg2 && Tied2))
5439         return nullptr;
5440 
5441       MachineInstr *CommutedMI =
5442           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5443       if (!CommutedMI) {
5444         // Unable to commute.
5445         return nullptr;
5446       }
5447       if (CommutedMI != &MI) {
5448         // New instruction. We can't fold from this.
5449         CommutedMI->eraseFromParent();
5450         return nullptr;
5451       }
5452 
5453       // Attempt to fold with the commuted version of the instruction.
5454       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5455                                     Alignment, /*AllowCommute=*/false);
5456       if (NewMI)
5457         return NewMI;
5458 
5459       // Folding failed again - undo the commute before returning.
5460       MachineInstr *UncommutedMI =
5461           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5462       if (!UncommutedMI) {
5463         // Unable to commute.
5464         return nullptr;
5465       }
5466       if (UncommutedMI != &MI) {
5467         // New instruction. It doesn't need to be kept.
5468         UncommutedMI->eraseFromParent();
5469         return nullptr;
5470       }
5471 
5472       // Return here to prevent duplicate fuse failure report.
5473       return nullptr;
5474     }
5475   }
5476 
5477   // No fusion
5478   if (PrintFailedFusing && !MI.isCopy())
5479     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5480   return nullptr;
5481 }
5482 
5483 MachineInstr *
5484 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5485                                     ArrayRef<unsigned> Ops,
5486                                     MachineBasicBlock::iterator InsertPt,
5487                                     int FrameIndex, LiveIntervals *LIS,
5488                                     VirtRegMap *VRM) const {
5489   // Check switch flag
5490   if (NoFusing)
5491     return nullptr;
5492 
5493   // Avoid partial and undef register update stalls unless optimizing for size.
5494   if (!MF.getFunction().hasOptSize() &&
5495       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5496        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5497     return nullptr;
5498 
5499   // Don't fold subreg spills, or reloads that use a high subreg.
5500   for (auto Op : Ops) {
5501     MachineOperand &MO = MI.getOperand(Op);
5502     auto SubReg = MO.getSubReg();
5503     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5504       return nullptr;
5505   }
5506 
5507   const MachineFrameInfo &MFI = MF.getFrameInfo();
5508   unsigned Size = MFI.getObjectSize(FrameIndex);
5509   Align Alignment = MFI.getObjectAlign(FrameIndex);
5510   // If the function stack isn't realigned we don't want to fold instructions
5511   // that need increased alignment.
5512   if (!RI.needsStackRealignment(MF))
5513     Alignment =
5514         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5515   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5516     unsigned NewOpc = 0;
5517     unsigned RCSize = 0;
5518     switch (MI.getOpcode()) {
5519     default: return nullptr;
5520     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5521     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5522     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5523     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5524     }
5525     // Check if it's safe to fold the load. If the size of the object is
5526     // narrower than the load width, then it's not.
5527     if (Size < RCSize)
5528       return nullptr;
5529     // Change to CMPXXri r, 0 first.
5530     MI.setDesc(get(NewOpc));
5531     MI.getOperand(1).ChangeToImmediate(0);
5532   } else if (Ops.size() != 1)
5533     return nullptr;
5534 
5535   return foldMemoryOperandImpl(MF, MI, Ops[0],
5536                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5537                                Size, Alignment, /*AllowCommute=*/true);
5538 }
5539 
5540 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5541 /// because the latter uses contents that wouldn't be defined in the folded
5542 /// version.  For instance, this transformation isn't legal:
5543 ///   movss (%rdi), %xmm0
5544 ///   addps %xmm0, %xmm0
5545 /// ->
5546 ///   addps (%rdi), %xmm0
5547 ///
5548 /// But this one is:
5549 ///   movss (%rdi), %xmm0
5550 ///   addss %xmm0, %xmm0
5551 /// ->
5552 ///   addss (%rdi), %xmm0
5553 ///
5554 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5555                                              const MachineInstr &UserMI,
5556                                              const MachineFunction &MF) {
5557   unsigned Opc = LoadMI.getOpcode();
5558   unsigned UserOpc = UserMI.getOpcode();
5559   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5560   const TargetRegisterClass *RC =
5561       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5562   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5563 
5564   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5565        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5566        Opc == X86::VMOVSSZrm_alt) &&
5567       RegSize > 32) {
5568     // These instructions only load 32 bits, we can't fold them if the
5569     // destination register is wider than 32 bits (4 bytes), and its user
5570     // instruction isn't scalar (SS).
5571     switch (UserOpc) {
5572     case X86::CVTSS2SDrr_Int:
5573     case X86::VCVTSS2SDrr_Int:
5574     case X86::VCVTSS2SDZrr_Int:
5575     case X86::VCVTSS2SDZrr_Intk:
5576     case X86::VCVTSS2SDZrr_Intkz:
5577     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5578     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5579     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5580     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5581     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5582     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5583     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5584     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5585     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5586     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5587     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5588     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5589     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5590     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5591     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5592     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5593     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5594     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5595     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5596     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5597     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5598     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5599     case X86::VCMPSSZrr_Intk:
5600     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5601     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5602     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5603     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5604     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5605     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5606     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5607     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5608     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5609     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5610     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5611     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5612     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5613     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5614     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5615     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5616     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5617     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5618     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5619     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5620     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5621     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5622     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5623     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5624     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5625     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5626     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5627     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5628     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5629     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5630     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5631     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5632     case X86::VFIXUPIMMSSZrri:
5633     case X86::VFIXUPIMMSSZrrik:
5634     case X86::VFIXUPIMMSSZrrikz:
5635     case X86::VFPCLASSSSZrr:
5636     case X86::VFPCLASSSSZrrk:
5637     case X86::VGETEXPSSZr:
5638     case X86::VGETEXPSSZrk:
5639     case X86::VGETEXPSSZrkz:
5640     case X86::VGETMANTSSZrri:
5641     case X86::VGETMANTSSZrrik:
5642     case X86::VGETMANTSSZrrikz:
5643     case X86::VRANGESSZrri:
5644     case X86::VRANGESSZrrik:
5645     case X86::VRANGESSZrrikz:
5646     case X86::VRCP14SSZrr:
5647     case X86::VRCP14SSZrrk:
5648     case X86::VRCP14SSZrrkz:
5649     case X86::VRCP28SSZr:
5650     case X86::VRCP28SSZrk:
5651     case X86::VRCP28SSZrkz:
5652     case X86::VREDUCESSZrri:
5653     case X86::VREDUCESSZrrik:
5654     case X86::VREDUCESSZrrikz:
5655     case X86::VRNDSCALESSZr_Int:
5656     case X86::VRNDSCALESSZr_Intk:
5657     case X86::VRNDSCALESSZr_Intkz:
5658     case X86::VRSQRT14SSZrr:
5659     case X86::VRSQRT14SSZrrk:
5660     case X86::VRSQRT14SSZrrkz:
5661     case X86::VRSQRT28SSZr:
5662     case X86::VRSQRT28SSZrk:
5663     case X86::VRSQRT28SSZrkz:
5664     case X86::VSCALEFSSZrr:
5665     case X86::VSCALEFSSZrrk:
5666     case X86::VSCALEFSSZrrkz:
5667       return false;
5668     default:
5669       return true;
5670     }
5671   }
5672 
5673   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5674        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5675        Opc == X86::VMOVSDZrm_alt) &&
5676       RegSize > 64) {
5677     // These instructions only load 64 bits, we can't fold them if the
5678     // destination register is wider than 64 bits (8 bytes), and its user
5679     // instruction isn't scalar (SD).
5680     switch (UserOpc) {
5681     case X86::CVTSD2SSrr_Int:
5682     case X86::VCVTSD2SSrr_Int:
5683     case X86::VCVTSD2SSZrr_Int:
5684     case X86::VCVTSD2SSZrr_Intk:
5685     case X86::VCVTSD2SSZrr_Intkz:
5686     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
5687     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
5688     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
5689     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
5690     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
5691     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
5692     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
5693     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
5694     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
5695     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
5696     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
5697     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5698     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5699     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5700     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5701     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5702     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5703     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
5704     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5705     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5706     case X86::VCMPSDZrr_Intk:
5707     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5708     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5709     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5710     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5711     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
5712     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5713     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
5714     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
5715     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
5716     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
5717     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
5718     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
5719     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
5720     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
5721     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5722     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5723     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5724     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5725     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5726     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5727     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5728     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5729     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5730     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5731     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5732     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5733     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5734     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5735     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5736     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5737     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5738     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5739     case X86::VFIXUPIMMSDZrri:
5740     case X86::VFIXUPIMMSDZrrik:
5741     case X86::VFIXUPIMMSDZrrikz:
5742     case X86::VFPCLASSSDZrr:
5743     case X86::VFPCLASSSDZrrk:
5744     case X86::VGETEXPSDZr:
5745     case X86::VGETEXPSDZrk:
5746     case X86::VGETEXPSDZrkz:
5747     case X86::VGETMANTSDZrri:
5748     case X86::VGETMANTSDZrrik:
5749     case X86::VGETMANTSDZrrikz:
5750     case X86::VRANGESDZrri:
5751     case X86::VRANGESDZrrik:
5752     case X86::VRANGESDZrrikz:
5753     case X86::VRCP14SDZrr:
5754     case X86::VRCP14SDZrrk:
5755     case X86::VRCP14SDZrrkz:
5756     case X86::VRCP28SDZr:
5757     case X86::VRCP28SDZrk:
5758     case X86::VRCP28SDZrkz:
5759     case X86::VREDUCESDZrri:
5760     case X86::VREDUCESDZrrik:
5761     case X86::VREDUCESDZrrikz:
5762     case X86::VRNDSCALESDZr_Int:
5763     case X86::VRNDSCALESDZr_Intk:
5764     case X86::VRNDSCALESDZr_Intkz:
5765     case X86::VRSQRT14SDZrr:
5766     case X86::VRSQRT14SDZrrk:
5767     case X86::VRSQRT14SDZrrkz:
5768     case X86::VRSQRT28SDZr:
5769     case X86::VRSQRT28SDZrk:
5770     case X86::VRSQRT28SDZrkz:
5771     case X86::VSCALEFSDZrr:
5772     case X86::VSCALEFSDZrrk:
5773     case X86::VSCALEFSDZrrkz:
5774       return false;
5775     default:
5776       return true;
5777     }
5778   }
5779 
5780   return false;
5781 }
5782 
5783 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5784     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5785     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5786     LiveIntervals *LIS) const {
5787 
5788   // TODO: Support the case where LoadMI loads a wide register, but MI
5789   // only uses a subreg.
5790   for (auto Op : Ops) {
5791     if (MI.getOperand(Op).getSubReg())
5792       return nullptr;
5793   }
5794 
5795   // If loading from a FrameIndex, fold directly from the FrameIndex.
5796   unsigned NumOps = LoadMI.getDesc().getNumOperands();
5797   int FrameIndex;
5798   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5799     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5800       return nullptr;
5801     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5802   }
5803 
5804   // Check switch flag
5805   if (NoFusing) return nullptr;
5806 
5807   // Avoid partial and undef register update stalls unless optimizing for size.
5808   if (!MF.getFunction().hasOptSize() &&
5809       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5810        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5811     return nullptr;
5812 
5813   // Determine the alignment of the load.
5814   Align Alignment;
5815   if (LoadMI.hasOneMemOperand())
5816     Alignment = (*LoadMI.memoperands_begin())->getAlign();
5817   else
5818     switch (LoadMI.getOpcode()) {
5819     case X86::AVX512_512_SET0:
5820     case X86::AVX512_512_SETALLONES:
5821       Alignment = Align(64);
5822       break;
5823     case X86::AVX2_SETALLONES:
5824     case X86::AVX1_SETALLONES:
5825     case X86::AVX_SET0:
5826     case X86::AVX512_256_SET0:
5827       Alignment = Align(32);
5828       break;
5829     case X86::V_SET0:
5830     case X86::V_SETALLONES:
5831     case X86::AVX512_128_SET0:
5832     case X86::FsFLD0F128:
5833     case X86::AVX512_FsFLD0F128:
5834       Alignment = Align(16);
5835       break;
5836     case X86::MMX_SET0:
5837     case X86::FsFLD0SD:
5838     case X86::AVX512_FsFLD0SD:
5839       Alignment = Align(8);
5840       break;
5841     case X86::FsFLD0SS:
5842     case X86::AVX512_FsFLD0SS:
5843       Alignment = Align(4);
5844       break;
5845     default:
5846       return nullptr;
5847     }
5848   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5849     unsigned NewOpc = 0;
5850     switch (MI.getOpcode()) {
5851     default: return nullptr;
5852     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
5853     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5854     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5855     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5856     }
5857     // Change to CMPXXri r, 0 first.
5858     MI.setDesc(get(NewOpc));
5859     MI.getOperand(1).ChangeToImmediate(0);
5860   } else if (Ops.size() != 1)
5861     return nullptr;
5862 
5863   // Make sure the subregisters match.
5864   // Otherwise we risk changing the size of the load.
5865   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5866     return nullptr;
5867 
5868   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5869   switch (LoadMI.getOpcode()) {
5870   case X86::MMX_SET0:
5871   case X86::V_SET0:
5872   case X86::V_SETALLONES:
5873   case X86::AVX2_SETALLONES:
5874   case X86::AVX1_SETALLONES:
5875   case X86::AVX_SET0:
5876   case X86::AVX512_128_SET0:
5877   case X86::AVX512_256_SET0:
5878   case X86::AVX512_512_SET0:
5879   case X86::AVX512_512_SETALLONES:
5880   case X86::FsFLD0SD:
5881   case X86::AVX512_FsFLD0SD:
5882   case X86::FsFLD0SS:
5883   case X86::AVX512_FsFLD0SS:
5884   case X86::FsFLD0F128:
5885   case X86::AVX512_FsFLD0F128: {
5886     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5887     // Create a constant-pool entry and operands to load from it.
5888 
5889     // Medium and large mode can't fold loads this way.
5890     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5891         MF.getTarget().getCodeModel() != CodeModel::Kernel)
5892       return nullptr;
5893 
5894     // x86-32 PIC requires a PIC base register for constant pools.
5895     unsigned PICBase = 0;
5896     if (MF.getTarget().isPositionIndependent()) {
5897       if (Subtarget.is64Bit())
5898         PICBase = X86::RIP;
5899       else
5900         // FIXME: PICBase = getGlobalBaseReg(&MF);
5901         // This doesn't work for several reasons.
5902         // 1. GlobalBaseReg may have been spilled.
5903         // 2. It may not be live at MI.
5904         return nullptr;
5905     }
5906 
5907     // Create a constant-pool entry.
5908     MachineConstantPool &MCP = *MF.getConstantPool();
5909     Type *Ty;
5910     unsigned Opc = LoadMI.getOpcode();
5911     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5912       Ty = Type::getFloatTy(MF.getFunction().getContext());
5913     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5914       Ty = Type::getDoubleTy(MF.getFunction().getContext());
5915     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
5916       Ty = Type::getFP128Ty(MF.getFunction().getContext());
5917     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5918       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5919     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5920              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5921       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5922     else if (Opc == X86::MMX_SET0)
5923       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5924     else
5925       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5926 
5927     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5928                       Opc == X86::AVX512_512_SETALLONES ||
5929                       Opc == X86::AVX1_SETALLONES);
5930     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5931                                     Constant::getNullValue(Ty);
5932     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment.value());
5933 
5934     // Create operands to load from the constant pool entry.
5935     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5936     MOs.push_back(MachineOperand::CreateImm(1));
5937     MOs.push_back(MachineOperand::CreateReg(0, false));
5938     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5939     MOs.push_back(MachineOperand::CreateReg(0, false));
5940     break;
5941   }
5942   default: {
5943     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5944       return nullptr;
5945 
5946     // Folding a normal load. Just copy the load's address operands.
5947     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5948                LoadMI.operands_begin() + NumOps);
5949     break;
5950   }
5951   }
5952   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5953                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
5954 }
5955 
5956 static SmallVector<MachineMemOperand *, 2>
5957 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5958   SmallVector<MachineMemOperand *, 2> LoadMMOs;
5959 
5960   for (MachineMemOperand *MMO : MMOs) {
5961     if (!MMO->isLoad())
5962       continue;
5963 
5964     if (!MMO->isStore()) {
5965       // Reuse the MMO.
5966       LoadMMOs.push_back(MMO);
5967     } else {
5968       // Clone the MMO and unset the store flag.
5969       LoadMMOs.push_back(MF.getMachineMemOperand(
5970           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
5971     }
5972   }
5973 
5974   return LoadMMOs;
5975 }
5976 
5977 static SmallVector<MachineMemOperand *, 2>
5978 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5979   SmallVector<MachineMemOperand *, 2> StoreMMOs;
5980 
5981   for (MachineMemOperand *MMO : MMOs) {
5982     if (!MMO->isStore())
5983       continue;
5984 
5985     if (!MMO->isLoad()) {
5986       // Reuse the MMO.
5987       StoreMMOs.push_back(MMO);
5988     } else {
5989       // Clone the MMO and unset the load flag.
5990       StoreMMOs.push_back(MF.getMachineMemOperand(
5991           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
5992     }
5993   }
5994 
5995   return StoreMMOs;
5996 }
5997 
5998 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
5999                                    const TargetRegisterClass *RC,
6000                                    const X86Subtarget &STI) {
6001   assert(STI.hasAVX512() && "Expected at least AVX512!");
6002   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6003   assert((SpillSize == 64 || STI.hasVLX()) &&
6004          "Can't broadcast less than 64 bytes without AVX512VL!");
6005 
6006   switch (I->Flags & TB_BCAST_MASK) {
6007   default: llvm_unreachable("Unexpected broadcast type!");
6008   case TB_BCAST_D:
6009     switch (SpillSize) {
6010     default: llvm_unreachable("Unknown spill size");
6011     case 16: return X86::VPBROADCASTDZ128rm;
6012     case 32: return X86::VPBROADCASTDZ256rm;
6013     case 64: return X86::VPBROADCASTDZrm;
6014     }
6015     break;
6016   case TB_BCAST_Q:
6017     switch (SpillSize) {
6018     default: llvm_unreachable("Unknown spill size");
6019     case 16: return X86::VPBROADCASTQZ128rm;
6020     case 32: return X86::VPBROADCASTQZ256rm;
6021     case 64: return X86::VPBROADCASTQZrm;
6022     }
6023     break;
6024   case TB_BCAST_SS:
6025     switch (SpillSize) {
6026     default: llvm_unreachable("Unknown spill size");
6027     case 16: return X86::VBROADCASTSSZ128rm;
6028     case 32: return X86::VBROADCASTSSZ256rm;
6029     case 64: return X86::VBROADCASTSSZrm;
6030     }
6031     break;
6032   case TB_BCAST_SD:
6033     switch (SpillSize) {
6034     default: llvm_unreachable("Unknown spill size");
6035     case 16: return X86::VMOVDDUPZ128rm;
6036     case 32: return X86::VBROADCASTSDZ256rm;
6037     case 64: return X86::VBROADCASTSDZrm;
6038     }
6039     break;
6040   }
6041 }
6042 
6043 bool X86InstrInfo::unfoldMemoryOperand(
6044     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6045     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6046   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6047   if (I == nullptr)
6048     return false;
6049   unsigned Opc = I->DstOp;
6050   unsigned Index = I->Flags & TB_INDEX_MASK;
6051   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6052   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6053   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6054   if (UnfoldLoad && !FoldedLoad)
6055     return false;
6056   UnfoldLoad &= FoldedLoad;
6057   if (UnfoldStore && !FoldedStore)
6058     return false;
6059   UnfoldStore &= FoldedStore;
6060 
6061   const MCInstrDesc &MCID = get(Opc);
6062 
6063   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6064   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6065   // TODO: Check if 32-byte or greater accesses are slow too?
6066   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6067       Subtarget.isUnalignedMem16Slow())
6068     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6069     // conservatively assume the address is unaligned. That's bad for
6070     // performance.
6071     return false;
6072   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6073   SmallVector<MachineOperand,2> BeforeOps;
6074   SmallVector<MachineOperand,2> AfterOps;
6075   SmallVector<MachineOperand,4> ImpOps;
6076   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6077     MachineOperand &Op = MI.getOperand(i);
6078     if (i >= Index && i < Index + X86::AddrNumOperands)
6079       AddrOps.push_back(Op);
6080     else if (Op.isReg() && Op.isImplicit())
6081       ImpOps.push_back(Op);
6082     else if (i < Index)
6083       BeforeOps.push_back(Op);
6084     else if (i > Index)
6085       AfterOps.push_back(Op);
6086   }
6087 
6088   // Emit the load or broadcast instruction.
6089   if (UnfoldLoad) {
6090     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6091 
6092     unsigned Opc;
6093     if (FoldedBCast) {
6094       Opc = getBroadcastOpcode(I, RC, Subtarget);
6095     } else {
6096       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6097       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6098       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6099     }
6100 
6101     DebugLoc DL;
6102     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6103     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6104       MIB.add(AddrOps[i]);
6105     MIB.setMemRefs(MMOs);
6106     NewMIs.push_back(MIB);
6107 
6108     if (UnfoldStore) {
6109       // Address operands cannot be marked isKill.
6110       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6111         MachineOperand &MO = NewMIs[0]->getOperand(i);
6112         if (MO.isReg())
6113           MO.setIsKill(false);
6114       }
6115     }
6116   }
6117 
6118   // Emit the data processing instruction.
6119   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6120   MachineInstrBuilder MIB(MF, DataMI);
6121 
6122   if (FoldedStore)
6123     MIB.addReg(Reg, RegState::Define);
6124   for (MachineOperand &BeforeOp : BeforeOps)
6125     MIB.add(BeforeOp);
6126   if (FoldedLoad)
6127     MIB.addReg(Reg);
6128   for (MachineOperand &AfterOp : AfterOps)
6129     MIB.add(AfterOp);
6130   for (MachineOperand &ImpOp : ImpOps) {
6131     MIB.addReg(ImpOp.getReg(),
6132                getDefRegState(ImpOp.isDef()) |
6133                RegState::Implicit |
6134                getKillRegState(ImpOp.isKill()) |
6135                getDeadRegState(ImpOp.isDead()) |
6136                getUndefRegState(ImpOp.isUndef()));
6137   }
6138   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6139   switch (DataMI->getOpcode()) {
6140   default: break;
6141   case X86::CMP64ri32:
6142   case X86::CMP64ri8:
6143   case X86::CMP32ri:
6144   case X86::CMP32ri8:
6145   case X86::CMP16ri:
6146   case X86::CMP16ri8:
6147   case X86::CMP8ri: {
6148     MachineOperand &MO0 = DataMI->getOperand(0);
6149     MachineOperand &MO1 = DataMI->getOperand(1);
6150     if (MO1.getImm() == 0) {
6151       unsigned NewOpc;
6152       switch (DataMI->getOpcode()) {
6153       default: llvm_unreachable("Unreachable!");
6154       case X86::CMP64ri8:
6155       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6156       case X86::CMP32ri8:
6157       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6158       case X86::CMP16ri8:
6159       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6160       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6161       }
6162       DataMI->setDesc(get(NewOpc));
6163       MO1.ChangeToRegister(MO0.getReg(), false);
6164     }
6165   }
6166   }
6167   NewMIs.push_back(DataMI);
6168 
6169   // Emit the store instruction.
6170   if (UnfoldStore) {
6171     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6172     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6173     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6174     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6175     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6176     DebugLoc DL;
6177     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6178     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6179       MIB.add(AddrOps[i]);
6180     MIB.addReg(Reg, RegState::Kill);
6181     MIB.setMemRefs(MMOs);
6182     NewMIs.push_back(MIB);
6183   }
6184 
6185   return true;
6186 }
6187 
6188 bool
6189 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6190                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6191   if (!N->isMachineOpcode())
6192     return false;
6193 
6194   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6195   if (I == nullptr)
6196     return false;
6197   unsigned Opc = I->DstOp;
6198   unsigned Index = I->Flags & TB_INDEX_MASK;
6199   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6200   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6201   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6202   const MCInstrDesc &MCID = get(Opc);
6203   MachineFunction &MF = DAG.getMachineFunction();
6204   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6205   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6206   unsigned NumDefs = MCID.NumDefs;
6207   std::vector<SDValue> AddrOps;
6208   std::vector<SDValue> BeforeOps;
6209   std::vector<SDValue> AfterOps;
6210   SDLoc dl(N);
6211   unsigned NumOps = N->getNumOperands();
6212   for (unsigned i = 0; i != NumOps-1; ++i) {
6213     SDValue Op = N->getOperand(i);
6214     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6215       AddrOps.push_back(Op);
6216     else if (i < Index-NumDefs)
6217       BeforeOps.push_back(Op);
6218     else if (i > Index-NumDefs)
6219       AfterOps.push_back(Op);
6220   }
6221   SDValue Chain = N->getOperand(NumOps-1);
6222   AddrOps.push_back(Chain);
6223 
6224   // Emit the load instruction.
6225   SDNode *Load = nullptr;
6226   if (FoldedLoad) {
6227     EVT VT = *TRI.legalclasstypes_begin(*RC);
6228     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6229     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6230         Subtarget.isUnalignedMem16Slow())
6231       // Do not introduce a slow unaligned load.
6232       return false;
6233     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6234     // memory access is slow above.
6235 
6236     unsigned Opc;
6237     if (FoldedBCast) {
6238       Opc = getBroadcastOpcode(I, RC, Subtarget);
6239     } else {
6240       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6241       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6242       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6243     }
6244 
6245     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6246     NewNodes.push_back(Load);
6247 
6248     // Preserve memory reference information.
6249     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6250   }
6251 
6252   // Emit the data processing instruction.
6253   std::vector<EVT> VTs;
6254   const TargetRegisterClass *DstRC = nullptr;
6255   if (MCID.getNumDefs() > 0) {
6256     DstRC = getRegClass(MCID, 0, &RI, MF);
6257     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6258   }
6259   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6260     EVT VT = N->getValueType(i);
6261     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6262       VTs.push_back(VT);
6263   }
6264   if (Load)
6265     BeforeOps.push_back(SDValue(Load, 0));
6266   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6267   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6268   switch (Opc) {
6269     default: break;
6270     case X86::CMP64ri32:
6271     case X86::CMP64ri8:
6272     case X86::CMP32ri:
6273     case X86::CMP32ri8:
6274     case X86::CMP16ri:
6275     case X86::CMP16ri8:
6276     case X86::CMP8ri:
6277       if (isNullConstant(BeforeOps[1])) {
6278         switch (Opc) {
6279           default: llvm_unreachable("Unreachable!");
6280           case X86::CMP64ri8:
6281           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6282           case X86::CMP32ri8:
6283           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6284           case X86::CMP16ri8:
6285           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6286           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6287         }
6288         BeforeOps[1] = BeforeOps[0];
6289       }
6290   }
6291   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6292   NewNodes.push_back(NewNode);
6293 
6294   // Emit the store instruction.
6295   if (FoldedStore) {
6296     AddrOps.pop_back();
6297     AddrOps.push_back(SDValue(NewNode, 0));
6298     AddrOps.push_back(Chain);
6299     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6300     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6301         Subtarget.isUnalignedMem16Slow())
6302       // Do not introduce a slow unaligned store.
6303       return false;
6304     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6305     // memory access is slow above.
6306     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6307     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6308     SDNode *Store =
6309         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6310                            dl, MVT::Other, AddrOps);
6311     NewNodes.push_back(Store);
6312 
6313     // Preserve memory reference information.
6314     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6315   }
6316 
6317   return true;
6318 }
6319 
6320 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6321                                       bool UnfoldLoad, bool UnfoldStore,
6322                                       unsigned *LoadRegIndex) const {
6323   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6324   if (I == nullptr)
6325     return 0;
6326   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6327   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6328   if (UnfoldLoad && !FoldedLoad)
6329     return 0;
6330   if (UnfoldStore && !FoldedStore)
6331     return 0;
6332   if (LoadRegIndex)
6333     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6334   return I->DstOp;
6335 }
6336 
6337 bool
6338 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6339                                      int64_t &Offset1, int64_t &Offset2) const {
6340   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6341     return false;
6342   unsigned Opc1 = Load1->getMachineOpcode();
6343   unsigned Opc2 = Load2->getMachineOpcode();
6344   switch (Opc1) {
6345   default: return false;
6346   case X86::MOV8rm:
6347   case X86::MOV16rm:
6348   case X86::MOV32rm:
6349   case X86::MOV64rm:
6350   case X86::LD_Fp32m:
6351   case X86::LD_Fp64m:
6352   case X86::LD_Fp80m:
6353   case X86::MOVSSrm:
6354   case X86::MOVSSrm_alt:
6355   case X86::MOVSDrm:
6356   case X86::MOVSDrm_alt:
6357   case X86::MMX_MOVD64rm:
6358   case X86::MMX_MOVQ64rm:
6359   case X86::MOVAPSrm:
6360   case X86::MOVUPSrm:
6361   case X86::MOVAPDrm:
6362   case X86::MOVUPDrm:
6363   case X86::MOVDQArm:
6364   case X86::MOVDQUrm:
6365   // AVX load instructions
6366   case X86::VMOVSSrm:
6367   case X86::VMOVSSrm_alt:
6368   case X86::VMOVSDrm:
6369   case X86::VMOVSDrm_alt:
6370   case X86::VMOVAPSrm:
6371   case X86::VMOVUPSrm:
6372   case X86::VMOVAPDrm:
6373   case X86::VMOVUPDrm:
6374   case X86::VMOVDQArm:
6375   case X86::VMOVDQUrm:
6376   case X86::VMOVAPSYrm:
6377   case X86::VMOVUPSYrm:
6378   case X86::VMOVAPDYrm:
6379   case X86::VMOVUPDYrm:
6380   case X86::VMOVDQAYrm:
6381   case X86::VMOVDQUYrm:
6382   // AVX512 load instructions
6383   case X86::VMOVSSZrm:
6384   case X86::VMOVSSZrm_alt:
6385   case X86::VMOVSDZrm:
6386   case X86::VMOVSDZrm_alt:
6387   case X86::VMOVAPSZ128rm:
6388   case X86::VMOVUPSZ128rm:
6389   case X86::VMOVAPSZ128rm_NOVLX:
6390   case X86::VMOVUPSZ128rm_NOVLX:
6391   case X86::VMOVAPDZ128rm:
6392   case X86::VMOVUPDZ128rm:
6393   case X86::VMOVDQU8Z128rm:
6394   case X86::VMOVDQU16Z128rm:
6395   case X86::VMOVDQA32Z128rm:
6396   case X86::VMOVDQU32Z128rm:
6397   case X86::VMOVDQA64Z128rm:
6398   case X86::VMOVDQU64Z128rm:
6399   case X86::VMOVAPSZ256rm:
6400   case X86::VMOVUPSZ256rm:
6401   case X86::VMOVAPSZ256rm_NOVLX:
6402   case X86::VMOVUPSZ256rm_NOVLX:
6403   case X86::VMOVAPDZ256rm:
6404   case X86::VMOVUPDZ256rm:
6405   case X86::VMOVDQU8Z256rm:
6406   case X86::VMOVDQU16Z256rm:
6407   case X86::VMOVDQA32Z256rm:
6408   case X86::VMOVDQU32Z256rm:
6409   case X86::VMOVDQA64Z256rm:
6410   case X86::VMOVDQU64Z256rm:
6411   case X86::VMOVAPSZrm:
6412   case X86::VMOVUPSZrm:
6413   case X86::VMOVAPDZrm:
6414   case X86::VMOVUPDZrm:
6415   case X86::VMOVDQU8Zrm:
6416   case X86::VMOVDQU16Zrm:
6417   case X86::VMOVDQA32Zrm:
6418   case X86::VMOVDQU32Zrm:
6419   case X86::VMOVDQA64Zrm:
6420   case X86::VMOVDQU64Zrm:
6421   case X86::KMOVBkm:
6422   case X86::KMOVWkm:
6423   case X86::KMOVDkm:
6424   case X86::KMOVQkm:
6425     break;
6426   }
6427   switch (Opc2) {
6428   default: return false;
6429   case X86::MOV8rm:
6430   case X86::MOV16rm:
6431   case X86::MOV32rm:
6432   case X86::MOV64rm:
6433   case X86::LD_Fp32m:
6434   case X86::LD_Fp64m:
6435   case X86::LD_Fp80m:
6436   case X86::MOVSSrm:
6437   case X86::MOVSSrm_alt:
6438   case X86::MOVSDrm:
6439   case X86::MOVSDrm_alt:
6440   case X86::MMX_MOVD64rm:
6441   case X86::MMX_MOVQ64rm:
6442   case X86::MOVAPSrm:
6443   case X86::MOVUPSrm:
6444   case X86::MOVAPDrm:
6445   case X86::MOVUPDrm:
6446   case X86::MOVDQArm:
6447   case X86::MOVDQUrm:
6448   // AVX load instructions
6449   case X86::VMOVSSrm:
6450   case X86::VMOVSSrm_alt:
6451   case X86::VMOVSDrm:
6452   case X86::VMOVSDrm_alt:
6453   case X86::VMOVAPSrm:
6454   case X86::VMOVUPSrm:
6455   case X86::VMOVAPDrm:
6456   case X86::VMOVUPDrm:
6457   case X86::VMOVDQArm:
6458   case X86::VMOVDQUrm:
6459   case X86::VMOVAPSYrm:
6460   case X86::VMOVUPSYrm:
6461   case X86::VMOVAPDYrm:
6462   case X86::VMOVUPDYrm:
6463   case X86::VMOVDQAYrm:
6464   case X86::VMOVDQUYrm:
6465   // AVX512 load instructions
6466   case X86::VMOVSSZrm:
6467   case X86::VMOVSSZrm_alt:
6468   case X86::VMOVSDZrm:
6469   case X86::VMOVSDZrm_alt:
6470   case X86::VMOVAPSZ128rm:
6471   case X86::VMOVUPSZ128rm:
6472   case X86::VMOVAPSZ128rm_NOVLX:
6473   case X86::VMOVUPSZ128rm_NOVLX:
6474   case X86::VMOVAPDZ128rm:
6475   case X86::VMOVUPDZ128rm:
6476   case X86::VMOVDQU8Z128rm:
6477   case X86::VMOVDQU16Z128rm:
6478   case X86::VMOVDQA32Z128rm:
6479   case X86::VMOVDQU32Z128rm:
6480   case X86::VMOVDQA64Z128rm:
6481   case X86::VMOVDQU64Z128rm:
6482   case X86::VMOVAPSZ256rm:
6483   case X86::VMOVUPSZ256rm:
6484   case X86::VMOVAPSZ256rm_NOVLX:
6485   case X86::VMOVUPSZ256rm_NOVLX:
6486   case X86::VMOVAPDZ256rm:
6487   case X86::VMOVUPDZ256rm:
6488   case X86::VMOVDQU8Z256rm:
6489   case X86::VMOVDQU16Z256rm:
6490   case X86::VMOVDQA32Z256rm:
6491   case X86::VMOVDQU32Z256rm:
6492   case X86::VMOVDQA64Z256rm:
6493   case X86::VMOVDQU64Z256rm:
6494   case X86::VMOVAPSZrm:
6495   case X86::VMOVUPSZrm:
6496   case X86::VMOVAPDZrm:
6497   case X86::VMOVUPDZrm:
6498   case X86::VMOVDQU8Zrm:
6499   case X86::VMOVDQU16Zrm:
6500   case X86::VMOVDQA32Zrm:
6501   case X86::VMOVDQU32Zrm:
6502   case X86::VMOVDQA64Zrm:
6503   case X86::VMOVDQU64Zrm:
6504   case X86::KMOVBkm:
6505   case X86::KMOVWkm:
6506   case X86::KMOVDkm:
6507   case X86::KMOVQkm:
6508     break;
6509   }
6510 
6511   // Lambda to check if both the loads have the same value for an operand index.
6512   auto HasSameOp = [&](int I) {
6513     return Load1->getOperand(I) == Load2->getOperand(I);
6514   };
6515 
6516   // All operands except the displacement should match.
6517   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6518       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6519     return false;
6520 
6521   // Chain Operand must be the same.
6522   if (!HasSameOp(5))
6523     return false;
6524 
6525   // Now let's examine if the displacements are constants.
6526   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6527   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6528   if (!Disp1 || !Disp2)
6529     return false;
6530 
6531   Offset1 = Disp1->getSExtValue();
6532   Offset2 = Disp2->getSExtValue();
6533   return true;
6534 }
6535 
6536 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6537                                            int64_t Offset1, int64_t Offset2,
6538                                            unsigned NumLoads) const {
6539   assert(Offset2 > Offset1);
6540   if ((Offset2 - Offset1) / 8 > 64)
6541     return false;
6542 
6543   unsigned Opc1 = Load1->getMachineOpcode();
6544   unsigned Opc2 = Load2->getMachineOpcode();
6545   if (Opc1 != Opc2)
6546     return false;  // FIXME: overly conservative?
6547 
6548   switch (Opc1) {
6549   default: break;
6550   case X86::LD_Fp32m:
6551   case X86::LD_Fp64m:
6552   case X86::LD_Fp80m:
6553   case X86::MMX_MOVD64rm:
6554   case X86::MMX_MOVQ64rm:
6555     return false;
6556   }
6557 
6558   EVT VT = Load1->getValueType(0);
6559   switch (VT.getSimpleVT().SimpleTy) {
6560   default:
6561     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6562     // have 16 of them to play with.
6563     if (Subtarget.is64Bit()) {
6564       if (NumLoads >= 3)
6565         return false;
6566     } else if (NumLoads) {
6567       return false;
6568     }
6569     break;
6570   case MVT::i8:
6571   case MVT::i16:
6572   case MVT::i32:
6573   case MVT::i64:
6574   case MVT::f32:
6575   case MVT::f64:
6576     if (NumLoads)
6577       return false;
6578     break;
6579   }
6580 
6581   return true;
6582 }
6583 
6584 bool X86InstrInfo::
6585 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6586   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6587   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6588   Cond[0].setImm(GetOppositeBranchCondition(CC));
6589   return false;
6590 }
6591 
6592 bool X86InstrInfo::
6593 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6594   // FIXME: Return false for x87 stack register classes for now. We can't
6595   // allow any loads of these registers before FpGet_ST0_80.
6596   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6597            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6598            RC == &X86::RFP80RegClass);
6599 }
6600 
6601 /// Return a virtual register initialized with the
6602 /// the global base register value. Output instructions required to
6603 /// initialize the register in the function entry block, if necessary.
6604 ///
6605 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6606 ///
6607 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6608   assert((!Subtarget.is64Bit() ||
6609           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6610           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6611          "X86-64 PIC uses RIP relative addressing");
6612 
6613   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6614   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6615   if (GlobalBaseReg != 0)
6616     return GlobalBaseReg;
6617 
6618   // Create the register. The code to initialize it is inserted
6619   // later, by the CGBR pass (below).
6620   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6621   GlobalBaseReg = RegInfo.createVirtualRegister(
6622       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6623   X86FI->setGlobalBaseReg(GlobalBaseReg);
6624   return GlobalBaseReg;
6625 }
6626 
6627 // These are the replaceable SSE instructions. Some of these have Int variants
6628 // that we don't include here. We don't want to replace instructions selected
6629 // by intrinsics.
6630 static const uint16_t ReplaceableInstrs[][3] = {
6631   //PackedSingle     PackedDouble    PackedInt
6632   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6633   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6634   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6635   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6636   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6637   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
6638   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
6639   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
6640   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
6641   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
6642   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
6643   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
6644   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6645   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6646   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6647   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6648   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6649   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6650   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6651   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6652   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6653   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
6654   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
6655   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
6656   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
6657   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
6658   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
6659   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
6660   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
6661   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
6662   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
6663   // AVX 128-bit support
6664   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6665   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6666   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6667   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6668   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6669   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
6670   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
6671   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
6672   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
6673   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
6674   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
6675   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
6676   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6677   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6678   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6679   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6680   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6681   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6682   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6683   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6684   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6685   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
6686   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
6687   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
6688   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
6689   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
6690   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
6691   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
6692   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
6693   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
6694   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
6695   // AVX 256-bit support
6696   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6697   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6698   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6699   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6700   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6701   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
6702   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
6703   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
6704   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
6705   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
6706   // AVX512 support
6707   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
6708   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6709   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6710   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
6711   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
6712   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
6713   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
6714   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
6715   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
6716   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
6717   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
6718   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
6719   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
6720   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
6721   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
6722   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
6723   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
6724   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
6725   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
6726   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
6727   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
6728   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
6729   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
6730   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
6731   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
6732   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
6733   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
6734   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
6735   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
6736   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
6737   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6738   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6739   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6740   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6741   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
6742   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
6743   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
6744   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
6745   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
6746   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
6747   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
6748   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
6749   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6750   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6751   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6752   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6753   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
6754   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
6755   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
6756   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
6757   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
6758   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
6759   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
6760   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
6761   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
6762   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
6763   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
6764   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
6765   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
6766   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
6767   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
6768   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
6769   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
6770   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
6771   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
6772   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
6773   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
6774   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
6775   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
6776   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
6777   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
6778   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
6779   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
6780   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
6781   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
6782   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
6783   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
6784   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
6785   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
6786   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
6787   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
6788   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
6789   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
6790   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
6791   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
6792   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
6793   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
6794   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
6795   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
6796   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
6797   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
6798   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
6799 };
6800 
6801 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6802   //PackedSingle       PackedDouble       PackedInt
6803   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6804   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6805   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6806   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6807   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6808   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6809   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6810   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6811   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6812   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6813   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6814   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6815   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
6816   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
6817   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6818   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6819   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6820   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6821   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
6822   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
6823   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
6824   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
6825   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
6826   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
6827   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
6828   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
6829   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
6830   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
6831   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
6832   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
6833   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
6834 };
6835 
6836 static const uint16_t ReplaceableInstrsFP[][3] = {
6837   //PackedSingle         PackedDouble
6838   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
6839   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
6840   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
6841   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
6842   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
6843   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
6844   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
6845   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
6846   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
6847 };
6848 
6849 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6850   //PackedSingle       PackedDouble       PackedInt
6851   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6852   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6853   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6854   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6855 };
6856 
6857 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6858   // Two integer columns for 64-bit and 32-bit elements.
6859   //PackedSingle        PackedDouble        PackedInt             PackedInt
6860   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
6861   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
6862   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
6863   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
6864   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
6865   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
6866   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
6867   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
6868   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
6869   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
6870   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
6871   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
6872   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
6873   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
6874   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
6875 };
6876 
6877 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6878   // Two integer columns for 64-bit and 32-bit elements.
6879   //PackedSingle        PackedDouble        PackedInt           PackedInt
6880   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6881   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6882   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
6883   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
6884   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
6885   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
6886   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
6887   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
6888   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6889   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6890   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
6891   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
6892   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
6893   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
6894   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
6895   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
6896   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
6897   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
6898   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
6899   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
6900   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
6901   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
6902   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
6903   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
6904 };
6905 
6906 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6907   // Two integer columns for 64-bit and 32-bit elements.
6908   //PackedSingle          PackedDouble
6909   //PackedInt             PackedInt
6910   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
6911     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
6912   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6913     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6914   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
6915     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
6916   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6917     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6918   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
6919     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
6920   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
6921     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
6922   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
6923     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
6924   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
6925     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
6926   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
6927     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
6928   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
6929     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
6930   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
6931     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
6932   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
6933     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
6934   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
6935     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
6936   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
6937     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
6938   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
6939     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
6940   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
6941     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
6942   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
6943     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
6944   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6945     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6946   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
6947     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
6948   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6949     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6950   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
6951     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
6952   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
6953     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
6954   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
6955     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
6956   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
6957     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
6958   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
6959     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
6960   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
6961     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
6962   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
6963     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
6964   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
6965     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
6966   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
6967     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
6968   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
6969     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
6970   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
6971     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
6972   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
6973     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
6974   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
6975     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
6976   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
6977     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
6978   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
6979     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
6980   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
6981     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
6982   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
6983     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
6984   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
6985     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
6986   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
6987     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
6988   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
6989     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
6990   { X86::VORPSZrmk,       X86::VORPDZrmk,
6991     X86::VPORQZrmk,       X86::VPORDZrmk       },
6992   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
6993     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
6994   { X86::VORPSZrrk,       X86::VORPDZrrk,
6995     X86::VPORQZrrk,       X86::VPORDZrrk       },
6996   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
6997     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
6998   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
6999     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7000   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7001     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7002   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7003     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7004   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7005     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7006   // Broadcast loads can be handled the same as masked operations to avoid
7007   // changing element size.
7008   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7009     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7010   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7011     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7012   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7013     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7014   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7015     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7016   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7017     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7018   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7019     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7020   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7021     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7022   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7023     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7024   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7025     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7026   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7027     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7028   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7029     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7030   { X86::VORPSZrmb,       X86::VORPDZrmb,
7031     X86::VPORQZrmb,       X86::VPORDZrmb       },
7032   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7033     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7034   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7035     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7036   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7037     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7038   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7039     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7040   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7041     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7042   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7043     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7044   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7045     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7046   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7047     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7048   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7049     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7050   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7051     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7052   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7053     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7054   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7055     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7056   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7057     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7058   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7059     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7060   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7061     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7062   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7063     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7064   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7065     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7066   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7067     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7068   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7069     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7070   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7071     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7072   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7073     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7074   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7075     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7076   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7077     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7078   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7079     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7080   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7081     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7082   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7083     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7084   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7085     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7086 };
7087 
7088 // NOTE: These should only be used by the custom domain methods.
7089 static const uint16_t ReplaceableBlendInstrs[][3] = {
7090   //PackedSingle             PackedDouble             PackedInt
7091   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7092   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7093   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7094   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7095   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7096   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7097 };
7098 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7099   //PackedSingle             PackedDouble             PackedInt
7100   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7101   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7102   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7103   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7104 };
7105 
7106 // Special table for changing EVEX logic instructions to VEX.
7107 // TODO: Should we run EVEX->VEX earlier?
7108 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7109   // Two integer columns for 64-bit and 32-bit elements.
7110   //PackedSingle     PackedDouble     PackedInt           PackedInt
7111   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7112   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7113   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7114   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7115   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7116   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7117   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7118   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7119   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7120   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7121   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7122   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7123   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7124   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7125   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7126   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7127 };
7128 
7129 // FIXME: Some shuffle and unpack instructions have equivalents in different
7130 // domains, but they require a bit more work than just switching opcodes.
7131 
7132 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7133                               ArrayRef<uint16_t[3]> Table) {
7134   for (const uint16_t (&Row)[3] : Table)
7135     if (Row[domain-1] == opcode)
7136       return Row;
7137   return nullptr;
7138 }
7139 
7140 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7141                                     ArrayRef<uint16_t[4]> Table) {
7142   // If this is the integer domain make sure to check both integer columns.
7143   for (const uint16_t (&Row)[4] : Table)
7144     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7145       return Row;
7146   return nullptr;
7147 }
7148 
7149 // Helper to attempt to widen/narrow blend masks.
7150 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7151                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7152   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7153          "Illegal blend mask scale");
7154   unsigned NewMask = 0;
7155 
7156   if ((OldWidth % NewWidth) == 0) {
7157     unsigned Scale = OldWidth / NewWidth;
7158     unsigned SubMask = (1u << Scale) - 1;
7159     for (unsigned i = 0; i != NewWidth; ++i) {
7160       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7161       if (Sub == SubMask)
7162         NewMask |= (1u << i);
7163       else if (Sub != 0x0)
7164         return false;
7165     }
7166   } else {
7167     unsigned Scale = NewWidth / OldWidth;
7168     unsigned SubMask = (1u << Scale) - 1;
7169     for (unsigned i = 0; i != OldWidth; ++i) {
7170       if (OldMask & (1 << i)) {
7171         NewMask |= (SubMask << (i * Scale));
7172       }
7173     }
7174   }
7175 
7176   if (pNewMask)
7177     *pNewMask = NewMask;
7178   return true;
7179 }
7180 
7181 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7182   unsigned Opcode = MI.getOpcode();
7183   unsigned NumOperands = MI.getDesc().getNumOperands();
7184 
7185   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7186     uint16_t validDomains = 0;
7187     if (MI.getOperand(NumOperands - 1).isImm()) {
7188       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7189       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7190         validDomains |= 0x2; // PackedSingle
7191       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7192         validDomains |= 0x4; // PackedDouble
7193       if (!Is256 || Subtarget.hasAVX2())
7194         validDomains |= 0x8; // PackedInt
7195     }
7196     return validDomains;
7197   };
7198 
7199   switch (Opcode) {
7200   case X86::BLENDPDrmi:
7201   case X86::BLENDPDrri:
7202   case X86::VBLENDPDrmi:
7203   case X86::VBLENDPDrri:
7204     return GetBlendDomains(2, false);
7205   case X86::VBLENDPDYrmi:
7206   case X86::VBLENDPDYrri:
7207     return GetBlendDomains(4, true);
7208   case X86::BLENDPSrmi:
7209   case X86::BLENDPSrri:
7210   case X86::VBLENDPSrmi:
7211   case X86::VBLENDPSrri:
7212   case X86::VPBLENDDrmi:
7213   case X86::VPBLENDDrri:
7214     return GetBlendDomains(4, false);
7215   case X86::VBLENDPSYrmi:
7216   case X86::VBLENDPSYrri:
7217   case X86::VPBLENDDYrmi:
7218   case X86::VPBLENDDYrri:
7219     return GetBlendDomains(8, true);
7220   case X86::PBLENDWrmi:
7221   case X86::PBLENDWrri:
7222   case X86::VPBLENDWrmi:
7223   case X86::VPBLENDWrri:
7224   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7225   case X86::VPBLENDWYrmi:
7226   case X86::VPBLENDWYrri:
7227     return GetBlendDomains(8, false);
7228   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7229   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7230   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7231   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7232   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7233   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7234   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7235   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7236   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7237   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7238   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7239   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7240   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7241   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7242   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7243   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7244     // If we don't have DQI see if we can still switch from an EVEX integer
7245     // instruction to a VEX floating point instruction.
7246     if (Subtarget.hasDQI())
7247       return 0;
7248 
7249     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7250       return 0;
7251     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7252       return 0;
7253     // Register forms will have 3 operands. Memory form will have more.
7254     if (NumOperands == 3 &&
7255         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7256       return 0;
7257 
7258     // All domains are valid.
7259     return 0xe;
7260   case X86::MOVHLPSrr:
7261     // We can swap domains when both inputs are the same register.
7262     // FIXME: This doesn't catch all the cases we would like. If the input
7263     // register isn't KILLed by the instruction, the two address instruction
7264     // pass puts a COPY on one input. The other input uses the original
7265     // register. This prevents the same physical register from being used by
7266     // both inputs.
7267     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7268         MI.getOperand(0).getSubReg() == 0 &&
7269         MI.getOperand(1).getSubReg() == 0 &&
7270         MI.getOperand(2).getSubReg() == 0)
7271       return 0x6;
7272     return 0;
7273   case X86::SHUFPDrri:
7274     return 0x6;
7275   }
7276   return 0;
7277 }
7278 
7279 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7280                                             unsigned Domain) const {
7281   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7282   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7283   assert(dom && "Not an SSE instruction");
7284 
7285   unsigned Opcode = MI.getOpcode();
7286   unsigned NumOperands = MI.getDesc().getNumOperands();
7287 
7288   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7289     if (MI.getOperand(NumOperands - 1).isImm()) {
7290       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7291       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7292       unsigned NewImm = Imm;
7293 
7294       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7295       if (!table)
7296         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7297 
7298       if (Domain == 1) { // PackedSingle
7299         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7300       } else if (Domain == 2) { // PackedDouble
7301         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7302       } else if (Domain == 3) { // PackedInt
7303         if (Subtarget.hasAVX2()) {
7304           // If we are already VPBLENDW use that, else use VPBLENDD.
7305           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7306             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7307             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7308           }
7309         } else {
7310           assert(!Is256 && "128-bit vector expected");
7311           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7312         }
7313       }
7314 
7315       assert(table && table[Domain - 1] && "Unknown domain op");
7316       MI.setDesc(get(table[Domain - 1]));
7317       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7318     }
7319     return true;
7320   };
7321 
7322   switch (Opcode) {
7323   case X86::BLENDPDrmi:
7324   case X86::BLENDPDrri:
7325   case X86::VBLENDPDrmi:
7326   case X86::VBLENDPDrri:
7327     return SetBlendDomain(2, false);
7328   case X86::VBLENDPDYrmi:
7329   case X86::VBLENDPDYrri:
7330     return SetBlendDomain(4, true);
7331   case X86::BLENDPSrmi:
7332   case X86::BLENDPSrri:
7333   case X86::VBLENDPSrmi:
7334   case X86::VBLENDPSrri:
7335   case X86::VPBLENDDrmi:
7336   case X86::VPBLENDDrri:
7337     return SetBlendDomain(4, false);
7338   case X86::VBLENDPSYrmi:
7339   case X86::VBLENDPSYrri:
7340   case X86::VPBLENDDYrmi:
7341   case X86::VPBLENDDYrri:
7342     return SetBlendDomain(8, true);
7343   case X86::PBLENDWrmi:
7344   case X86::PBLENDWrri:
7345   case X86::VPBLENDWrmi:
7346   case X86::VPBLENDWrri:
7347     return SetBlendDomain(8, false);
7348   case X86::VPBLENDWYrmi:
7349   case X86::VPBLENDWYrri:
7350     return SetBlendDomain(16, true);
7351   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7352   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7353   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7354   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7355   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7356   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7357   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7358   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7359   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7360   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7361   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7362   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7363   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7364   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7365   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7366   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7367     // Without DQI, convert EVEX instructions to VEX instructions.
7368     if (Subtarget.hasDQI())
7369       return false;
7370 
7371     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7372                                          ReplaceableCustomAVX512LogicInstrs);
7373     assert(table && "Instruction not found in table?");
7374     // Don't change integer Q instructions to D instructions and
7375     // use D intructions if we started with a PS instruction.
7376     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7377       Domain = 4;
7378     MI.setDesc(get(table[Domain - 1]));
7379     return true;
7380   }
7381   case X86::UNPCKHPDrr:
7382   case X86::MOVHLPSrr:
7383     // We just need to commute the instruction which will switch the domains.
7384     if (Domain != dom && Domain != 3 &&
7385         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7386         MI.getOperand(0).getSubReg() == 0 &&
7387         MI.getOperand(1).getSubReg() == 0 &&
7388         MI.getOperand(2).getSubReg() == 0) {
7389       commuteInstruction(MI, false);
7390       return true;
7391     }
7392     // We must always return true for MOVHLPSrr.
7393     if (Opcode == X86::MOVHLPSrr)
7394       return true;
7395     break;
7396   case X86::SHUFPDrri: {
7397     if (Domain == 1) {
7398       unsigned Imm = MI.getOperand(3).getImm();
7399       unsigned NewImm = 0x44;
7400       if (Imm & 1) NewImm |= 0x0a;
7401       if (Imm & 2) NewImm |= 0xa0;
7402       MI.getOperand(3).setImm(NewImm);
7403       MI.setDesc(get(X86::SHUFPSrri));
7404     }
7405     return true;
7406   }
7407   }
7408   return false;
7409 }
7410 
7411 std::pair<uint16_t, uint16_t>
7412 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7413   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7414   unsigned opcode = MI.getOpcode();
7415   uint16_t validDomains = 0;
7416   if (domain) {
7417     // Attempt to match for custom instructions.
7418     validDomains = getExecutionDomainCustom(MI);
7419     if (validDomains)
7420       return std::make_pair(domain, validDomains);
7421 
7422     if (lookup(opcode, domain, ReplaceableInstrs)) {
7423       validDomains = 0xe;
7424     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7425       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7426     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7427       validDomains = 0x6;
7428     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7429       // Insert/extract instructions should only effect domain if AVX2
7430       // is enabled.
7431       if (!Subtarget.hasAVX2())
7432         return std::make_pair(0, 0);
7433       validDomains = 0xe;
7434     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7435       validDomains = 0xe;
7436     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7437                                                   ReplaceableInstrsAVX512DQ)) {
7438       validDomains = 0xe;
7439     } else if (Subtarget.hasDQI()) {
7440       if (const uint16_t *table = lookupAVX512(opcode, domain,
7441                                              ReplaceableInstrsAVX512DQMasked)) {
7442         if (domain == 1 || (domain == 3 && table[3] == opcode))
7443           validDomains = 0xa;
7444         else
7445           validDomains = 0xc;
7446       }
7447     }
7448   }
7449   return std::make_pair(domain, validDomains);
7450 }
7451 
7452 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7453   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7454   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7455   assert(dom && "Not an SSE instruction");
7456 
7457   // Attempt to match for custom instructions.
7458   if (setExecutionDomainCustom(MI, Domain))
7459     return;
7460 
7461   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7462   if (!table) { // try the other table
7463     assert((Subtarget.hasAVX2() || Domain < 3) &&
7464            "256-bit vector operations only available in AVX2");
7465     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7466   }
7467   if (!table) { // try the FP table
7468     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7469     assert((!table || Domain < 3) &&
7470            "Can only select PackedSingle or PackedDouble");
7471   }
7472   if (!table) { // try the other table
7473     assert(Subtarget.hasAVX2() &&
7474            "256-bit insert/extract only available in AVX2");
7475     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7476   }
7477   if (!table) { // try the AVX512 table
7478     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7479     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7480     // Don't change integer Q instructions to D instructions.
7481     if (table && Domain == 3 && table[3] == MI.getOpcode())
7482       Domain = 4;
7483   }
7484   if (!table) { // try the AVX512DQ table
7485     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7486     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7487     // Don't change integer Q instructions to D instructions and
7488     // use D intructions if we started with a PS instruction.
7489     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7490       Domain = 4;
7491   }
7492   if (!table) { // try the AVX512DQMasked table
7493     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7494     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7495     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7496       Domain = 4;
7497   }
7498   assert(table && "Cannot change domain");
7499   MI.setDesc(get(table[Domain - 1]));
7500 }
7501 
7502 /// Return the noop instruction to use for a noop.
7503 void X86InstrInfo::getNoop(MCInst &NopInst) const {
7504   NopInst.setOpcode(X86::NOOP);
7505 }
7506 
7507 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7508   switch (opc) {
7509   default: return false;
7510   case X86::DIVPDrm:
7511   case X86::DIVPDrr:
7512   case X86::DIVPSrm:
7513   case X86::DIVPSrr:
7514   case X86::DIVSDrm:
7515   case X86::DIVSDrm_Int:
7516   case X86::DIVSDrr:
7517   case X86::DIVSDrr_Int:
7518   case X86::DIVSSrm:
7519   case X86::DIVSSrm_Int:
7520   case X86::DIVSSrr:
7521   case X86::DIVSSrr_Int:
7522   case X86::SQRTPDm:
7523   case X86::SQRTPDr:
7524   case X86::SQRTPSm:
7525   case X86::SQRTPSr:
7526   case X86::SQRTSDm:
7527   case X86::SQRTSDm_Int:
7528   case X86::SQRTSDr:
7529   case X86::SQRTSDr_Int:
7530   case X86::SQRTSSm:
7531   case X86::SQRTSSm_Int:
7532   case X86::SQRTSSr:
7533   case X86::SQRTSSr_Int:
7534   // AVX instructions with high latency
7535   case X86::VDIVPDrm:
7536   case X86::VDIVPDrr:
7537   case X86::VDIVPDYrm:
7538   case X86::VDIVPDYrr:
7539   case X86::VDIVPSrm:
7540   case X86::VDIVPSrr:
7541   case X86::VDIVPSYrm:
7542   case X86::VDIVPSYrr:
7543   case X86::VDIVSDrm:
7544   case X86::VDIVSDrm_Int:
7545   case X86::VDIVSDrr:
7546   case X86::VDIVSDrr_Int:
7547   case X86::VDIVSSrm:
7548   case X86::VDIVSSrm_Int:
7549   case X86::VDIVSSrr:
7550   case X86::VDIVSSrr_Int:
7551   case X86::VSQRTPDm:
7552   case X86::VSQRTPDr:
7553   case X86::VSQRTPDYm:
7554   case X86::VSQRTPDYr:
7555   case X86::VSQRTPSm:
7556   case X86::VSQRTPSr:
7557   case X86::VSQRTPSYm:
7558   case X86::VSQRTPSYr:
7559   case X86::VSQRTSDm:
7560   case X86::VSQRTSDm_Int:
7561   case X86::VSQRTSDr:
7562   case X86::VSQRTSDr_Int:
7563   case X86::VSQRTSSm:
7564   case X86::VSQRTSSm_Int:
7565   case X86::VSQRTSSr:
7566   case X86::VSQRTSSr_Int:
7567   // AVX512 instructions with high latency
7568   case X86::VDIVPDZ128rm:
7569   case X86::VDIVPDZ128rmb:
7570   case X86::VDIVPDZ128rmbk:
7571   case X86::VDIVPDZ128rmbkz:
7572   case X86::VDIVPDZ128rmk:
7573   case X86::VDIVPDZ128rmkz:
7574   case X86::VDIVPDZ128rr:
7575   case X86::VDIVPDZ128rrk:
7576   case X86::VDIVPDZ128rrkz:
7577   case X86::VDIVPDZ256rm:
7578   case X86::VDIVPDZ256rmb:
7579   case X86::VDIVPDZ256rmbk:
7580   case X86::VDIVPDZ256rmbkz:
7581   case X86::VDIVPDZ256rmk:
7582   case X86::VDIVPDZ256rmkz:
7583   case X86::VDIVPDZ256rr:
7584   case X86::VDIVPDZ256rrk:
7585   case X86::VDIVPDZ256rrkz:
7586   case X86::VDIVPDZrrb:
7587   case X86::VDIVPDZrrbk:
7588   case X86::VDIVPDZrrbkz:
7589   case X86::VDIVPDZrm:
7590   case X86::VDIVPDZrmb:
7591   case X86::VDIVPDZrmbk:
7592   case X86::VDIVPDZrmbkz:
7593   case X86::VDIVPDZrmk:
7594   case X86::VDIVPDZrmkz:
7595   case X86::VDIVPDZrr:
7596   case X86::VDIVPDZrrk:
7597   case X86::VDIVPDZrrkz:
7598   case X86::VDIVPSZ128rm:
7599   case X86::VDIVPSZ128rmb:
7600   case X86::VDIVPSZ128rmbk:
7601   case X86::VDIVPSZ128rmbkz:
7602   case X86::VDIVPSZ128rmk:
7603   case X86::VDIVPSZ128rmkz:
7604   case X86::VDIVPSZ128rr:
7605   case X86::VDIVPSZ128rrk:
7606   case X86::VDIVPSZ128rrkz:
7607   case X86::VDIVPSZ256rm:
7608   case X86::VDIVPSZ256rmb:
7609   case X86::VDIVPSZ256rmbk:
7610   case X86::VDIVPSZ256rmbkz:
7611   case X86::VDIVPSZ256rmk:
7612   case X86::VDIVPSZ256rmkz:
7613   case X86::VDIVPSZ256rr:
7614   case X86::VDIVPSZ256rrk:
7615   case X86::VDIVPSZ256rrkz:
7616   case X86::VDIVPSZrrb:
7617   case X86::VDIVPSZrrbk:
7618   case X86::VDIVPSZrrbkz:
7619   case X86::VDIVPSZrm:
7620   case X86::VDIVPSZrmb:
7621   case X86::VDIVPSZrmbk:
7622   case X86::VDIVPSZrmbkz:
7623   case X86::VDIVPSZrmk:
7624   case X86::VDIVPSZrmkz:
7625   case X86::VDIVPSZrr:
7626   case X86::VDIVPSZrrk:
7627   case X86::VDIVPSZrrkz:
7628   case X86::VDIVSDZrm:
7629   case X86::VDIVSDZrr:
7630   case X86::VDIVSDZrm_Int:
7631   case X86::VDIVSDZrm_Intk:
7632   case X86::VDIVSDZrm_Intkz:
7633   case X86::VDIVSDZrr_Int:
7634   case X86::VDIVSDZrr_Intk:
7635   case X86::VDIVSDZrr_Intkz:
7636   case X86::VDIVSDZrrb_Int:
7637   case X86::VDIVSDZrrb_Intk:
7638   case X86::VDIVSDZrrb_Intkz:
7639   case X86::VDIVSSZrm:
7640   case X86::VDIVSSZrr:
7641   case X86::VDIVSSZrm_Int:
7642   case X86::VDIVSSZrm_Intk:
7643   case X86::VDIVSSZrm_Intkz:
7644   case X86::VDIVSSZrr_Int:
7645   case X86::VDIVSSZrr_Intk:
7646   case X86::VDIVSSZrr_Intkz:
7647   case X86::VDIVSSZrrb_Int:
7648   case X86::VDIVSSZrrb_Intk:
7649   case X86::VDIVSSZrrb_Intkz:
7650   case X86::VSQRTPDZ128m:
7651   case X86::VSQRTPDZ128mb:
7652   case X86::VSQRTPDZ128mbk:
7653   case X86::VSQRTPDZ128mbkz:
7654   case X86::VSQRTPDZ128mk:
7655   case X86::VSQRTPDZ128mkz:
7656   case X86::VSQRTPDZ128r:
7657   case X86::VSQRTPDZ128rk:
7658   case X86::VSQRTPDZ128rkz:
7659   case X86::VSQRTPDZ256m:
7660   case X86::VSQRTPDZ256mb:
7661   case X86::VSQRTPDZ256mbk:
7662   case X86::VSQRTPDZ256mbkz:
7663   case X86::VSQRTPDZ256mk:
7664   case X86::VSQRTPDZ256mkz:
7665   case X86::VSQRTPDZ256r:
7666   case X86::VSQRTPDZ256rk:
7667   case X86::VSQRTPDZ256rkz:
7668   case X86::VSQRTPDZm:
7669   case X86::VSQRTPDZmb:
7670   case X86::VSQRTPDZmbk:
7671   case X86::VSQRTPDZmbkz:
7672   case X86::VSQRTPDZmk:
7673   case X86::VSQRTPDZmkz:
7674   case X86::VSQRTPDZr:
7675   case X86::VSQRTPDZrb:
7676   case X86::VSQRTPDZrbk:
7677   case X86::VSQRTPDZrbkz:
7678   case X86::VSQRTPDZrk:
7679   case X86::VSQRTPDZrkz:
7680   case X86::VSQRTPSZ128m:
7681   case X86::VSQRTPSZ128mb:
7682   case X86::VSQRTPSZ128mbk:
7683   case X86::VSQRTPSZ128mbkz:
7684   case X86::VSQRTPSZ128mk:
7685   case X86::VSQRTPSZ128mkz:
7686   case X86::VSQRTPSZ128r:
7687   case X86::VSQRTPSZ128rk:
7688   case X86::VSQRTPSZ128rkz:
7689   case X86::VSQRTPSZ256m:
7690   case X86::VSQRTPSZ256mb:
7691   case X86::VSQRTPSZ256mbk:
7692   case X86::VSQRTPSZ256mbkz:
7693   case X86::VSQRTPSZ256mk:
7694   case X86::VSQRTPSZ256mkz:
7695   case X86::VSQRTPSZ256r:
7696   case X86::VSQRTPSZ256rk:
7697   case X86::VSQRTPSZ256rkz:
7698   case X86::VSQRTPSZm:
7699   case X86::VSQRTPSZmb:
7700   case X86::VSQRTPSZmbk:
7701   case X86::VSQRTPSZmbkz:
7702   case X86::VSQRTPSZmk:
7703   case X86::VSQRTPSZmkz:
7704   case X86::VSQRTPSZr:
7705   case X86::VSQRTPSZrb:
7706   case X86::VSQRTPSZrbk:
7707   case X86::VSQRTPSZrbkz:
7708   case X86::VSQRTPSZrk:
7709   case X86::VSQRTPSZrkz:
7710   case X86::VSQRTSDZm:
7711   case X86::VSQRTSDZm_Int:
7712   case X86::VSQRTSDZm_Intk:
7713   case X86::VSQRTSDZm_Intkz:
7714   case X86::VSQRTSDZr:
7715   case X86::VSQRTSDZr_Int:
7716   case X86::VSQRTSDZr_Intk:
7717   case X86::VSQRTSDZr_Intkz:
7718   case X86::VSQRTSDZrb_Int:
7719   case X86::VSQRTSDZrb_Intk:
7720   case X86::VSQRTSDZrb_Intkz:
7721   case X86::VSQRTSSZm:
7722   case X86::VSQRTSSZm_Int:
7723   case X86::VSQRTSSZm_Intk:
7724   case X86::VSQRTSSZm_Intkz:
7725   case X86::VSQRTSSZr:
7726   case X86::VSQRTSSZr_Int:
7727   case X86::VSQRTSSZr_Intk:
7728   case X86::VSQRTSSZr_Intkz:
7729   case X86::VSQRTSSZrb_Int:
7730   case X86::VSQRTSSZrb_Intk:
7731   case X86::VSQRTSSZrb_Intkz:
7732 
7733   case X86::VGATHERDPDYrm:
7734   case X86::VGATHERDPDZ128rm:
7735   case X86::VGATHERDPDZ256rm:
7736   case X86::VGATHERDPDZrm:
7737   case X86::VGATHERDPDrm:
7738   case X86::VGATHERDPSYrm:
7739   case X86::VGATHERDPSZ128rm:
7740   case X86::VGATHERDPSZ256rm:
7741   case X86::VGATHERDPSZrm:
7742   case X86::VGATHERDPSrm:
7743   case X86::VGATHERPF0DPDm:
7744   case X86::VGATHERPF0DPSm:
7745   case X86::VGATHERPF0QPDm:
7746   case X86::VGATHERPF0QPSm:
7747   case X86::VGATHERPF1DPDm:
7748   case X86::VGATHERPF1DPSm:
7749   case X86::VGATHERPF1QPDm:
7750   case X86::VGATHERPF1QPSm:
7751   case X86::VGATHERQPDYrm:
7752   case X86::VGATHERQPDZ128rm:
7753   case X86::VGATHERQPDZ256rm:
7754   case X86::VGATHERQPDZrm:
7755   case X86::VGATHERQPDrm:
7756   case X86::VGATHERQPSYrm:
7757   case X86::VGATHERQPSZ128rm:
7758   case X86::VGATHERQPSZ256rm:
7759   case X86::VGATHERQPSZrm:
7760   case X86::VGATHERQPSrm:
7761   case X86::VPGATHERDDYrm:
7762   case X86::VPGATHERDDZ128rm:
7763   case X86::VPGATHERDDZ256rm:
7764   case X86::VPGATHERDDZrm:
7765   case X86::VPGATHERDDrm:
7766   case X86::VPGATHERDQYrm:
7767   case X86::VPGATHERDQZ128rm:
7768   case X86::VPGATHERDQZ256rm:
7769   case X86::VPGATHERDQZrm:
7770   case X86::VPGATHERDQrm:
7771   case X86::VPGATHERQDYrm:
7772   case X86::VPGATHERQDZ128rm:
7773   case X86::VPGATHERQDZ256rm:
7774   case X86::VPGATHERQDZrm:
7775   case X86::VPGATHERQDrm:
7776   case X86::VPGATHERQQYrm:
7777   case X86::VPGATHERQQZ128rm:
7778   case X86::VPGATHERQQZ256rm:
7779   case X86::VPGATHERQQZrm:
7780   case X86::VPGATHERQQrm:
7781   case X86::VSCATTERDPDZ128mr:
7782   case X86::VSCATTERDPDZ256mr:
7783   case X86::VSCATTERDPDZmr:
7784   case X86::VSCATTERDPSZ128mr:
7785   case X86::VSCATTERDPSZ256mr:
7786   case X86::VSCATTERDPSZmr:
7787   case X86::VSCATTERPF0DPDm:
7788   case X86::VSCATTERPF0DPSm:
7789   case X86::VSCATTERPF0QPDm:
7790   case X86::VSCATTERPF0QPSm:
7791   case X86::VSCATTERPF1DPDm:
7792   case X86::VSCATTERPF1DPSm:
7793   case X86::VSCATTERPF1QPDm:
7794   case X86::VSCATTERPF1QPSm:
7795   case X86::VSCATTERQPDZ128mr:
7796   case X86::VSCATTERQPDZ256mr:
7797   case X86::VSCATTERQPDZmr:
7798   case X86::VSCATTERQPSZ128mr:
7799   case X86::VSCATTERQPSZ256mr:
7800   case X86::VSCATTERQPSZmr:
7801   case X86::VPSCATTERDDZ128mr:
7802   case X86::VPSCATTERDDZ256mr:
7803   case X86::VPSCATTERDDZmr:
7804   case X86::VPSCATTERDQZ128mr:
7805   case X86::VPSCATTERDQZ256mr:
7806   case X86::VPSCATTERDQZmr:
7807   case X86::VPSCATTERQDZ128mr:
7808   case X86::VPSCATTERQDZ256mr:
7809   case X86::VPSCATTERQDZmr:
7810   case X86::VPSCATTERQQZ128mr:
7811   case X86::VPSCATTERQQZ256mr:
7812   case X86::VPSCATTERQQZmr:
7813     return true;
7814   }
7815 }
7816 
7817 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7818                                          const MachineRegisterInfo *MRI,
7819                                          const MachineInstr &DefMI,
7820                                          unsigned DefIdx,
7821                                          const MachineInstr &UseMI,
7822                                          unsigned UseIdx) const {
7823   return isHighLatencyDef(DefMI.getOpcode());
7824 }
7825 
7826 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7827                                            const MachineBasicBlock *MBB) const {
7828   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
7829          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
7830 
7831   // Integer binary math/logic instructions have a third source operand:
7832   // the EFLAGS register. That operand must be both defined here and never
7833   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7834   // not change anything because rearranging the operands could affect other
7835   // instructions that depend on the exact status flags (zero, sign, etc.)
7836   // that are set by using these particular operands with this operation.
7837   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
7838   assert((Inst.getNumDefs() == 1 || FlagDef) &&
7839          "Implicit def isn't flags?");
7840   if (FlagDef && !FlagDef->isDead())
7841     return false;
7842 
7843   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7844 }
7845 
7846 // TODO: There are many more machine instruction opcodes to match:
7847 //       1. Other data types (integer, vectors)
7848 //       2. Other math / logic operations (xor, or)
7849 //       3. Other forms of the same operation (intrinsics and other variants)
7850 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7851   switch (Inst.getOpcode()) {
7852   case X86::AND8rr:
7853   case X86::AND16rr:
7854   case X86::AND32rr:
7855   case X86::AND64rr:
7856   case X86::OR8rr:
7857   case X86::OR16rr:
7858   case X86::OR32rr:
7859   case X86::OR64rr:
7860   case X86::XOR8rr:
7861   case X86::XOR16rr:
7862   case X86::XOR32rr:
7863   case X86::XOR64rr:
7864   case X86::IMUL16rr:
7865   case X86::IMUL32rr:
7866   case X86::IMUL64rr:
7867   case X86::PANDrr:
7868   case X86::PORrr:
7869   case X86::PXORrr:
7870   case X86::ANDPDrr:
7871   case X86::ANDPSrr:
7872   case X86::ORPDrr:
7873   case X86::ORPSrr:
7874   case X86::XORPDrr:
7875   case X86::XORPSrr:
7876   case X86::PADDBrr:
7877   case X86::PADDWrr:
7878   case X86::PADDDrr:
7879   case X86::PADDQrr:
7880   case X86::PMULLWrr:
7881   case X86::PMULLDrr:
7882   case X86::PMAXSBrr:
7883   case X86::PMAXSDrr:
7884   case X86::PMAXSWrr:
7885   case X86::PMAXUBrr:
7886   case X86::PMAXUDrr:
7887   case X86::PMAXUWrr:
7888   case X86::PMINSBrr:
7889   case X86::PMINSDrr:
7890   case X86::PMINSWrr:
7891   case X86::PMINUBrr:
7892   case X86::PMINUDrr:
7893   case X86::PMINUWrr:
7894   case X86::VPANDrr:
7895   case X86::VPANDYrr:
7896   case X86::VPANDDZ128rr:
7897   case X86::VPANDDZ256rr:
7898   case X86::VPANDDZrr:
7899   case X86::VPANDQZ128rr:
7900   case X86::VPANDQZ256rr:
7901   case X86::VPANDQZrr:
7902   case X86::VPORrr:
7903   case X86::VPORYrr:
7904   case X86::VPORDZ128rr:
7905   case X86::VPORDZ256rr:
7906   case X86::VPORDZrr:
7907   case X86::VPORQZ128rr:
7908   case X86::VPORQZ256rr:
7909   case X86::VPORQZrr:
7910   case X86::VPXORrr:
7911   case X86::VPXORYrr:
7912   case X86::VPXORDZ128rr:
7913   case X86::VPXORDZ256rr:
7914   case X86::VPXORDZrr:
7915   case X86::VPXORQZ128rr:
7916   case X86::VPXORQZ256rr:
7917   case X86::VPXORQZrr:
7918   case X86::VANDPDrr:
7919   case X86::VANDPSrr:
7920   case X86::VANDPDYrr:
7921   case X86::VANDPSYrr:
7922   case X86::VANDPDZ128rr:
7923   case X86::VANDPSZ128rr:
7924   case X86::VANDPDZ256rr:
7925   case X86::VANDPSZ256rr:
7926   case X86::VANDPDZrr:
7927   case X86::VANDPSZrr:
7928   case X86::VORPDrr:
7929   case X86::VORPSrr:
7930   case X86::VORPDYrr:
7931   case X86::VORPSYrr:
7932   case X86::VORPDZ128rr:
7933   case X86::VORPSZ128rr:
7934   case X86::VORPDZ256rr:
7935   case X86::VORPSZ256rr:
7936   case X86::VORPDZrr:
7937   case X86::VORPSZrr:
7938   case X86::VXORPDrr:
7939   case X86::VXORPSrr:
7940   case X86::VXORPDYrr:
7941   case X86::VXORPSYrr:
7942   case X86::VXORPDZ128rr:
7943   case X86::VXORPSZ128rr:
7944   case X86::VXORPDZ256rr:
7945   case X86::VXORPSZ256rr:
7946   case X86::VXORPDZrr:
7947   case X86::VXORPSZrr:
7948   case X86::KADDBrr:
7949   case X86::KADDWrr:
7950   case X86::KADDDrr:
7951   case X86::KADDQrr:
7952   case X86::KANDBrr:
7953   case X86::KANDWrr:
7954   case X86::KANDDrr:
7955   case X86::KANDQrr:
7956   case X86::KORBrr:
7957   case X86::KORWrr:
7958   case X86::KORDrr:
7959   case X86::KORQrr:
7960   case X86::KXORBrr:
7961   case X86::KXORWrr:
7962   case X86::KXORDrr:
7963   case X86::KXORQrr:
7964   case X86::VPADDBrr:
7965   case X86::VPADDWrr:
7966   case X86::VPADDDrr:
7967   case X86::VPADDQrr:
7968   case X86::VPADDBYrr:
7969   case X86::VPADDWYrr:
7970   case X86::VPADDDYrr:
7971   case X86::VPADDQYrr:
7972   case X86::VPADDBZ128rr:
7973   case X86::VPADDWZ128rr:
7974   case X86::VPADDDZ128rr:
7975   case X86::VPADDQZ128rr:
7976   case X86::VPADDBZ256rr:
7977   case X86::VPADDWZ256rr:
7978   case X86::VPADDDZ256rr:
7979   case X86::VPADDQZ256rr:
7980   case X86::VPADDBZrr:
7981   case X86::VPADDWZrr:
7982   case X86::VPADDDZrr:
7983   case X86::VPADDQZrr:
7984   case X86::VPMULLWrr:
7985   case X86::VPMULLWYrr:
7986   case X86::VPMULLWZ128rr:
7987   case X86::VPMULLWZ256rr:
7988   case X86::VPMULLWZrr:
7989   case X86::VPMULLDrr:
7990   case X86::VPMULLDYrr:
7991   case X86::VPMULLDZ128rr:
7992   case X86::VPMULLDZ256rr:
7993   case X86::VPMULLDZrr:
7994   case X86::VPMULLQZ128rr:
7995   case X86::VPMULLQZ256rr:
7996   case X86::VPMULLQZrr:
7997   case X86::VPMAXSBrr:
7998   case X86::VPMAXSBYrr:
7999   case X86::VPMAXSBZ128rr:
8000   case X86::VPMAXSBZ256rr:
8001   case X86::VPMAXSBZrr:
8002   case X86::VPMAXSDrr:
8003   case X86::VPMAXSDYrr:
8004   case X86::VPMAXSDZ128rr:
8005   case X86::VPMAXSDZ256rr:
8006   case X86::VPMAXSDZrr:
8007   case X86::VPMAXSQZ128rr:
8008   case X86::VPMAXSQZ256rr:
8009   case X86::VPMAXSQZrr:
8010   case X86::VPMAXSWrr:
8011   case X86::VPMAXSWYrr:
8012   case X86::VPMAXSWZ128rr:
8013   case X86::VPMAXSWZ256rr:
8014   case X86::VPMAXSWZrr:
8015   case X86::VPMAXUBrr:
8016   case X86::VPMAXUBYrr:
8017   case X86::VPMAXUBZ128rr:
8018   case X86::VPMAXUBZ256rr:
8019   case X86::VPMAXUBZrr:
8020   case X86::VPMAXUDrr:
8021   case X86::VPMAXUDYrr:
8022   case X86::VPMAXUDZ128rr:
8023   case X86::VPMAXUDZ256rr:
8024   case X86::VPMAXUDZrr:
8025   case X86::VPMAXUQZ128rr:
8026   case X86::VPMAXUQZ256rr:
8027   case X86::VPMAXUQZrr:
8028   case X86::VPMAXUWrr:
8029   case X86::VPMAXUWYrr:
8030   case X86::VPMAXUWZ128rr:
8031   case X86::VPMAXUWZ256rr:
8032   case X86::VPMAXUWZrr:
8033   case X86::VPMINSBrr:
8034   case X86::VPMINSBYrr:
8035   case X86::VPMINSBZ128rr:
8036   case X86::VPMINSBZ256rr:
8037   case X86::VPMINSBZrr:
8038   case X86::VPMINSDrr:
8039   case X86::VPMINSDYrr:
8040   case X86::VPMINSDZ128rr:
8041   case X86::VPMINSDZ256rr:
8042   case X86::VPMINSDZrr:
8043   case X86::VPMINSQZ128rr:
8044   case X86::VPMINSQZ256rr:
8045   case X86::VPMINSQZrr:
8046   case X86::VPMINSWrr:
8047   case X86::VPMINSWYrr:
8048   case X86::VPMINSWZ128rr:
8049   case X86::VPMINSWZ256rr:
8050   case X86::VPMINSWZrr:
8051   case X86::VPMINUBrr:
8052   case X86::VPMINUBYrr:
8053   case X86::VPMINUBZ128rr:
8054   case X86::VPMINUBZ256rr:
8055   case X86::VPMINUBZrr:
8056   case X86::VPMINUDrr:
8057   case X86::VPMINUDYrr:
8058   case X86::VPMINUDZ128rr:
8059   case X86::VPMINUDZ256rr:
8060   case X86::VPMINUDZrr:
8061   case X86::VPMINUQZ128rr:
8062   case X86::VPMINUQZ256rr:
8063   case X86::VPMINUQZrr:
8064   case X86::VPMINUWrr:
8065   case X86::VPMINUWYrr:
8066   case X86::VPMINUWZ128rr:
8067   case X86::VPMINUWZ256rr:
8068   case X86::VPMINUWZrr:
8069   // Normal min/max instructions are not commutative because of NaN and signed
8070   // zero semantics, but these are. Thus, there's no need to check for global
8071   // relaxed math; the instructions themselves have the properties we need.
8072   case X86::MAXCPDrr:
8073   case X86::MAXCPSrr:
8074   case X86::MAXCSDrr:
8075   case X86::MAXCSSrr:
8076   case X86::MINCPDrr:
8077   case X86::MINCPSrr:
8078   case X86::MINCSDrr:
8079   case X86::MINCSSrr:
8080   case X86::VMAXCPDrr:
8081   case X86::VMAXCPSrr:
8082   case X86::VMAXCPDYrr:
8083   case X86::VMAXCPSYrr:
8084   case X86::VMAXCPDZ128rr:
8085   case X86::VMAXCPSZ128rr:
8086   case X86::VMAXCPDZ256rr:
8087   case X86::VMAXCPSZ256rr:
8088   case X86::VMAXCPDZrr:
8089   case X86::VMAXCPSZrr:
8090   case X86::VMAXCSDrr:
8091   case X86::VMAXCSSrr:
8092   case X86::VMAXCSDZrr:
8093   case X86::VMAXCSSZrr:
8094   case X86::VMINCPDrr:
8095   case X86::VMINCPSrr:
8096   case X86::VMINCPDYrr:
8097   case X86::VMINCPSYrr:
8098   case X86::VMINCPDZ128rr:
8099   case X86::VMINCPSZ128rr:
8100   case X86::VMINCPDZ256rr:
8101   case X86::VMINCPSZ256rr:
8102   case X86::VMINCPDZrr:
8103   case X86::VMINCPSZrr:
8104   case X86::VMINCSDrr:
8105   case X86::VMINCSSrr:
8106   case X86::VMINCSDZrr:
8107   case X86::VMINCSSZrr:
8108     return true;
8109   case X86::ADDPDrr:
8110   case X86::ADDPSrr:
8111   case X86::ADDSDrr:
8112   case X86::ADDSSrr:
8113   case X86::MULPDrr:
8114   case X86::MULPSrr:
8115   case X86::MULSDrr:
8116   case X86::MULSSrr:
8117   case X86::VADDPDrr:
8118   case X86::VADDPSrr:
8119   case X86::VADDPDYrr:
8120   case X86::VADDPSYrr:
8121   case X86::VADDPDZ128rr:
8122   case X86::VADDPSZ128rr:
8123   case X86::VADDPDZ256rr:
8124   case X86::VADDPSZ256rr:
8125   case X86::VADDPDZrr:
8126   case X86::VADDPSZrr:
8127   case X86::VADDSDrr:
8128   case X86::VADDSSrr:
8129   case X86::VADDSDZrr:
8130   case X86::VADDSSZrr:
8131   case X86::VMULPDrr:
8132   case X86::VMULPSrr:
8133   case X86::VMULPDYrr:
8134   case X86::VMULPSYrr:
8135   case X86::VMULPDZ128rr:
8136   case X86::VMULPSZ128rr:
8137   case X86::VMULPDZ256rr:
8138   case X86::VMULPSZ256rr:
8139   case X86::VMULPDZrr:
8140   case X86::VMULPSZrr:
8141   case X86::VMULSDrr:
8142   case X86::VMULSSrr:
8143   case X86::VMULSDZrr:
8144   case X86::VMULSSZrr:
8145     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8146            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8147   default:
8148     return false;
8149   }
8150 }
8151 
8152 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8153 /// register then, if possible, describe the value in terms of the source
8154 /// register.
8155 static Optional<ParamLoadedValue>
8156 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8157                          const TargetRegisterInfo *TRI) {
8158   Register DestReg = MI.getOperand(0).getReg();
8159   Register SrcReg = MI.getOperand(1).getReg();
8160 
8161   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8162 
8163   // If the described register is the destination, just return the source.
8164   if (DestReg == DescribedReg)
8165     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8166 
8167   // If the described register is a sub-register of the destination register,
8168   // then pick out the source register's corresponding sub-register.
8169   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8170     unsigned SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8171     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8172   }
8173 
8174   // The remaining case to consider is when the described register is a
8175   // super-register of the destination register. MOV8rr and MOV16rr does not
8176   // write to any of the other bytes in the register, meaning that we'd have to
8177   // describe the value using a combination of the source register and the
8178   // non-overlapping bits in the described register, which is not currently
8179   // possible.
8180   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8181       !TRI->isSuperRegister(DestReg, DescribedReg))
8182     return None;
8183 
8184   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8185   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8186 }
8187 
8188 Optional<ParamLoadedValue>
8189 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8190   const MachineOperand *Op = nullptr;
8191   DIExpression *Expr = nullptr;
8192 
8193   const TargetRegisterInfo *TRI = &getRegisterInfo();
8194 
8195   switch (MI.getOpcode()) {
8196   case X86::LEA32r:
8197   case X86::LEA64r:
8198   case X86::LEA64_32r: {
8199     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8200     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8201       return None;
8202 
8203     // Operand 4 could be global address. For now we do not support
8204     // such situation.
8205     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8206       return None;
8207 
8208     const MachineOperand &Op1 = MI.getOperand(1);
8209     const MachineOperand &Op2 = MI.getOperand(3);
8210     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8211                            Register::isPhysicalRegister(Op2.getReg())));
8212 
8213     // Omit situations like:
8214     // %rsi = lea %rsi, 4, ...
8215     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8216         Op2.getReg() == MI.getOperand(0).getReg())
8217       return None;
8218     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8219               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8220              (Op2.getReg() != X86::NoRegister &&
8221               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8222       return None;
8223 
8224     int64_t Coef = MI.getOperand(2).getImm();
8225     int64_t Offset = MI.getOperand(4).getImm();
8226     SmallVector<uint64_t, 8> Ops;
8227 
8228     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8229       Op = &Op1;
8230     } else if (Op1.isFI())
8231       Op = &Op1;
8232 
8233     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8234       Ops.push_back(dwarf::DW_OP_constu);
8235       Ops.push_back(Coef + 1);
8236       Ops.push_back(dwarf::DW_OP_mul);
8237     } else {
8238       if (Op && Op2.getReg() != X86::NoRegister) {
8239         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8240         if (dwarfReg < 0)
8241           return None;
8242         else if (dwarfReg < 32) {
8243           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8244           Ops.push_back(0);
8245         } else {
8246           Ops.push_back(dwarf::DW_OP_bregx);
8247           Ops.push_back(dwarfReg);
8248           Ops.push_back(0);
8249         }
8250       } else if (!Op) {
8251         assert(Op2.getReg() != X86::NoRegister);
8252         Op = &Op2;
8253       }
8254 
8255       if (Coef > 1) {
8256         assert(Op2.getReg() != X86::NoRegister);
8257         Ops.push_back(dwarf::DW_OP_constu);
8258         Ops.push_back(Coef);
8259         Ops.push_back(dwarf::DW_OP_mul);
8260       }
8261 
8262       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8263           Op2.getReg() != X86::NoRegister) {
8264         Ops.push_back(dwarf::DW_OP_plus);
8265       }
8266     }
8267 
8268     DIExpression::appendOffset(Ops, Offset);
8269     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8270 
8271     return ParamLoadedValue(*Op, Expr);;
8272   }
8273   case X86::MOV8ri:
8274   case X86::MOV16ri:
8275     // TODO: Handle MOV8ri and MOV16ri.
8276     return None;
8277   case X86::MOV32ri:
8278   case X86::MOV64ri:
8279   case X86::MOV64ri32:
8280     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8281     // 64-bit parameters, so we need to consider super-registers.
8282     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8283       return None;
8284     return ParamLoadedValue(MI.getOperand(1), Expr);
8285   case X86::MOV8rr:
8286   case X86::MOV16rr:
8287   case X86::MOV32rr:
8288   case X86::MOV64rr:
8289     return describeMOVrrLoadedValue(MI, Reg, TRI);
8290   case X86::XOR32rr: {
8291     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8292     // super-registers.
8293     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8294       return None;
8295     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8296       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8297     return None;
8298   }
8299   case X86::MOVSX64rr32: {
8300     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8301     // cases like this:
8302     //
8303     //  $ebx = [...]
8304     //  $rdi = MOVSX64rr32 $ebx
8305     //  $esi = MOV32rr $edi
8306     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8307       return None;
8308 
8309     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8310 
8311     // If the described register is the destination register we need to
8312     // sign-extend the source register from 32 bits. The other case we handle
8313     // is when the described register is the 32-bit sub-register of the
8314     // destination register, in case we just need to return the source
8315     // register.
8316     if (Reg == MI.getOperand(0).getReg())
8317       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8318     else
8319       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8320              "Unhandled sub-register case for MOVSX64rr32");
8321 
8322     return ParamLoadedValue(MI.getOperand(1), Expr);
8323   }
8324   default:
8325     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8326     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8327   }
8328 }
8329 
8330 /// This is an architecture-specific helper function of reassociateOps.
8331 /// Set special operand attributes for new instructions after reassociation.
8332 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8333                                          MachineInstr &OldMI2,
8334                                          MachineInstr &NewMI1,
8335                                          MachineInstr &NewMI2) const {
8336   // Propagate FP flags from the original instructions.
8337   // But clear poison-generating flags because those may not be valid now.
8338   // TODO: There should be a helper function for copying only fast-math-flags.
8339   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8340   NewMI1.setFlags(IntersectedFlags);
8341   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8342   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8343   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8344 
8345   NewMI2.setFlags(IntersectedFlags);
8346   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8347   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8348   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8349 
8350   // Integer instructions may define an implicit EFLAGS dest register operand.
8351   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8352   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8353 
8354   assert(!OldFlagDef1 == !OldFlagDef2 &&
8355          "Unexpected instruction type for reassociation");
8356 
8357   if (!OldFlagDef1 || !OldFlagDef2)
8358     return;
8359 
8360   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8361          "Must have dead EFLAGS operand in reassociable instruction");
8362 
8363   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8364   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8365 
8366   assert(NewFlagDef1 && NewFlagDef2 &&
8367          "Unexpected operand in reassociable instruction");
8368 
8369   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8370   // of this pass or other passes. The EFLAGS operands must be dead in these new
8371   // instructions because the EFLAGS operands in the original instructions must
8372   // be dead in order for reassociation to occur.
8373   NewFlagDef1->setIsDead();
8374   NewFlagDef2->setIsDead();
8375 }
8376 
8377 std::pair<unsigned, unsigned>
8378 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8379   return std::make_pair(TF, 0u);
8380 }
8381 
8382 ArrayRef<std::pair<unsigned, const char *>>
8383 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8384   using namespace X86II;
8385   static const std::pair<unsigned, const char *> TargetFlags[] = {
8386       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8387       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8388       {MO_GOT, "x86-got"},
8389       {MO_GOTOFF, "x86-gotoff"},
8390       {MO_GOTPCREL, "x86-gotpcrel"},
8391       {MO_PLT, "x86-plt"},
8392       {MO_TLSGD, "x86-tlsgd"},
8393       {MO_TLSLD, "x86-tlsld"},
8394       {MO_TLSLDM, "x86-tlsldm"},
8395       {MO_GOTTPOFF, "x86-gottpoff"},
8396       {MO_INDNTPOFF, "x86-indntpoff"},
8397       {MO_TPOFF, "x86-tpoff"},
8398       {MO_DTPOFF, "x86-dtpoff"},
8399       {MO_NTPOFF, "x86-ntpoff"},
8400       {MO_GOTNTPOFF, "x86-gotntpoff"},
8401       {MO_DLLIMPORT, "x86-dllimport"},
8402       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8403       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8404       {MO_TLVP, "x86-tlvp"},
8405       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8406       {MO_SECREL, "x86-secrel"},
8407       {MO_COFFSTUB, "x86-coffstub"}};
8408   return makeArrayRef(TargetFlags);
8409 }
8410 
8411 namespace {
8412   /// Create Global Base Reg pass. This initializes the PIC
8413   /// global base register for x86-32.
8414   struct CGBR : public MachineFunctionPass {
8415     static char ID;
8416     CGBR() : MachineFunctionPass(ID) {}
8417 
8418     bool runOnMachineFunction(MachineFunction &MF) override {
8419       const X86TargetMachine *TM =
8420         static_cast<const X86TargetMachine *>(&MF.getTarget());
8421       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8422 
8423       // Don't do anything in the 64-bit small and kernel code models. They use
8424       // RIP-relative addressing for everything.
8425       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8426                             TM->getCodeModel() == CodeModel::Kernel))
8427         return false;
8428 
8429       // Only emit a global base reg in PIC mode.
8430       if (!TM->isPositionIndependent())
8431         return false;
8432 
8433       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8434       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8435 
8436       // If we didn't need a GlobalBaseReg, don't insert code.
8437       if (GlobalBaseReg == 0)
8438         return false;
8439 
8440       // Insert the set of GlobalBaseReg into the first MBB of the function
8441       MachineBasicBlock &FirstMBB = MF.front();
8442       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8443       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8444       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8445       const X86InstrInfo *TII = STI.getInstrInfo();
8446 
8447       unsigned PC;
8448       if (STI.isPICStyleGOT())
8449         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8450       else
8451         PC = GlobalBaseReg;
8452 
8453       if (STI.is64Bit()) {
8454         if (TM->getCodeModel() == CodeModel::Medium) {
8455           // In the medium code model, use a RIP-relative LEA to materialize the
8456           // GOT.
8457           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8458               .addReg(X86::RIP)
8459               .addImm(0)
8460               .addReg(0)
8461               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8462               .addReg(0);
8463         } else if (TM->getCodeModel() == CodeModel::Large) {
8464           // In the large code model, we are aiming for this code, though the
8465           // register allocation may vary:
8466           //   leaq .LN$pb(%rip), %rax
8467           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8468           //   addq %rcx, %rax
8469           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8470           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8471           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8472           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8473               .addReg(X86::RIP)
8474               .addImm(0)
8475               .addReg(0)
8476               .addSym(MF.getPICBaseSymbol())
8477               .addReg(0);
8478           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8479           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8480               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8481                                  X86II::MO_PIC_BASE_OFFSET);
8482           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8483               .addReg(PBReg, RegState::Kill)
8484               .addReg(GOTReg, RegState::Kill);
8485         } else {
8486           llvm_unreachable("unexpected code model");
8487         }
8488       } else {
8489         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8490         // only used in JIT code emission as displacement to pc.
8491         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8492 
8493         // If we're using vanilla 'GOT' PIC style, we should use relative
8494         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8495         if (STI.isPICStyleGOT()) {
8496           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8497           // %some_register
8498           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8499               .addReg(PC)
8500               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8501                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8502         }
8503       }
8504 
8505       return true;
8506     }
8507 
8508     StringRef getPassName() const override {
8509       return "X86 PIC Global Base Reg Initialization";
8510     }
8511 
8512     void getAnalysisUsage(AnalysisUsage &AU) const override {
8513       AU.setPreservesCFG();
8514       MachineFunctionPass::getAnalysisUsage(AU);
8515     }
8516   };
8517 }
8518 
8519 char CGBR::ID = 0;
8520 FunctionPass*
8521 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8522 
8523 namespace {
8524   struct LDTLSCleanup : public MachineFunctionPass {
8525     static char ID;
8526     LDTLSCleanup() : MachineFunctionPass(ID) {}
8527 
8528     bool runOnMachineFunction(MachineFunction &MF) override {
8529       if (skipFunction(MF.getFunction()))
8530         return false;
8531 
8532       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8533       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8534         // No point folding accesses if there isn't at least two.
8535         return false;
8536       }
8537 
8538       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8539       return VisitNode(DT->getRootNode(), 0);
8540     }
8541 
8542     // Visit the dominator subtree rooted at Node in pre-order.
8543     // If TLSBaseAddrReg is non-null, then use that to replace any
8544     // TLS_base_addr instructions. Otherwise, create the register
8545     // when the first such instruction is seen, and then use it
8546     // as we encounter more instructions.
8547     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8548       MachineBasicBlock *BB = Node->getBlock();
8549       bool Changed = false;
8550 
8551       // Traverse the current block.
8552       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8553            ++I) {
8554         switch (I->getOpcode()) {
8555           case X86::TLS_base_addr32:
8556           case X86::TLS_base_addr64:
8557             if (TLSBaseAddrReg)
8558               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8559             else
8560               I = SetRegister(*I, &TLSBaseAddrReg);
8561             Changed = true;
8562             break;
8563           default:
8564             break;
8565         }
8566       }
8567 
8568       // Visit the children of this block in the dominator tree.
8569       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8570            I != E; ++I) {
8571         Changed |= VisitNode(*I, TLSBaseAddrReg);
8572       }
8573 
8574       return Changed;
8575     }
8576 
8577     // Replace the TLS_base_addr instruction I with a copy from
8578     // TLSBaseAddrReg, returning the new instruction.
8579     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8580                                          unsigned TLSBaseAddrReg) {
8581       MachineFunction *MF = I.getParent()->getParent();
8582       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8583       const bool is64Bit = STI.is64Bit();
8584       const X86InstrInfo *TII = STI.getInstrInfo();
8585 
8586       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8587       MachineInstr *Copy =
8588           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8589                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8590               .addReg(TLSBaseAddrReg);
8591 
8592       // Erase the TLS_base_addr instruction.
8593       I.eraseFromParent();
8594 
8595       return Copy;
8596     }
8597 
8598     // Create a virtual register in *TLSBaseAddrReg, and populate it by
8599     // inserting a copy instruction after I. Returns the new instruction.
8600     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8601       MachineFunction *MF = I.getParent()->getParent();
8602       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8603       const bool is64Bit = STI.is64Bit();
8604       const X86InstrInfo *TII = STI.getInstrInfo();
8605 
8606       // Create a virtual register for the TLS base address.
8607       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8608       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8609                                                       ? &X86::GR64RegClass
8610                                                       : &X86::GR32RegClass);
8611 
8612       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8613       MachineInstr *Next = I.getNextNode();
8614       MachineInstr *Copy =
8615           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8616                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8617               .addReg(is64Bit ? X86::RAX : X86::EAX);
8618 
8619       return Copy;
8620     }
8621 
8622     StringRef getPassName() const override {
8623       return "Local Dynamic TLS Access Clean-up";
8624     }
8625 
8626     void getAnalysisUsage(AnalysisUsage &AU) const override {
8627       AU.setPreservesCFG();
8628       AU.addRequired<MachineDominatorTree>();
8629       MachineFunctionPass::getAnalysisUsage(AU);
8630     }
8631   };
8632 }
8633 
8634 char LDTLSCleanup::ID = 0;
8635 FunctionPass*
8636 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8637 
8638 /// Constants defining how certain sequences should be outlined.
8639 ///
8640 /// \p MachineOutlinerDefault implies that the function is called with a call
8641 /// instruction, and a return must be emitted for the outlined function frame.
8642 ///
8643 /// That is,
8644 ///
8645 /// I1                                 OUTLINED_FUNCTION:
8646 /// I2 --> call OUTLINED_FUNCTION       I1
8647 /// I3                                  I2
8648 ///                                     I3
8649 ///                                     ret
8650 ///
8651 /// * Call construction overhead: 1 (call instruction)
8652 /// * Frame construction overhead: 1 (return instruction)
8653 ///
8654 /// \p MachineOutlinerTailCall implies that the function is being tail called.
8655 /// A jump is emitted instead of a call, and the return is already present in
8656 /// the outlined sequence. That is,
8657 ///
8658 /// I1                                 OUTLINED_FUNCTION:
8659 /// I2 --> jmp OUTLINED_FUNCTION       I1
8660 /// ret                                I2
8661 ///                                    ret
8662 ///
8663 /// * Call construction overhead: 1 (jump instruction)
8664 /// * Frame construction overhead: 0 (don't need to return)
8665 ///
8666 enum MachineOutlinerClass {
8667   MachineOutlinerDefault,
8668   MachineOutlinerTailCall
8669 };
8670 
8671 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
8672     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
8673   unsigned SequenceSize =
8674       std::accumulate(RepeatedSequenceLocs[0].front(),
8675                       std::next(RepeatedSequenceLocs[0].back()), 0,
8676                       [](unsigned Sum, const MachineInstr &MI) {
8677                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
8678                         // we can't tell the cost.  Just assume each instruction
8679                         // is one byte.
8680                         if (MI.isDebugInstr() || MI.isKill())
8681                           return Sum;
8682                         return Sum + 1;
8683                       });
8684 
8685   // FIXME: Use real size in bytes for call and ret instructions.
8686   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
8687     for (outliner::Candidate &C : RepeatedSequenceLocs)
8688       C.setCallInfo(MachineOutlinerTailCall, 1);
8689 
8690     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
8691                                       0, // Number of bytes to emit frame.
8692                                       MachineOutlinerTailCall // Type of frame.
8693     );
8694   }
8695 
8696   for (outliner::Candidate &C : RepeatedSequenceLocs)
8697     C.setCallInfo(MachineOutlinerDefault, 1);
8698 
8699   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
8700                                     MachineOutlinerDefault);
8701 }
8702 
8703 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
8704                                            bool OutlineFromLinkOnceODRs) const {
8705   const Function &F = MF.getFunction();
8706 
8707   // Does the function use a red zone? If it does, then we can't risk messing
8708   // with the stack.
8709   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
8710     // It could have a red zone. If it does, then we don't want to touch it.
8711     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8712     if (!X86FI || X86FI->getUsesRedZone())
8713       return false;
8714   }
8715 
8716   // If we *don't* want to outline from things that could potentially be deduped
8717   // then return false.
8718   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
8719       return false;
8720 
8721   // This function is viable for outlining, so return true.
8722   return true;
8723 }
8724 
8725 outliner::InstrType
8726 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
8727   MachineInstr &MI = *MIT;
8728   // Don't allow debug values to impact outlining type.
8729   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
8730     return outliner::InstrType::Invisible;
8731 
8732   // At this point, KILL instructions don't really tell us much so we can go
8733   // ahead and skip over them.
8734   if (MI.isKill())
8735     return outliner::InstrType::Invisible;
8736 
8737   // Is this a tail call? If yes, we can outline as a tail call.
8738   if (isTailCall(MI))
8739     return outliner::InstrType::Legal;
8740 
8741   // Is this the terminator of a basic block?
8742   if (MI.isTerminator() || MI.isReturn()) {
8743 
8744     // Does its parent have any successors in its MachineFunction?
8745     if (MI.getParent()->succ_empty())
8746       return outliner::InstrType::Legal;
8747 
8748     // It does, so we can't tail call it.
8749     return outliner::InstrType::Illegal;
8750   }
8751 
8752   // Don't outline anything that modifies or reads from the stack pointer.
8753   //
8754   // FIXME: There are instructions which are being manually built without
8755   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
8756   // able to remove the extra checks once those are fixed up. For example,
8757   // sometimes we might get something like %rax = POP64r 1. This won't be
8758   // caught by modifiesRegister or readsRegister even though the instruction
8759   // really ought to be formed so that modifiesRegister/readsRegister would
8760   // catch it.
8761   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8762       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8763       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
8764     return outliner::InstrType::Illegal;
8765 
8766   // Outlined calls change the instruction pointer, so don't read from it.
8767   if (MI.readsRegister(X86::RIP, &RI) ||
8768       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8769       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
8770     return outliner::InstrType::Illegal;
8771 
8772   // Positions can't safely be outlined.
8773   if (MI.isPosition())
8774     return outliner::InstrType::Illegal;
8775 
8776   // Make sure none of the operands of this instruction do anything tricky.
8777   for (const MachineOperand &MOP : MI.operands())
8778     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
8779         MOP.isTargetIndex())
8780       return outliner::InstrType::Illegal;
8781 
8782   return outliner::InstrType::Legal;
8783 }
8784 
8785 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
8786                                           MachineFunction &MF,
8787                                           const outliner::OutlinedFunction &OF)
8788                                           const {
8789   // If we're a tail call, we already have a return, so don't do anything.
8790   if (OF.FrameConstructionID == MachineOutlinerTailCall)
8791     return;
8792 
8793   // We're a normal call, so our sequence doesn't have a return instruction.
8794   // Add it in.
8795   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
8796   MBB.insert(MBB.end(), retq);
8797 }
8798 
8799 MachineBasicBlock::iterator
8800 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
8801                                  MachineBasicBlock::iterator &It,
8802                                  MachineFunction &MF,
8803                                  const outliner::Candidate &C) const {
8804   // Is it a tail call?
8805   if (C.CallConstructionID == MachineOutlinerTailCall) {
8806     // Yes, just insert a JMP.
8807     It = MBB.insert(It,
8808                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
8809                       .addGlobalAddress(M.getNamedValue(MF.getName())));
8810   } else {
8811     // No, insert a call.
8812     It = MBB.insert(It,
8813                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
8814                       .addGlobalAddress(M.getNamedValue(MF.getName())));
8815   }
8816 
8817   return It;
8818 }
8819 
8820 #define GET_INSTRINFO_HELPERS
8821 #include "X86GenInstrInfo.inc"
8822