1// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*- 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly Instruction definitions. 11/// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// WebAssembly Instruction Predicate Definitions. 16//===----------------------------------------------------------------------===// 17 18def IsPIC : Predicate<"TM.isPositionIndependent()">; 19def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 20 21def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">; 22 23def HasAddr64 : Predicate<"Subtarget->hasAddr64()">; 24 25def HasSIMD128 : 26 Predicate<"Subtarget->hasSIMD128()">, 27 AssemblerPredicate<"FeatureSIMD128", "simd128">; 28 29def HasUnimplementedSIMD128 : 30 Predicate<"Subtarget->hasUnimplementedSIMD128()">, 31 AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">; 32 33def HasAtomics : 34 Predicate<"Subtarget->hasAtomics()">, 35 AssemblerPredicate<"FeatureAtomics", "atomics">; 36 37def HasMultivalue : 38 Predicate<"Subtarget->hasMultivalue()">, 39 AssemblerPredicate<"FeatureMultivalue", "multivalue">; 40 41def HasNontrappingFPToInt : 42 Predicate<"Subtarget->hasNontrappingFPToInt()">, 43 AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">; 44 45def NotHasNontrappingFPToInt : 46 Predicate<"!Subtarget->hasNontrappingFPToInt()">, 47 AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">; 48 49def HasSignExt : 50 Predicate<"Subtarget->hasSignExt()">, 51 AssemblerPredicate<"FeatureSignExt", "sign-ext">; 52 53def HasTailCall : 54 Predicate<"Subtarget->hasTailCall()">, 55 AssemblerPredicate<"FeatureTailCall", "tail-call">; 56 57def HasExceptionHandling : 58 Predicate<"Subtarget->hasExceptionHandling()">, 59 AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">; 60 61def HasBulkMemory : 62 Predicate<"Subtarget->hasBulkMemory()">, 63 AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">; 64 65def HasReferenceTypes : 66 Predicate<"Subtarget->hasReferenceTypes()">, 67 AssemblerPredicate<"FeatureReferenceTypes", "reference-types">; 68 69//===----------------------------------------------------------------------===// 70// WebAssembly-specific DAG Node Types. 71//===----------------------------------------------------------------------===// 72 73def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>, 74 SDTCisVT<1, iPTR>]>; 75def SDT_WebAssemblyCallSeqEnd : 76 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 77def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 78def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>; 79def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 80def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>; 81def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>; 82def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 83 SDTCisPtrTy<0>]>; 84def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 85 SDTCisPtrTy<0>]>; 86def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 87 88//===----------------------------------------------------------------------===// 89// WebAssembly-specific DAG Nodes. 90//===----------------------------------------------------------------------===// 91 92def WebAssemblycallseq_start : 93 SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart, 94 [SDNPHasChain, SDNPOutGlue]>; 95def WebAssemblycallseq_end : 96 SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd, 97 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 98def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0", 99 SDT_WebAssemblyCall0, 100 [SDNPHasChain, SDNPVariadic]>; 101def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1", 102 SDT_WebAssemblyCall1, 103 [SDNPHasChain, SDNPVariadic]>; 104def WebAssemblyretcall : SDNode<"WebAssemblyISD::RET_CALL", 105 SDT_WebAssemblyCall0, 106 [SDNPHasChain, SDNPVariadic]>; 107def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE", 108 SDT_WebAssemblyBrTable, 109 [SDNPHasChain, SDNPVariadic]>; 110def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT", 111 SDT_WebAssemblyArgument>; 112def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN", 113 SDT_WebAssemblyReturn, 114 [SDNPHasChain, SDNPVariadic]>; 115def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper", 116 SDT_WebAssemblyWrapper>; 117def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC", 118 SDT_WebAssemblyWrapperPIC>; 119def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow, 120 [SDNPHasChain, SDNPVariadic]>; 121 122//===----------------------------------------------------------------------===// 123// WebAssembly-specific Operands. 124//===----------------------------------------------------------------------===// 125 126// Default Operand has AsmOperandClass "Imm" which is for integers (and 127// symbols), so specialize one for floats: 128def FPImmAsmOperand : AsmOperandClass { 129 let Name = "FPImm"; 130 let PredicateMethod = "isFPImm"; 131} 132 133class FPOperand<ValueType ty> : Operand<ty> { 134 AsmOperandClass ParserMatchClass = FPImmAsmOperand; 135} 136 137let OperandNamespace = "WebAssembly" in { 138 139let OperandType = "OPERAND_BASIC_BLOCK" in 140def bb_op : Operand<OtherVT>; 141 142let OperandType = "OPERAND_LOCAL" in 143def local_op : Operand<i32>; 144 145let OperandType = "OPERAND_GLOBAL" in 146def global_op : Operand<i32>; 147 148let OperandType = "OPERAND_I32IMM" in 149def i32imm_op : Operand<i32>; 150 151let OperandType = "OPERAND_I64IMM" in 152def i64imm_op : Operand<i64>; 153 154let OperandType = "OPERAND_F32IMM" in 155def f32imm_op : FPOperand<f32>; 156 157let OperandType = "OPERAND_F64IMM" in 158def f64imm_op : FPOperand<f64>; 159 160let OperandType = "OPERAND_VEC_I8IMM" in 161def vec_i8imm_op : Operand<i32>; 162 163let OperandType = "OPERAND_VEC_I16IMM" in 164def vec_i16imm_op : Operand<i32>; 165 166let OperandType = "OPERAND_VEC_I32IMM" in 167def vec_i32imm_op : Operand<i32>; 168 169let OperandType = "OPERAND_VEC_I64IMM" in 170def vec_i64imm_op : Operand<i64>; 171 172let OperandType = "OPERAND_FUNCTION32" in 173def function32_op : Operand<i32>; 174 175let OperandType = "OPERAND_OFFSET32" in 176def offset32_op : Operand<i32>; 177 178let OperandType = "OPERAND_P2ALIGN" in { 179def P2Align : Operand<i32> { 180 let PrintMethod = "printWebAssemblyP2AlignOperand"; 181} 182 183let OperandType = "OPERAND_EVENT" in 184def event_op : Operand<i32>; 185 186} // OperandType = "OPERAND_P2ALIGN" 187 188let OperandType = "OPERAND_SIGNATURE" in 189def Signature : Operand<i32> { 190 let PrintMethod = "printWebAssemblySignatureOperand"; 191} 192 193let OperandType = "OPERAND_TYPEINDEX" in 194def TypeIndex : Operand<i32>; 195 196} // OperandNamespace = "WebAssembly" 197 198//===----------------------------------------------------------------------===// 199// WebAssembly Register to Stack instruction mapping 200//===----------------------------------------------------------------------===// 201 202class StackRel; 203def getStackOpcode : InstrMapping { 204 let FilterClass = "StackRel"; 205 let RowFields = ["BaseName"]; 206 let ColFields = ["StackBased"]; 207 let KeyCol = ["false"]; 208 let ValueCols = [["true"]]; 209} 210 211//===----------------------------------------------------------------------===// 212// WebAssembly Instruction Format Definitions. 213//===----------------------------------------------------------------------===// 214 215include "WebAssemblyInstrFormats.td" 216 217//===----------------------------------------------------------------------===// 218// Additional instructions. 219//===----------------------------------------------------------------------===// 220 221multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> { 222 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>, 223 Uses = [ARGUMENTS] in 224 defm ARGUMENT_#vt : 225 I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno), 226 [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>; 227} 228defm "": ARGUMENT<I32, i32>; 229defm "": ARGUMENT<I64, i64>; 230defm "": ARGUMENT<F32, f32>; 231defm "": ARGUMENT<F64, f64>; 232defm "": ARGUMENT<EXNREF, exnref>; 233 234// local.get and local.set are not generated by instruction selection; they 235// are implied by virtual register uses and defs. 236multiclass LOCAL<WebAssemblyRegClass vt> { 237 let hasSideEffects = 0 in { 238 // COPY is not an actual instruction in wasm, but since we allow local.get and 239 // local.set to be implicit during most of codegen, we can have a COPY which 240 // is actually a no-op because all the work is done in the implied local.get 241 // and local.set. COPYs are eliminated (and replaced with 242 // local.get/local.set) in the ExplicitLocals pass. 243 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in 244 defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [], 245 "local.copy\t$res, $src", "local.copy">; 246 247 // TEE is similar to COPY, but writes two copies of its result. Typically 248 // this would be used to stackify one result and write the other result to a 249 // local. 250 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in 251 defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [], 252 "local.tee\t$res, $also, $src", "local.tee">; 253 254 // This is the actual local.get instruction in wasm. These are made explicit 255 // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm 256 // local, which is a side effect not otherwise modeled in LLVM. 257 let mayLoad = 1, isAsCheapAsAMove = 1 in 258 defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local), 259 (outs), (ins local_op:$local), [], 260 "local.get\t$res, $local", "local.get\t$local", 0x20>; 261 262 // This is the actual local.set instruction in wasm. These are made explicit 263 // by the ExplicitLocals pass. It has mayStore because it writes to a wasm 264 // local, which is a side effect not otherwise modeled in LLVM. 265 let mayStore = 1, isAsCheapAsAMove = 1 in 266 defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src), 267 (outs), (ins local_op:$local), [], 268 "local.set\t$local, $src", "local.set\t$local", 0x21>; 269 270 // This is the actual local.tee instruction in wasm. TEEs are turned into 271 // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason 272 // as LOCAL_SET. 273 let mayStore = 1, isAsCheapAsAMove = 1 in 274 defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), 275 (outs), (ins local_op:$local), [], 276 "local.tee\t$res, $local, $src", "local.tee\t$local", 277 0x22>; 278 279 // Unused values must be dropped in some contexts. 280 defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [], 281 "drop\t$src", "drop", 0x1a>; 282 283 let mayLoad = 1 in 284 defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local), 285 (outs), (ins global_op:$local), [], 286 "global.get\t$res, $local", "global.get\t$local", 287 0x23>; 288 289 let mayStore = 1 in 290 defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src), 291 (outs), (ins global_op:$local), [], 292 "global.set\t$local, $src", "global.set\t$local", 293 0x24>; 294 295} // hasSideEffects = 0 296} 297defm "" : LOCAL<I32>; 298defm "" : LOCAL<I64>; 299defm "" : LOCAL<F32>; 300defm "" : LOCAL<F64>; 301defm "" : LOCAL<V128>, Requires<[HasSIMD128]>; 302defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>; 303 304let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { 305defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm), 306 (outs), (ins i32imm_op:$imm), 307 [(set I32:$res, imm:$imm)], 308 "i32.const\t$res, $imm", "i32.const\t$imm", 0x41>; 309defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm), 310 (outs), (ins i64imm_op:$imm), 311 [(set I64:$res, imm:$imm)], 312 "i64.const\t$res, $imm", "i64.const\t$imm", 0x42>; 313defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm), 314 (outs), (ins f32imm_op:$imm), 315 [(set F32:$res, fpimm:$imm)], 316 "f32.const\t$res, $imm", "f32.const\t$imm", 0x43>; 317defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm), 318 (outs), (ins f64imm_op:$imm), 319 [(set F64:$res, fpimm:$imm)], 320 "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>; 321} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 322 323def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), 324 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>; 325 326def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), 327 (GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; 328 329def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)), 330 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; 331 332def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), 333 (GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>; 334 335def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), 336 (CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>; 337 338def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>; 339def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>; 340 341//===----------------------------------------------------------------------===// 342// Additional sets of instructions. 343//===----------------------------------------------------------------------===// 344 345include "WebAssemblyInstrMemory.td" 346include "WebAssemblyInstrCall.td" 347include "WebAssemblyInstrControl.td" 348include "WebAssemblyInstrInteger.td" 349include "WebAssemblyInstrConv.td" 350include "WebAssemblyInstrFloat.td" 351include "WebAssemblyInstrAtomics.td" 352include "WebAssemblyInstrSIMD.td" 353include "WebAssemblyInstrRef.td" 354include "WebAssemblyInstrBulkMemory.td" 355