1// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// WebAssembly Instruction definitions.
12///
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// WebAssembly Instruction Predicate Definitions.
17//===----------------------------------------------------------------------===//
18
19def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
20def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
21def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
22                           AssemblerPredicate<"FeatureSIMD128", "simd128">;
23def HasUnimplementedSIMD : Predicate<"EnableUnimplementedWasmSIMDInstrs">;
24def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
25                           AssemblerPredicate<"FeatureAtomics", "atomics">;
26def HasNontrappingFPToInt :
27    Predicate<"Subtarget->hasNontrappingFPToInt()">,
28              AssemblerPredicate<"FeatureNontrappingFPToInt",
29                                 "nontrapping-fptoint">;
30def NotHasNontrappingFPToInt :
31    Predicate<"!Subtarget->hasNontrappingFPToInt()">,
32              AssemblerPredicate<"!FeatureNontrappingFPToInt",
33                                 "nontrapping-fptoint">;
34def HasSignExt :
35    Predicate<"Subtarget->hasSignExt()">,
36              AssemblerPredicate<"FeatureSignExt",
37                                 "sign-ext">;
38def NotHasSignExt :
39    Predicate<"!Subtarget->hasSignExt()">,
40              AssemblerPredicate<"!FeatureSignExt",
41                                 "sign-ext">;
42
43def HasExceptionHandling :
44    Predicate<"Subtarget->hasExceptionHandling()">,
45              AssemblerPredicate<"FeatureExceptionHandling",
46                                 "exception-handling">;
47
48def NotHasExceptionHandling :
49    Predicate<"!Subtarget->hasExceptionHandling()">,
50              AssemblerPredicate<"!FeatureExceptionHandling",
51                                 "exception-handling">;
52
53//===----------------------------------------------------------------------===//
54// WebAssembly-specific DAG Node Types.
55//===----------------------------------------------------------------------===//
56
57def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
58                                                  SDTCisVT<1, iPTR>]>;
59def SDT_WebAssemblyCallSeqEnd :
60    SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
61def SDT_WebAssemblyCall0    : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
62def SDT_WebAssemblyCall1    : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
63def SDT_WebAssemblyBrTable  : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
64def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
65def SDT_WebAssemblyReturn   : SDTypeProfile<0, -1, []>;
66def SDT_WebAssemblyWrapper  : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
67                                                   SDTCisPtrTy<0>]>;
68def SDT_WebAssemblyThrow    : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
69
70//===----------------------------------------------------------------------===//
71// WebAssembly-specific DAG Nodes.
72//===----------------------------------------------------------------------===//
73
74def WebAssemblycallseq_start :
75    SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
76           [SDNPHasChain, SDNPOutGlue]>;
77def WebAssemblycallseq_end :
78    SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
79           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
80def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
81                              SDT_WebAssemblyCall0,
82                              [SDNPHasChain, SDNPVariadic]>;
83def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
84                              SDT_WebAssemblyCall1,
85                              [SDNPHasChain, SDNPVariadic]>;
86def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE",
87                                 SDT_WebAssemblyBrTable,
88                                 [SDNPHasChain, SDNPVariadic]>;
89def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
90                                 SDT_WebAssemblyArgument>;
91def WebAssemblyreturn   : SDNode<"WebAssemblyISD::RETURN",
92                                 SDT_WebAssemblyReturn, [SDNPHasChain]>;
93def WebAssemblywrapper  : SDNode<"WebAssemblyISD::Wrapper",
94                                 SDT_WebAssemblyWrapper>;
95def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow,
96                              [SDNPHasChain]>;
97
98//===----------------------------------------------------------------------===//
99// WebAssembly-specific Operands.
100//===----------------------------------------------------------------------===//
101
102let OperandNamespace = "WebAssembly" in {
103
104let OperandType = "OPERAND_BASIC_BLOCK" in
105def bb_op : Operand<OtherVT>;
106
107let OperandType = "OPERAND_LOCAL" in
108def local_op : Operand<i32>;
109
110let OperandType = "OPERAND_GLOBAL" in
111def global_op : Operand<i32>;
112
113let OperandType = "OPERAND_I32IMM" in
114def i32imm_op : Operand<i32>;
115
116let OperandType = "OPERAND_I64IMM" in
117def i64imm_op : Operand<i64>;
118
119let OperandType = "OPERAND_F32IMM" in
120def f32imm_op : Operand<f32>;
121
122let OperandType = "OPERAND_F64IMM" in
123def f64imm_op : Operand<f64>;
124
125let OperandType = "OPERAND_VEC_I8IMM" in
126def vec_i8imm_op : Operand<i32>;
127
128let OperandType = "OPERAND_VEC_I16IMM" in
129def vec_i16imm_op : Operand<i32>;
130
131let OperandType = "OPERAND_VEC_I32IMM" in
132def vec_i32imm_op : Operand<i32>;
133
134let OperandType = "OPERAND_VEC_I64IMM" in
135def vec_i64imm_op : Operand<i64>;
136
137let OperandType = "OPERAND_FUNCTION32" in
138def function32_op : Operand<i32>;
139
140let OperandType = "OPERAND_OFFSET32" in
141def offset32_op : Operand<i32>;
142
143let OperandType = "OPERAND_P2ALIGN" in {
144def P2Align : Operand<i32> {
145  let PrintMethod = "printWebAssemblyP2AlignOperand";
146}
147
148let OperandType = "OPERAND_EVENT" in
149def event_op : Operand<i32>;
150
151} // OperandType = "OPERAND_P2ALIGN"
152
153let OperandType = "OPERAND_SIGNATURE" in {
154def Signature : Operand<i32> {
155  let PrintMethod = "printWebAssemblySignatureOperand";
156}
157} // OperandType = "OPERAND_SIGNATURE"
158
159let OperandType = "OPERAND_TYPEINDEX" in
160def TypeIndex : Operand<i32>;
161
162} // OperandNamespace = "WebAssembly"
163
164//===----------------------------------------------------------------------===//
165// WebAssembly Register to Stack instruction mapping
166//===----------------------------------------------------------------------===//
167
168class StackRel;
169def getStackOpcode : InstrMapping {
170  let FilterClass = "StackRel";
171  let RowFields = ["BaseName"];
172  let ColFields = ["StackBased"];
173  let KeyCol = ["false"];
174  let ValueCols = [["true"]];
175}
176
177//===----------------------------------------------------------------------===//
178// WebAssembly Instruction Format Definitions.
179//===----------------------------------------------------------------------===//
180
181include "WebAssemblyInstrFormats.td"
182
183//===----------------------------------------------------------------------===//
184// Additional instructions.
185//===----------------------------------------------------------------------===//
186
187multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> {
188  let hasSideEffects = 1, isCodeGenOnly = 1,
189      Defs = []<Register>, Uses = [ARGUMENTS] in
190  defm ARGUMENT_#vt :
191    I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno),
192      [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>;
193}
194defm "": ARGUMENT<I32, i32>;
195defm "": ARGUMENT<I64, i64>;
196defm "": ARGUMENT<F32, f32>;
197defm "": ARGUMENT<F64, f64>;
198defm "": ARGUMENT<EXCEPT_REF, ExceptRef>;
199
200// local.get and local.set are not generated by instruction selection; they
201// are implied by virtual register uses and defs.
202multiclass LOCAL<WebAssemblyRegClass vt> {
203let hasSideEffects = 0 in {
204  // COPY is not an actual instruction in wasm, but since we allow local.get and
205  // local.set to be implicit during most of codegen, we can have a COPY which
206  // is actually a no-op because all the work is done in the implied local.get
207  // and local.set. COPYs are eliminated (and replaced with
208  // local.get/local.set) in the ExplicitLocals pass.
209  let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
210  defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [],
211                    "local.copy\t$res, $src", "local.copy">;
212
213  // TEE is similar to COPY, but writes two copies of its result. Typically
214  // this would be used to stackify one result and write the other result to a
215  // local.
216  let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
217  defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [],
218                   "local.tee\t$res, $also, $src", "local.tee">;
219
220  // This is the actual local.get instruction in wasm. These are made explicit
221  // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm
222  // local, which is a side effect not otherwise modeled in LLVM.
223  let mayLoad = 1, isAsCheapAsAMove = 1 in
224  defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local),
225                         (outs), (ins local_op:$local), [],
226                         "local.get\t$res, $local", "local.get\t$local", 0x20>;
227
228  // This is the actual local.set instruction in wasm. These are made explicit
229  // by the ExplicitLocals pass. It has mayStore because it writes to a wasm
230  // local, which is a side effect not otherwise modeled in LLVM.
231  let mayStore = 1, isAsCheapAsAMove = 1 in
232  defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src),
233                         (outs), (ins local_op:$local), [],
234                         "local.set\t$local, $src", "local.set\t$local", 0x21>;
235
236  // This is the actual local.tee instruction in wasm. TEEs are turned into
237  // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason
238  // as LOCAL_SET.
239  let mayStore = 1, isAsCheapAsAMove = 1 in
240  defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src),
241                         (outs), (ins local_op:$local), [],
242                         "local.tee\t$res, $local, $src", "local.tee\t$local",
243                         0x22>;
244
245  // Unused values must be dropped in some contexts.
246  defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [],
247                    "drop\t$src", "drop", 0x1a>;
248
249  let mayLoad = 1 in
250  defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local),
251                          (outs), (ins global_op:$local), [],
252                          "global.get\t$res, $local", "global.get\t$local",
253                          0x23>;
254
255  let mayStore = 1 in
256  defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src),
257                          (outs), (ins global_op:$local), [],
258                          "global.set\t$local, $src", "global.set\t$local",
259                          0x24>;
260
261} // hasSideEffects = 0
262}
263defm "" : LOCAL<I32>;
264defm "" : LOCAL<I64>;
265defm "" : LOCAL<F32>;
266defm "" : LOCAL<F64>;
267defm "" : LOCAL<V128>, Requires<[HasSIMD128]>;
268defm "" : LOCAL<EXCEPT_REF>, Requires<[HasExceptionHandling]>;
269
270let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
271defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
272                   (outs), (ins i32imm_op:$imm),
273                   [(set I32:$res, imm:$imm)],
274                   "i32.const\t$res, $imm", "i32.const\t$imm", 0x41>;
275defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
276                   (outs), (ins i64imm_op:$imm),
277                   [(set I64:$res, imm:$imm)],
278                   "i64.const\t$res, $imm", "i64.const\t$imm", 0x42>;
279defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
280                   (outs), (ins f32imm_op:$imm),
281                   [(set F32:$res, fpimm:$imm)],
282                   "f32.const\t$res, $imm", "f32.const\t$imm", 0x43>;
283defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
284                   (outs), (ins f64imm_op:$imm),
285                   [(set F64:$res, fpimm:$imm)],
286                   "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>;
287} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
288
289def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
290          (CONST_I32 tglobaladdr:$addr)>;
291def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
292          (CONST_I32 texternalsym:$addr)>;
293def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>;
294def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>;
295
296//===----------------------------------------------------------------------===//
297// Additional sets of instructions.
298//===----------------------------------------------------------------------===//
299
300include "WebAssemblyInstrMemory.td"
301include "WebAssemblyInstrCall.td"
302include "WebAssemblyInstrControl.td"
303include "WebAssemblyInstrInteger.td"
304include "WebAssemblyInstrConv.td"
305include "WebAssemblyInstrFloat.td"
306include "WebAssemblyInstrAtomics.td"
307include "WebAssemblyInstrSIMD.td"
308include "WebAssemblyInstrExceptRef.td"
309