1//=- WebAssemblyInstrFormats.td - WebAssembly Instr. Formats -*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// WebAssembly instruction format definitions.
12///
13//===----------------------------------------------------------------------===//
14
15// WebAssembly Instruction Format.
16// We instantiate 2 of these for every actual instruction (register based
17// and stack based), see below.
18class WebAssemblyInst<bits<32> inst, string asmstr, bit stack> : Instruction {
19  field bits<32> Inst = inst; // Instruction encoding.
20  field bit StackBased = stack;
21  let Namespace   = "WebAssembly";
22  let Pattern     = [];
23  let AsmString   = asmstr;
24}
25
26// Normal instructions. Default instantiation of a WebAssemblyInst.
27class NI<dag oops, dag iops, list<dag> pattern, bit stack, string asmstr = "",
28         bits<32> inst = -1>
29    : WebAssemblyInst<inst, asmstr, stack> {
30  dag OutOperandList = oops;
31  dag InOperandList  = iops;
32  let Pattern        = pattern;
33}
34
35// Generates both register and stack based versions of one actual instruction.
36// We have 2 sets of operands (oops & iops) for the register and stack
37// based version of this instruction, as well as the corresponding asmstr.
38// The register versions have virtual-register operands which correspond to wasm
39// locals or stack locations. Each use and def of the register corresponds to an
40// implicit get_local / set_local or access of stack operands in wasm. These
41// instructions are used for ISel and all MI passes. The stack versions of the
42// instructions do not have register operands (they implicitly operate on the
43// stack), and get_locals and set_locals are explicit. The register instructions
44// are converted to their corresponding stack instructions before lowering to
45// MC.
46// Every instruction should want to be based on this multi-class to guarantee
47// there is always an equivalent pair of instructions.
48multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
49             list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "",
50             bits<32> inst = -1> {
51  def "" : NI<oops_r, iops_r, pattern_r, 0, asmstr_r, inst>;
52  def _S : NI<oops_s, iops_s, [], 1, asmstr_s, inst>;
53}
54
55// For instructions that have no register ops, so both sets are the same.
56multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
57               bits<32> inst = -1> {
58  defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
59}
60
61// Instructions requiring HasSIMD128 and the simd128 prefix byte
62multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
63                  list<dag> pattern_r, string asmstr_r = "",
64                  string asmstr_s = "", bits<32> simdop = -1> {
65  defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
66              !or(0xfd00, !and(0xff, simdop))>,
67            Requires<[HasSIMD128]>;
68}
69