1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16 17 #include "SystemZ.h" 18 #include "SystemZInstrInfo.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38 // (The call target is implicitly __tls_get_offset.) 39 TLS_GDCALL, 40 TLS_LDCALL, 41 42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43 // accesses (LARL). Operand 0 is the address. 44 PCREL_WRAPPER, 45 46 // Used in cases where an offset is applied to a TargetGlobalAddress. 47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48 // PCREL_WRAPPER for an anchor point. This is used so that we can 49 // cheaply refer to either the full address or the anchor point 50 // as a register base. 51 PCREL_OFFSET, 52 53 // Integer comparisons. There are three operands: the two values 54 // to compare, and an integer of type SystemZICMP. 55 ICMP, 56 57 // Floating-point comparisons. The two operands are the values to compare. 58 FCMP, 59 60 // Test under mask. The first operand is ANDed with the second operand 61 // and the condition codes are set on the result. The third operand is 62 // a boolean that is true if the condition codes need to distinguish 63 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 64 // register forms do but the memory forms don't). 65 TM, 66 67 // Branches if a condition is true. Operand 0 is the chain operand; 68 // operand 1 is the 4-bit condition-code mask, with bit N in 69 // big-endian order meaning "branch if CC=N"; operand 2 is the 70 // target block and operand 3 is the flag operand. 71 BR_CCMASK, 72 73 // Selects between operand 0 and operand 1. Operand 2 is the 74 // mask of condition-code values for which operand 0 should be 75 // chosen over operand 1; it has the same form as BR_CCMASK. 76 // Operand 3 is the flag operand. 77 SELECT_CCMASK, 78 79 // Evaluates to the gap between the stack pointer and the 80 // base of the dynamically-allocatable area. 81 ADJDYNALLOC, 82 83 // For allocating stack space when using stack clash protector. 84 // Allocation is performed by block, and each block is probed. 85 PROBED_ALLOCA, 86 87 // Count number of bits set in operand 0 per byte. 88 POPCNT, 89 90 // Wrappers around the ISD opcodes of the same name. The output is GR128. 91 // Input operands may be GR64 or GR32, depending on the instruction. 92 SMUL_LOHI, 93 UMUL_LOHI, 94 SDIVREM, 95 UDIVREM, 96 97 // Add/subtract with overflow/carry. These have the same operands as 98 // the corresponding standard operations, except with the carry flag 99 // replaced by a condition code value. 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, 101 102 // Set the condition code from a boolean value in operand 0. 103 // Operand 1 is a mask of all condition-code values that may result of this 104 // operation, operand 2 is a mask of condition-code values that may result 105 // if the boolean is true. 106 // Note that this operation is always optimized away, we will never 107 // generate any code for it. 108 GET_CCMASK, 109 110 // Use a series of MVCs to copy bytes from one memory location to another. 111 // The operands are: 112 // - the target address 113 // - the source address 114 // - the constant length 115 // 116 // This isn't a memory opcode because we'd need to attach two 117 // MachineMemOperands rather than one. 118 MVC, 119 120 // Similar to MVC, but for logic operations (AND, OR, XOR). 121 NC, 122 OC, 123 XC, 124 125 // Use CLC to compare two blocks of memory, with the same comments 126 // as for MVC. 127 CLC, 128 129 // Use MVC to set a block of memory after storing the first byte. 130 MEMSET_MVC, 131 132 // Use an MVST-based sequence to implement stpcpy(). 133 STPCPY, 134 135 // Use a CLST-based sequence to implement strcmp(). The two input operands 136 // are the addresses of the strings to compare. 137 STRCMP, 138 139 // Use an SRST-based sequence to search a block of memory. The first 140 // operand is the end address, the second is the start, and the third 141 // is the character to search for. CC is set to 1 on success and 2 142 // on failure. 143 SEARCH_STRING, 144 145 // Store the CC value in bits 29 and 28 of an integer. 146 IPM, 147 148 // Compiler barrier only; generate a no-op. 149 MEMBARRIER, 150 151 // Transaction begin. The first operand is the chain, the second 152 // the TDB pointer, and the third the immediate control field. 153 // Returns CC value and chain. 154 TBEGIN, 155 TBEGIN_NOFLOAT, 156 157 // Transaction end. Just the chain operand. Returns CC value and chain. 158 TEND, 159 160 // Create a vector constant by filling byte N of the result with bit 161 // 15-N of the single operand. 162 BYTE_MASK, 163 164 // Create a vector constant by replicating an element-sized RISBG-style mask. 165 // The first operand specifies the starting set bit and the second operand 166 // specifies the ending set bit. Both operands count from the MSB of the 167 // element. 168 ROTATE_MASK, 169 170 // Replicate a GPR scalar value into all elements of a vector. 171 REPLICATE, 172 173 // Create a vector from two i64 GPRs. 174 JOIN_DWORDS, 175 176 // Replicate one element of a vector into all elements. The first operand 177 // is the vector and the second is the index of the element to replicate. 178 SPLAT, 179 180 // Interleave elements from the high half of operand 0 and the high half 181 // of operand 1. 182 MERGE_HIGH, 183 184 // Likewise for the low halves. 185 MERGE_LOW, 186 187 // Concatenate the vectors in the first two operands, shift them left 188 // by the third operand, and take the first half of the result. 189 SHL_DOUBLE, 190 191 // Take one element of the first v2i64 operand and the one element of 192 // the second v2i64 operand and concatenate them to form a v2i64 result. 193 // The third operand is a 4-bit value of the form 0A0B, where A and B 194 // are the element selectors for the first operand and second operands 195 // respectively. 196 PERMUTE_DWORDS, 197 198 // Perform a general vector permute on vector operands 0 and 1. 199 // Each byte of operand 2 controls the corresponding byte of the result, 200 // in the same way as a byte-level VECTOR_SHUFFLE mask. 201 PERMUTE, 202 203 // Pack vector operands 0 and 1 into a single vector with half-sized elements. 204 PACK, 205 206 // Likewise, but saturate the result and set CC. PACKS_CC does signed 207 // saturation and PACKLS_CC does unsigned saturation. 208 PACKS_CC, 209 PACKLS_CC, 210 211 // Unpack the first half of vector operand 0 into double-sized elements. 212 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 213 UNPACK_HIGH, 214 UNPACKL_HIGH, 215 216 // Likewise for the second half. 217 UNPACK_LOW, 218 UNPACKL_LOW, 219 220 // Shift each element of vector operand 0 by the number of bits specified 221 // by scalar operand 1. 222 VSHL_BY_SCALAR, 223 VSRL_BY_SCALAR, 224 VSRA_BY_SCALAR, 225 226 // For each element of the output type, sum across all sub-elements of 227 // operand 0 belonging to the corresponding element, and add in the 228 // rightmost sub-element of the corresponding element of operand 1. 229 VSUM, 230 231 // Compare integer vector operands 0 and 1 to produce the usual 0/-1 232 // vector result. VICMPE is for equality, VICMPH for "signed greater than" 233 // and VICMPHL for "unsigned greater than". 234 VICMPE, 235 VICMPH, 236 VICMPHL, 237 238 // Likewise, but also set the condition codes on the result. 239 VICMPES, 240 VICMPHS, 241 VICMPHLS, 242 243 // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1 244 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 245 // greater than" and VFCMPHE for "ordered and greater than or equal to". 246 VFCMPE, 247 VFCMPH, 248 VFCMPHE, 249 250 // Likewise, but also set the condition codes on the result. 251 VFCMPES, 252 VFCMPHS, 253 VFCMPHES, 254 255 // Test floating-point data class for vectors. 256 VFTCI, 257 258 // Extend the even f32 elements of vector operand 0 to produce a vector 259 // of f64 elements. 260 VEXTEND, 261 262 // Round the f64 elements of vector operand 0 to f32s and store them in the 263 // even elements of the result. 264 VROUND, 265 266 // AND the two vector operands together and set CC based on the result. 267 VTM, 268 269 // String operations that set CC as a side-effect. 270 VFAE_CC, 271 VFAEZ_CC, 272 VFEE_CC, 273 VFEEZ_CC, 274 VFENE_CC, 275 VFENEZ_CC, 276 VISTR_CC, 277 VSTRC_CC, 278 VSTRCZ_CC, 279 VSTRS_CC, 280 VSTRSZ_CC, 281 282 // Test Data Class. 283 // 284 // Operand 0: the value to test 285 // Operand 1: the bit mask 286 TDC, 287 288 // Strict variants of scalar floating-point comparisons. 289 // Quiet and signaling versions. 290 STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 291 STRICT_FCMPS, 292 293 // Strict variants of vector floating-point comparisons. 294 // Quiet and signaling versions. 295 STRICT_VFCMPE, 296 STRICT_VFCMPH, 297 STRICT_VFCMPHE, 298 STRICT_VFCMPES, 299 STRICT_VFCMPHS, 300 STRICT_VFCMPHES, 301 302 // Strict variants of VEXTEND and VROUND. 303 STRICT_VEXTEND, 304 STRICT_VROUND, 305 306 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 307 // ATOMIC_LOAD_<op>. 308 // 309 // Operand 0: the address of the containing 32-bit-aligned field 310 // Operand 1: the second operand of <op>, in the high bits of an i32 311 // for everything except ATOMIC_SWAPW 312 // Operand 2: how many bits to rotate the i32 left to bring the first 313 // operand into the high bits 314 // Operand 3: the negative of operand 2, for rotating the other way 315 // Operand 4: the width of the field in bits (8 or 16) 316 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 317 ATOMIC_LOADW_ADD, 318 ATOMIC_LOADW_SUB, 319 ATOMIC_LOADW_AND, 320 ATOMIC_LOADW_OR, 321 ATOMIC_LOADW_XOR, 322 ATOMIC_LOADW_NAND, 323 ATOMIC_LOADW_MIN, 324 ATOMIC_LOADW_MAX, 325 ATOMIC_LOADW_UMIN, 326 ATOMIC_LOADW_UMAX, 327 328 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 329 // 330 // Operand 0: the address of the containing 32-bit-aligned field 331 // Operand 1: the compare value, in the low bits of an i32 332 // Operand 2: the swap value, in the low bits of an i32 333 // Operand 3: how many bits to rotate the i32 left to bring the first 334 // operand into the high bits 335 // Operand 4: the negative of operand 2, for rotating the other way 336 // Operand 5: the width of the field in bits (8 or 16) 337 ATOMIC_CMP_SWAPW, 338 339 // Atomic compare-and-swap returning CC value. 340 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 341 ATOMIC_CMP_SWAP, 342 343 // 128-bit atomic load. 344 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr) 345 ATOMIC_LOAD_128, 346 347 // 128-bit atomic store. 348 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr) 349 ATOMIC_STORE_128, 350 351 // 128-bit atomic compare-and-swap. 352 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 353 ATOMIC_CMP_SWAP_128, 354 355 // Byte swapping load/store. Same operands as regular load/store. 356 LRV, STRV, 357 358 // Element swapping load/store. Same operands as regular load/store. 359 VLER, VSTER, 360 361 // Prefetch from the second operand using the 4-bit control code in 362 // the first operand. The code is 1 for a load prefetch and 2 for 363 // a store prefetch. 364 PREFETCH 365 }; 366 367 // Return true if OPCODE is some kind of PC-relative address. 368 inline bool isPCREL(unsigned Opcode) { 369 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 370 } 371 } // end namespace SystemZISD 372 373 namespace SystemZICMP { 374 // Describes whether an integer comparison needs to be signed or unsigned, 375 // or whether either type is OK. 376 enum { 377 Any, 378 UnsignedOnly, 379 SignedOnly 380 }; 381 } // end namespace SystemZICMP 382 383 class SystemZSubtarget; 384 385 class SystemZTargetLowering : public TargetLowering { 386 public: 387 explicit SystemZTargetLowering(const TargetMachine &TM, 388 const SystemZSubtarget &STI); 389 390 bool useSoftFloat() const override; 391 392 // Override TargetLowering. 393 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 394 return MVT::i32; 395 } 396 MVT getVectorIdxTy(const DataLayout &DL) const override { 397 // Only the lower 12 bits of an element index are used, so we don't 398 // want to clobber the upper 32 bits of a GPR unnecessarily. 399 return MVT::i32; 400 } 401 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 402 const override { 403 // Widen subvectors to the full width rather than promoting integer 404 // elements. This is better because: 405 // 406 // (a) it means that we can handle the ABI for passing and returning 407 // sub-128 vectors without having to handle them as legal types. 408 // 409 // (b) we don't have instructions to extend on load and truncate on store, 410 // so promoting the integers is less efficient. 411 // 412 // (c) there are no multiplication instructions for the widest integer 413 // type (v2i64). 414 if (VT.getScalarSizeInBits() % 8 == 0) 415 return TypeWidenVector; 416 return TargetLoweringBase::getPreferredVectorAction(VT); 417 } 418 unsigned 419 getNumRegisters(LLVMContext &Context, EVT VT, 420 Optional<MVT> RegisterVT) const override { 421 // i128 inline assembly operand. 422 if (VT == MVT::i128 && 423 RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped) 424 return 1; 425 return TargetLowering::getNumRegisters(Context, VT); 426 } 427 bool isCheapToSpeculateCtlz() const override { return true; } 428 bool preferZeroCompareBranch() const override { return true; } 429 bool hasBitPreservingFPLogic(EVT VT) const override { 430 EVT ScVT = VT.getScalarType(); 431 return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128; 432 } 433 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override { 434 ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1)); 435 return Mask && Mask->getValue().isIntN(16); 436 } 437 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 438 return VT.isScalarInteger(); 439 } 440 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 441 EVT) const override; 442 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 443 EVT VT) const override; 444 bool isFPImmLegal(const APFloat &Imm, EVT VT, 445 bool ForCodeSize) const override; 446 bool ShouldShrinkFPConstant(EVT VT) const override { 447 // Do not shrink 64-bit FP constpool entries since LDEB is slower than 448 // LD, and having the full constant in memory enables reg/mem opcodes. 449 return VT != MVT::f64; 450 } 451 bool hasInlineStackProbe(MachineFunction &MF) const override; 452 bool isLegalICmpImmediate(int64_t Imm) const override; 453 bool isLegalAddImmediate(int64_t Imm) const override; 454 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 455 unsigned AS, 456 Instruction *I = nullptr) const override; 457 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, 458 MachineMemOperand::Flags Flags, 459 bool *Fast) const override; 460 bool isTruncateFree(Type *, Type *) const override; 461 bool isTruncateFree(EVT, EVT) const override; 462 463 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 464 bool MathUsed) const override { 465 // Form add and sub with overflow intrinsics regardless of any extra 466 // users of the math result. 467 return VT == MVT::i32 || VT == MVT::i64; 468 } 469 470 const char *getTargetNodeName(unsigned Opcode) const override; 471 std::pair<unsigned, const TargetRegisterClass *> 472 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 473 StringRef Constraint, MVT VT) const override; 474 TargetLowering::ConstraintType 475 getConstraintType(StringRef Constraint) const override; 476 TargetLowering::ConstraintWeight 477 getSingleConstraintMatchWeight(AsmOperandInfo &info, 478 const char *constraint) const override; 479 void LowerAsmOperandForConstraint(SDValue Op, 480 std::string &Constraint, 481 std::vector<SDValue> &Ops, 482 SelectionDAG &DAG) const override; 483 484 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 485 if (ConstraintCode.size() == 1) { 486 switch(ConstraintCode[0]) { 487 default: 488 break; 489 case 'o': 490 return InlineAsm::Constraint_o; 491 case 'Q': 492 return InlineAsm::Constraint_Q; 493 case 'R': 494 return InlineAsm::Constraint_R; 495 case 'S': 496 return InlineAsm::Constraint_S; 497 case 'T': 498 return InlineAsm::Constraint_T; 499 } 500 } else if (ConstraintCode.size() == 2 && ConstraintCode[0] == 'Z') { 501 switch (ConstraintCode[1]) { 502 default: 503 break; 504 case 'Q': 505 return InlineAsm::Constraint_ZQ; 506 case 'R': 507 return InlineAsm::Constraint_ZR; 508 case 'S': 509 return InlineAsm::Constraint_ZS; 510 case 'T': 511 return InlineAsm::Constraint_ZT; 512 } 513 } 514 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 515 } 516 517 Register getRegisterByName(const char *RegName, LLT VT, 518 const MachineFunction &MF) const override; 519 520 /// If a physical register, this returns the register that receives the 521 /// exception address on entry to an EH pad. 522 Register 523 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 524 return SystemZ::R6D; 525 } 526 527 /// If a physical register, this returns the register that receives the 528 /// exception typeid on entry to a landing pad. 529 Register 530 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 531 return SystemZ::R7D; 532 } 533 534 /// Override to support customized stack guard loading. 535 bool useLoadStackGuardNode() const override { 536 return true; 537 } 538 void insertSSPDeclarations(Module &M) const override { 539 } 540 541 MachineBasicBlock * 542 EmitInstrWithCustomInserter(MachineInstr &MI, 543 MachineBasicBlock *BB) const override; 544 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 545 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, 546 SelectionDAG &DAG) const override; 547 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 548 SelectionDAG &DAG) const override; 549 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 550 bool allowTruncateForTailCall(Type *, Type *) const override; 551 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 552 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 553 SDValue Val, SDValue *Parts, 554 unsigned NumParts, MVT PartVT, 555 Optional<CallingConv::ID> CC) const override; 556 SDValue 557 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 558 const SDValue *Parts, unsigned NumParts, 559 MVT PartVT, EVT ValueVT, 560 Optional<CallingConv::ID> CC) const override; 561 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 562 bool isVarArg, 563 const SmallVectorImpl<ISD::InputArg> &Ins, 564 const SDLoc &DL, SelectionDAG &DAG, 565 SmallVectorImpl<SDValue> &InVals) const override; 566 SDValue LowerCall(CallLoweringInfo &CLI, 567 SmallVectorImpl<SDValue> &InVals) const override; 568 569 std::pair<SDValue, SDValue> 570 makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, 571 EVT RetVT, ArrayRef<SDValue> Ops, CallingConv::ID CallConv, 572 bool IsSigned, SDLoc DL, bool DoesNotReturn, 573 bool IsReturnValueUsed) const; 574 575 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 576 bool isVarArg, 577 const SmallVectorImpl<ISD::OutputArg> &Outs, 578 LLVMContext &Context) const override; 579 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 580 const SmallVectorImpl<ISD::OutputArg> &Outs, 581 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 582 SelectionDAG &DAG) const override; 583 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 584 585 /// Determine which of the bits specified in Mask are known to be either 586 /// zero or one and return them in the KnownZero/KnownOne bitsets. 587 void computeKnownBitsForTargetNode(const SDValue Op, 588 KnownBits &Known, 589 const APInt &DemandedElts, 590 const SelectionDAG &DAG, 591 unsigned Depth = 0) const override; 592 593 /// Determine the number of bits in the operation that are sign bits. 594 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 595 const APInt &DemandedElts, 596 const SelectionDAG &DAG, 597 unsigned Depth) const override; 598 599 ISD::NodeType getExtendForAtomicOps() const override { 600 return ISD::ANY_EXTEND; 601 } 602 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 603 return ISD::ZERO_EXTEND; 604 } 605 606 bool supportSwiftError() const override { 607 return true; 608 } 609 610 unsigned getStackProbeSize(MachineFunction &MF) const; 611 612 private: 613 const SystemZSubtarget &Subtarget; 614 615 // Implement LowerOperation for individual opcodes. 616 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, 617 const SDLoc &DL, EVT VT, 618 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const; 619 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, 620 EVT VT, ISD::CondCode CC, 621 SDValue CmpOp0, SDValue CmpOp1, 622 SDValue Chain = SDValue(), 623 bool IsSignaling = false) const; 624 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 625 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG, 626 bool IsSignaling) const; 627 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 628 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 629 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 630 SelectionDAG &DAG) const; 631 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 632 SelectionDAG &DAG, unsigned Opcode, 633 SDValue GOTOffset) const; 634 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; 635 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 636 SelectionDAG &DAG) const; 637 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 638 SelectionDAG &DAG) const; 639 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 640 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 641 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 642 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 643 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 644 SDValue lowerVASTART_ELF(SDValue Op, SelectionDAG &DAG) const; 645 SDValue lowerVASTART_XPLINK(SDValue Op, SelectionDAG &DAG) const; 646 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 647 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 648 SDValue lowerDYNAMIC_STACKALLOC_ELF(SDValue Op, SelectionDAG &DAG) const; 649 SDValue lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op, SelectionDAG &DAG) const; 650 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 651 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 652 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 653 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 654 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 655 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const; 656 SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const; 657 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 658 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 659 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 660 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 661 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 662 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 663 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 664 unsigned Opcode) const; 665 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 666 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 667 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 668 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 669 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 670 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 671 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 672 bool isVectorElementLoad(SDValue Op) const; 673 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, 674 SmallVectorImpl<SDValue> &Elems) const; 675 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 676 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 677 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 678 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 679 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 680 SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 681 SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 682 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 683 SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const; 684 685 bool canTreatAsByteVector(EVT VT) const; 686 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 687 unsigned Index, DAGCombinerInfo &DCI, 688 bool Force) const; 689 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op, 690 DAGCombinerInfo &DCI) const; 691 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 692 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 693 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const; 694 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const; 695 bool canLoadStoreByteSwapped(EVT VT) const; 696 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const; 697 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const; 698 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const; 699 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const; 700 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const; 701 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const; 702 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 703 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const; 704 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const; 705 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 706 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 707 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 708 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const; 709 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const; 710 711 SDValue unwrapAddress(SDValue N) const override; 712 713 // If the last instruction before MBBI in MBB was some form of COMPARE, 714 // try to replace it with a COMPARE AND BRANCH just before MBBI. 715 // CCMask and Target are the BRC-like operands for the branch. 716 // Return true if the change was made. 717 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 718 MachineBasicBlock::iterator MBBI, 719 unsigned CCMask, 720 MachineBasicBlock *Target) const; 721 722 // Implement EmitInstrWithCustomInserter for individual operation types. 723 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const; 724 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, 725 unsigned StoreOpcode, unsigned STOCOpcode, 726 bool Invert) const; 727 MachineBasicBlock *emitPair128(MachineInstr &MI, 728 MachineBasicBlock *MBB) const; 729 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, 730 bool ClearEven) const; 731 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, 732 MachineBasicBlock *BB, 733 unsigned BinOpcode, unsigned BitSize, 734 bool Invert = false) const; 735 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, 736 MachineBasicBlock *MBB, 737 unsigned CompareOpcode, 738 unsigned KeepOldMask, 739 unsigned BitSize) const; 740 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, 741 MachineBasicBlock *BB) const; 742 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, 743 unsigned Opcode, 744 bool IsMemset = false) const; 745 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, 746 unsigned Opcode) const; 747 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, 748 MachineBasicBlock *MBB, 749 unsigned Opcode, bool NoFloat) const; 750 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, 751 MachineBasicBlock *MBB, 752 unsigned Opcode) const; 753 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 754 MachineBasicBlock *MBB) const; 755 756 SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const; 757 758 MachineMemOperand::Flags 759 getTargetMMOFlags(const Instruction &I) const override; 760 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 761 }; 762 763 struct SystemZVectorConstantInfo { 764 private: 765 APInt IntBits; // The 128 bits as an integer. 766 APInt SplatBits; // Smallest splat value. 767 APInt SplatUndef; // Bits correspoding to undef operands of the BVN. 768 unsigned SplatBitSize = 0; 769 bool isFP128 = false; 770 771 public: 772 unsigned Opcode = 0; 773 SmallVector<unsigned, 2> OpVals; 774 MVT VecVT; 775 SystemZVectorConstantInfo(APFloat FPImm); 776 SystemZVectorConstantInfo(BuildVectorSDNode *BVN); 777 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget); 778 }; 779 780 } // end namespace llvm 781 782 #endif 783