1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 17 18 #include "SystemZ.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38 // (The call target is implicitly __tls_get_offset.) 39 TLS_GDCALL, 40 TLS_LDCALL, 41 42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43 // accesses (LARL). Operand 0 is the address. 44 PCREL_WRAPPER, 45 46 // Used in cases where an offset is applied to a TargetGlobalAddress. 47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48 // PCREL_WRAPPER for an anchor point. This is used so that we can 49 // cheaply refer to either the full address or the anchor point 50 // as a register base. 51 PCREL_OFFSET, 52 53 // Integer absolute. 54 IABS, 55 56 // Integer comparisons. There are three operands: the two values 57 // to compare, and an integer of type SystemZICMP. 58 ICMP, 59 60 // Floating-point comparisons. The two operands are the values to compare. 61 FCMP, 62 63 // Test under mask. The first operand is ANDed with the second operand 64 // and the condition codes are set on the result. The third operand is 65 // a boolean that is true if the condition codes need to distinguish 66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 67 // register forms do but the memory forms don't). 68 TM, 69 70 // Branches if a condition is true. Operand 0 is the chain operand; 71 // operand 1 is the 4-bit condition-code mask, with bit N in 72 // big-endian order meaning "branch if CC=N"; operand 2 is the 73 // target block and operand 3 is the flag operand. 74 BR_CCMASK, 75 76 // Selects between operand 0 and operand 1. Operand 2 is the 77 // mask of condition-code values for which operand 0 should be 78 // chosen over operand 1; it has the same form as BR_CCMASK. 79 // Operand 3 is the flag operand. 80 SELECT_CCMASK, 81 82 // Evaluates to the gap between the stack pointer and the 83 // base of the dynamically-allocatable area. 84 ADJDYNALLOC, 85 86 // Extracts the value of a 32-bit access register. Operand 0 is 87 // the number of the register. 88 EXTRACT_ACCESS, 89 90 // Count number of bits set in operand 0 per byte. 91 POPCNT, 92 93 // Wrappers around the ISD opcodes of the same name. The output and 94 // first input operands are GR128s. The trailing numbers are the 95 // widths of the second operand in bits. 96 UMUL_LOHI64, 97 SDIVREM32, 98 SDIVREM64, 99 UDIVREM32, 100 UDIVREM64, 101 102 // Use a series of MVCs to copy bytes from one memory location to another. 103 // The operands are: 104 // - the target address 105 // - the source address 106 // - the constant length 107 // 108 // This isn't a memory opcode because we'd need to attach two 109 // MachineMemOperands rather than one. 110 MVC, 111 112 // Like MVC, but implemented as a loop that handles X*256 bytes 113 // followed by straight-line code to handle the rest (if any). 114 // The value of X is passed as an additional operand. 115 MVC_LOOP, 116 117 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). 118 NC, 119 NC_LOOP, 120 OC, 121 OC_LOOP, 122 XC, 123 XC_LOOP, 124 125 // Use CLC to compare two blocks of memory, with the same comments 126 // as for MVC and MVC_LOOP. 127 CLC, 128 CLC_LOOP, 129 130 // Use an MVST-based sequence to implement stpcpy(). 131 STPCPY, 132 133 // Use a CLST-based sequence to implement strcmp(). The two input operands 134 // are the addresses of the strings to compare. 135 STRCMP, 136 137 // Use an SRST-based sequence to search a block of memory. The first 138 // operand is the end address, the second is the start, and the third 139 // is the character to search for. CC is set to 1 on success and 2 140 // on failure. 141 SEARCH_STRING, 142 143 // Store the CC value in bits 29 and 28 of an integer. 144 IPM, 145 146 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.) 147 SERIALIZE, 148 149 // Compiler barrier only; generate a no-op. 150 MEMBARRIER, 151 152 // Transaction begin. The first operand is the chain, the second 153 // the TDB pointer, and the third the immediate control field. 154 // Returns chain and glue. 155 TBEGIN, 156 TBEGIN_NOFLOAT, 157 158 // Transaction end. Just the chain operand. Returns chain and glue. 159 TEND, 160 161 // Create a vector constant by filling byte N of the result with bit 162 // 15-N of the single operand. 163 BYTE_MASK, 164 165 // Create a vector constant by replicating an element-sized RISBG-style mask. 166 // The first operand specifies the starting set bit and the second operand 167 // specifies the ending set bit. Both operands count from the MSB of the 168 // element. 169 ROTATE_MASK, 170 171 // Replicate a GPR scalar value into all elements of a vector. 172 REPLICATE, 173 174 // Create a vector from two i64 GPRs. 175 JOIN_DWORDS, 176 177 // Replicate one element of a vector into all elements. The first operand 178 // is the vector and the second is the index of the element to replicate. 179 SPLAT, 180 181 // Interleave elements from the high half of operand 0 and the high half 182 // of operand 1. 183 MERGE_HIGH, 184 185 // Likewise for the low halves. 186 MERGE_LOW, 187 188 // Concatenate the vectors in the first two operands, shift them left 189 // by the third operand, and take the first half of the result. 190 SHL_DOUBLE, 191 192 // Take one element of the first v2i64 operand and the one element of 193 // the second v2i64 operand and concatenate them to form a v2i64 result. 194 // The third operand is a 4-bit value of the form 0A0B, where A and B 195 // are the element selectors for the first operand and second operands 196 // respectively. 197 PERMUTE_DWORDS, 198 199 // Perform a general vector permute on vector operands 0 and 1. 200 // Each byte of operand 2 controls the corresponding byte of the result, 201 // in the same way as a byte-level VECTOR_SHUFFLE mask. 202 PERMUTE, 203 204 // Pack vector operands 0 and 1 into a single vector with half-sized elements. 205 PACK, 206 207 // Likewise, but saturate the result and set CC. PACKS_CC does signed 208 // saturation and PACKLS_CC does unsigned saturation. 209 PACKS_CC, 210 PACKLS_CC, 211 212 // Unpack the first half of vector operand 0 into double-sized elements. 213 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 214 UNPACK_HIGH, 215 UNPACKL_HIGH, 216 217 // Likewise for the second half. 218 UNPACK_LOW, 219 UNPACKL_LOW, 220 221 // Shift each element of vector operand 0 by the number of bits specified 222 // by scalar operand 1. 223 VSHL_BY_SCALAR, 224 VSRL_BY_SCALAR, 225 VSRA_BY_SCALAR, 226 227 // For each element of the output type, sum across all sub-elements of 228 // operand 0 belonging to the corresponding element, and add in the 229 // rightmost sub-element of the corresponding element of operand 1. 230 VSUM, 231 232 // Compare integer vector operands 0 and 1 to produce the usual 0/-1 233 // vector result. VICMPE is for equality, VICMPH for "signed greater than" 234 // and VICMPHL for "unsigned greater than". 235 VICMPE, 236 VICMPH, 237 VICMPHL, 238 239 // Likewise, but also set the condition codes on the result. 240 VICMPES, 241 VICMPHS, 242 VICMPHLS, 243 244 // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1 245 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 246 // greater than" and VFCMPHE for "ordered and greater than or equal to". 247 VFCMPE, 248 VFCMPH, 249 VFCMPHE, 250 251 // Likewise, but also set the condition codes on the result. 252 VFCMPES, 253 VFCMPHS, 254 VFCMPHES, 255 256 // Test floating-point data class for vectors. 257 VFTCI, 258 259 // Extend the even f32 elements of vector operand 0 to produce a vector 260 // of f64 elements. 261 VEXTEND, 262 263 // Round the f64 elements of vector operand 0 to f32s and store them in the 264 // even elements of the result. 265 VROUND, 266 267 // AND the two vector operands together and set CC based on the result. 268 VTM, 269 270 // String operations that set CC as a side-effect. 271 VFAE_CC, 272 VFAEZ_CC, 273 VFEE_CC, 274 VFEEZ_CC, 275 VFENE_CC, 276 VFENEZ_CC, 277 VISTR_CC, 278 VSTRC_CC, 279 VSTRCZ_CC, 280 281 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 282 // ATOMIC_LOAD_<op>. 283 // 284 // Operand 0: the address of the containing 32-bit-aligned field 285 // Operand 1: the second operand of <op>, in the high bits of an i32 286 // for everything except ATOMIC_SWAPW 287 // Operand 2: how many bits to rotate the i32 left to bring the first 288 // operand into the high bits 289 // Operand 3: the negative of operand 2, for rotating the other way 290 // Operand 4: the width of the field in bits (8 or 16) 291 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 292 ATOMIC_LOADW_ADD, 293 ATOMIC_LOADW_SUB, 294 ATOMIC_LOADW_AND, 295 ATOMIC_LOADW_OR, 296 ATOMIC_LOADW_XOR, 297 ATOMIC_LOADW_NAND, 298 ATOMIC_LOADW_MIN, 299 ATOMIC_LOADW_MAX, 300 ATOMIC_LOADW_UMIN, 301 ATOMIC_LOADW_UMAX, 302 303 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 304 // 305 // Operand 0: the address of the containing 32-bit-aligned field 306 // Operand 1: the compare value, in the low bits of an i32 307 // Operand 2: the swap value, in the low bits of an i32 308 // Operand 3: how many bits to rotate the i32 left to bring the first 309 // operand into the high bits 310 // Operand 4: the negative of operand 2, for rotating the other way 311 // Operand 5: the width of the field in bits (8 or 16) 312 ATOMIC_CMP_SWAPW, 313 314 // Prefetch from the second operand using the 4-bit control code in 315 // the first operand. The code is 1 for a load prefetch and 2 for 316 // a store prefetch. 317 PREFETCH 318 }; 319 320 // Return true if OPCODE is some kind of PC-relative address. 321 inline bool isPCREL(unsigned Opcode) { 322 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 323 } 324 } // end namespace SystemZISD 325 326 namespace SystemZICMP { 327 // Describes whether an integer comparison needs to be signed or unsigned, 328 // or whether either type is OK. 329 enum { 330 Any, 331 UnsignedOnly, 332 SignedOnly 333 }; 334 } // end namespace SystemZICMP 335 336 class SystemZSubtarget; 337 class SystemZTargetMachine; 338 339 class SystemZTargetLowering : public TargetLowering { 340 public: 341 explicit SystemZTargetLowering(const TargetMachine &TM, 342 const SystemZSubtarget &STI); 343 344 // Override TargetLowering. 345 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 346 return MVT::i32; 347 } 348 MVT getVectorIdxTy(const DataLayout &DL) const override { 349 // Only the lower 12 bits of an element index are used, so we don't 350 // want to clobber the upper 32 bits of a GPR unnecessarily. 351 return MVT::i32; 352 } 353 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) 354 const override { 355 // Widen subvectors to the full width rather than promoting integer 356 // elements. This is better because: 357 // 358 // (a) it means that we can handle the ABI for passing and returning 359 // sub-128 vectors without having to handle them as legal types. 360 // 361 // (b) we don't have instructions to extend on load and truncate on store, 362 // so promoting the integers is less efficient. 363 // 364 // (c) there are no multiplication instructions for the widest integer 365 // type (v2i64). 366 if (VT.getVectorElementType().getSizeInBits() % 8 == 0) 367 return TypeWidenVector; 368 return TargetLoweringBase::getPreferredVectorAction(VT); 369 } 370 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 371 EVT) const override; 372 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 373 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 374 bool isLegalICmpImmediate(int64_t Imm) const override; 375 bool isLegalAddImmediate(int64_t Imm) const override; 376 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 377 unsigned AS) const override; 378 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 379 unsigned Align, 380 bool *Fast) const override; 381 bool isTruncateFree(Type *, Type *) const override; 382 bool isTruncateFree(EVT, EVT) const override; 383 const char *getTargetNodeName(unsigned Opcode) const override; 384 std::pair<unsigned, const TargetRegisterClass *> 385 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 386 StringRef Constraint, MVT VT) const override; 387 TargetLowering::ConstraintType 388 getConstraintType(StringRef Constraint) const override; 389 TargetLowering::ConstraintWeight 390 getSingleConstraintMatchWeight(AsmOperandInfo &info, 391 const char *constraint) const override; 392 void LowerAsmOperandForConstraint(SDValue Op, 393 std::string &Constraint, 394 std::vector<SDValue> &Ops, 395 SelectionDAG &DAG) const override; 396 397 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 398 if (ConstraintCode.size() == 1) { 399 switch(ConstraintCode[0]) { 400 default: 401 break; 402 case 'Q': 403 return InlineAsm::Constraint_Q; 404 case 'R': 405 return InlineAsm::Constraint_R; 406 case 'S': 407 return InlineAsm::Constraint_S; 408 case 'T': 409 return InlineAsm::Constraint_T; 410 } 411 } 412 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 413 } 414 415 /// If a physical register, this returns the register that receives the 416 /// exception address on entry to an EH pad. 417 unsigned 418 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 419 return SystemZ::R6D; 420 } 421 422 /// If a physical register, this returns the register that receives the 423 /// exception typeid on entry to a landing pad. 424 unsigned 425 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 426 return SystemZ::R7D; 427 } 428 429 /// Override to support customized stack guard loading. 430 bool useLoadStackGuardNode() const override { 431 return true; 432 } 433 void insertSSPDeclarations(Module &M) const override { 434 } 435 436 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 437 MachineBasicBlock *BB) const 438 override; 439 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 440 bool allowTruncateForTailCall(Type *, Type *) const override; 441 bool mayBeEmittedAsTailCall(CallInst *CI) const override; 442 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 443 bool isVarArg, 444 const SmallVectorImpl<ISD::InputArg> &Ins, 445 SDLoc DL, SelectionDAG &DAG, 446 SmallVectorImpl<SDValue> &InVals) const override; 447 SDValue LowerCall(CallLoweringInfo &CLI, 448 SmallVectorImpl<SDValue> &InVals) const override; 449 450 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 451 bool isVarArg, 452 const SmallVectorImpl<ISD::OutputArg> &Outs, 453 LLVMContext &Context) const override; 454 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 455 const SmallVectorImpl<ISD::OutputArg> &Outs, 456 const SmallVectorImpl<SDValue> &OutVals, 457 SDLoc DL, SelectionDAG &DAG) const override; 458 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, 459 SelectionDAG &DAG) const override; 460 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 461 462 bool supportSwiftError() const override { 463 return true; 464 } 465 466 private: 467 const SystemZSubtarget &Subtarget; 468 469 // Implement LowerOperation for individual opcodes. 470 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 471 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 472 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 473 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 474 SelectionDAG &DAG) const; 475 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 476 SelectionDAG &DAG, unsigned Opcode, 477 SDValue GOTOffset) const; 478 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; 479 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 480 SelectionDAG &DAG) const; 481 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 482 SelectionDAG &DAG) const; 483 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 484 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 485 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 486 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 487 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 488 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 489 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 490 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 491 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 492 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 493 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 494 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 495 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 496 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 497 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 498 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 499 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 500 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 501 unsigned Opcode) const; 502 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 503 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 504 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const; 505 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 506 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 507 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 508 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 509 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 510 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 511 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 512 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 513 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 514 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 515 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG, 516 unsigned UnpackHigh) const; 517 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 518 519 SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 520 unsigned Index, DAGCombinerInfo &DCI, 521 bool Force) const; 522 SDValue combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op, 523 DAGCombinerInfo &DCI) const; 524 525 // If the last instruction before MBBI in MBB was some form of COMPARE, 526 // try to replace it with a COMPARE AND BRANCH just before MBBI. 527 // CCMask and Target are the BRC-like operands for the branch. 528 // Return true if the change was made. 529 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 530 MachineBasicBlock::iterator MBBI, 531 unsigned CCMask, 532 MachineBasicBlock *Target) const; 533 534 // Implement EmitInstrWithCustomInserter for individual operation types. 535 MachineBasicBlock *emitSelect(MachineInstr *MI, 536 MachineBasicBlock *BB) const; 537 MachineBasicBlock *emitCondStore(MachineInstr *MI, 538 MachineBasicBlock *BB, 539 unsigned StoreOpcode, unsigned STOCOpcode, 540 bool Invert) const; 541 MachineBasicBlock *emitExt128(MachineInstr *MI, 542 MachineBasicBlock *MBB, 543 bool ClearEven, unsigned SubReg) const; 544 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, 545 MachineBasicBlock *BB, 546 unsigned BinOpcode, unsigned BitSize, 547 bool Invert = false) const; 548 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, 549 MachineBasicBlock *MBB, 550 unsigned CompareOpcode, 551 unsigned KeepOldMask, 552 unsigned BitSize) const; 553 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, 554 MachineBasicBlock *BB) const; 555 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI, 556 MachineBasicBlock *BB, 557 unsigned Opcode) const; 558 MachineBasicBlock *emitStringWrapper(MachineInstr *MI, 559 MachineBasicBlock *BB, 560 unsigned Opcode) const; 561 MachineBasicBlock *emitTransactionBegin(MachineInstr *MI, 562 MachineBasicBlock *MBB, 563 unsigned Opcode, 564 bool NoFloat) const; 565 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr *MI, 566 MachineBasicBlock *MBB, 567 unsigned Opcode) const; 568 569 }; 570 } // end namespace llvm 571 572 #endif 573