1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16 17 #include "SystemZ.h" 18 #include "SystemZInstrInfo.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38 // (The call target is implicitly __tls_get_offset.) 39 TLS_GDCALL, 40 TLS_LDCALL, 41 42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43 // accesses (LARL). Operand 0 is the address. 44 PCREL_WRAPPER, 45 46 // Used in cases where an offset is applied to a TargetGlobalAddress. 47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48 // PCREL_WRAPPER for an anchor point. This is used so that we can 49 // cheaply refer to either the full address or the anchor point 50 // as a register base. 51 PCREL_OFFSET, 52 53 // Integer comparisons. There are three operands: the two values 54 // to compare, and an integer of type SystemZICMP. 55 ICMP, 56 57 // Floating-point comparisons. The two operands are the values to compare. 58 FCMP, 59 60 // Test under mask. The first operand is ANDed with the second operand 61 // and the condition codes are set on the result. The third operand is 62 // a boolean that is true if the condition codes need to distinguish 63 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 64 // register forms do but the memory forms don't). 65 TM, 66 67 // Branches if a condition is true. Operand 0 is the chain operand; 68 // operand 1 is the 4-bit condition-code mask, with bit N in 69 // big-endian order meaning "branch if CC=N"; operand 2 is the 70 // target block and operand 3 is the flag operand. 71 BR_CCMASK, 72 73 // Selects between operand 0 and operand 1. Operand 2 is the 74 // mask of condition-code values for which operand 0 should be 75 // chosen over operand 1; it has the same form as BR_CCMASK. 76 // Operand 3 is the flag operand. 77 SELECT_CCMASK, 78 79 // Evaluates to the gap between the stack pointer and the 80 // base of the dynamically-allocatable area. 81 ADJDYNALLOC, 82 83 // For allocating stack space when using stack clash protector. 84 // Allocation is performed by block, and each block is probed. 85 PROBED_ALLOCA, 86 87 // Count number of bits set in operand 0 per byte. 88 POPCNT, 89 90 // Wrappers around the ISD opcodes of the same name. The output is GR128. 91 // Input operands may be GR64 or GR32, depending on the instruction. 92 SMUL_LOHI, 93 UMUL_LOHI, 94 SDIVREM, 95 UDIVREM, 96 97 // Add/subtract with overflow/carry. These have the same operands as 98 // the corresponding standard operations, except with the carry flag 99 // replaced by a condition code value. 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, 101 102 // Set the condition code from a boolean value in operand 0. 103 // Operand 1 is a mask of all condition-code values that may result of this 104 // operation, operand 2 is a mask of condition-code values that may result 105 // if the boolean is true. 106 // Note that this operation is always optimized away, we will never 107 // generate any code for it. 108 GET_CCMASK, 109 110 // Use a series of MVCs to copy bytes from one memory location to another. 111 // The operands are: 112 // - the target address 113 // - the source address 114 // - the constant length 115 // 116 // This isn't a memory opcode because we'd need to attach two 117 // MachineMemOperands rather than one. 118 MVC, 119 120 // Similar to MVC, but for logic operations (AND, OR, XOR). 121 NC, 122 OC, 123 XC, 124 125 // Use CLC to compare two blocks of memory, with the same comments 126 // as for MVC. 127 CLC, 128 129 // Use an MVST-based sequence to implement stpcpy(). 130 STPCPY, 131 132 // Use a CLST-based sequence to implement strcmp(). The two input operands 133 // are the addresses of the strings to compare. 134 STRCMP, 135 136 // Use an SRST-based sequence to search a block of memory. The first 137 // operand is the end address, the second is the start, and the third 138 // is the character to search for. CC is set to 1 on success and 2 139 // on failure. 140 SEARCH_STRING, 141 142 // Store the CC value in bits 29 and 28 of an integer. 143 IPM, 144 145 // Compiler barrier only; generate a no-op. 146 MEMBARRIER, 147 148 // Transaction begin. The first operand is the chain, the second 149 // the TDB pointer, and the third the immediate control field. 150 // Returns CC value and chain. 151 TBEGIN, 152 TBEGIN_NOFLOAT, 153 154 // Transaction end. Just the chain operand. Returns CC value and chain. 155 TEND, 156 157 // Create a vector constant by filling byte N of the result with bit 158 // 15-N of the single operand. 159 BYTE_MASK, 160 161 // Create a vector constant by replicating an element-sized RISBG-style mask. 162 // The first operand specifies the starting set bit and the second operand 163 // specifies the ending set bit. Both operands count from the MSB of the 164 // element. 165 ROTATE_MASK, 166 167 // Replicate a GPR scalar value into all elements of a vector. 168 REPLICATE, 169 170 // Create a vector from two i64 GPRs. 171 JOIN_DWORDS, 172 173 // Replicate one element of a vector into all elements. The first operand 174 // is the vector and the second is the index of the element to replicate. 175 SPLAT, 176 177 // Interleave elements from the high half of operand 0 and the high half 178 // of operand 1. 179 MERGE_HIGH, 180 181 // Likewise for the low halves. 182 MERGE_LOW, 183 184 // Concatenate the vectors in the first two operands, shift them left 185 // by the third operand, and take the first half of the result. 186 SHL_DOUBLE, 187 188 // Take one element of the first v2i64 operand and the one element of 189 // the second v2i64 operand and concatenate them to form a v2i64 result. 190 // The third operand is a 4-bit value of the form 0A0B, where A and B 191 // are the element selectors for the first operand and second operands 192 // respectively. 193 PERMUTE_DWORDS, 194 195 // Perform a general vector permute on vector operands 0 and 1. 196 // Each byte of operand 2 controls the corresponding byte of the result, 197 // in the same way as a byte-level VECTOR_SHUFFLE mask. 198 PERMUTE, 199 200 // Pack vector operands 0 and 1 into a single vector with half-sized elements. 201 PACK, 202 203 // Likewise, but saturate the result and set CC. PACKS_CC does signed 204 // saturation and PACKLS_CC does unsigned saturation. 205 PACKS_CC, 206 PACKLS_CC, 207 208 // Unpack the first half of vector operand 0 into double-sized elements. 209 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 210 UNPACK_HIGH, 211 UNPACKL_HIGH, 212 213 // Likewise for the second half. 214 UNPACK_LOW, 215 UNPACKL_LOW, 216 217 // Shift each element of vector operand 0 by the number of bits specified 218 // by scalar operand 1. 219 VSHL_BY_SCALAR, 220 VSRL_BY_SCALAR, 221 VSRA_BY_SCALAR, 222 223 // For each element of the output type, sum across all sub-elements of 224 // operand 0 belonging to the corresponding element, and add in the 225 // rightmost sub-element of the corresponding element of operand 1. 226 VSUM, 227 228 // Compare integer vector operands 0 and 1 to produce the usual 0/-1 229 // vector result. VICMPE is for equality, VICMPH for "signed greater than" 230 // and VICMPHL for "unsigned greater than". 231 VICMPE, 232 VICMPH, 233 VICMPHL, 234 235 // Likewise, but also set the condition codes on the result. 236 VICMPES, 237 VICMPHS, 238 VICMPHLS, 239 240 // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1 241 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 242 // greater than" and VFCMPHE for "ordered and greater than or equal to". 243 VFCMPE, 244 VFCMPH, 245 VFCMPHE, 246 247 // Likewise, but also set the condition codes on the result. 248 VFCMPES, 249 VFCMPHS, 250 VFCMPHES, 251 252 // Test floating-point data class for vectors. 253 VFTCI, 254 255 // Extend the even f32 elements of vector operand 0 to produce a vector 256 // of f64 elements. 257 VEXTEND, 258 259 // Round the f64 elements of vector operand 0 to f32s and store them in the 260 // even elements of the result. 261 VROUND, 262 263 // AND the two vector operands together and set CC based on the result. 264 VTM, 265 266 // String operations that set CC as a side-effect. 267 VFAE_CC, 268 VFAEZ_CC, 269 VFEE_CC, 270 VFEEZ_CC, 271 VFENE_CC, 272 VFENEZ_CC, 273 VISTR_CC, 274 VSTRC_CC, 275 VSTRCZ_CC, 276 VSTRS_CC, 277 VSTRSZ_CC, 278 279 // Test Data Class. 280 // 281 // Operand 0: the value to test 282 // Operand 1: the bit mask 283 TDC, 284 285 // Strict variants of scalar floating-point comparisons. 286 // Quiet and signaling versions. 287 STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 288 STRICT_FCMPS, 289 290 // Strict variants of vector floating-point comparisons. 291 // Quiet and signaling versions. 292 STRICT_VFCMPE, 293 STRICT_VFCMPH, 294 STRICT_VFCMPHE, 295 STRICT_VFCMPES, 296 STRICT_VFCMPHS, 297 STRICT_VFCMPHES, 298 299 // Strict variants of VEXTEND and VROUND. 300 STRICT_VEXTEND, 301 STRICT_VROUND, 302 303 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 304 // ATOMIC_LOAD_<op>. 305 // 306 // Operand 0: the address of the containing 32-bit-aligned field 307 // Operand 1: the second operand of <op>, in the high bits of an i32 308 // for everything except ATOMIC_SWAPW 309 // Operand 2: how many bits to rotate the i32 left to bring the first 310 // operand into the high bits 311 // Operand 3: the negative of operand 2, for rotating the other way 312 // Operand 4: the width of the field in bits (8 or 16) 313 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 314 ATOMIC_LOADW_ADD, 315 ATOMIC_LOADW_SUB, 316 ATOMIC_LOADW_AND, 317 ATOMIC_LOADW_OR, 318 ATOMIC_LOADW_XOR, 319 ATOMIC_LOADW_NAND, 320 ATOMIC_LOADW_MIN, 321 ATOMIC_LOADW_MAX, 322 ATOMIC_LOADW_UMIN, 323 ATOMIC_LOADW_UMAX, 324 325 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 326 // 327 // Operand 0: the address of the containing 32-bit-aligned field 328 // Operand 1: the compare value, in the low bits of an i32 329 // Operand 2: the swap value, in the low bits of an i32 330 // Operand 3: how many bits to rotate the i32 left to bring the first 331 // operand into the high bits 332 // Operand 4: the negative of operand 2, for rotating the other way 333 // Operand 5: the width of the field in bits (8 or 16) 334 ATOMIC_CMP_SWAPW, 335 336 // Atomic compare-and-swap returning CC value. 337 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 338 ATOMIC_CMP_SWAP, 339 340 // 128-bit atomic load. 341 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr) 342 ATOMIC_LOAD_128, 343 344 // 128-bit atomic store. 345 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr) 346 ATOMIC_STORE_128, 347 348 // 128-bit atomic compare-and-swap. 349 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 350 ATOMIC_CMP_SWAP_128, 351 352 // Byte swapping load/store. Same operands as regular load/store. 353 LRV, STRV, 354 355 // Element swapping load/store. Same operands as regular load/store. 356 VLER, VSTER, 357 358 // Prefetch from the second operand using the 4-bit control code in 359 // the first operand. The code is 1 for a load prefetch and 2 for 360 // a store prefetch. 361 PREFETCH 362 }; 363 364 // Return true if OPCODE is some kind of PC-relative address. 365 inline bool isPCREL(unsigned Opcode) { 366 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 367 } 368 } // end namespace SystemZISD 369 370 namespace SystemZICMP { 371 // Describes whether an integer comparison needs to be signed or unsigned, 372 // or whether either type is OK. 373 enum { 374 Any, 375 UnsignedOnly, 376 SignedOnly 377 }; 378 } // end namespace SystemZICMP 379 380 class SystemZSubtarget; 381 class SystemZTargetMachine; 382 383 class SystemZTargetLowering : public TargetLowering { 384 public: 385 explicit SystemZTargetLowering(const TargetMachine &TM, 386 const SystemZSubtarget &STI); 387 388 bool useSoftFloat() const override; 389 390 // Override TargetLowering. 391 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 392 return MVT::i32; 393 } 394 MVT getVectorIdxTy(const DataLayout &DL) const override { 395 // Only the lower 12 bits of an element index are used, so we don't 396 // want to clobber the upper 32 bits of a GPR unnecessarily. 397 return MVT::i32; 398 } 399 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 400 const override { 401 // Widen subvectors to the full width rather than promoting integer 402 // elements. This is better because: 403 // 404 // (a) it means that we can handle the ABI for passing and returning 405 // sub-128 vectors without having to handle them as legal types. 406 // 407 // (b) we don't have instructions to extend on load and truncate on store, 408 // so promoting the integers is less efficient. 409 // 410 // (c) there are no multiplication instructions for the widest integer 411 // type (v2i64). 412 if (VT.getScalarSizeInBits() % 8 == 0) 413 return TypeWidenVector; 414 return TargetLoweringBase::getPreferredVectorAction(VT); 415 } 416 unsigned 417 getNumRegisters(LLVMContext &Context, EVT VT, 418 Optional<MVT> RegisterVT) const override { 419 // i128 inline assembly operand. 420 if (VT == MVT::i128 && 421 RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped) 422 return 1; 423 return TargetLowering::getNumRegisters(Context, VT); 424 } 425 bool isCheapToSpeculateCtlz() const override { return true; } 426 bool preferZeroCompareBranch() const override { return true; } 427 bool hasBitPreservingFPLogic(EVT VT) const override { 428 EVT ScVT = VT.getScalarType(); 429 return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128; 430 } 431 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override { 432 ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1)); 433 return Mask && Mask->getValue().isIntN(16); 434 } 435 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 436 return VT.isScalarInteger(); 437 } 438 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 439 EVT) const override; 440 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 441 EVT VT) const override; 442 bool isFPImmLegal(const APFloat &Imm, EVT VT, 443 bool ForCodeSize) const override; 444 bool hasInlineStackProbe(MachineFunction &MF) const override; 445 bool isLegalICmpImmediate(int64_t Imm) const override; 446 bool isLegalAddImmediate(int64_t Imm) const override; 447 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 448 unsigned AS, 449 Instruction *I = nullptr) const override; 450 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, 451 MachineMemOperand::Flags Flags, 452 bool *Fast) const override; 453 bool isTruncateFree(Type *, Type *) const override; 454 bool isTruncateFree(EVT, EVT) const override; 455 456 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 457 bool MathUsed) const override { 458 // Form add and sub with overflow intrinsics regardless of any extra 459 // users of the math result. 460 return VT == MVT::i32 || VT == MVT::i64; 461 } 462 463 const char *getTargetNodeName(unsigned Opcode) const override; 464 std::pair<unsigned, const TargetRegisterClass *> 465 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 466 StringRef Constraint, MVT VT) const override; 467 TargetLowering::ConstraintType 468 getConstraintType(StringRef Constraint) const override; 469 TargetLowering::ConstraintWeight 470 getSingleConstraintMatchWeight(AsmOperandInfo &info, 471 const char *constraint) const override; 472 void LowerAsmOperandForConstraint(SDValue Op, 473 std::string &Constraint, 474 std::vector<SDValue> &Ops, 475 SelectionDAG &DAG) const override; 476 477 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 478 if (ConstraintCode.size() == 1) { 479 switch(ConstraintCode[0]) { 480 default: 481 break; 482 case 'o': 483 return InlineAsm::Constraint_o; 484 case 'Q': 485 return InlineAsm::Constraint_Q; 486 case 'R': 487 return InlineAsm::Constraint_R; 488 case 'S': 489 return InlineAsm::Constraint_S; 490 case 'T': 491 return InlineAsm::Constraint_T; 492 } 493 } 494 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 495 } 496 497 Register getRegisterByName(const char *RegName, LLT VT, 498 const MachineFunction &MF) const override; 499 500 /// If a physical register, this returns the register that receives the 501 /// exception address on entry to an EH pad. 502 Register 503 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 504 return SystemZ::R6D; 505 } 506 507 /// If a physical register, this returns the register that receives the 508 /// exception typeid on entry to a landing pad. 509 Register 510 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 511 return SystemZ::R7D; 512 } 513 514 /// Override to support customized stack guard loading. 515 bool useLoadStackGuardNode() const override { 516 return true; 517 } 518 void insertSSPDeclarations(Module &M) const override { 519 } 520 521 MachineBasicBlock * 522 EmitInstrWithCustomInserter(MachineInstr &MI, 523 MachineBasicBlock *BB) const override; 524 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 525 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, 526 SelectionDAG &DAG) const override; 527 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 528 SelectionDAG &DAG) const override; 529 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 530 bool allowTruncateForTailCall(Type *, Type *) const override; 531 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 532 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 533 SDValue Val, SDValue *Parts, 534 unsigned NumParts, MVT PartVT, 535 Optional<CallingConv::ID> CC) const override; 536 SDValue 537 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 538 const SDValue *Parts, unsigned NumParts, 539 MVT PartVT, EVT ValueVT, 540 Optional<CallingConv::ID> CC) const override; 541 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 542 bool isVarArg, 543 const SmallVectorImpl<ISD::InputArg> &Ins, 544 const SDLoc &DL, SelectionDAG &DAG, 545 SmallVectorImpl<SDValue> &InVals) const override; 546 SDValue LowerCall(CallLoweringInfo &CLI, 547 SmallVectorImpl<SDValue> &InVals) const override; 548 549 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 550 bool isVarArg, 551 const SmallVectorImpl<ISD::OutputArg> &Outs, 552 LLVMContext &Context) const override; 553 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 554 const SmallVectorImpl<ISD::OutputArg> &Outs, 555 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 556 SelectionDAG &DAG) const override; 557 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 558 559 /// Determine which of the bits specified in Mask are known to be either 560 /// zero or one and return them in the KnownZero/KnownOne bitsets. 561 void computeKnownBitsForTargetNode(const SDValue Op, 562 KnownBits &Known, 563 const APInt &DemandedElts, 564 const SelectionDAG &DAG, 565 unsigned Depth = 0) const override; 566 567 /// Determine the number of bits in the operation that are sign bits. 568 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 569 const APInt &DemandedElts, 570 const SelectionDAG &DAG, 571 unsigned Depth) const override; 572 573 ISD::NodeType getExtendForAtomicOps() const override { 574 return ISD::ANY_EXTEND; 575 } 576 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 577 return ISD::ZERO_EXTEND; 578 } 579 580 bool supportSwiftError() const override { 581 return true; 582 } 583 584 unsigned getStackProbeSize(MachineFunction &MF) const; 585 586 private: 587 const SystemZSubtarget &Subtarget; 588 589 // Implement LowerOperation for individual opcodes. 590 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, 591 const SDLoc &DL, EVT VT, 592 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const; 593 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, 594 EVT VT, ISD::CondCode CC, 595 SDValue CmpOp0, SDValue CmpOp1, 596 SDValue Chain = SDValue(), 597 bool IsSignaling = false) const; 598 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 599 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG, 600 bool IsSignaling) const; 601 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 602 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 603 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 604 SelectionDAG &DAG) const; 605 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 606 SelectionDAG &DAG, unsigned Opcode, 607 SDValue GOTOffset) const; 608 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; 609 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 610 SelectionDAG &DAG) const; 611 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 612 SelectionDAG &DAG) const; 613 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 614 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 615 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 616 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 617 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 618 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 619 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 620 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 621 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 622 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 623 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 624 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 625 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const; 626 SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const; 627 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 628 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 629 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 630 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 631 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 632 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 633 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 634 unsigned Opcode) const; 635 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 636 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 637 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 638 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 639 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 640 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 641 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 642 bool isVectorElementLoad(SDValue Op) const; 643 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, 644 SmallVectorImpl<SDValue> &Elems) const; 645 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 646 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 647 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 648 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 649 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 650 SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 651 SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 652 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 653 654 bool canTreatAsByteVector(EVT VT) const; 655 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 656 unsigned Index, DAGCombinerInfo &DCI, 657 bool Force) const; 658 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op, 659 DAGCombinerInfo &DCI) const; 660 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 661 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 662 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const; 663 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const; 664 bool canLoadStoreByteSwapped(EVT VT) const; 665 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const; 666 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const; 667 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const; 668 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const; 669 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const; 670 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const; 671 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 672 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const; 673 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const; 674 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 675 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 676 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 677 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const; 678 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const; 679 680 SDValue unwrapAddress(SDValue N) const override; 681 682 // If the last instruction before MBBI in MBB was some form of COMPARE, 683 // try to replace it with a COMPARE AND BRANCH just before MBBI. 684 // CCMask and Target are the BRC-like operands for the branch. 685 // Return true if the change was made. 686 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 687 MachineBasicBlock::iterator MBBI, 688 unsigned CCMask, 689 MachineBasicBlock *Target) const; 690 691 // Implement EmitInstrWithCustomInserter for individual operation types. 692 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const; 693 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, 694 unsigned StoreOpcode, unsigned STOCOpcode, 695 bool Invert) const; 696 MachineBasicBlock *emitPair128(MachineInstr &MI, 697 MachineBasicBlock *MBB) const; 698 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, 699 bool ClearEven) const; 700 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, 701 MachineBasicBlock *BB, 702 unsigned BinOpcode, unsigned BitSize, 703 bool Invert = false) const; 704 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, 705 MachineBasicBlock *MBB, 706 unsigned CompareOpcode, 707 unsigned KeepOldMask, 708 unsigned BitSize) const; 709 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, 710 MachineBasicBlock *BB) const; 711 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, 712 unsigned Opcode) const; 713 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, 714 unsigned Opcode) const; 715 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, 716 MachineBasicBlock *MBB, 717 unsigned Opcode, bool NoFloat) const; 718 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, 719 MachineBasicBlock *MBB, 720 unsigned Opcode) const; 721 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 722 MachineBasicBlock *MBB) const; 723 724 SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const; 725 726 MachineMemOperand::Flags 727 getTargetMMOFlags(const Instruction &I) const override; 728 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 729 }; 730 731 struct SystemZVectorConstantInfo { 732 private: 733 APInt IntBits; // The 128 bits as an integer. 734 APInt SplatBits; // Smallest splat value. 735 APInt SplatUndef; // Bits correspoding to undef operands of the BVN. 736 unsigned SplatBitSize = 0; 737 bool isFP128 = false; 738 739 public: 740 unsigned Opcode = 0; 741 SmallVector<unsigned, 2> OpVals; 742 MVT VecVT; 743 SystemZVectorConstantInfo(APFloat FPImm); 744 SystemZVectorConstantInfo(BuildVectorSDNode *BVN); 745 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget); 746 }; 747 748 } // end namespace llvm 749 750 #endif 751