1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16 17 #include "SystemZ.h" 18 #include "SystemZInstrInfo.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38 // (The call target is implicitly __tls_get_offset.) 39 TLS_GDCALL, 40 TLS_LDCALL, 41 42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43 // accesses (LARL). Operand 0 is the address. 44 PCREL_WRAPPER, 45 46 // Used in cases where an offset is applied to a TargetGlobalAddress. 47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48 // PCREL_WRAPPER for an anchor point. This is used so that we can 49 // cheaply refer to either the full address or the anchor point 50 // as a register base. 51 PCREL_OFFSET, 52 53 // Integer absolute. 54 IABS, 55 56 // Integer comparisons. There are three operands: the two values 57 // to compare, and an integer of type SystemZICMP. 58 ICMP, 59 60 // Floating-point comparisons. The two operands are the values to compare. 61 FCMP, 62 63 // Test under mask. The first operand is ANDed with the second operand 64 // and the condition codes are set on the result. The third operand is 65 // a boolean that is true if the condition codes need to distinguish 66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 67 // register forms do but the memory forms don't). 68 TM, 69 70 // Branches if a condition is true. Operand 0 is the chain operand; 71 // operand 1 is the 4-bit condition-code mask, with bit N in 72 // big-endian order meaning "branch if CC=N"; operand 2 is the 73 // target block and operand 3 is the flag operand. 74 BR_CCMASK, 75 76 // Selects between operand 0 and operand 1. Operand 2 is the 77 // mask of condition-code values for which operand 0 should be 78 // chosen over operand 1; it has the same form as BR_CCMASK. 79 // Operand 3 is the flag operand. 80 SELECT_CCMASK, 81 82 // Evaluates to the gap between the stack pointer and the 83 // base of the dynamically-allocatable area. 84 ADJDYNALLOC, 85 86 // Count number of bits set in operand 0 per byte. 87 POPCNT, 88 89 // Wrappers around the ISD opcodes of the same name. The output is GR128. 90 // Input operands may be GR64 or GR32, depending on the instruction. 91 SMUL_LOHI, 92 UMUL_LOHI, 93 SDIVREM, 94 UDIVREM, 95 96 // Add/subtract with overflow/carry. These have the same operands as 97 // the corresponding standard operations, except with the carry flag 98 // replaced by a condition code value. 99 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, 100 101 // Set the condition code from a boolean value in operand 0. 102 // Operand 1 is a mask of all condition-code values that may result of this 103 // operation, operand 2 is a mask of condition-code values that may result 104 // if the boolean is true. 105 // Note that this operation is always optimized away, we will never 106 // generate any code for it. 107 GET_CCMASK, 108 109 // Use a series of MVCs to copy bytes from one memory location to another. 110 // The operands are: 111 // - the target address 112 // - the source address 113 // - the constant length 114 // 115 // This isn't a memory opcode because we'd need to attach two 116 // MachineMemOperands rather than one. 117 MVC, 118 119 // Like MVC, but implemented as a loop that handles X*256 bytes 120 // followed by straight-line code to handle the rest (if any). 121 // The value of X is passed as an additional operand. 122 MVC_LOOP, 123 124 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). 125 NC, 126 NC_LOOP, 127 OC, 128 OC_LOOP, 129 XC, 130 XC_LOOP, 131 132 // Use CLC to compare two blocks of memory, with the same comments 133 // as for MVC and MVC_LOOP. 134 CLC, 135 CLC_LOOP, 136 137 // Use an MVST-based sequence to implement stpcpy(). 138 STPCPY, 139 140 // Use a CLST-based sequence to implement strcmp(). The two input operands 141 // are the addresses of the strings to compare. 142 STRCMP, 143 144 // Use an SRST-based sequence to search a block of memory. The first 145 // operand is the end address, the second is the start, and the third 146 // is the character to search for. CC is set to 1 on success and 2 147 // on failure. 148 SEARCH_STRING, 149 150 // Store the CC value in bits 29 and 28 of an integer. 151 IPM, 152 153 // Compiler barrier only; generate a no-op. 154 MEMBARRIER, 155 156 // Transaction begin. The first operand is the chain, the second 157 // the TDB pointer, and the third the immediate control field. 158 // Returns CC value and chain. 159 TBEGIN, 160 TBEGIN_NOFLOAT, 161 162 // Transaction end. Just the chain operand. Returns CC value and chain. 163 TEND, 164 165 // Create a vector constant by filling byte N of the result with bit 166 // 15-N of the single operand. 167 BYTE_MASK, 168 169 // Create a vector constant by replicating an element-sized RISBG-style mask. 170 // The first operand specifies the starting set bit and the second operand 171 // specifies the ending set bit. Both operands count from the MSB of the 172 // element. 173 ROTATE_MASK, 174 175 // Replicate a GPR scalar value into all elements of a vector. 176 REPLICATE, 177 178 // Create a vector from two i64 GPRs. 179 JOIN_DWORDS, 180 181 // Replicate one element of a vector into all elements. The first operand 182 // is the vector and the second is the index of the element to replicate. 183 SPLAT, 184 185 // Interleave elements from the high half of operand 0 and the high half 186 // of operand 1. 187 MERGE_HIGH, 188 189 // Likewise for the low halves. 190 MERGE_LOW, 191 192 // Concatenate the vectors in the first two operands, shift them left 193 // by the third operand, and take the first half of the result. 194 SHL_DOUBLE, 195 196 // Take one element of the first v2i64 operand and the one element of 197 // the second v2i64 operand and concatenate them to form a v2i64 result. 198 // The third operand is a 4-bit value of the form 0A0B, where A and B 199 // are the element selectors for the first operand and second operands 200 // respectively. 201 PERMUTE_DWORDS, 202 203 // Perform a general vector permute on vector operands 0 and 1. 204 // Each byte of operand 2 controls the corresponding byte of the result, 205 // in the same way as a byte-level VECTOR_SHUFFLE mask. 206 PERMUTE, 207 208 // Pack vector operands 0 and 1 into a single vector with half-sized elements. 209 PACK, 210 211 // Likewise, but saturate the result and set CC. PACKS_CC does signed 212 // saturation and PACKLS_CC does unsigned saturation. 213 PACKS_CC, 214 PACKLS_CC, 215 216 // Unpack the first half of vector operand 0 into double-sized elements. 217 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 218 UNPACK_HIGH, 219 UNPACKL_HIGH, 220 221 // Likewise for the second half. 222 UNPACK_LOW, 223 UNPACKL_LOW, 224 225 // Shift each element of vector operand 0 by the number of bits specified 226 // by scalar operand 1. 227 VSHL_BY_SCALAR, 228 VSRL_BY_SCALAR, 229 VSRA_BY_SCALAR, 230 231 // For each element of the output type, sum across all sub-elements of 232 // operand 0 belonging to the corresponding element, and add in the 233 // rightmost sub-element of the corresponding element of operand 1. 234 VSUM, 235 236 // Compare integer vector operands 0 and 1 to produce the usual 0/-1 237 // vector result. VICMPE is for equality, VICMPH for "signed greater than" 238 // and VICMPHL for "unsigned greater than". 239 VICMPE, 240 VICMPH, 241 VICMPHL, 242 243 // Likewise, but also set the condition codes on the result. 244 VICMPES, 245 VICMPHS, 246 VICMPHLS, 247 248 // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1 249 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 250 // greater than" and VFCMPHE for "ordered and greater than or equal to". 251 VFCMPE, 252 VFCMPH, 253 VFCMPHE, 254 255 // Likewise, but also set the condition codes on the result. 256 VFCMPES, 257 VFCMPHS, 258 VFCMPHES, 259 260 // Test floating-point data class for vectors. 261 VFTCI, 262 263 // Extend the even f32 elements of vector operand 0 to produce a vector 264 // of f64 elements. 265 VEXTEND, 266 267 // Round the f64 elements of vector operand 0 to f32s and store them in the 268 // even elements of the result. 269 VROUND, 270 271 // AND the two vector operands together and set CC based on the result. 272 VTM, 273 274 // String operations that set CC as a side-effect. 275 VFAE_CC, 276 VFAEZ_CC, 277 VFEE_CC, 278 VFEEZ_CC, 279 VFENE_CC, 280 VFENEZ_CC, 281 VISTR_CC, 282 VSTRC_CC, 283 VSTRCZ_CC, 284 VSTRS_CC, 285 VSTRSZ_CC, 286 287 // Test Data Class. 288 // 289 // Operand 0: the value to test 290 // Operand 1: the bit mask 291 TDC, 292 293 // Strict variants of scalar floating-point comparisons. 294 // Quiet and signaling versions. 295 STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 296 STRICT_FCMPS, 297 298 // Strict variants of vector floating-point comparisons. 299 // Quiet and signaling versions. 300 STRICT_VFCMPE, 301 STRICT_VFCMPH, 302 STRICT_VFCMPHE, 303 STRICT_VFCMPES, 304 STRICT_VFCMPHS, 305 STRICT_VFCMPHES, 306 307 // Strict variants of VEXTEND and VROUND. 308 STRICT_VEXTEND, 309 STRICT_VROUND, 310 311 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 312 // ATOMIC_LOAD_<op>. 313 // 314 // Operand 0: the address of the containing 32-bit-aligned field 315 // Operand 1: the second operand of <op>, in the high bits of an i32 316 // for everything except ATOMIC_SWAPW 317 // Operand 2: how many bits to rotate the i32 left to bring the first 318 // operand into the high bits 319 // Operand 3: the negative of operand 2, for rotating the other way 320 // Operand 4: the width of the field in bits (8 or 16) 321 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 322 ATOMIC_LOADW_ADD, 323 ATOMIC_LOADW_SUB, 324 ATOMIC_LOADW_AND, 325 ATOMIC_LOADW_OR, 326 ATOMIC_LOADW_XOR, 327 ATOMIC_LOADW_NAND, 328 ATOMIC_LOADW_MIN, 329 ATOMIC_LOADW_MAX, 330 ATOMIC_LOADW_UMIN, 331 ATOMIC_LOADW_UMAX, 332 333 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 334 // 335 // Operand 0: the address of the containing 32-bit-aligned field 336 // Operand 1: the compare value, in the low bits of an i32 337 // Operand 2: the swap value, in the low bits of an i32 338 // Operand 3: how many bits to rotate the i32 left to bring the first 339 // operand into the high bits 340 // Operand 4: the negative of operand 2, for rotating the other way 341 // Operand 5: the width of the field in bits (8 or 16) 342 ATOMIC_CMP_SWAPW, 343 344 // Atomic compare-and-swap returning CC value. 345 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 346 ATOMIC_CMP_SWAP, 347 348 // 128-bit atomic load. 349 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr) 350 ATOMIC_LOAD_128, 351 352 // 128-bit atomic store. 353 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr) 354 ATOMIC_STORE_128, 355 356 // 128-bit atomic compare-and-swap. 357 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 358 ATOMIC_CMP_SWAP_128, 359 360 // Byte swapping load/store. Same operands as regular load/store. 361 LRV, STRV, 362 363 // Element swapping load/store. Same operands as regular load/store. 364 VLER, VSTER, 365 366 // Prefetch from the second operand using the 4-bit control code in 367 // the first operand. The code is 1 for a load prefetch and 2 for 368 // a store prefetch. 369 PREFETCH 370 }; 371 372 // Return true if OPCODE is some kind of PC-relative address. 373 inline bool isPCREL(unsigned Opcode) { 374 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 375 } 376 } // end namespace SystemZISD 377 378 namespace SystemZICMP { 379 // Describes whether an integer comparison needs to be signed or unsigned, 380 // or whether either type is OK. 381 enum { 382 Any, 383 UnsignedOnly, 384 SignedOnly 385 }; 386 } // end namespace SystemZICMP 387 388 class SystemZSubtarget; 389 class SystemZTargetMachine; 390 391 class SystemZTargetLowering : public TargetLowering { 392 public: 393 explicit SystemZTargetLowering(const TargetMachine &TM, 394 const SystemZSubtarget &STI); 395 396 bool useSoftFloat() const override; 397 398 // Override TargetLowering. 399 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 400 return MVT::i32; 401 } 402 MVT getVectorIdxTy(const DataLayout &DL) const override { 403 // Only the lower 12 bits of an element index are used, so we don't 404 // want to clobber the upper 32 bits of a GPR unnecessarily. 405 return MVT::i32; 406 } 407 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 408 const override { 409 // Widen subvectors to the full width rather than promoting integer 410 // elements. This is better because: 411 // 412 // (a) it means that we can handle the ABI for passing and returning 413 // sub-128 vectors without having to handle them as legal types. 414 // 415 // (b) we don't have instructions to extend on load and truncate on store, 416 // so promoting the integers is less efficient. 417 // 418 // (c) there are no multiplication instructions for the widest integer 419 // type (v2i64). 420 if (VT.getScalarSizeInBits() % 8 == 0) 421 return TypeWidenVector; 422 return TargetLoweringBase::getPreferredVectorAction(VT); 423 } 424 bool isCheapToSpeculateCtlz() const override { return true; } 425 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 426 EVT) const override; 427 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 428 EVT VT) const override; 429 bool isFPImmLegal(const APFloat &Imm, EVT VT, 430 bool ForCodeSize) const override; 431 bool isLegalICmpImmediate(int64_t Imm) const override; 432 bool isLegalAddImmediate(int64_t Imm) const override; 433 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 434 unsigned AS, 435 Instruction *I = nullptr) const override; 436 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 437 unsigned Align, 438 MachineMemOperand::Flags Flags, 439 bool *Fast) const override; 440 bool isTruncateFree(Type *, Type *) const override; 441 bool isTruncateFree(EVT, EVT) const override; 442 443 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 444 bool MathUsed) const override { 445 // Form add and sub with overflow intrinsics regardless of any extra 446 // users of the math result. 447 return VT == MVT::i32 || VT == MVT::i64; 448 } 449 450 const char *getTargetNodeName(unsigned Opcode) const override; 451 std::pair<unsigned, const TargetRegisterClass *> 452 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 453 StringRef Constraint, MVT VT) const override; 454 TargetLowering::ConstraintType 455 getConstraintType(StringRef Constraint) const override; 456 TargetLowering::ConstraintWeight 457 getSingleConstraintMatchWeight(AsmOperandInfo &info, 458 const char *constraint) const override; 459 void LowerAsmOperandForConstraint(SDValue Op, 460 std::string &Constraint, 461 std::vector<SDValue> &Ops, 462 SelectionDAG &DAG) const override; 463 464 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 465 if (ConstraintCode.size() == 1) { 466 switch(ConstraintCode[0]) { 467 default: 468 break; 469 case 'o': 470 return InlineAsm::Constraint_o; 471 case 'Q': 472 return InlineAsm::Constraint_Q; 473 case 'R': 474 return InlineAsm::Constraint_R; 475 case 'S': 476 return InlineAsm::Constraint_S; 477 case 'T': 478 return InlineAsm::Constraint_T; 479 } 480 } 481 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 482 } 483 484 Register getRegisterByName(const char *RegName, LLT VT, 485 const MachineFunction &MF) const override; 486 487 /// If a physical register, this returns the register that receives the 488 /// exception address on entry to an EH pad. 489 Register 490 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 491 return SystemZ::R6D; 492 } 493 494 /// If a physical register, this returns the register that receives the 495 /// exception typeid on entry to a landing pad. 496 Register 497 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 498 return SystemZ::R7D; 499 } 500 501 /// Override to support customized stack guard loading. 502 bool useLoadStackGuardNode() const override { 503 return true; 504 } 505 void insertSSPDeclarations(Module &M) const override { 506 } 507 508 MachineBasicBlock * 509 EmitInstrWithCustomInserter(MachineInstr &MI, 510 MachineBasicBlock *BB) const override; 511 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 512 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, 513 SelectionDAG &DAG) const override; 514 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 515 SelectionDAG &DAG) const override; 516 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 517 bool allowTruncateForTailCall(Type *, Type *) const override; 518 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 519 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 520 bool isVarArg, 521 const SmallVectorImpl<ISD::InputArg> &Ins, 522 const SDLoc &DL, SelectionDAG &DAG, 523 SmallVectorImpl<SDValue> &InVals) const override; 524 SDValue LowerCall(CallLoweringInfo &CLI, 525 SmallVectorImpl<SDValue> &InVals) const override; 526 527 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 528 bool isVarArg, 529 const SmallVectorImpl<ISD::OutputArg> &Outs, 530 LLVMContext &Context) const override; 531 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 532 const SmallVectorImpl<ISD::OutputArg> &Outs, 533 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 534 SelectionDAG &DAG) const override; 535 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 536 537 /// Determine which of the bits specified in Mask are known to be either 538 /// zero or one and return them in the KnownZero/KnownOne bitsets. 539 void computeKnownBitsForTargetNode(const SDValue Op, 540 KnownBits &Known, 541 const APInt &DemandedElts, 542 const SelectionDAG &DAG, 543 unsigned Depth = 0) const override; 544 545 /// Determine the number of bits in the operation that are sign bits. 546 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 547 const APInt &DemandedElts, 548 const SelectionDAG &DAG, 549 unsigned Depth) const override; 550 551 ISD::NodeType getExtendForAtomicOps() const override { 552 return ISD::ANY_EXTEND; 553 } 554 555 bool supportSwiftError() const override { 556 return true; 557 } 558 559 private: 560 const SystemZSubtarget &Subtarget; 561 562 // Implement LowerOperation for individual opcodes. 563 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, 564 const SDLoc &DL, EVT VT, 565 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const; 566 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, 567 EVT VT, ISD::CondCode CC, 568 SDValue CmpOp0, SDValue CmpOp1, 569 SDValue Chain = SDValue(), 570 bool IsSignaling = false) const; 571 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 572 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG, 573 bool IsSignaling) const; 574 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 575 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 576 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 577 SelectionDAG &DAG) const; 578 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 579 SelectionDAG &DAG, unsigned Opcode, 580 SDValue GOTOffset) const; 581 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; 582 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 583 SelectionDAG &DAG) const; 584 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 585 SelectionDAG &DAG) const; 586 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 587 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 588 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 589 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 590 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 591 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 592 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 593 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 594 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 595 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 596 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 597 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 598 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const; 599 SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const; 600 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 601 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 602 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 603 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 604 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 605 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 606 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 607 unsigned Opcode) const; 608 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 609 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 610 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 611 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 612 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 613 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 614 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 615 bool isVectorElementLoad(SDValue Op) const; 616 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, 617 SmallVectorImpl<SDValue> &Elems) const; 618 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 619 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 620 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 621 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 622 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 623 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG, 624 unsigned UnpackHigh) const; 625 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 626 627 bool canTreatAsByteVector(EVT VT) const; 628 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 629 unsigned Index, DAGCombinerInfo &DCI, 630 bool Force) const; 631 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op, 632 DAGCombinerInfo &DCI) const; 633 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 634 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 635 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const; 636 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const; 637 bool canLoadStoreByteSwapped(EVT VT) const; 638 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const; 639 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const; 640 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const; 641 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const; 642 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const; 643 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const; 644 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 645 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const; 646 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const; 647 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 648 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 649 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 650 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const; 651 652 SDValue unwrapAddress(SDValue N) const override; 653 654 // If the last instruction before MBBI in MBB was some form of COMPARE, 655 // try to replace it with a COMPARE AND BRANCH just before MBBI. 656 // CCMask and Target are the BRC-like operands for the branch. 657 // Return true if the change was made. 658 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 659 MachineBasicBlock::iterator MBBI, 660 unsigned CCMask, 661 MachineBasicBlock *Target) const; 662 663 // Implement EmitInstrWithCustomInserter for individual operation types. 664 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const; 665 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, 666 unsigned StoreOpcode, unsigned STOCOpcode, 667 bool Invert) const; 668 MachineBasicBlock *emitPair128(MachineInstr &MI, 669 MachineBasicBlock *MBB) const; 670 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, 671 bool ClearEven) const; 672 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, 673 MachineBasicBlock *BB, 674 unsigned BinOpcode, unsigned BitSize, 675 bool Invert = false) const; 676 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, 677 MachineBasicBlock *MBB, 678 unsigned CompareOpcode, 679 unsigned KeepOldMask, 680 unsigned BitSize) const; 681 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, 682 MachineBasicBlock *BB) const; 683 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, 684 unsigned Opcode) const; 685 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, 686 unsigned Opcode) const; 687 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, 688 MachineBasicBlock *MBB, 689 unsigned Opcode, bool NoFloat) const; 690 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, 691 MachineBasicBlock *MBB, 692 unsigned Opcode) const; 693 694 MachineMemOperand::Flags 695 getTargetMMOFlags(const Instruction &I) const override; 696 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 697 }; 698 699 struct SystemZVectorConstantInfo { 700 private: 701 APInt IntBits; // The 128 bits as an integer. 702 APInt SplatBits; // Smallest splat value. 703 APInt SplatUndef; // Bits correspoding to undef operands of the BVN. 704 unsigned SplatBitSize = 0; 705 bool isFP128 = false; 706 707 public: 708 unsigned Opcode = 0; 709 SmallVector<unsigned, 2> OpVals; 710 MVT VecVT; 711 SystemZVectorConstantInfo(APFloat FPImm); 712 SystemZVectorConstantInfo(BuildVectorSDNode *BVN); 713 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget); 714 }; 715 716 } // end namespace llvm 717 718 #endif 719