1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16 17 #include "SystemZ.h" 18 #include "SystemZInstrInfo.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/CodeGen/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38 // (The call target is implicitly __tls_get_offset.) 39 TLS_GDCALL, 40 TLS_LDCALL, 41 42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43 // accesses (LARL). Operand 0 is the address. 44 PCREL_WRAPPER, 45 46 // Used in cases where an offset is applied to a TargetGlobalAddress. 47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48 // PCREL_WRAPPER for an anchor point. This is used so that we can 49 // cheaply refer to either the full address or the anchor point 50 // as a register base. 51 PCREL_OFFSET, 52 53 // Integer comparisons. There are three operands: the two values 54 // to compare, and an integer of type SystemZICMP. 55 ICMP, 56 57 // Floating-point comparisons. The two operands are the values to compare. 58 FCMP, 59 60 // Test under mask. The first operand is ANDed with the second operand 61 // and the condition codes are set on the result. The third operand is 62 // a boolean that is true if the condition codes need to distinguish 63 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 64 // register forms do but the memory forms don't). 65 TM, 66 67 // Branches if a condition is true. Operand 0 is the chain operand; 68 // operand 1 is the 4-bit condition-code mask, with bit N in 69 // big-endian order meaning "branch if CC=N"; operand 2 is the 70 // target block and operand 3 is the flag operand. 71 BR_CCMASK, 72 73 // Selects between operand 0 and operand 1. Operand 2 is the 74 // mask of condition-code values for which operand 0 should be 75 // chosen over operand 1; it has the same form as BR_CCMASK. 76 // Operand 3 is the flag operand. 77 SELECT_CCMASK, 78 79 // Evaluates to the gap between the stack pointer and the 80 // base of the dynamically-allocatable area. 81 ADJDYNALLOC, 82 83 // For allocating stack space when using stack clash protector. 84 // Allocation is performed by block, and each block is probed. 85 PROBED_ALLOCA, 86 87 // Count number of bits set in operand 0 per byte. 88 POPCNT, 89 90 // Wrappers around the ISD opcodes of the same name. The output is GR128. 91 // Input operands may be GR64 or GR32, depending on the instruction. 92 SMUL_LOHI, 93 UMUL_LOHI, 94 SDIVREM, 95 UDIVREM, 96 97 // Add/subtract with overflow/carry. These have the same operands as 98 // the corresponding standard operations, except with the carry flag 99 // replaced by a condition code value. 100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, 101 102 // Set the condition code from a boolean value in operand 0. 103 // Operand 1 is a mask of all condition-code values that may result of this 104 // operation, operand 2 is a mask of condition-code values that may result 105 // if the boolean is true. 106 // Note that this operation is always optimized away, we will never 107 // generate any code for it. 108 GET_CCMASK, 109 110 // Use a series of MVCs to copy bytes from one memory location to another. 111 // The operands are: 112 // - the target address 113 // - the source address 114 // - the constant length 115 // 116 // This isn't a memory opcode because we'd need to attach two 117 // MachineMemOperands rather than one. 118 MVC, 119 120 // Like MVC, but implemented as a loop that handles X*256 bytes 121 // followed by straight-line code to handle the rest (if any). 122 // The value of X is passed as an additional operand. 123 MVC_LOOP, 124 125 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). 126 NC, 127 NC_LOOP, 128 OC, 129 OC_LOOP, 130 XC, 131 XC_LOOP, 132 133 // Use CLC to compare two blocks of memory, with the same comments 134 // as for MVC and MVC_LOOP. 135 CLC, 136 CLC_LOOP, 137 138 // Use an MVST-based sequence to implement stpcpy(). 139 STPCPY, 140 141 // Use a CLST-based sequence to implement strcmp(). The two input operands 142 // are the addresses of the strings to compare. 143 STRCMP, 144 145 // Use an SRST-based sequence to search a block of memory. The first 146 // operand is the end address, the second is the start, and the third 147 // is the character to search for. CC is set to 1 on success and 2 148 // on failure. 149 SEARCH_STRING, 150 151 // Store the CC value in bits 29 and 28 of an integer. 152 IPM, 153 154 // Compiler barrier only; generate a no-op. 155 MEMBARRIER, 156 157 // Transaction begin. The first operand is the chain, the second 158 // the TDB pointer, and the third the immediate control field. 159 // Returns CC value and chain. 160 TBEGIN, 161 TBEGIN_NOFLOAT, 162 163 // Transaction end. Just the chain operand. Returns CC value and chain. 164 TEND, 165 166 // Create a vector constant by filling byte N of the result with bit 167 // 15-N of the single operand. 168 BYTE_MASK, 169 170 // Create a vector constant by replicating an element-sized RISBG-style mask. 171 // The first operand specifies the starting set bit and the second operand 172 // specifies the ending set bit. Both operands count from the MSB of the 173 // element. 174 ROTATE_MASK, 175 176 // Replicate a GPR scalar value into all elements of a vector. 177 REPLICATE, 178 179 // Create a vector from two i64 GPRs. 180 JOIN_DWORDS, 181 182 // Replicate one element of a vector into all elements. The first operand 183 // is the vector and the second is the index of the element to replicate. 184 SPLAT, 185 186 // Interleave elements from the high half of operand 0 and the high half 187 // of operand 1. 188 MERGE_HIGH, 189 190 // Likewise for the low halves. 191 MERGE_LOW, 192 193 // Concatenate the vectors in the first two operands, shift them left 194 // by the third operand, and take the first half of the result. 195 SHL_DOUBLE, 196 197 // Take one element of the first v2i64 operand and the one element of 198 // the second v2i64 operand and concatenate them to form a v2i64 result. 199 // The third operand is a 4-bit value of the form 0A0B, where A and B 200 // are the element selectors for the first operand and second operands 201 // respectively. 202 PERMUTE_DWORDS, 203 204 // Perform a general vector permute on vector operands 0 and 1. 205 // Each byte of operand 2 controls the corresponding byte of the result, 206 // in the same way as a byte-level VECTOR_SHUFFLE mask. 207 PERMUTE, 208 209 // Pack vector operands 0 and 1 into a single vector with half-sized elements. 210 PACK, 211 212 // Likewise, but saturate the result and set CC. PACKS_CC does signed 213 // saturation and PACKLS_CC does unsigned saturation. 214 PACKS_CC, 215 PACKLS_CC, 216 217 // Unpack the first half of vector operand 0 into double-sized elements. 218 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 219 UNPACK_HIGH, 220 UNPACKL_HIGH, 221 222 // Likewise for the second half. 223 UNPACK_LOW, 224 UNPACKL_LOW, 225 226 // Shift each element of vector operand 0 by the number of bits specified 227 // by scalar operand 1. 228 VSHL_BY_SCALAR, 229 VSRL_BY_SCALAR, 230 VSRA_BY_SCALAR, 231 232 // For each element of the output type, sum across all sub-elements of 233 // operand 0 belonging to the corresponding element, and add in the 234 // rightmost sub-element of the corresponding element of operand 1. 235 VSUM, 236 237 // Compare integer vector operands 0 and 1 to produce the usual 0/-1 238 // vector result. VICMPE is for equality, VICMPH for "signed greater than" 239 // and VICMPHL for "unsigned greater than". 240 VICMPE, 241 VICMPH, 242 VICMPHL, 243 244 // Likewise, but also set the condition codes on the result. 245 VICMPES, 246 VICMPHS, 247 VICMPHLS, 248 249 // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1 250 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 251 // greater than" and VFCMPHE for "ordered and greater than or equal to". 252 VFCMPE, 253 VFCMPH, 254 VFCMPHE, 255 256 // Likewise, but also set the condition codes on the result. 257 VFCMPES, 258 VFCMPHS, 259 VFCMPHES, 260 261 // Test floating-point data class for vectors. 262 VFTCI, 263 264 // Extend the even f32 elements of vector operand 0 to produce a vector 265 // of f64 elements. 266 VEXTEND, 267 268 // Round the f64 elements of vector operand 0 to f32s and store them in the 269 // even elements of the result. 270 VROUND, 271 272 // AND the two vector operands together and set CC based on the result. 273 VTM, 274 275 // String operations that set CC as a side-effect. 276 VFAE_CC, 277 VFAEZ_CC, 278 VFEE_CC, 279 VFEEZ_CC, 280 VFENE_CC, 281 VFENEZ_CC, 282 VISTR_CC, 283 VSTRC_CC, 284 VSTRCZ_CC, 285 VSTRS_CC, 286 VSTRSZ_CC, 287 288 // Test Data Class. 289 // 290 // Operand 0: the value to test 291 // Operand 1: the bit mask 292 TDC, 293 294 // Strict variants of scalar floating-point comparisons. 295 // Quiet and signaling versions. 296 STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 297 STRICT_FCMPS, 298 299 // Strict variants of vector floating-point comparisons. 300 // Quiet and signaling versions. 301 STRICT_VFCMPE, 302 STRICT_VFCMPH, 303 STRICT_VFCMPHE, 304 STRICT_VFCMPES, 305 STRICT_VFCMPHS, 306 STRICT_VFCMPHES, 307 308 // Strict variants of VEXTEND and VROUND. 309 STRICT_VEXTEND, 310 STRICT_VROUND, 311 312 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 313 // ATOMIC_LOAD_<op>. 314 // 315 // Operand 0: the address of the containing 32-bit-aligned field 316 // Operand 1: the second operand of <op>, in the high bits of an i32 317 // for everything except ATOMIC_SWAPW 318 // Operand 2: how many bits to rotate the i32 left to bring the first 319 // operand into the high bits 320 // Operand 3: the negative of operand 2, for rotating the other way 321 // Operand 4: the width of the field in bits (8 or 16) 322 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 323 ATOMIC_LOADW_ADD, 324 ATOMIC_LOADW_SUB, 325 ATOMIC_LOADW_AND, 326 ATOMIC_LOADW_OR, 327 ATOMIC_LOADW_XOR, 328 ATOMIC_LOADW_NAND, 329 ATOMIC_LOADW_MIN, 330 ATOMIC_LOADW_MAX, 331 ATOMIC_LOADW_UMIN, 332 ATOMIC_LOADW_UMAX, 333 334 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 335 // 336 // Operand 0: the address of the containing 32-bit-aligned field 337 // Operand 1: the compare value, in the low bits of an i32 338 // Operand 2: the swap value, in the low bits of an i32 339 // Operand 3: how many bits to rotate the i32 left to bring the first 340 // operand into the high bits 341 // Operand 4: the negative of operand 2, for rotating the other way 342 // Operand 5: the width of the field in bits (8 or 16) 343 ATOMIC_CMP_SWAPW, 344 345 // Atomic compare-and-swap returning CC value. 346 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 347 ATOMIC_CMP_SWAP, 348 349 // 128-bit atomic load. 350 // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr) 351 ATOMIC_LOAD_128, 352 353 // 128-bit atomic store. 354 // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr) 355 ATOMIC_STORE_128, 356 357 // 128-bit atomic compare-and-swap. 358 // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 359 ATOMIC_CMP_SWAP_128, 360 361 // Byte swapping load/store. Same operands as regular load/store. 362 LRV, STRV, 363 364 // Element swapping load/store. Same operands as regular load/store. 365 VLER, VSTER, 366 367 // Prefetch from the second operand using the 4-bit control code in 368 // the first operand. The code is 1 for a load prefetch and 2 for 369 // a store prefetch. 370 PREFETCH 371 }; 372 373 // Return true if OPCODE is some kind of PC-relative address. 374 inline bool isPCREL(unsigned Opcode) { 375 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 376 } 377 } // end namespace SystemZISD 378 379 namespace SystemZICMP { 380 // Describes whether an integer comparison needs to be signed or unsigned, 381 // or whether either type is OK. 382 enum { 383 Any, 384 UnsignedOnly, 385 SignedOnly 386 }; 387 } // end namespace SystemZICMP 388 389 class SystemZSubtarget; 390 class SystemZTargetMachine; 391 392 class SystemZTargetLowering : public TargetLowering { 393 public: 394 explicit SystemZTargetLowering(const TargetMachine &TM, 395 const SystemZSubtarget &STI); 396 397 bool useSoftFloat() const override; 398 399 // Override TargetLowering. 400 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 401 return MVT::i32; 402 } 403 MVT getVectorIdxTy(const DataLayout &DL) const override { 404 // Only the lower 12 bits of an element index are used, so we don't 405 // want to clobber the upper 32 bits of a GPR unnecessarily. 406 return MVT::i32; 407 } 408 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) 409 const override { 410 // Widen subvectors to the full width rather than promoting integer 411 // elements. This is better because: 412 // 413 // (a) it means that we can handle the ABI for passing and returning 414 // sub-128 vectors without having to handle them as legal types. 415 // 416 // (b) we don't have instructions to extend on load and truncate on store, 417 // so promoting the integers is less efficient. 418 // 419 // (c) there are no multiplication instructions for the widest integer 420 // type (v2i64). 421 if (VT.getScalarSizeInBits() % 8 == 0) 422 return TypeWidenVector; 423 return TargetLoweringBase::getPreferredVectorAction(VT); 424 } 425 unsigned 426 getNumRegisters(LLVMContext &Context, EVT VT, 427 Optional<MVT> RegisterVT) const override { 428 // i128 inline assembly operand. 429 if (VT == MVT::i128 && 430 RegisterVT.hasValue() && RegisterVT.getValue() == MVT::Untyped) 431 return 1; 432 return TargetLowering::getNumRegisters(Context, VT); 433 } 434 bool isCheapToSpeculateCtlz() const override { return true; } 435 bool preferZeroCompareBranch() const override { return true; } 436 bool hasBitPreservingFPLogic(EVT VT) const override { 437 EVT ScVT = VT.getScalarType(); 438 return ScVT == MVT::f32 || ScVT == MVT::f64 || ScVT == MVT::f128; 439 } 440 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 441 EVT) const override; 442 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 443 EVT VT) const override; 444 bool isFPImmLegal(const APFloat &Imm, EVT VT, 445 bool ForCodeSize) const override; 446 bool hasInlineStackProbe(MachineFunction &MF) const override; 447 bool isLegalICmpImmediate(int64_t Imm) const override; 448 bool isLegalAddImmediate(int64_t Imm) const override; 449 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 450 unsigned AS, 451 Instruction *I = nullptr) const override; 452 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, 453 MachineMemOperand::Flags Flags, 454 bool *Fast) const override; 455 bool isTruncateFree(Type *, Type *) const override; 456 bool isTruncateFree(EVT, EVT) const override; 457 458 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 459 bool MathUsed) const override { 460 // Form add and sub with overflow intrinsics regardless of any extra 461 // users of the math result. 462 return VT == MVT::i32 || VT == MVT::i64; 463 } 464 465 const char *getTargetNodeName(unsigned Opcode) const override; 466 std::pair<unsigned, const TargetRegisterClass *> 467 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 468 StringRef Constraint, MVT VT) const override; 469 TargetLowering::ConstraintType 470 getConstraintType(StringRef Constraint) const override; 471 TargetLowering::ConstraintWeight 472 getSingleConstraintMatchWeight(AsmOperandInfo &info, 473 const char *constraint) const override; 474 void LowerAsmOperandForConstraint(SDValue Op, 475 std::string &Constraint, 476 std::vector<SDValue> &Ops, 477 SelectionDAG &DAG) const override; 478 479 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 480 if (ConstraintCode.size() == 1) { 481 switch(ConstraintCode[0]) { 482 default: 483 break; 484 case 'o': 485 return InlineAsm::Constraint_o; 486 case 'Q': 487 return InlineAsm::Constraint_Q; 488 case 'R': 489 return InlineAsm::Constraint_R; 490 case 'S': 491 return InlineAsm::Constraint_S; 492 case 'T': 493 return InlineAsm::Constraint_T; 494 } 495 } 496 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 497 } 498 499 Register getRegisterByName(const char *RegName, LLT VT, 500 const MachineFunction &MF) const override; 501 502 /// If a physical register, this returns the register that receives the 503 /// exception address on entry to an EH pad. 504 Register 505 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 506 return SystemZ::R6D; 507 } 508 509 /// If a physical register, this returns the register that receives the 510 /// exception typeid on entry to a landing pad. 511 Register 512 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 513 return SystemZ::R7D; 514 } 515 516 /// Override to support customized stack guard loading. 517 bool useLoadStackGuardNode() const override { 518 return true; 519 } 520 void insertSSPDeclarations(Module &M) const override { 521 } 522 523 MachineBasicBlock * 524 EmitInstrWithCustomInserter(MachineInstr &MI, 525 MachineBasicBlock *BB) const override; 526 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 527 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, 528 SelectionDAG &DAG) const override; 529 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 530 SelectionDAG &DAG) const override; 531 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 532 bool allowTruncateForTailCall(Type *, Type *) const override; 533 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 534 bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 535 SDValue Val, SDValue *Parts, 536 unsigned NumParts, MVT PartVT, 537 Optional<CallingConv::ID> CC) const override; 538 SDValue 539 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 540 const SDValue *Parts, unsigned NumParts, 541 MVT PartVT, EVT ValueVT, 542 Optional<CallingConv::ID> CC) const override; 543 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 544 bool isVarArg, 545 const SmallVectorImpl<ISD::InputArg> &Ins, 546 const SDLoc &DL, SelectionDAG &DAG, 547 SmallVectorImpl<SDValue> &InVals) const override; 548 SDValue LowerCall(CallLoweringInfo &CLI, 549 SmallVectorImpl<SDValue> &InVals) const override; 550 551 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 552 bool isVarArg, 553 const SmallVectorImpl<ISD::OutputArg> &Outs, 554 LLVMContext &Context) const override; 555 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 556 const SmallVectorImpl<ISD::OutputArg> &Outs, 557 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 558 SelectionDAG &DAG) const override; 559 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 560 561 /// Determine which of the bits specified in Mask are known to be either 562 /// zero or one and return them in the KnownZero/KnownOne bitsets. 563 void computeKnownBitsForTargetNode(const SDValue Op, 564 KnownBits &Known, 565 const APInt &DemandedElts, 566 const SelectionDAG &DAG, 567 unsigned Depth = 0) const override; 568 569 /// Determine the number of bits in the operation that are sign bits. 570 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 571 const APInt &DemandedElts, 572 const SelectionDAG &DAG, 573 unsigned Depth) const override; 574 575 ISD::NodeType getExtendForAtomicOps() const override { 576 return ISD::ANY_EXTEND; 577 } 578 ISD::NodeType getExtendForAtomicCmpSwapArg() const override { 579 return ISD::ZERO_EXTEND; 580 } 581 582 bool supportSwiftError() const override { 583 return true; 584 } 585 586 unsigned getStackProbeSize(MachineFunction &MF) const; 587 588 private: 589 const SystemZSubtarget &Subtarget; 590 591 // Implement LowerOperation for individual opcodes. 592 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, 593 const SDLoc &DL, EVT VT, 594 SDValue CmpOp0, SDValue CmpOp1, SDValue Chain) const; 595 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, 596 EVT VT, ISD::CondCode CC, 597 SDValue CmpOp0, SDValue CmpOp1, 598 SDValue Chain = SDValue(), 599 bool IsSignaling = false) const; 600 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 601 SDValue lowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG, 602 bool IsSignaling) const; 603 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 604 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 605 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 606 SelectionDAG &DAG) const; 607 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 608 SelectionDAG &DAG, unsigned Opcode, 609 SDValue GOTOffset) const; 610 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; 611 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 612 SelectionDAG &DAG) const; 613 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 614 SelectionDAG &DAG) const; 615 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 616 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 617 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 618 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 619 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 620 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 621 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 622 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 623 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 624 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 625 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 626 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 627 SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const; 628 SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const; 629 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 630 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 631 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 632 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 633 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 634 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 635 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 636 unsigned Opcode) const; 637 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 638 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 639 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 640 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 641 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 642 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 643 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 644 bool isVectorElementLoad(SDValue Op) const; 645 SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, 646 SmallVectorImpl<SDValue> &Elems) const; 647 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 648 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 649 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 650 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 651 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 652 SDValue lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 653 SDValue lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 654 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 655 656 bool canTreatAsByteVector(EVT VT) const; 657 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 658 unsigned Index, DAGCombinerInfo &DCI, 659 bool Force) const; 660 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op, 661 DAGCombinerInfo &DCI) const; 662 SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 663 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 664 SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const; 665 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const; 666 bool canLoadStoreByteSwapped(EVT VT) const; 667 SDValue combineLOAD(SDNode *N, DAGCombinerInfo &DCI) const; 668 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const; 669 SDValue combineVECTOR_SHUFFLE(SDNode *N, DAGCombinerInfo &DCI) const; 670 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const; 671 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const; 672 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const; 673 SDValue combineFP_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 674 SDValue combineINT_TO_FP(SDNode *N, DAGCombinerInfo &DCI) const; 675 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const; 676 SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 677 SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 678 SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const; 679 SDValue combineIntDIVREM(SDNode *N, DAGCombinerInfo &DCI) const; 680 SDValue combineINTRINSIC(SDNode *N, DAGCombinerInfo &DCI) const; 681 682 SDValue unwrapAddress(SDValue N) const override; 683 684 // If the last instruction before MBBI in MBB was some form of COMPARE, 685 // try to replace it with a COMPARE AND BRANCH just before MBBI. 686 // CCMask and Target are the BRC-like operands for the branch. 687 // Return true if the change was made. 688 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 689 MachineBasicBlock::iterator MBBI, 690 unsigned CCMask, 691 MachineBasicBlock *Target) const; 692 693 // Implement EmitInstrWithCustomInserter for individual operation types. 694 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const; 695 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, 696 unsigned StoreOpcode, unsigned STOCOpcode, 697 bool Invert) const; 698 MachineBasicBlock *emitPair128(MachineInstr &MI, 699 MachineBasicBlock *MBB) const; 700 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, 701 bool ClearEven) const; 702 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, 703 MachineBasicBlock *BB, 704 unsigned BinOpcode, unsigned BitSize, 705 bool Invert = false) const; 706 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, 707 MachineBasicBlock *MBB, 708 unsigned CompareOpcode, 709 unsigned KeepOldMask, 710 unsigned BitSize) const; 711 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, 712 MachineBasicBlock *BB) const; 713 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, 714 unsigned Opcode) const; 715 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, 716 unsigned Opcode) const; 717 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, 718 MachineBasicBlock *MBB, 719 unsigned Opcode, bool NoFloat) const; 720 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, 721 MachineBasicBlock *MBB, 722 unsigned Opcode) const; 723 MachineBasicBlock *emitProbedAlloca(MachineInstr &MI, 724 MachineBasicBlock *MBB) const; 725 726 SDValue getBackchainAddress(SDValue SP, SelectionDAG &DAG) const; 727 728 MachineMemOperand::Flags 729 getTargetMMOFlags(const Instruction &I) const override; 730 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 731 }; 732 733 struct SystemZVectorConstantInfo { 734 private: 735 APInt IntBits; // The 128 bits as an integer. 736 APInt SplatBits; // Smallest splat value. 737 APInt SplatUndef; // Bits correspoding to undef operands of the BVN. 738 unsigned SplatBitSize = 0; 739 bool isFP128 = false; 740 741 public: 742 unsigned Opcode = 0; 743 SmallVector<unsigned, 2> OpVals; 744 MVT VecVT; 745 SystemZVectorConstantInfo(APFloat FPImm); 746 SystemZVectorConstantInfo(BuildVectorSDNode *BVN); 747 bool isVectorConstantLegal(const SystemZSubtarget &Subtarget); 748 }; 749 750 } // end namespace llvm 751 752 #endif 753