1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17 
18 #include "SystemZ.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
26   FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 
28   // Return with a flag operand.  Operand 0 is the chain operand.
29   RET_FLAG,
30 
31   // Calls a function.  Operand 0 is the chain operand and operand 1
32   // is the target address.  The arguments start at operand 2.
33   // There is an optional glue operand at the end.
34   CALL,
35   SIBCALL,
36 
37   // TLS calls.  Like regular calls, except operand 1 is the TLS symbol.
38   // (The call target is implicitly __tls_get_offset.)
39   TLS_GDCALL,
40   TLS_LDCALL,
41 
42   // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43   // accesses (LARL).  Operand 0 is the address.
44   PCREL_WRAPPER,
45 
46   // Used in cases where an offset is applied to a TargetGlobalAddress.
47   // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48   // PCREL_WRAPPER for an anchor point.  This is used so that we can
49   // cheaply refer to either the full address or the anchor point
50   // as a register base.
51   PCREL_OFFSET,
52 
53   // Integer absolute.
54   IABS,
55 
56   // Integer comparisons.  There are three operands: the two values
57   // to compare, and an integer of type SystemZICMP.
58   ICMP,
59 
60   // Floating-point comparisons.  The two operands are the values to compare.
61   FCMP,
62 
63   // Test under mask.  The first operand is ANDed with the second operand
64   // and the condition codes are set on the result.  The third operand is
65   // a boolean that is true if the condition codes need to distinguish
66   // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67   // register forms do but the memory forms don't).
68   TM,
69 
70   // Branches if a condition is true.  Operand 0 is the chain operand;
71   // operand 1 is the 4-bit condition-code mask, with bit N in
72   // big-endian order meaning "branch if CC=N"; operand 2 is the
73   // target block and operand 3 is the flag operand.
74   BR_CCMASK,
75 
76   // Selects between operand 0 and operand 1.  Operand 2 is the
77   // mask of condition-code values for which operand 0 should be
78   // chosen over operand 1; it has the same form as BR_CCMASK.
79   // Operand 3 is the flag operand.
80   SELECT_CCMASK,
81 
82   // Evaluates to the gap between the stack pointer and the
83   // base of the dynamically-allocatable area.
84   ADJDYNALLOC,
85 
86   // Count number of bits set in operand 0 per byte.
87   POPCNT,
88 
89   // Wrappers around the ISD opcodes of the same name.  The output and
90   // first input operands are GR128s.  The trailing numbers are the
91   // widths of the second operand in bits.
92   UMUL_LOHI64,
93   SDIVREM32,
94   SDIVREM64,
95   UDIVREM32,
96   UDIVREM64,
97 
98   // Use a series of MVCs to copy bytes from one memory location to another.
99   // The operands are:
100   // - the target address
101   // - the source address
102   // - the constant length
103   //
104   // This isn't a memory opcode because we'd need to attach two
105   // MachineMemOperands rather than one.
106   MVC,
107 
108   // Like MVC, but implemented as a loop that handles X*256 bytes
109   // followed by straight-line code to handle the rest (if any).
110   // The value of X is passed as an additional operand.
111   MVC_LOOP,
112 
113   // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
114   NC,
115   NC_LOOP,
116   OC,
117   OC_LOOP,
118   XC,
119   XC_LOOP,
120 
121   // Use CLC to compare two blocks of memory, with the same comments
122   // as for MVC and MVC_LOOP.
123   CLC,
124   CLC_LOOP,
125 
126   // Use an MVST-based sequence to implement stpcpy().
127   STPCPY,
128 
129   // Use a CLST-based sequence to implement strcmp().  The two input operands
130   // are the addresses of the strings to compare.
131   STRCMP,
132 
133   // Use an SRST-based sequence to search a block of memory.  The first
134   // operand is the end address, the second is the start, and the third
135   // is the character to search for.  CC is set to 1 on success and 2
136   // on failure.
137   SEARCH_STRING,
138 
139   // Store the CC value in bits 29 and 28 of an integer.
140   IPM,
141 
142   // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
143   SERIALIZE,
144 
145   // Compiler barrier only; generate a no-op.
146   MEMBARRIER,
147 
148   // Transaction begin.  The first operand is the chain, the second
149   // the TDB pointer, and the third the immediate control field.
150   // Returns chain and glue.
151   TBEGIN,
152   TBEGIN_NOFLOAT,
153 
154   // Transaction end.  Just the chain operand.  Returns chain and glue.
155   TEND,
156 
157   // Create a vector constant by filling byte N of the result with bit
158   // 15-N of the single operand.
159   BYTE_MASK,
160 
161   // Create a vector constant by replicating an element-sized RISBG-style mask.
162   // The first operand specifies the starting set bit and the second operand
163   // specifies the ending set bit.  Both operands count from the MSB of the
164   // element.
165   ROTATE_MASK,
166 
167   // Replicate a GPR scalar value into all elements of a vector.
168   REPLICATE,
169 
170   // Create a vector from two i64 GPRs.
171   JOIN_DWORDS,
172 
173   // Replicate one element of a vector into all elements.  The first operand
174   // is the vector and the second is the index of the element to replicate.
175   SPLAT,
176 
177   // Interleave elements from the high half of operand 0 and the high half
178   // of operand 1.
179   MERGE_HIGH,
180 
181   // Likewise for the low halves.
182   MERGE_LOW,
183 
184   // Concatenate the vectors in the first two operands, shift them left
185   // by the third operand, and take the first half of the result.
186   SHL_DOUBLE,
187 
188   // Take one element of the first v2i64 operand and the one element of
189   // the second v2i64 operand and concatenate them to form a v2i64 result.
190   // The third operand is a 4-bit value of the form 0A0B, where A and B
191   // are the element selectors for the first operand and second operands
192   // respectively.
193   PERMUTE_DWORDS,
194 
195   // Perform a general vector permute on vector operands 0 and 1.
196   // Each byte of operand 2 controls the corresponding byte of the result,
197   // in the same way as a byte-level VECTOR_SHUFFLE mask.
198   PERMUTE,
199 
200   // Pack vector operands 0 and 1 into a single vector with half-sized elements.
201   PACK,
202 
203   // Likewise, but saturate the result and set CC.  PACKS_CC does signed
204   // saturation and PACKLS_CC does unsigned saturation.
205   PACKS_CC,
206   PACKLS_CC,
207 
208   // Unpack the first half of vector operand 0 into double-sized elements.
209   // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
210   UNPACK_HIGH,
211   UNPACKL_HIGH,
212 
213   // Likewise for the second half.
214   UNPACK_LOW,
215   UNPACKL_LOW,
216 
217   // Shift each element of vector operand 0 by the number of bits specified
218   // by scalar operand 1.
219   VSHL_BY_SCALAR,
220   VSRL_BY_SCALAR,
221   VSRA_BY_SCALAR,
222 
223   // For each element of the output type, sum across all sub-elements of
224   // operand 0 belonging to the corresponding element, and add in the
225   // rightmost sub-element of the corresponding element of operand 1.
226   VSUM,
227 
228   // Compare integer vector operands 0 and 1 to produce the usual 0/-1
229   // vector result.  VICMPE is for equality, VICMPH for "signed greater than"
230   // and VICMPHL for "unsigned greater than".
231   VICMPE,
232   VICMPH,
233   VICMPHL,
234 
235   // Likewise, but also set the condition codes on the result.
236   VICMPES,
237   VICMPHS,
238   VICMPHLS,
239 
240   // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
241   // vector result.  VFCMPE is for "ordered and equal", VFCMPH for "ordered and
242   // greater than" and VFCMPHE for "ordered and greater than or equal to".
243   VFCMPE,
244   VFCMPH,
245   VFCMPHE,
246 
247   // Likewise, but also set the condition codes on the result.
248   VFCMPES,
249   VFCMPHS,
250   VFCMPHES,
251 
252   // Test floating-point data class for vectors.
253   VFTCI,
254 
255   // Extend the even f32 elements of vector operand 0 to produce a vector
256   // of f64 elements.
257   VEXTEND,
258 
259   // Round the f64 elements of vector operand 0 to f32s and store them in the
260   // even elements of the result.
261   VROUND,
262 
263   // AND the two vector operands together and set CC based on the result.
264   VTM,
265 
266   // String operations that set CC as a side-effect.
267   VFAE_CC,
268   VFAEZ_CC,
269   VFEE_CC,
270   VFEEZ_CC,
271   VFENE_CC,
272   VFENEZ_CC,
273   VISTR_CC,
274   VSTRC_CC,
275   VSTRCZ_CC,
276 
277   // Test Data Class.
278   //
279   // Operand 0: the value to test
280   // Operand 1: the bit mask
281   TDC,
282 
283   // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
284   // ATOMIC_LOAD_<op>.
285   //
286   // Operand 0: the address of the containing 32-bit-aligned field
287   // Operand 1: the second operand of <op>, in the high bits of an i32
288   //            for everything except ATOMIC_SWAPW
289   // Operand 2: how many bits to rotate the i32 left to bring the first
290   //            operand into the high bits
291   // Operand 3: the negative of operand 2, for rotating the other way
292   // Operand 4: the width of the field in bits (8 or 16)
293   ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
294   ATOMIC_LOADW_ADD,
295   ATOMIC_LOADW_SUB,
296   ATOMIC_LOADW_AND,
297   ATOMIC_LOADW_OR,
298   ATOMIC_LOADW_XOR,
299   ATOMIC_LOADW_NAND,
300   ATOMIC_LOADW_MIN,
301   ATOMIC_LOADW_MAX,
302   ATOMIC_LOADW_UMIN,
303   ATOMIC_LOADW_UMAX,
304 
305   // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
306   //
307   // Operand 0: the address of the containing 32-bit-aligned field
308   // Operand 1: the compare value, in the low bits of an i32
309   // Operand 2: the swap value, in the low bits of an i32
310   // Operand 3: how many bits to rotate the i32 left to bring the first
311   //            operand into the high bits
312   // Operand 4: the negative of operand 2, for rotating the other way
313   // Operand 5: the width of the field in bits (8 or 16)
314   ATOMIC_CMP_SWAPW,
315 
316   // Byte swapping load.
317   //
318   // Operand 0: the address to load from
319   // Operand 1: the type of load (i16, i32, i64)
320   LRV,
321 
322   // Byte swapping store.
323   //
324   // Operand 0: the value to store
325   // Operand 1: the address to store to
326   // Operand 2: the type of store (i16, i32, i64)
327   STRV,
328 
329   // Prefetch from the second operand using the 4-bit control code in
330   // the first operand.  The code is 1 for a load prefetch and 2 for
331   // a store prefetch.
332   PREFETCH
333 };
334 
335 // Return true if OPCODE is some kind of PC-relative address.
336 inline bool isPCREL(unsigned Opcode) {
337   return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
338 }
339 } // end namespace SystemZISD
340 
341 namespace SystemZICMP {
342 // Describes whether an integer comparison needs to be signed or unsigned,
343 // or whether either type is OK.
344 enum {
345   Any,
346   UnsignedOnly,
347   SignedOnly
348 };
349 } // end namespace SystemZICMP
350 
351 class SystemZSubtarget;
352 class SystemZTargetMachine;
353 
354 class SystemZTargetLowering : public TargetLowering {
355 public:
356   explicit SystemZTargetLowering(const TargetMachine &TM,
357                                  const SystemZSubtarget &STI);
358 
359   // Override TargetLowering.
360   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
361     return MVT::i32;
362   }
363   MVT getVectorIdxTy(const DataLayout &DL) const override {
364     // Only the lower 12 bits of an element index are used, so we don't
365     // want to clobber the upper 32 bits of a GPR unnecessarily.
366     return MVT::i32;
367   }
368   TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
369     const override {
370     // Widen subvectors to the full width rather than promoting integer
371     // elements.  This is better because:
372     //
373     // (a) it means that we can handle the ABI for passing and returning
374     //     sub-128 vectors without having to handle them as legal types.
375     //
376     // (b) we don't have instructions to extend on load and truncate on store,
377     //     so promoting the integers is less efficient.
378     //
379     // (c) there are no multiplication instructions for the widest integer
380     //     type (v2i64).
381     if (VT.getScalarSizeInBits() % 8 == 0)
382       return TypeWidenVector;
383     return TargetLoweringBase::getPreferredVectorAction(VT);
384   }
385   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
386                          EVT) const override;
387   bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
388   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
389   bool isLegalICmpImmediate(int64_t Imm) const override;
390   bool isLegalAddImmediate(int64_t Imm) const override;
391   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
392                              unsigned AS) const override;
393   bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override;
394   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
395                                       unsigned Align,
396                                       bool *Fast) const override;
397   bool isTruncateFree(Type *, Type *) const override;
398   bool isTruncateFree(EVT, EVT) const override;
399   const char *getTargetNodeName(unsigned Opcode) const override;
400   std::pair<unsigned, const TargetRegisterClass *>
401   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
402                                StringRef Constraint, MVT VT) const override;
403   TargetLowering::ConstraintType
404   getConstraintType(StringRef Constraint) const override;
405   TargetLowering::ConstraintWeight
406     getSingleConstraintMatchWeight(AsmOperandInfo &info,
407                                    const char *constraint) const override;
408   void LowerAsmOperandForConstraint(SDValue Op,
409                                     std::string &Constraint,
410                                     std::vector<SDValue> &Ops,
411                                     SelectionDAG &DAG) const override;
412 
413   unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
414     if (ConstraintCode.size() == 1) {
415       switch(ConstraintCode[0]) {
416       default:
417         break;
418       case 'Q':
419         return InlineAsm::Constraint_Q;
420       case 'R':
421         return InlineAsm::Constraint_R;
422       case 'S':
423         return InlineAsm::Constraint_S;
424       case 'T':
425         return InlineAsm::Constraint_T;
426       }
427     }
428     return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
429   }
430 
431   /// If a physical register, this returns the register that receives the
432   /// exception address on entry to an EH pad.
433   unsigned
434   getExceptionPointerRegister(const Constant *PersonalityFn) const override {
435     return SystemZ::R6D;
436   }
437 
438   /// If a physical register, this returns the register that receives the
439   /// exception typeid on entry to a landing pad.
440   unsigned
441   getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
442     return SystemZ::R7D;
443   }
444 
445   /// Override to support customized stack guard loading.
446   bool useLoadStackGuardNode() const override {
447     return true;
448   }
449   void insertSSPDeclarations(Module &M) const override {
450   }
451 
452   MachineBasicBlock *
453   EmitInstrWithCustomInserter(MachineInstr &MI,
454                               MachineBasicBlock *BB) const override;
455   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
456   bool allowTruncateForTailCall(Type *, Type *) const override;
457   bool mayBeEmittedAsTailCall(CallInst *CI) const override;
458   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
459                                bool isVarArg,
460                                const SmallVectorImpl<ISD::InputArg> &Ins,
461                                const SDLoc &DL, SelectionDAG &DAG,
462                                SmallVectorImpl<SDValue> &InVals) const override;
463   SDValue LowerCall(CallLoweringInfo &CLI,
464                     SmallVectorImpl<SDValue> &InVals) const override;
465 
466   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
467                       bool isVarArg,
468                       const SmallVectorImpl<ISD::OutputArg> &Outs,
469                       LLVMContext &Context) const override;
470   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
471                       const SmallVectorImpl<ISD::OutputArg> &Outs,
472                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
473                       SelectionDAG &DAG) const override;
474   SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
475                                       SelectionDAG &DAG) const override;
476   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
477 
478   ISD::NodeType getExtendForAtomicOps() const override {
479     return ISD::ANY_EXTEND;
480   }
481 
482   bool supportSwiftError() const override {
483     return true;
484   }
485 
486 private:
487   const SystemZSubtarget &Subtarget;
488 
489   // Implement LowerOperation for individual opcodes.
490   SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
491   SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
492   SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
493   SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
494                              SelectionDAG &DAG) const;
495   SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
496                             SelectionDAG &DAG, unsigned Opcode,
497                             SDValue GOTOffset) const;
498   SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
499   SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
500                                 SelectionDAG &DAG) const;
501   SDValue lowerBlockAddress(BlockAddressSDNode *Node,
502                             SelectionDAG &DAG) const;
503   SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
504   SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
505   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
506   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
507   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
508   SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
509   SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
510   SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
511   SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
512   SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
513   SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
514   SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
515   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
516   SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
517   SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
518   SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
519   SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
520   SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
521   SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
522                               unsigned Opcode) const;
523   SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
524   SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
525   SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
526   SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
527   SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
528   SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
529   SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
530   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
531   SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
532   SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
533   SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
534   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
535   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
536   SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
537                                  unsigned UnpackHigh) const;
538   SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
539 
540   SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
541                          unsigned Index, DAGCombinerInfo &DCI,
542                          bool Force) const;
543   SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
544                                  DAGCombinerInfo &DCI) const;
545   SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
546   SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
547   SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
548   SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
549   SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
550   SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
551   SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
552   SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const;
553 
554   // If the last instruction before MBBI in MBB was some form of COMPARE,
555   // try to replace it with a COMPARE AND BRANCH just before MBBI.
556   // CCMask and Target are the BRC-like operands for the branch.
557   // Return true if the change was made.
558   bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
559                                   MachineBasicBlock::iterator MBBI,
560                                   unsigned CCMask,
561                                   MachineBasicBlock *Target) const;
562 
563   // Implement EmitInstrWithCustomInserter for individual operation types.
564   MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB,
565                                 unsigned LOCROpcode) const;
566   MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
567                                    unsigned StoreOpcode, unsigned STOCOpcode,
568                                    bool Invert) const;
569   MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
570                                 bool ClearEven, unsigned SubReg) const;
571   MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
572                                           MachineBasicBlock *BB,
573                                           unsigned BinOpcode, unsigned BitSize,
574                                           bool Invert = false) const;
575   MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
576                                           MachineBasicBlock *MBB,
577                                           unsigned CompareOpcode,
578                                           unsigned KeepOldMask,
579                                           unsigned BitSize) const;
580   MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
581                                         MachineBasicBlock *BB) const;
582   MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
583                                        unsigned Opcode) const;
584   MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
585                                        unsigned Opcode) const;
586   MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
587                                           MachineBasicBlock *MBB,
588                                           unsigned Opcode, bool NoFloat) const;
589   MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
590                                          MachineBasicBlock *MBB,
591                                          unsigned Opcode) const;
592 };
593 } // end namespace llvm
594 
595 #endif
596