1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCInstBuilder.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 // Return true if Expr is in the range [MinValue, MaxValue].
25 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
26   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
27     int64_t Value = CE->getValue();
28     return Value >= MinValue && Value <= MaxValue;
29   }
30   return false;
31 }
32 
33 namespace {
34 enum RegisterKind {
35   GR32Reg,
36   GRH32Reg,
37   GR64Reg,
38   GR128Reg,
39   ADDR32Reg,
40   ADDR64Reg,
41   FP32Reg,
42   FP64Reg,
43   FP128Reg,
44   VR32Reg,
45   VR64Reg,
46   VR128Reg,
47   AR32Reg,
48 };
49 
50 enum MemoryKind {
51   BDMem,
52   BDXMem,
53   BDLMem,
54   BDRMem,
55   BDVMem
56 };
57 
58 class SystemZOperand : public MCParsedAsmOperand {
59 public:
60 private:
61   enum OperandKind {
62     KindInvalid,
63     KindToken,
64     KindReg,
65     KindImm,
66     KindImmTLS,
67     KindMem
68   };
69 
70   OperandKind Kind;
71   SMLoc StartLoc, EndLoc;
72 
73   // A string of length Length, starting at Data.
74   struct TokenOp {
75     const char *Data;
76     unsigned Length;
77   };
78 
79   // LLVM register Num, which has kind Kind.  In some ways it might be
80   // easier for this class to have a register bank (general, floating-point
81   // or access) and a raw register number (0-15).  This would postpone the
82   // interpretation of the operand to the add*() methods and avoid the need
83   // for context-dependent parsing.  However, we do things the current way
84   // because of the virtual getReg() method, which needs to distinguish
85   // between (say) %r0 used as a single register and %r0 used as a pair.
86   // Context-dependent parsing can also give us slightly better error
87   // messages when invalid pairs like %r1 are used.
88   struct RegOp {
89     RegisterKind Kind;
90     unsigned Num;
91   };
92 
93   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
94   // MemKind says what type of memory this is and RegKind says what type
95   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
96   // length for D(L,B)-style operands, otherwise it is null.
97   struct MemOp {
98     unsigned Base : 12;
99     unsigned Index : 12;
100     unsigned MemKind : 4;
101     unsigned RegKind : 4;
102     const MCExpr *Disp;
103     union {
104       const MCExpr *Imm;
105       unsigned Reg;
106     } Length;
107   };
108 
109   // Imm is an immediate operand, and Sym is an optional TLS symbol
110   // for use with a __tls_get_offset marker relocation.
111   struct ImmTLSOp {
112     const MCExpr *Imm;
113     const MCExpr *Sym;
114   };
115 
116   union {
117     TokenOp Token;
118     RegOp Reg;
119     const MCExpr *Imm;
120     ImmTLSOp ImmTLS;
121     MemOp Mem;
122   };
123 
124   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
125     // Add as immediates when possible.  Null MCExpr = 0.
126     if (!Expr)
127       Inst.addOperand(MCOperand::createImm(0));
128     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
129       Inst.addOperand(MCOperand::createImm(CE->getValue()));
130     else
131       Inst.addOperand(MCOperand::createExpr(Expr));
132   }
133 
134 public:
135   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
136       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
137 
138   // Create particular kinds of operand.
139   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
140                                                        SMLoc EndLoc) {
141     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
142   }
143   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
144     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
145     Op->Token.Data = Str.data();
146     Op->Token.Length = Str.size();
147     return Op;
148   }
149   static std::unique_ptr<SystemZOperand>
150   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
151     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
152     Op->Reg.Kind = Kind;
153     Op->Reg.Num = Num;
154     return Op;
155   }
156   static std::unique_ptr<SystemZOperand>
157   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
158     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
159     Op->Imm = Expr;
160     return Op;
161   }
162   static std::unique_ptr<SystemZOperand>
163   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
164             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
165             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
166     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
167     Op->Mem.MemKind = MemKind;
168     Op->Mem.RegKind = RegKind;
169     Op->Mem.Base = Base;
170     Op->Mem.Index = Index;
171     Op->Mem.Disp = Disp;
172     if (MemKind == BDLMem)
173       Op->Mem.Length.Imm = LengthImm;
174     if (MemKind == BDRMem)
175       Op->Mem.Length.Reg = LengthReg;
176     return Op;
177   }
178   static std::unique_ptr<SystemZOperand>
179   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
180                SMLoc StartLoc, SMLoc EndLoc) {
181     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
182     Op->ImmTLS.Imm = Imm;
183     Op->ImmTLS.Sym = Sym;
184     return Op;
185   }
186 
187   // Token operands
188   bool isToken() const override {
189     return Kind == KindToken;
190   }
191   StringRef getToken() const {
192     assert(Kind == KindToken && "Not a token");
193     return StringRef(Token.Data, Token.Length);
194   }
195 
196   // Register operands.
197   bool isReg() const override {
198     return Kind == KindReg;
199   }
200   bool isReg(RegisterKind RegKind) const {
201     return Kind == KindReg && Reg.Kind == RegKind;
202   }
203   unsigned getReg() const override {
204     assert(Kind == KindReg && "Not a register");
205     return Reg.Num;
206   }
207 
208   // Immediate operands.
209   bool isImm() const override {
210     return Kind == KindImm;
211   }
212   bool isImm(int64_t MinValue, int64_t MaxValue) const {
213     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
214   }
215   const MCExpr *getImm() const {
216     assert(Kind == KindImm && "Not an immediate");
217     return Imm;
218   }
219 
220   // Immediate operands with optional TLS symbol.
221   bool isImmTLS() const {
222     return Kind == KindImmTLS;
223   }
224 
225   // Memory operands.
226   bool isMem() const override {
227     return Kind == KindMem;
228   }
229   bool isMem(MemoryKind MemKind) const {
230     return (Kind == KindMem &&
231             (Mem.MemKind == MemKind ||
232              // A BDMem can be treated as a BDXMem in which the index
233              // register field is 0.
234              (Mem.MemKind == BDMem && MemKind == BDXMem)));
235   }
236   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
237     return isMem(MemKind) && Mem.RegKind == RegKind;
238   }
239   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
240     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
241   }
242   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
243     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
244   }
245   bool isMemDisp12Len8(RegisterKind RegKind) const {
246     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
247   }
248 
249   // Override MCParsedAsmOperand.
250   SMLoc getStartLoc() const override { return StartLoc; }
251   SMLoc getEndLoc() const override { return EndLoc; }
252   void print(raw_ostream &OS) const override;
253 
254   // Used by the TableGen code to add particular types of operand
255   // to an instruction.
256   void addRegOperands(MCInst &Inst, unsigned N) const {
257     assert(N == 1 && "Invalid number of operands");
258     Inst.addOperand(MCOperand::createReg(getReg()));
259   }
260   void addImmOperands(MCInst &Inst, unsigned N) const {
261     assert(N == 1 && "Invalid number of operands");
262     addExpr(Inst, getImm());
263   }
264   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
265     assert(N == 2 && "Invalid number of operands");
266     assert(isMem(BDMem) && "Invalid operand type");
267     Inst.addOperand(MCOperand::createReg(Mem.Base));
268     addExpr(Inst, Mem.Disp);
269   }
270   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
271     assert(N == 3 && "Invalid number of operands");
272     assert(isMem(BDXMem) && "Invalid operand type");
273     Inst.addOperand(MCOperand::createReg(Mem.Base));
274     addExpr(Inst, Mem.Disp);
275     Inst.addOperand(MCOperand::createReg(Mem.Index));
276   }
277   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
278     assert(N == 3 && "Invalid number of operands");
279     assert(isMem(BDLMem) && "Invalid operand type");
280     Inst.addOperand(MCOperand::createReg(Mem.Base));
281     addExpr(Inst, Mem.Disp);
282     addExpr(Inst, Mem.Length.Imm);
283   }
284   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
285     assert(N == 3 && "Invalid number of operands");
286     assert(isMem(BDRMem) && "Invalid operand type");
287     Inst.addOperand(MCOperand::createReg(Mem.Base));
288     addExpr(Inst, Mem.Disp);
289     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
290   }
291   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
292     assert(N == 3 && "Invalid number of operands");
293     assert(isMem(BDVMem) && "Invalid operand type");
294     Inst.addOperand(MCOperand::createReg(Mem.Base));
295     addExpr(Inst, Mem.Disp);
296     Inst.addOperand(MCOperand::createReg(Mem.Index));
297   }
298   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
299     assert(N == 2 && "Invalid number of operands");
300     assert(Kind == KindImmTLS && "Invalid operand type");
301     addExpr(Inst, ImmTLS.Imm);
302     if (ImmTLS.Sym)
303       addExpr(Inst, ImmTLS.Sym);
304   }
305 
306   // Used by the TableGen code to check for particular operand types.
307   bool isGR32() const { return isReg(GR32Reg); }
308   bool isGRH32() const { return isReg(GRH32Reg); }
309   bool isGRX32() const { return false; }
310   bool isGR64() const { return isReg(GR64Reg); }
311   bool isGR128() const { return isReg(GR128Reg); }
312   bool isADDR32() const { return isReg(ADDR32Reg); }
313   bool isADDR64() const { return isReg(ADDR64Reg); }
314   bool isADDR128() const { return false; }
315   bool isFP32() const { return isReg(FP32Reg); }
316   bool isFP64() const { return isReg(FP64Reg); }
317   bool isFP128() const { return isReg(FP128Reg); }
318   bool isVR32() const { return isReg(VR32Reg); }
319   bool isVR64() const { return isReg(VR64Reg); }
320   bool isVF128() const { return false; }
321   bool isVR128() const { return isReg(VR128Reg); }
322   bool isAR32() const { return isReg(AR32Reg); }
323   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
324   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
325   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
326   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
327   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
328   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
329   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
330   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
331   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
332   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
333   bool isU1Imm() const { return isImm(0, 1); }
334   bool isU2Imm() const { return isImm(0, 3); }
335   bool isU3Imm() const { return isImm(0, 7); }
336   bool isU4Imm() const { return isImm(0, 15); }
337   bool isU6Imm() const { return isImm(0, 63); }
338   bool isU8Imm() const { return isImm(0, 255); }
339   bool isS8Imm() const { return isImm(-128, 127); }
340   bool isU12Imm() const { return isImm(0, 4095); }
341   bool isU16Imm() const { return isImm(0, 65535); }
342   bool isS16Imm() const { return isImm(-32768, 32767); }
343   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
344   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
345   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
346 };
347 
348 class SystemZAsmParser : public MCTargetAsmParser {
349 #define GET_ASSEMBLER_HEADER
350 #include "SystemZGenAsmMatcher.inc"
351 
352 private:
353   MCAsmParser &Parser;
354   enum RegisterGroup {
355     RegGR,
356     RegFP,
357     RegV,
358     RegAR
359   };
360   struct Register {
361     RegisterGroup Group;
362     unsigned Num;
363     SMLoc StartLoc, EndLoc;
364   };
365 
366   bool parseRegister(Register &Reg);
367 
368   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
369                      bool IsAddress = false);
370 
371   OperandMatchResultTy parseRegister(OperandVector &Operands,
372                                      RegisterGroup Group, const unsigned *Regs,
373                                      RegisterKind Kind);
374 
375   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
376 
377   bool parseAddress(bool &HaveReg1, Register &Reg1,
378                     bool &HaveReg2, Register &Reg2,
379                     const MCExpr *&Disp, const MCExpr *&Length);
380   bool parseAddressRegister(Register &Reg);
381 
382   bool ParseDirectiveInsn(SMLoc L);
383 
384   OperandMatchResultTy parseAddress(OperandVector &Operands,
385                                     MemoryKind MemKind, const unsigned *Regs,
386                                     RegisterKind RegKind);
387 
388   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
389                                   int64_t MaxVal, bool AllowTLS);
390 
391   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
392 
393 public:
394   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
395                    const MCInstrInfo &MII,
396                    const MCTargetOptions &Options)
397     : MCTargetAsmParser(Options, sti), Parser(parser) {
398     MCAsmParserExtension::Initialize(Parser);
399 
400     // Alias the .word directive to .short.
401     parser.addAliasForDirective(".word", ".short");
402 
403     // Initialize the set of available features.
404     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
405   }
406 
407   // Override MCTargetAsmParser.
408   bool ParseDirective(AsmToken DirectiveID) override;
409   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
410   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
411                         SMLoc NameLoc, OperandVector &Operands) override;
412   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
413                                OperandVector &Operands, MCStreamer &Out,
414                                uint64_t &ErrorInfo,
415                                bool MatchingInlineAsm) override;
416 
417   // Used by the TableGen code to parse particular operand types.
418   OperandMatchResultTy parseGR32(OperandVector &Operands) {
419     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
420   }
421   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
422     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
423   }
424   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
425     llvm_unreachable("GRX32 should only be used for pseudo instructions");
426   }
427   OperandMatchResultTy parseGR64(OperandVector &Operands) {
428     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
429   }
430   OperandMatchResultTy parseGR128(OperandVector &Operands) {
431     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
432   }
433   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
434     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
435   }
436   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
437     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
438   }
439   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
440     llvm_unreachable("Shouldn't be used as an operand");
441   }
442   OperandMatchResultTy parseFP32(OperandVector &Operands) {
443     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
444   }
445   OperandMatchResultTy parseFP64(OperandVector &Operands) {
446     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
447   }
448   OperandMatchResultTy parseFP128(OperandVector &Operands) {
449     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
450   }
451   OperandMatchResultTy parseVR32(OperandVector &Operands) {
452     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
453   }
454   OperandMatchResultTy parseVR64(OperandVector &Operands) {
455     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
456   }
457   OperandMatchResultTy parseVF128(OperandVector &Operands) {
458     llvm_unreachable("Shouldn't be used as an operand");
459   }
460   OperandMatchResultTy parseVR128(OperandVector &Operands) {
461     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
462   }
463   OperandMatchResultTy parseAR32(OperandVector &Operands) {
464     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
465   }
466   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
467     return parseAnyRegister(Operands);
468   }
469   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
470     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
471   }
472   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
473     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
474   }
475   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
476     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
477   }
478   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
479     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
480   }
481   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
482     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
483   }
484   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
485     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
486   }
487   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
488     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
489   }
490   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
491     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
492   }
493   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
494     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
495   }
496   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
497     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
498   }
499 };
500 } // end anonymous namespace
501 
502 #define GET_REGISTER_MATCHER
503 #define GET_SUBTARGET_FEATURE_NAME
504 #define GET_MATCHER_IMPLEMENTATION
505 #include "SystemZGenAsmMatcher.inc"
506 
507 // Used for the .insn directives; contains information needed to parse the
508 // operands in the directive.
509 struct InsnMatchEntry {
510   StringRef Format;
511   uint64_t Opcode;
512   int32_t NumOperands;
513   MatchClassKind OperandKinds[5];
514 };
515 
516 // For equal_range comparison.
517 struct CompareInsn {
518   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
519     return LHS.Format < RHS;
520   }
521   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
522     return LHS < RHS.Format;
523   }
524   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
525     return LHS.Format < RHS.Format;
526   }
527 };
528 
529 // Table initializing information for parsing the .insn directive.
530 static struct InsnMatchEntry InsnMatchTable[] = {
531   /* Format, Opcode, NumOperands, OperandKinds */
532   { "e", SystemZ::InsnE, 1,
533     { MCK_U16Imm } },
534   { "ri", SystemZ::InsnRI, 3,
535     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
536   { "rie", SystemZ::InsnRIE, 4,
537     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
538   { "ril", SystemZ::InsnRIL, 3,
539     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
540   { "rilu", SystemZ::InsnRILU, 3,
541     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
542   { "ris", SystemZ::InsnRIS, 5,
543     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
544   { "rr", SystemZ::InsnRR, 3,
545     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
546   { "rre", SystemZ::InsnRRE, 3,
547     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
548   { "rrf", SystemZ::InsnRRF, 5,
549     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
550   { "rrs", SystemZ::InsnRRS, 5,
551     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
552   { "rs", SystemZ::InsnRS, 4,
553     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
554   { "rse", SystemZ::InsnRSE, 4,
555     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
556   { "rsi", SystemZ::InsnRSI, 4,
557     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
558   { "rsy", SystemZ::InsnRSY, 4,
559     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
560   { "rx", SystemZ::InsnRX, 3,
561     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
562   { "rxe", SystemZ::InsnRXE, 3,
563     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
564   { "rxf", SystemZ::InsnRXF, 4,
565     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
566   { "rxy", SystemZ::InsnRXY, 3,
567     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
568   { "s", SystemZ::InsnS, 2,
569     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
570   { "si", SystemZ::InsnSI, 3,
571     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
572   { "sil", SystemZ::InsnSIL, 3,
573     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
574   { "siy", SystemZ::InsnSIY, 3,
575     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
576   { "ss", SystemZ::InsnSS, 4,
577     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
578   { "sse", SystemZ::InsnSSE, 3,
579     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
580   { "ssf", SystemZ::InsnSSF, 4,
581     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
582 };
583 
584 void SystemZOperand::print(raw_ostream &OS) const {
585   llvm_unreachable("Not implemented");
586 }
587 
588 // Parse one register of the form %<prefix><number>.
589 bool SystemZAsmParser::parseRegister(Register &Reg) {
590   Reg.StartLoc = Parser.getTok().getLoc();
591 
592   // Eat the % prefix.
593   if (Parser.getTok().isNot(AsmToken::Percent))
594     return Error(Parser.getTok().getLoc(), "register expected");
595   Parser.Lex();
596 
597   // Expect a register name.
598   if (Parser.getTok().isNot(AsmToken::Identifier))
599     return Error(Reg.StartLoc, "invalid register");
600 
601   // Check that there's a prefix.
602   StringRef Name = Parser.getTok().getString();
603   if (Name.size() < 2)
604     return Error(Reg.StartLoc, "invalid register");
605   char Prefix = Name[0];
606 
607   // Treat the rest of the register name as a register number.
608   if (Name.substr(1).getAsInteger(10, Reg.Num))
609     return Error(Reg.StartLoc, "invalid register");
610 
611   // Look for valid combinations of prefix and number.
612   if (Prefix == 'r' && Reg.Num < 16)
613     Reg.Group = RegGR;
614   else if (Prefix == 'f' && Reg.Num < 16)
615     Reg.Group = RegFP;
616   else if (Prefix == 'v' && Reg.Num < 32)
617     Reg.Group = RegV;
618   else if (Prefix == 'a' && Reg.Num < 16)
619     Reg.Group = RegAR;
620   else
621     return Error(Reg.StartLoc, "invalid register");
622 
623   Reg.EndLoc = Parser.getTok().getLoc();
624   Parser.Lex();
625   return false;
626 }
627 
628 // Parse a register of group Group.  If Regs is nonnull, use it to map
629 // the raw register number to LLVM numbering, with zero entries
630 // indicating an invalid register.  IsAddress says whether the
631 // register appears in an address context. Allow FP Group if expecting
632 // RegV Group, since the f-prefix yields the FP group even while used
633 // with vector instructions.
634 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
635                                      const unsigned *Regs, bool IsAddress) {
636   if (parseRegister(Reg))
637     return true;
638   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
639     return Error(Reg.StartLoc, "invalid operand for instruction");
640   if (Regs && Regs[Reg.Num] == 0)
641     return Error(Reg.StartLoc, "invalid register pair");
642   if (Reg.Num == 0 && IsAddress)
643     return Error(Reg.StartLoc, "%r0 used in an address");
644   if (Regs)
645     Reg.Num = Regs[Reg.Num];
646   return false;
647 }
648 
649 // Parse a register and add it to Operands.  The other arguments are as above.
650 OperandMatchResultTy
651 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
652                                 const unsigned *Regs, RegisterKind Kind) {
653   if (Parser.getTok().isNot(AsmToken::Percent))
654     return MatchOperand_NoMatch;
655 
656   Register Reg;
657   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
658   if (parseRegister(Reg, Group, Regs, IsAddress))
659     return MatchOperand_ParseFail;
660 
661   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
662                                                Reg.StartLoc, Reg.EndLoc));
663   return MatchOperand_Success;
664 }
665 
666 // Parse any type of register (including integers) and add it to Operands.
667 OperandMatchResultTy
668 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
669   // Handle integer values.
670   if (Parser.getTok().is(AsmToken::Integer)) {
671     const MCExpr *Register;
672     SMLoc StartLoc = Parser.getTok().getLoc();
673     if (Parser.parseExpression(Register))
674       return MatchOperand_ParseFail;
675 
676     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
677       int64_t Value = CE->getValue();
678       if (Value < 0 || Value > 15) {
679         Error(StartLoc, "invalid register");
680         return MatchOperand_ParseFail;
681       }
682     }
683 
684     SMLoc EndLoc =
685       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
686 
687     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
688   }
689   else {
690     Register Reg;
691     if (parseRegister(Reg))
692       return MatchOperand_ParseFail;
693 
694     // Map to the correct register kind.
695     RegisterKind Kind;
696     unsigned RegNo;
697     if (Reg.Group == RegGR) {
698       Kind = GR64Reg;
699       RegNo = SystemZMC::GR64Regs[Reg.Num];
700     }
701     else if (Reg.Group == RegFP) {
702       Kind = FP64Reg;
703       RegNo = SystemZMC::FP64Regs[Reg.Num];
704     }
705     else if (Reg.Group == RegV) {
706       Kind = VR128Reg;
707       RegNo = SystemZMC::VR128Regs[Reg.Num];
708     }
709     else if (Reg.Group == RegAR) {
710       Kind = AR32Reg;
711       RegNo = SystemZMC::AR32Regs[Reg.Num];
712     }
713     else {
714       return MatchOperand_ParseFail;
715     }
716 
717     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
718                                                  Reg.StartLoc, Reg.EndLoc));
719   }
720   return MatchOperand_Success;
721 }
722 
723 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
724 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
725                                     bool &HaveReg2, Register &Reg2,
726                                     const MCExpr *&Disp,
727                                     const MCExpr *&Length) {
728   // Parse the displacement, which must always be present.
729   if (getParser().parseExpression(Disp))
730     return true;
731 
732   // Parse the optional base and index.
733   HaveReg1 = false;
734   HaveReg2 = false;
735   Length = nullptr;
736   if (getLexer().is(AsmToken::LParen)) {
737     Parser.Lex();
738 
739     if (getLexer().is(AsmToken::Percent)) {
740       // Parse the first register.
741       HaveReg1 = true;
742       if (parseRegister(Reg1))
743         return true;
744     } else {
745       // Parse the length.
746       if (getParser().parseExpression(Length))
747         return true;
748     }
749 
750     // Check whether there's a second register.
751     if (getLexer().is(AsmToken::Comma)) {
752       Parser.Lex();
753       HaveReg2 = true;
754       if (parseRegister(Reg2))
755         return true;
756     }
757 
758     // Consume the closing bracket.
759     if (getLexer().isNot(AsmToken::RParen))
760       return Error(Parser.getTok().getLoc(), "unexpected token in address");
761     Parser.Lex();
762   }
763   return false;
764 }
765 
766 // Verify that Reg is a valid address register (base or index).
767 bool
768 SystemZAsmParser::parseAddressRegister(Register &Reg) {
769   if (Reg.Group == RegV) {
770     Error(Reg.StartLoc, "invalid use of vector addressing");
771     return true;
772   } else if (Reg.Group != RegGR) {
773     Error(Reg.StartLoc, "invalid address register");
774     return true;
775   } else if (Reg.Num == 0) {
776     Error(Reg.StartLoc, "%r0 used in an address");
777     return true;
778   }
779   return false;
780 }
781 
782 // Parse a memory operand and add it to Operands.  The other arguments
783 // are as above.
784 OperandMatchResultTy
785 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
786                                const unsigned *Regs, RegisterKind RegKind) {
787   SMLoc StartLoc = Parser.getTok().getLoc();
788   unsigned Base = 0, Index = 0, LengthReg = 0;
789   Register Reg1, Reg2;
790   bool HaveReg1, HaveReg2;
791   const MCExpr *Disp;
792   const MCExpr *Length;
793   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
794     return MatchOperand_ParseFail;
795 
796   switch (MemKind) {
797   case BDMem:
798     // If we have Reg1, it must be an address register.
799     if (HaveReg1) {
800       if (parseAddressRegister(Reg1))
801         return MatchOperand_ParseFail;
802       Base = Regs[Reg1.Num];
803     }
804     // There must be no Reg2 or length.
805     if (Length) {
806       Error(StartLoc, "invalid use of length addressing");
807       return MatchOperand_ParseFail;
808     }
809     if (HaveReg2) {
810       Error(StartLoc, "invalid use of indexed addressing");
811       return MatchOperand_ParseFail;
812     }
813     break;
814   case BDXMem:
815     // If we have Reg1, it must be an address register.
816     if (HaveReg1) {
817       if (parseAddressRegister(Reg1))
818         return MatchOperand_ParseFail;
819       // If the are two registers, the first one is the index and the
820       // second is the base.
821       if (HaveReg2)
822         Index = Regs[Reg1.Num];
823       else
824         Base = Regs[Reg1.Num];
825     }
826     // If we have Reg2, it must be an address register.
827     if (HaveReg2) {
828       if (parseAddressRegister(Reg2))
829         return MatchOperand_ParseFail;
830       Base = Regs[Reg2.Num];
831     }
832     // There must be no length.
833     if (Length) {
834       Error(StartLoc, "invalid use of length addressing");
835       return MatchOperand_ParseFail;
836     }
837     break;
838   case BDLMem:
839     // If we have Reg2, it must be an address register.
840     if (HaveReg2) {
841       if (parseAddressRegister(Reg2))
842         return MatchOperand_ParseFail;
843       Base = Regs[Reg2.Num];
844     }
845     // We cannot support base+index addressing.
846     if (HaveReg1 && HaveReg2) {
847       Error(StartLoc, "invalid use of indexed addressing");
848       return MatchOperand_ParseFail;
849     }
850     // We must have a length.
851     if (!Length) {
852       Error(StartLoc, "missing length in address");
853       return MatchOperand_ParseFail;
854     }
855     break;
856   case BDRMem:
857     // We must have Reg1, and it must be a GPR.
858     if (!HaveReg1 || Reg1.Group != RegGR) {
859       Error(StartLoc, "invalid operand for instruction");
860       return MatchOperand_ParseFail;
861     }
862     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
863     // If we have Reg2, it must be an address register.
864     if (HaveReg2) {
865       if (parseAddressRegister(Reg2))
866         return MatchOperand_ParseFail;
867       Base = Regs[Reg2.Num];
868     }
869     // There must be no length.
870     if (Length) {
871       Error(StartLoc, "invalid use of length addressing");
872       return MatchOperand_ParseFail;
873     }
874     break;
875   case BDVMem:
876     // We must have Reg1, and it must be a vector register.
877     if (!HaveReg1 || Reg1.Group != RegV) {
878       Error(StartLoc, "vector index required in address");
879       return MatchOperand_ParseFail;
880     }
881     Index = SystemZMC::VR128Regs[Reg1.Num];
882     // If we have Reg2, it must be an address register.
883     if (HaveReg2) {
884       if (parseAddressRegister(Reg2))
885         return MatchOperand_ParseFail;
886       Base = Regs[Reg2.Num];
887     }
888     // There must be no length.
889     if (Length) {
890       Error(StartLoc, "invalid use of length addressing");
891       return MatchOperand_ParseFail;
892     }
893     break;
894   }
895 
896   SMLoc EndLoc =
897     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
898   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
899                                                Index, Length, LengthReg,
900                                                StartLoc, EndLoc));
901   return MatchOperand_Success;
902 }
903 
904 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
905   StringRef IDVal = DirectiveID.getIdentifier();
906 
907   if (IDVal == ".insn")
908     return ParseDirectiveInsn(DirectiveID.getLoc());
909 
910   return true;
911 }
912 
913 /// ParseDirectiveInsn
914 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
915 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
916   MCAsmParser &Parser = getParser();
917 
918   // Expect instruction format as identifier.
919   StringRef Format;
920   SMLoc ErrorLoc = Parser.getTok().getLoc();
921   if (Parser.parseIdentifier(Format))
922     return Error(ErrorLoc, "expected instruction format");
923 
924   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
925 
926   // Find entry for this format in InsnMatchTable.
927   auto EntryRange =
928     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
929                      Format, CompareInsn());
930 
931   // If first == second, couldn't find a match in the table.
932   if (EntryRange.first == EntryRange.second)
933     return Error(ErrorLoc, "unrecognized format");
934 
935   struct InsnMatchEntry *Entry = EntryRange.first;
936 
937   // Format should match from equal_range.
938   assert(Entry->Format == Format);
939 
940   // Parse the following operands using the table's information.
941   for (int i = 0; i < Entry->NumOperands; i++) {
942     MatchClassKind Kind = Entry->OperandKinds[i];
943 
944     SMLoc StartLoc = Parser.getTok().getLoc();
945 
946     // Always expect commas as separators for operands.
947     if (getLexer().isNot(AsmToken::Comma))
948       return Error(StartLoc, "unexpected token in directive");
949     Lex();
950 
951     // Parse operands.
952     OperandMatchResultTy ResTy;
953     if (Kind == MCK_AnyReg)
954       ResTy = parseAnyReg(Operands);
955     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
956       ResTy = parseBDXAddr64(Operands);
957     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
958       ResTy = parseBDAddr64(Operands);
959     else if (Kind == MCK_PCRel32)
960       ResTy = parsePCRel32(Operands);
961     else if (Kind == MCK_PCRel16)
962       ResTy = parsePCRel16(Operands);
963     else {
964       // Only remaining operand kind is an immediate.
965       const MCExpr *Expr;
966       SMLoc StartLoc = Parser.getTok().getLoc();
967 
968       // Expect immediate expression.
969       if (Parser.parseExpression(Expr))
970         return Error(StartLoc, "unexpected token in directive");
971 
972       SMLoc EndLoc =
973         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
974 
975       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
976       ResTy = MatchOperand_Success;
977     }
978 
979     if (ResTy != MatchOperand_Success)
980       return true;
981   }
982 
983   // Build the instruction with the parsed operands.
984   MCInst Inst = MCInstBuilder(Entry->Opcode);
985 
986   for (size_t i = 0; i < Operands.size(); i++) {
987     MCParsedAsmOperand &Operand = *Operands[i];
988     MatchClassKind Kind = Entry->OperandKinds[i];
989 
990     // Verify operand.
991     unsigned Res = validateOperandClass(Operand, Kind);
992     if (Res != Match_Success)
993       return Error(Operand.getStartLoc(), "unexpected operand type");
994 
995     // Add operands to instruction.
996     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
997     if (ZOperand.isReg())
998       ZOperand.addRegOperands(Inst, 1);
999     else if (ZOperand.isMem(BDMem))
1000       ZOperand.addBDAddrOperands(Inst, 2);
1001     else if (ZOperand.isMem(BDXMem))
1002       ZOperand.addBDXAddrOperands(Inst, 3);
1003     else if (ZOperand.isImm())
1004       ZOperand.addImmOperands(Inst, 1);
1005     else
1006       llvm_unreachable("unexpected operand type");
1007   }
1008 
1009   // Emit as a regular instruction.
1010   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1011 
1012   return false;
1013 }
1014 
1015 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1016                                      SMLoc &EndLoc) {
1017   Register Reg;
1018   if (parseRegister(Reg))
1019     return true;
1020   if (Reg.Group == RegGR)
1021     RegNo = SystemZMC::GR64Regs[Reg.Num];
1022   else if (Reg.Group == RegFP)
1023     RegNo = SystemZMC::FP64Regs[Reg.Num];
1024   else if (Reg.Group == RegV)
1025     RegNo = SystemZMC::VR128Regs[Reg.Num];
1026   else if (Reg.Group == RegAR)
1027     RegNo = SystemZMC::AR32Regs[Reg.Num];
1028   StartLoc = Reg.StartLoc;
1029   EndLoc = Reg.EndLoc;
1030   return false;
1031 }
1032 
1033 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1034                                         StringRef Name, SMLoc NameLoc,
1035                                         OperandVector &Operands) {
1036   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1037 
1038   // Read the remaining operands.
1039   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1040     // Read the first operand.
1041     if (parseOperand(Operands, Name)) {
1042       return true;
1043     }
1044 
1045     // Read any subsequent operands.
1046     while (getLexer().is(AsmToken::Comma)) {
1047       Parser.Lex();
1048       if (parseOperand(Operands, Name)) {
1049         return true;
1050       }
1051     }
1052     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1053       SMLoc Loc = getLexer().getLoc();
1054       return Error(Loc, "unexpected token in argument list");
1055     }
1056   }
1057 
1058   // Consume the EndOfStatement.
1059   Parser.Lex();
1060   return false;
1061 }
1062 
1063 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1064                                     StringRef Mnemonic) {
1065   // Check if the current operand has a custom associated parser, if so, try to
1066   // custom parse the operand, or fallback to the general approach.  Force all
1067   // features to be available during the operand check, or else we will fail to
1068   // find the custom parser, and then we will later get an InvalidOperand error
1069   // instead of a MissingFeature errror.
1070   uint64_t AvailableFeatures = getAvailableFeatures();
1071   setAvailableFeatures(~(uint64_t)0);
1072   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1073   setAvailableFeatures(AvailableFeatures);
1074   if (ResTy == MatchOperand_Success)
1075     return false;
1076 
1077   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1078   // there was a match, but an error occurred, in which case, just return that
1079   // the operand parsing failed.
1080   if (ResTy == MatchOperand_ParseFail)
1081     return true;
1082 
1083   // Check for a register.  All real register operands should have used
1084   // a context-dependent parse routine, which gives the required register
1085   // class.  The code is here to mop up other cases, like those where
1086   // the instruction isn't recognized.
1087   if (Parser.getTok().is(AsmToken::Percent)) {
1088     Register Reg;
1089     if (parseRegister(Reg))
1090       return true;
1091     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1092     return false;
1093   }
1094 
1095   // The only other type of operand is an immediate or address.  As above,
1096   // real address operands should have used a context-dependent parse routine,
1097   // so we treat any plain expression as an immediate.
1098   SMLoc StartLoc = Parser.getTok().getLoc();
1099   Register Reg1, Reg2;
1100   bool HaveReg1, HaveReg2;
1101   const MCExpr *Expr;
1102   const MCExpr *Length;
1103   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1104     return true;
1105   // If the register combination is not valid for any instruction, reject it.
1106   // Otherwise, fall back to reporting an unrecognized instruction.
1107   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1108       && parseAddressRegister(Reg1))
1109     return true;
1110   if (HaveReg2 && parseAddressRegister(Reg2))
1111     return true;
1112 
1113   SMLoc EndLoc =
1114     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1115   if (HaveReg1 || HaveReg2 || Length)
1116     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1117   else
1118     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1119   return false;
1120 }
1121 
1122 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1123                                                OperandVector &Operands,
1124                                                MCStreamer &Out,
1125                                                uint64_t &ErrorInfo,
1126                                                bool MatchingInlineAsm) {
1127   MCInst Inst;
1128   unsigned MatchResult;
1129 
1130   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1131                                      MatchingInlineAsm);
1132   switch (MatchResult) {
1133   case Match_Success:
1134     Inst.setLoc(IDLoc);
1135     Out.EmitInstruction(Inst, getSTI());
1136     return false;
1137 
1138   case Match_MissingFeature: {
1139     assert(ErrorInfo && "Unknown missing feature!");
1140     // Special case the error message for the very common case where only
1141     // a single subtarget feature is missing
1142     std::string Msg = "instruction requires:";
1143     uint64_t Mask = 1;
1144     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1145       if (ErrorInfo & Mask) {
1146         Msg += " ";
1147         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1148       }
1149       Mask <<= 1;
1150     }
1151     return Error(IDLoc, Msg);
1152   }
1153 
1154   case Match_InvalidOperand: {
1155     SMLoc ErrorLoc = IDLoc;
1156     if (ErrorInfo != ~0ULL) {
1157       if (ErrorInfo >= Operands.size())
1158         return Error(IDLoc, "too few operands for instruction");
1159 
1160       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1161       if (ErrorLoc == SMLoc())
1162         ErrorLoc = IDLoc;
1163     }
1164     return Error(ErrorLoc, "invalid operand for instruction");
1165   }
1166 
1167   case Match_MnemonicFail:
1168     return Error(IDLoc, "invalid instruction");
1169   }
1170 
1171   llvm_unreachable("Unexpected match type");
1172 }
1173 
1174 OperandMatchResultTy
1175 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1176                              int64_t MaxVal, bool AllowTLS) {
1177   MCContext &Ctx = getContext();
1178   MCStreamer &Out = getStreamer();
1179   const MCExpr *Expr;
1180   SMLoc StartLoc = Parser.getTok().getLoc();
1181   if (getParser().parseExpression(Expr))
1182     return MatchOperand_NoMatch;
1183 
1184   // For consistency with the GNU assembler, treat immediates as offsets
1185   // from ".".
1186   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1187     int64_t Value = CE->getValue();
1188     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1189       Error(StartLoc, "offset out of range");
1190       return MatchOperand_ParseFail;
1191     }
1192     MCSymbol *Sym = Ctx.createTempSymbol();
1193     Out.EmitLabel(Sym);
1194     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1195                                                  Ctx);
1196     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1197   }
1198 
1199   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1200   const MCExpr *Sym = nullptr;
1201   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1202     Parser.Lex();
1203 
1204     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1205       Error(Parser.getTok().getLoc(), "unexpected token");
1206       return MatchOperand_ParseFail;
1207     }
1208 
1209     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1210     StringRef Name = Parser.getTok().getString();
1211     if (Name == "tls_gdcall")
1212       Kind = MCSymbolRefExpr::VK_TLSGD;
1213     else if (Name == "tls_ldcall")
1214       Kind = MCSymbolRefExpr::VK_TLSLDM;
1215     else {
1216       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1217       return MatchOperand_ParseFail;
1218     }
1219     Parser.Lex();
1220 
1221     if (Parser.getTok().isNot(AsmToken::Colon)) {
1222       Error(Parser.getTok().getLoc(), "unexpected token");
1223       return MatchOperand_ParseFail;
1224     }
1225     Parser.Lex();
1226 
1227     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1228       Error(Parser.getTok().getLoc(), "unexpected token");
1229       return MatchOperand_ParseFail;
1230     }
1231 
1232     StringRef Identifier = Parser.getTok().getString();
1233     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1234                                   Kind, Ctx);
1235     Parser.Lex();
1236   }
1237 
1238   SMLoc EndLoc =
1239     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1240 
1241   if (AllowTLS)
1242     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1243                                                     StartLoc, EndLoc));
1244   else
1245     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1246 
1247   return MatchOperand_Success;
1248 }
1249 
1250 // Force static initialization.
1251 extern "C" void LLVMInitializeSystemZAsmParser() {
1252   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1253 }
1254