1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/MC/MCContext.h"
12 #include "llvm/MC/MCExpr.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCSubtargetInfo.h"
17 #include "llvm/MC/MCTargetAsmParser.h"
18 #include "llvm/Support/TargetRegistry.h"
19 
20 using namespace llvm;
21 
22 // Return true if Expr is in the range [MinValue, MaxValue].
23 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
24   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
25     int64_t Value = CE->getValue();
26     return Value >= MinValue && Value <= MaxValue;
27   }
28   return false;
29 }
30 
31 namespace {
32 class SystemZOperand : public MCParsedAsmOperand {
33 public:
34   enum RegisterKind {
35     GR32Reg,
36     GR64Reg,
37     GR128Reg,
38     ADDR32Reg,
39     ADDR64Reg,
40     FP32Reg,
41     FP64Reg,
42     FP128Reg
43   };
44 
45 private:
46   enum OperandKind {
47     KindInvalid,
48     KindToken,
49     KindReg,
50     KindAccessReg,
51     KindImm,
52     KindMem
53   };
54 
55   OperandKind Kind;
56   SMLoc StartLoc, EndLoc;
57 
58   // A string of length Length, starting at Data.
59   struct TokenOp {
60     const char *Data;
61     unsigned Length;
62   };
63 
64   // LLVM register Num, which has kind Kind.  In some ways it might be
65   // easier for this class to have a register bank (general, floating-point
66   // or access) and a raw register number (0-15).  This would postpone the
67   // interpretation of the operand to the add*() methods and avoid the need
68   // for context-dependent parsing.  However, we do things the current way
69   // because of the virtual getReg() method, which needs to distinguish
70   // between (say) %r0 used as a single register and %r0 used as a pair.
71   // Context-dependent parsing can also give us slightly better error
72   // messages when invalid pairs like %r1 are used.
73   struct RegOp {
74     RegisterKind Kind;
75     unsigned Num;
76   };
77 
78   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
79   // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
80   struct MemOp {
81     unsigned Base : 8;
82     unsigned Index : 8;
83     unsigned RegKind : 8;
84     unsigned Unused : 8;
85     const MCExpr *Disp;
86   };
87 
88   union {
89     TokenOp Token;
90     RegOp Reg;
91     unsigned AccessReg;
92     const MCExpr *Imm;
93     MemOp Mem;
94   };
95 
96   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
97     : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
98   {}
99 
100   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
101     // Add as immediates when possible.  Null MCExpr = 0.
102     if (Expr == 0)
103       Inst.addOperand(MCOperand::CreateImm(0));
104     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
105       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
106     else
107       Inst.addOperand(MCOperand::CreateExpr(Expr));
108   }
109 
110 public:
111   // Create particular kinds of operand.
112   static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
113     return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
114   }
115   static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
116     SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
117     Op->Token.Data = Str.data();
118     Op->Token.Length = Str.size();
119     return Op;
120   }
121   static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
122                                    SMLoc StartLoc, SMLoc EndLoc) {
123     SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
124     Op->Reg.Kind = Kind;
125     Op->Reg.Num = Num;
126     return Op;
127   }
128   static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
129                                          SMLoc EndLoc) {
130     SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
131     Op->AccessReg = Num;
132     return Op;
133   }
134   static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
135                                    SMLoc EndLoc) {
136     SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
137     Op->Imm = Expr;
138     return Op;
139   }
140   static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
141                                    const MCExpr *Disp, unsigned Index,
142                                    SMLoc StartLoc, SMLoc EndLoc) {
143     SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
144     Op->Mem.RegKind = RegKind;
145     Op->Mem.Base = Base;
146     Op->Mem.Index = Index;
147     Op->Mem.Disp = Disp;
148     return Op;
149   }
150 
151   // Token operands
152   virtual bool isToken() const LLVM_OVERRIDE {
153     return Kind == KindToken;
154   }
155   StringRef getToken() const {
156     assert(Kind == KindToken && "Not a token");
157     return StringRef(Token.Data, Token.Length);
158   }
159 
160   // Register operands.
161   virtual bool isReg() const LLVM_OVERRIDE {
162     return Kind == KindReg;
163   }
164   bool isReg(RegisterKind RegKind) const {
165     return Kind == KindReg && Reg.Kind == RegKind;
166   }
167   virtual unsigned getReg() const LLVM_OVERRIDE {
168     assert(Kind == KindReg && "Not a register");
169     return Reg.Num;
170   }
171 
172   // Access register operands.  Access registers aren't exposed to LLVM
173   // as registers.
174   bool isAccessReg() const {
175     return Kind == KindAccessReg;
176   }
177 
178   // Immediate operands.
179   virtual bool isImm() const LLVM_OVERRIDE {
180     return Kind == KindImm;
181   }
182   bool isImm(int64_t MinValue, int64_t MaxValue) const {
183     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
184   }
185   const MCExpr *getImm() const {
186     assert(Kind == KindImm && "Not an immediate");
187     return Imm;
188   }
189 
190   // Memory operands.
191   virtual bool isMem() const LLVM_OVERRIDE {
192     return Kind == KindMem;
193   }
194   bool isMem(RegisterKind RegKind, bool HasIndex) const {
195     return (Kind == KindMem &&
196             Mem.RegKind == RegKind &&
197             (HasIndex || !Mem.Index));
198   }
199   bool isMemDisp12(RegisterKind RegKind, bool HasIndex) const {
200     return isMem(RegKind, HasIndex) && inRange(Mem.Disp, 0, 0xfff);
201   }
202   bool isMemDisp20(RegisterKind RegKind, bool HasIndex) const {
203     return isMem(RegKind, HasIndex) && inRange(Mem.Disp, -524288, 524287);
204   }
205 
206   // Override MCParsedAsmOperand.
207   virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
208   virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
209   virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
210 
211   // Used by the TableGen code to add particular types of operand
212   // to an instruction.
213   void addRegOperands(MCInst &Inst, unsigned N) const {
214     assert(N == 1 && "Invalid number of operands");
215     Inst.addOperand(MCOperand::CreateReg(getReg()));
216   }
217   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
218     assert(N == 1 && "Invalid number of operands");
219     assert(Kind == KindAccessReg && "Invalid operand type");
220     Inst.addOperand(MCOperand::CreateImm(AccessReg));
221   }
222   void addImmOperands(MCInst &Inst, unsigned N) const {
223     assert(N == 1 && "Invalid number of operands");
224     addExpr(Inst, getImm());
225   }
226   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
227     assert(N == 2 && "Invalid number of operands");
228     assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
229     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
230     addExpr(Inst, Mem.Disp);
231   }
232   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
233     assert(N == 3 && "Invalid number of operands");
234     assert(Kind == KindMem && "Invalid operand type");
235     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
236     addExpr(Inst, Mem.Disp);
237     Inst.addOperand(MCOperand::CreateReg(Mem.Index));
238   }
239 
240   // Used by the TableGen code to check for particular operand types.
241   bool isGR32() const { return isReg(GR32Reg); }
242   bool isGR64() const { return isReg(GR64Reg); }
243   bool isGR128() const { return isReg(GR128Reg); }
244   bool isADDR32() const { return isReg(ADDR32Reg); }
245   bool isADDR64() const { return isReg(ADDR64Reg); }
246   bool isADDR128() const { return false; }
247   bool isFP32() const { return isReg(FP32Reg); }
248   bool isFP64() const { return isReg(FP64Reg); }
249   bool isFP128() const { return isReg(FP128Reg); }
250   bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, false); }
251   bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, false); }
252   bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, false); }
253   bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, false); }
254   bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, true); }
255   bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, true); }
256   bool isU4Imm() const { return isImm(0, 15); }
257   bool isU6Imm() const { return isImm(0, 63); }
258   bool isU8Imm() const { return isImm(0, 255); }
259   bool isS8Imm() const { return isImm(-128, 127); }
260   bool isU16Imm() const { return isImm(0, 65535); }
261   bool isS16Imm() const { return isImm(-32768, 32767); }
262   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
263   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
264 };
265 
266 class SystemZAsmParser : public MCTargetAsmParser {
267 #define GET_ASSEMBLER_HEADER
268 #include "SystemZGenAsmMatcher.inc"
269 
270 private:
271   MCSubtargetInfo &STI;
272   MCAsmParser &Parser;
273   enum RegisterGroup {
274     RegGR,
275     RegFP,
276     RegAccess
277   };
278   struct Register {
279     RegisterGroup Group;
280     unsigned Num;
281     SMLoc StartLoc, EndLoc;
282   };
283 
284   bool parseRegister(Register &Reg);
285 
286   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
287                      bool IsAddress = false);
288 
289   OperandMatchResultTy
290   parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
291                 RegisterGroup Group, const unsigned *Regs,
292                 SystemZOperand::RegisterKind Kind,
293                 bool IsAddress = false);
294 
295   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
296                     unsigned &Index, const unsigned *Regs,
297                     SystemZOperand::RegisterKind RegKind,
298                     bool HasIndex);
299 
300   OperandMatchResultTy
301   parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
302                const unsigned *Regs, SystemZOperand::RegisterKind RegKind,
303                bool HasIndex);
304 
305   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
306                     StringRef Mnemonic);
307 
308 public:
309   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
310     : MCTargetAsmParser(), STI(sti), Parser(parser) {
311     MCAsmParserExtension::Initialize(Parser);
312 
313     // Initialize the set of available features.
314     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
315   }
316 
317   // Override MCTargetAsmParser.
318   virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
319   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
320                              SMLoc &EndLoc) LLVM_OVERRIDE;
321   virtual bool ParseInstruction(ParseInstructionInfo &Info,
322                                 StringRef Name, SMLoc NameLoc,
323                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
324     LLVM_OVERRIDE;
325   virtual bool
326     MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
327                             SmallVectorImpl<MCParsedAsmOperand*> &Operands,
328                             MCStreamer &Out, unsigned &ErrorInfo,
329                             bool MatchingInlineAsm) LLVM_OVERRIDE;
330 
331   // Used by the TableGen code to parse particular operand types.
332   OperandMatchResultTy
333   parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
334     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs,
335                          SystemZOperand::GR32Reg);
336   }
337   OperandMatchResultTy
338   parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
339     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs,
340                          SystemZOperand::GR64Reg);
341   }
342   OperandMatchResultTy
343   parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
344     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs,
345                          SystemZOperand::GR128Reg);
346   }
347   OperandMatchResultTy
348   parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
349     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs,
350                          SystemZOperand::ADDR32Reg, true);
351   }
352   OperandMatchResultTy
353   parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
354     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs,
355                          SystemZOperand::ADDR64Reg, true);
356   }
357   OperandMatchResultTy
358   parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
359     llvm_unreachable("Shouldn't be used as an operand");
360   }
361   OperandMatchResultTy
362   parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
363     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs,
364                          SystemZOperand::FP32Reg);
365   }
366   OperandMatchResultTy
367   parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
368     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs,
369                          SystemZOperand::FP64Reg);
370   }
371   OperandMatchResultTy
372   parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
373     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs,
374                          SystemZOperand::FP128Reg);
375   }
376   OperandMatchResultTy
377   parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
378     return parseAddress(Operands, SystemZMC::GR32Regs,
379                         SystemZOperand::ADDR32Reg, false);
380   }
381   OperandMatchResultTy
382   parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
383     return parseAddress(Operands, SystemZMC::GR64Regs,
384                         SystemZOperand::ADDR64Reg, false);
385   }
386   OperandMatchResultTy
387   parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
388     return parseAddress(Operands, SystemZMC::GR64Regs,
389                         SystemZOperand::ADDR64Reg, true);
390   }
391   OperandMatchResultTy
392   parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
393   OperandMatchResultTy
394   parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
395              int64_t MinVal, int64_t MaxVal);
396   OperandMatchResultTy
397   parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
398     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
399   }
400   OperandMatchResultTy
401   parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
402     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
403   }
404 };
405 }
406 
407 #define GET_REGISTER_MATCHER
408 #define GET_SUBTARGET_FEATURE_NAME
409 #define GET_MATCHER_IMPLEMENTATION
410 #include "SystemZGenAsmMatcher.inc"
411 
412 void SystemZOperand::print(raw_ostream &OS) const {
413   llvm_unreachable("Not implemented");
414 }
415 
416 // Parse one register of the form %<prefix><number>.
417 bool SystemZAsmParser::parseRegister(Register &Reg) {
418   Reg.StartLoc = Parser.getTok().getLoc();
419 
420   // Eat the % prefix.
421   if (Parser.getTok().isNot(AsmToken::Percent))
422     return Error(Parser.getTok().getLoc(), "register expected");
423   Parser.Lex();
424 
425   // Expect a register name.
426   if (Parser.getTok().isNot(AsmToken::Identifier))
427     return Error(Reg.StartLoc, "invalid register");
428 
429   // Check that there's a prefix.
430   StringRef Name = Parser.getTok().getString();
431   if (Name.size() < 2)
432     return Error(Reg.StartLoc, "invalid register");
433   char Prefix = Name[0];
434 
435   // Treat the rest of the register name as a register number.
436   if (Name.substr(1).getAsInteger(10, Reg.Num))
437     return Error(Reg.StartLoc, "invalid register");
438 
439   // Look for valid combinations of prefix and number.
440   if (Prefix == 'r' && Reg.Num < 16)
441     Reg.Group = RegGR;
442   else if (Prefix == 'f' && Reg.Num < 16)
443     Reg.Group = RegFP;
444   else if (Prefix == 'a' && Reg.Num < 16)
445     Reg.Group = RegAccess;
446   else
447     return Error(Reg.StartLoc, "invalid register");
448 
449   Reg.EndLoc = Parser.getTok().getLoc();
450   Parser.Lex();
451   return false;
452 }
453 
454 // Parse a register of group Group.  If Regs is nonnull, use it to map
455 // the raw register number to LLVM numbering, with zero entries indicating
456 // an invalid register.  IsAddress says whether the register appears in an
457 // address context.
458 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
459                                      const unsigned *Regs, bool IsAddress) {
460   if (parseRegister(Reg))
461     return true;
462   if (Reg.Group != Group)
463     return Error(Reg.StartLoc, "invalid operand for instruction");
464   if (Regs && Regs[Reg.Num] == 0)
465     return Error(Reg.StartLoc, "invalid register pair");
466   if (Reg.Num == 0 && IsAddress)
467     return Error(Reg.StartLoc, "%r0 used in an address");
468   if (Regs)
469     Reg.Num = Regs[Reg.Num];
470   return false;
471 }
472 
473 // Parse a register and add it to Operands.  The other arguments are as above.
474 SystemZAsmParser::OperandMatchResultTy
475 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
476                                 RegisterGroup Group, const unsigned *Regs,
477                                 SystemZOperand::RegisterKind Kind,
478                                 bool IsAddress) {
479   if (Parser.getTok().isNot(AsmToken::Percent))
480     return MatchOperand_NoMatch;
481 
482   Register Reg;
483   if (parseRegister(Reg, Group, Regs, IsAddress))
484     return MatchOperand_ParseFail;
485 
486   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
487                                                Reg.StartLoc, Reg.EndLoc));
488   return MatchOperand_Success;
489 }
490 
491 // Parse a memory operand into Base, Disp and Index.  Regs maps asm
492 // register numbers to LLVM register numbers and RegKind says what kind
493 // of address register we're using (ADDR32Reg or ADDR64Reg).  HasIndex
494 // says whether the address allows index registers.
495 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
496                                     unsigned &Index, const unsigned *Regs,
497                                     SystemZOperand::RegisterKind RegKind,
498                                     bool HasIndex) {
499   // Parse the displacement, which must always be present.
500   if (getParser().parseExpression(Disp))
501     return true;
502 
503   // Parse the optional base and index.
504   Index = 0;
505   Base = 0;
506   if (getLexer().is(AsmToken::LParen)) {
507     Parser.Lex();
508 
509     // Parse the first register.
510     Register Reg;
511     if (parseRegister(Reg, RegGR, Regs, RegKind))
512       return true;
513 
514     // Check whether there's a second register.  If so, the one that we
515     // just parsed was the index.
516     if (getLexer().is(AsmToken::Comma)) {
517       Parser.Lex();
518 
519       if (!HasIndex)
520         return Error(Reg.StartLoc, "invalid use of indexed addressing");
521 
522       Index = Reg.Num;
523       if (parseRegister(Reg, RegGR, Regs, RegKind))
524         return true;
525     }
526     Base = Reg.Num;
527 
528     // Consume the closing bracket.
529     if (getLexer().isNot(AsmToken::RParen))
530       return Error(Parser.getTok().getLoc(), "unexpected token in address");
531     Parser.Lex();
532   }
533   return false;
534 }
535 
536 // Parse a memory operand and add it to Operands.  The other arguments
537 // are as above.
538 SystemZAsmParser::OperandMatchResultTy
539 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
540                                const unsigned *Regs,
541                                SystemZOperand::RegisterKind RegKind,
542                                bool HasIndex) {
543   SMLoc StartLoc = Parser.getTok().getLoc();
544   unsigned Base, Index;
545   const MCExpr *Disp;
546   if (parseAddress(Base, Disp, Index, Regs, RegKind, HasIndex))
547     return MatchOperand_ParseFail;
548 
549   SMLoc EndLoc =
550     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
551   Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
552                                                StartLoc, EndLoc));
553   return MatchOperand_Success;
554 }
555 
556 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
557   return true;
558 }
559 
560 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
561                                      SMLoc &EndLoc) {
562   Register Reg;
563   if (parseRegister(Reg))
564     return true;
565   if (Reg.Group == RegGR)
566     RegNo = SystemZMC::GR64Regs[Reg.Num];
567   else if (Reg.Group == RegFP)
568     RegNo = SystemZMC::FP64Regs[Reg.Num];
569   else
570     // FIXME: Access registers aren't modelled as LLVM registers yet.
571     return Error(Reg.StartLoc, "invalid operand for instruction");
572   StartLoc = Reg.StartLoc;
573   EndLoc = Reg.EndLoc;
574   return false;
575 }
576 
577 bool SystemZAsmParser::
578 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
579                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
580   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
581 
582   // Read the remaining operands.
583   if (getLexer().isNot(AsmToken::EndOfStatement)) {
584     // Read the first operand.
585     if (parseOperand(Operands, Name)) {
586       Parser.eatToEndOfStatement();
587       return true;
588     }
589 
590     // Read any subsequent operands.
591     while (getLexer().is(AsmToken::Comma)) {
592       Parser.Lex();
593       if (parseOperand(Operands, Name)) {
594         Parser.eatToEndOfStatement();
595         return true;
596       }
597     }
598     if (getLexer().isNot(AsmToken::EndOfStatement)) {
599       SMLoc Loc = getLexer().getLoc();
600       Parser.eatToEndOfStatement();
601       return Error(Loc, "unexpected token in argument list");
602     }
603   }
604 
605   // Consume the EndOfStatement.
606   Parser.Lex();
607   return false;
608 }
609 
610 bool SystemZAsmParser::
611 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
612              StringRef Mnemonic) {
613   // Check if the current operand has a custom associated parser, if so, try to
614   // custom parse the operand, or fallback to the general approach.
615   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
616   if (ResTy == MatchOperand_Success)
617     return false;
618 
619   // If there wasn't a custom match, try the generic matcher below. Otherwise,
620   // there was a match, but an error occurred, in which case, just return that
621   // the operand parsing failed.
622   if (ResTy == MatchOperand_ParseFail)
623     return true;
624 
625   // Check for a register.  All real register operands should have used
626   // a context-dependent parse routine, which gives the required register
627   // class.  The code is here to mop up other cases, like those where
628   // the instruction isn't recognized.
629   if (Parser.getTok().is(AsmToken::Percent)) {
630     Register Reg;
631     if (parseRegister(Reg))
632       return true;
633     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
634     return false;
635   }
636 
637   // The only other type of operand is an immediate or address.  As above,
638   // real address operands should have used a context-dependent parse routine,
639   // so we treat any plain expression as an immediate.
640   SMLoc StartLoc = Parser.getTok().getLoc();
641   unsigned Base, Index;
642   const MCExpr *Expr;
643   if (parseAddress(Base, Expr, Index, SystemZMC::GR64Regs,
644                    SystemZOperand::ADDR64Reg, true))
645     return true;
646 
647   SMLoc EndLoc =
648     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
649   if (Base || Index)
650     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
651   else
652     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
653   return false;
654 }
655 
656 bool SystemZAsmParser::
657 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
658                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
659                         MCStreamer &Out, unsigned &ErrorInfo,
660                         bool MatchingInlineAsm) {
661   MCInst Inst;
662   unsigned MatchResult;
663 
664   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
665                                      MatchingInlineAsm);
666   switch (MatchResult) {
667   default: break;
668   case Match_Success:
669     Inst.setLoc(IDLoc);
670     Out.EmitInstruction(Inst);
671     return false;
672 
673   case Match_MissingFeature: {
674     assert(ErrorInfo && "Unknown missing feature!");
675     // Special case the error message for the very common case where only
676     // a single subtarget feature is missing
677     std::string Msg = "instruction requires:";
678     unsigned Mask = 1;
679     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
680       if (ErrorInfo & Mask) {
681         Msg += " ";
682         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
683       }
684       Mask <<= 1;
685     }
686     return Error(IDLoc, Msg);
687   }
688 
689   case Match_InvalidOperand: {
690     SMLoc ErrorLoc = IDLoc;
691     if (ErrorInfo != ~0U) {
692       if (ErrorInfo >= Operands.size())
693         return Error(IDLoc, "too few operands for instruction");
694 
695       ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
696       if (ErrorLoc == SMLoc())
697         ErrorLoc = IDLoc;
698     }
699     return Error(ErrorLoc, "invalid operand for instruction");
700   }
701 
702   case Match_MnemonicFail:
703     return Error(IDLoc, "invalid instruction");
704   }
705 
706   llvm_unreachable("Unexpected match type");
707 }
708 
709 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
710 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
711   if (Parser.getTok().isNot(AsmToken::Percent))
712     return MatchOperand_NoMatch;
713 
714   Register Reg;
715   if (parseRegister(Reg, RegAccess, 0))
716     return MatchOperand_ParseFail;
717 
718   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
719                                                      Reg.StartLoc,
720                                                      Reg.EndLoc));
721   return MatchOperand_Success;
722 }
723 
724 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
725 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
726            int64_t MinVal, int64_t MaxVal) {
727   MCContext &Ctx = getContext();
728   MCStreamer &Out = getStreamer();
729   const MCExpr *Expr;
730   SMLoc StartLoc = Parser.getTok().getLoc();
731   if (getParser().parseExpression(Expr))
732     return MatchOperand_NoMatch;
733 
734   // For consistency with the GNU assembler, treat immediates as offsets
735   // from ".".
736   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
737     int64_t Value = CE->getValue();
738     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
739       Error(StartLoc, "offset out of range");
740       return MatchOperand_ParseFail;
741     }
742     MCSymbol *Sym = Ctx.CreateTempSymbol();
743     Out.EmitLabel(Sym);
744     const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
745                                                  Ctx);
746     Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
747   }
748 
749   SMLoc EndLoc =
750     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
751   Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
752   return MatchOperand_Success;
753 }
754 
755 // Force static initialization.
756 extern "C" void LLVMInitializeSystemZAsmParser() {
757   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
758 }
759