1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCInstBuilder.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 // Return true if Expr is in the range [MinValue, MaxValue].
25 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
26   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
27     int64_t Value = CE->getValue();
28     return Value >= MinValue && Value <= MaxValue;
29   }
30   return false;
31 }
32 
33 namespace {
34 enum RegisterKind {
35   GR32Reg,
36   GRH32Reg,
37   GR64Reg,
38   GR128Reg,
39   ADDR32Reg,
40   ADDR64Reg,
41   FP32Reg,
42   FP64Reg,
43   FP128Reg,
44   VR32Reg,
45   VR64Reg,
46   VR128Reg
47 };
48 
49 enum MemoryKind {
50   BDMem,
51   BDXMem,
52   BDLMem,
53   BDVMem
54 };
55 
56 class SystemZOperand : public MCParsedAsmOperand {
57 public:
58 private:
59   enum OperandKind {
60     KindInvalid,
61     KindToken,
62     KindReg,
63     KindAccessReg,
64     KindImm,
65     KindImmTLS,
66     KindMem
67   };
68 
69   OperandKind Kind;
70   SMLoc StartLoc, EndLoc;
71 
72   // A string of length Length, starting at Data.
73   struct TokenOp {
74     const char *Data;
75     unsigned Length;
76   };
77 
78   // LLVM register Num, which has kind Kind.  In some ways it might be
79   // easier for this class to have a register bank (general, floating-point
80   // or access) and a raw register number (0-15).  This would postpone the
81   // interpretation of the operand to the add*() methods and avoid the need
82   // for context-dependent parsing.  However, we do things the current way
83   // because of the virtual getReg() method, which needs to distinguish
84   // between (say) %r0 used as a single register and %r0 used as a pair.
85   // Context-dependent parsing can also give us slightly better error
86   // messages when invalid pairs like %r1 are used.
87   struct RegOp {
88     RegisterKind Kind;
89     unsigned Num;
90   };
91 
92   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
93   // MemKind says what type of memory this is and RegKind says what type
94   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
95   // length for D(L,B)-style operands, otherwise it is null.
96   struct MemOp {
97     unsigned Base : 12;
98     unsigned Index : 12;
99     unsigned MemKind : 4;
100     unsigned RegKind : 4;
101     const MCExpr *Disp;
102     const MCExpr *Length;
103   };
104 
105   // Imm is an immediate operand, and Sym is an optional TLS symbol
106   // for use with a __tls_get_offset marker relocation.
107   struct ImmTLSOp {
108     const MCExpr *Imm;
109     const MCExpr *Sym;
110   };
111 
112   union {
113     TokenOp Token;
114     RegOp Reg;
115     unsigned AccessReg;
116     const MCExpr *Imm;
117     ImmTLSOp ImmTLS;
118     MemOp Mem;
119   };
120 
121   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
122     // Add as immediates when possible.  Null MCExpr = 0.
123     if (!Expr)
124       Inst.addOperand(MCOperand::createImm(0));
125     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
126       Inst.addOperand(MCOperand::createImm(CE->getValue()));
127     else
128       Inst.addOperand(MCOperand::createExpr(Expr));
129   }
130 
131 public:
132   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
133       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
134 
135   // Create particular kinds of operand.
136   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
137                                                        SMLoc EndLoc) {
138     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
139   }
140   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
141     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
142     Op->Token.Data = Str.data();
143     Op->Token.Length = Str.size();
144     return Op;
145   }
146   static std::unique_ptr<SystemZOperand>
147   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
148     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
149     Op->Reg.Kind = Kind;
150     Op->Reg.Num = Num;
151     return Op;
152   }
153   static std::unique_ptr<SystemZOperand>
154   createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
155     auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
156     Op->AccessReg = Num;
157     return Op;
158   }
159   static std::unique_ptr<SystemZOperand>
160   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
161     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
162     Op->Imm = Expr;
163     return Op;
164   }
165   static std::unique_ptr<SystemZOperand>
166   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
167             const MCExpr *Disp, unsigned Index, const MCExpr *Length,
168             SMLoc StartLoc, SMLoc EndLoc) {
169     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
170     Op->Mem.MemKind = MemKind;
171     Op->Mem.RegKind = RegKind;
172     Op->Mem.Base = Base;
173     Op->Mem.Index = Index;
174     Op->Mem.Disp = Disp;
175     Op->Mem.Length = Length;
176     return Op;
177   }
178   static std::unique_ptr<SystemZOperand>
179   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
180                SMLoc StartLoc, SMLoc EndLoc) {
181     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
182     Op->ImmTLS.Imm = Imm;
183     Op->ImmTLS.Sym = Sym;
184     return Op;
185   }
186 
187   // Token operands
188   bool isToken() const override {
189     return Kind == KindToken;
190   }
191   StringRef getToken() const {
192     assert(Kind == KindToken && "Not a token");
193     return StringRef(Token.Data, Token.Length);
194   }
195 
196   // Register operands.
197   bool isReg() const override {
198     return Kind == KindReg;
199   }
200   bool isReg(RegisterKind RegKind) const {
201     return Kind == KindReg && Reg.Kind == RegKind;
202   }
203   unsigned getReg() const override {
204     assert(Kind == KindReg && "Not a register");
205     return Reg.Num;
206   }
207 
208   // Access register operands.  Access registers aren't exposed to LLVM
209   // as registers.
210   bool isAccessReg() const {
211     return Kind == KindAccessReg;
212   }
213 
214   // Immediate operands.
215   bool isImm() const override {
216     return Kind == KindImm;
217   }
218   bool isImm(int64_t MinValue, int64_t MaxValue) const {
219     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
220   }
221   const MCExpr *getImm() const {
222     assert(Kind == KindImm && "Not an immediate");
223     return Imm;
224   }
225 
226   // Immediate operands with optional TLS symbol.
227   bool isImmTLS() const {
228     return Kind == KindImmTLS;
229   }
230 
231   // Memory operands.
232   bool isMem() const override {
233     return Kind == KindMem;
234   }
235   bool isMem(MemoryKind MemKind) const {
236     return (Kind == KindMem &&
237             (Mem.MemKind == MemKind ||
238              // A BDMem can be treated as a BDXMem in which the index
239              // register field is 0.
240              (Mem.MemKind == BDMem && MemKind == BDXMem)));
241   }
242   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
243     return isMem(MemKind) && Mem.RegKind == RegKind;
244   }
245   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
246     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
247   }
248   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
249     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
250   }
251   bool isMemDisp12Len8(RegisterKind RegKind) const {
252     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
253   }
254   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
255     assert(N == 3 && "Invalid number of operands");
256     assert(isMem(BDVMem) && "Invalid operand type");
257     Inst.addOperand(MCOperand::createReg(Mem.Base));
258     addExpr(Inst, Mem.Disp);
259     Inst.addOperand(MCOperand::createReg(Mem.Index));
260   }
261 
262   // Override MCParsedAsmOperand.
263   SMLoc getStartLoc() const override { return StartLoc; }
264   SMLoc getEndLoc() const override { return EndLoc; }
265   void print(raw_ostream &OS) const override;
266 
267   // Used by the TableGen code to add particular types of operand
268   // to an instruction.
269   void addRegOperands(MCInst &Inst, unsigned N) const {
270     assert(N == 1 && "Invalid number of operands");
271     Inst.addOperand(MCOperand::createReg(getReg()));
272   }
273   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
274     assert(N == 1 && "Invalid number of operands");
275     assert(Kind == KindAccessReg && "Invalid operand type");
276     Inst.addOperand(MCOperand::createImm(AccessReg));
277   }
278   void addImmOperands(MCInst &Inst, unsigned N) const {
279     assert(N == 1 && "Invalid number of operands");
280     addExpr(Inst, getImm());
281   }
282   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
283     assert(N == 2 && "Invalid number of operands");
284     assert(isMem(BDMem) && "Invalid operand type");
285     Inst.addOperand(MCOperand::createReg(Mem.Base));
286     addExpr(Inst, Mem.Disp);
287   }
288   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
289     assert(N == 3 && "Invalid number of operands");
290     assert(isMem(BDXMem) && "Invalid operand type");
291     Inst.addOperand(MCOperand::createReg(Mem.Base));
292     addExpr(Inst, Mem.Disp);
293     Inst.addOperand(MCOperand::createReg(Mem.Index));
294   }
295   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
296     assert(N == 3 && "Invalid number of operands");
297     assert(isMem(BDLMem) && "Invalid operand type");
298     Inst.addOperand(MCOperand::createReg(Mem.Base));
299     addExpr(Inst, Mem.Disp);
300     addExpr(Inst, Mem.Length);
301   }
302   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
303     assert(N == 2 && "Invalid number of operands");
304     assert(Kind == KindImmTLS && "Invalid operand type");
305     addExpr(Inst, ImmTLS.Imm);
306     if (ImmTLS.Sym)
307       addExpr(Inst, ImmTLS.Sym);
308   }
309 
310   // Used by the TableGen code to check for particular operand types.
311   bool isGR32() const { return isReg(GR32Reg); }
312   bool isGRH32() const { return isReg(GRH32Reg); }
313   bool isGRX32() const { return false; }
314   bool isGR64() const { return isReg(GR64Reg); }
315   bool isGR128() const { return isReg(GR128Reg); }
316   bool isADDR32() const { return isReg(ADDR32Reg); }
317   bool isADDR64() const { return isReg(ADDR64Reg); }
318   bool isADDR128() const { return false; }
319   bool isFP32() const { return isReg(FP32Reg); }
320   bool isFP64() const { return isReg(FP64Reg); }
321   bool isFP128() const { return isReg(FP128Reg); }
322   bool isVR32() const { return isReg(VR32Reg); }
323   bool isVR64() const { return isReg(VR64Reg); }
324   bool isVF128() const { return false; }
325   bool isVR128() const { return isReg(VR128Reg); }
326   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
327   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
328   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
329   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
330   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
331   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
332   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
333   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
334   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
335   bool isU1Imm() const { return isImm(0, 1); }
336   bool isU2Imm() const { return isImm(0, 3); }
337   bool isU3Imm() const { return isImm(0, 7); }
338   bool isU4Imm() const { return isImm(0, 15); }
339   bool isU6Imm() const { return isImm(0, 63); }
340   bool isU8Imm() const { return isImm(0, 255); }
341   bool isS8Imm() const { return isImm(-128, 127); }
342   bool isU12Imm() const { return isImm(0, 4095); }
343   bool isU16Imm() const { return isImm(0, 65535); }
344   bool isS16Imm() const { return isImm(-32768, 32767); }
345   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
346   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
347   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
348 };
349 
350 class SystemZAsmParser : public MCTargetAsmParser {
351 #define GET_ASSEMBLER_HEADER
352 #include "SystemZGenAsmMatcher.inc"
353 
354 private:
355   MCAsmParser &Parser;
356   enum RegisterGroup {
357     RegGR,
358     RegFP,
359     RegV,
360     RegAccess
361   };
362   struct Register {
363     RegisterGroup Group;
364     unsigned Num;
365     SMLoc StartLoc, EndLoc;
366   };
367 
368   bool parseRegister(Register &Reg);
369 
370   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
371                      bool IsAddress = false);
372 
373   OperandMatchResultTy parseRegister(OperandVector &Operands,
374                                      RegisterGroup Group, const unsigned *Regs,
375                                      RegisterKind Kind);
376 
377   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
378 
379   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
380                     unsigned &Index, bool &IsVector, const MCExpr *&Length,
381                     const unsigned *Regs, RegisterKind RegKind);
382 
383   bool ParseDirectiveInsn(SMLoc L);
384 
385   OperandMatchResultTy parseAddress(OperandVector &Operands,
386                                     MemoryKind MemKind, const unsigned *Regs,
387                                     RegisterKind RegKind);
388 
389   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
390                                   int64_t MaxVal, bool AllowTLS);
391 
392   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
393 
394 public:
395   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
396                    const MCInstrInfo &MII,
397                    const MCTargetOptions &Options)
398     : MCTargetAsmParser(Options, sti), Parser(parser) {
399     MCAsmParserExtension::Initialize(Parser);
400 
401     // Alias the .word directive to .short.
402     parser.addAliasForDirective(".word", ".short");
403 
404     // Initialize the set of available features.
405     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
406   }
407 
408   // Override MCTargetAsmParser.
409   bool ParseDirective(AsmToken DirectiveID) override;
410   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
411   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
412                         SMLoc NameLoc, OperandVector &Operands) override;
413   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
414                                OperandVector &Operands, MCStreamer &Out,
415                                uint64_t &ErrorInfo,
416                                bool MatchingInlineAsm) override;
417 
418   // Used by the TableGen code to parse particular operand types.
419   OperandMatchResultTy parseGR32(OperandVector &Operands) {
420     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
421   }
422   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
423     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
424   }
425   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
426     llvm_unreachable("GRX32 should only be used for pseudo instructions");
427   }
428   OperandMatchResultTy parseGR64(OperandVector &Operands) {
429     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
430   }
431   OperandMatchResultTy parseGR128(OperandVector &Operands) {
432     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
433   }
434   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
435     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
436   }
437   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
438     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
439   }
440   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
441     llvm_unreachable("Shouldn't be used as an operand");
442   }
443   OperandMatchResultTy parseFP32(OperandVector &Operands) {
444     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
445   }
446   OperandMatchResultTy parseFP64(OperandVector &Operands) {
447     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
448   }
449   OperandMatchResultTy parseFP128(OperandVector &Operands) {
450     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
451   }
452   OperandMatchResultTy parseVR32(OperandVector &Operands) {
453     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
454   }
455   OperandMatchResultTy parseVR64(OperandVector &Operands) {
456     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
457   }
458   OperandMatchResultTy parseVF128(OperandVector &Operands) {
459     llvm_unreachable("Shouldn't be used as an operand");
460   }
461   OperandMatchResultTy parseVR128(OperandVector &Operands) {
462     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
463   }
464   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
465     return parseAnyRegister(Operands);
466   }
467   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
468     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
469   }
470   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
471     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
472   }
473   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
474     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
475   }
476   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
477     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
478   }
479   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
480     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
481   }
482   OperandMatchResultTy parseAccessReg(OperandVector &Operands);
483   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
484     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
485   }
486   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
487     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
488   }
489   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
490     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
491   }
492   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
493     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
494   }
495 };
496 } // end anonymous namespace
497 
498 #define GET_REGISTER_MATCHER
499 #define GET_SUBTARGET_FEATURE_NAME
500 #define GET_MATCHER_IMPLEMENTATION
501 #include "SystemZGenAsmMatcher.inc"
502 
503 // Used for the .insn directives; contains information needed to parse the
504 // operands in the directive.
505 struct InsnMatchEntry {
506   StringRef Format;
507   uint64_t Opcode;
508   int32_t NumOperands;
509   MatchClassKind OperandKinds[5];
510 };
511 
512 // For equal_range comparison.
513 struct CompareInsn {
514   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
515     return LHS.Format < RHS;
516   }
517   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
518     return LHS < RHS.Format;
519   }
520 };
521 
522 // Table initializing information for parsing the .insn directive.
523 static struct InsnMatchEntry InsnMatchTable[] = {
524   /* Format, Opcode, NumOperands, OperandKinds */
525   { "e", SystemZ::InsnE, 1,
526     { MCK_U16Imm } },
527   { "ri", SystemZ::InsnRI, 3,
528     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
529   { "rie", SystemZ::InsnRIE, 4,
530     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
531   { "ril", SystemZ::InsnRIL, 3,
532     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
533   { "rilu", SystemZ::InsnRILU, 3,
534     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
535   { "ris", SystemZ::InsnRIS, 5,
536     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
537   { "rr", SystemZ::InsnRR, 3,
538     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
539   { "rre", SystemZ::InsnRRE, 3,
540     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
541   { "rrf", SystemZ::InsnRRF, 5,
542     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
543   { "rrs", SystemZ::InsnRRS, 5,
544     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
545   { "rs", SystemZ::InsnRS, 4,
546     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
547   { "rse", SystemZ::InsnRSE, 4,
548     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
549   { "rsi", SystemZ::InsnRSI, 4,
550     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
551   { "rsy", SystemZ::InsnRSY, 4,
552     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
553   { "rx", SystemZ::InsnRX, 3,
554     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
555   { "rxe", SystemZ::InsnRXE, 3,
556     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
557   { "rxf", SystemZ::InsnRXF, 4,
558     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
559   { "rxy", SystemZ::InsnRXY, 3,
560     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
561   { "s", SystemZ::InsnS, 2,
562     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
563   { "si", SystemZ::InsnSI, 3,
564     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
565   { "sil", SystemZ::InsnSIL, 3,
566     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
567   { "siy", SystemZ::InsnSIY, 3,
568     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
569   { "ss", SystemZ::InsnSS, 4,
570     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
571   { "sse", SystemZ::InsnSSE, 3,
572     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
573   { "ssf", SystemZ::InsnSSF, 4,
574     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
575 };
576 
577 void SystemZOperand::print(raw_ostream &OS) const {
578   llvm_unreachable("Not implemented");
579 }
580 
581 // Parse one register of the form %<prefix><number>.
582 bool SystemZAsmParser::parseRegister(Register &Reg) {
583   Reg.StartLoc = Parser.getTok().getLoc();
584 
585   // Eat the % prefix.
586   if (Parser.getTok().isNot(AsmToken::Percent))
587     return Error(Parser.getTok().getLoc(), "register expected");
588   Parser.Lex();
589 
590   // Expect a register name.
591   if (Parser.getTok().isNot(AsmToken::Identifier))
592     return Error(Reg.StartLoc, "invalid register");
593 
594   // Check that there's a prefix.
595   StringRef Name = Parser.getTok().getString();
596   if (Name.size() < 2)
597     return Error(Reg.StartLoc, "invalid register");
598   char Prefix = Name[0];
599 
600   // Treat the rest of the register name as a register number.
601   if (Name.substr(1).getAsInteger(10, Reg.Num))
602     return Error(Reg.StartLoc, "invalid register");
603 
604   // Look for valid combinations of prefix and number.
605   if (Prefix == 'r' && Reg.Num < 16)
606     Reg.Group = RegGR;
607   else if (Prefix == 'f' && Reg.Num < 16)
608     Reg.Group = RegFP;
609   else if (Prefix == 'v' && Reg.Num < 32)
610     Reg.Group = RegV;
611   else if (Prefix == 'a' && Reg.Num < 16)
612     Reg.Group = RegAccess;
613   else
614     return Error(Reg.StartLoc, "invalid register");
615 
616   Reg.EndLoc = Parser.getTok().getLoc();
617   Parser.Lex();
618   return false;
619 }
620 
621 // Parse a register of group Group.  If Regs is nonnull, use it to map
622 // the raw register number to LLVM numbering, with zero entries
623 // indicating an invalid register.  IsAddress says whether the
624 // register appears in an address context. Allow FP Group if expecting
625 // RegV Group, since the f-prefix yields the FP group even while used
626 // with vector instructions.
627 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
628                                      const unsigned *Regs, bool IsAddress) {
629   if (parseRegister(Reg))
630     return true;
631   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
632     return Error(Reg.StartLoc, "invalid operand for instruction");
633   if (Regs && Regs[Reg.Num] == 0)
634     return Error(Reg.StartLoc, "invalid register pair");
635   if (Reg.Num == 0 && IsAddress)
636     return Error(Reg.StartLoc, "%r0 used in an address");
637   if (Regs)
638     Reg.Num = Regs[Reg.Num];
639   return false;
640 }
641 
642 // Parse a register and add it to Operands.  The other arguments are as above.
643 SystemZAsmParser::OperandMatchResultTy
644 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
645                                 const unsigned *Regs, RegisterKind Kind) {
646   if (Parser.getTok().isNot(AsmToken::Percent))
647     return MatchOperand_NoMatch;
648 
649   Register Reg;
650   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
651   if (parseRegister(Reg, Group, Regs, IsAddress))
652     return MatchOperand_ParseFail;
653 
654   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
655                                                Reg.StartLoc, Reg.EndLoc));
656   return MatchOperand_Success;
657 }
658 
659 // Parse any type of register (including integers) and add it to Operands.
660 SystemZAsmParser::OperandMatchResultTy
661 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
662   // Handle integer values.
663   if (Parser.getTok().is(AsmToken::Integer)) {
664     const MCExpr *Register;
665     SMLoc StartLoc = Parser.getTok().getLoc();
666     if (Parser.parseExpression(Register))
667       return MatchOperand_ParseFail;
668 
669     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
670       int64_t Value = CE->getValue();
671       if (Value < 0 || Value > 15) {
672         Error(StartLoc, "invalid register");
673         return MatchOperand_ParseFail;
674       }
675     }
676 
677     SMLoc EndLoc =
678       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
679 
680     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
681   }
682   else {
683     Register Reg;
684     if (parseRegister(Reg))
685       return MatchOperand_ParseFail;
686 
687     // Map to the correct register kind.
688     RegisterKind Kind;
689     unsigned RegNo;
690     if (Reg.Group == RegGR) {
691       Kind = GR64Reg;
692       RegNo = SystemZMC::GR64Regs[Reg.Num];
693     }
694     else if (Reg.Group == RegFP) {
695       Kind = FP64Reg;
696       RegNo = SystemZMC::FP64Regs[Reg.Num];
697     }
698     else if (Reg.Group == RegV) {
699       Kind = VR128Reg;
700       RegNo = SystemZMC::VR128Regs[Reg.Num];
701     }
702     else {
703       return MatchOperand_ParseFail;
704     }
705 
706     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
707                                                  Reg.StartLoc, Reg.EndLoc));
708   }
709   return MatchOperand_Success;
710 }
711 
712 // Parse a memory operand into Base, Disp, Index and Length.
713 // Regs maps asm register numbers to LLVM register numbers and RegKind
714 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
715 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
716                                     unsigned &Index, bool &IsVector,
717                                     const MCExpr *&Length, const unsigned *Regs,
718                                     RegisterKind RegKind) {
719   // Parse the displacement, which must always be present.
720   if (getParser().parseExpression(Disp))
721     return true;
722 
723   // Parse the optional base and index.
724   Index = 0;
725   Base = 0;
726   IsVector = false;
727   Length = nullptr;
728   if (getLexer().is(AsmToken::LParen)) {
729     Parser.Lex();
730 
731     if (getLexer().is(AsmToken::Percent)) {
732       // Parse the first register and decide whether it's a base or an index.
733       Register Reg;
734       if (parseRegister(Reg))
735         return true;
736       if (Reg.Group == RegV) {
737         // A vector index register.  The base register is optional.
738         IsVector = true;
739         Index = SystemZMC::VR128Regs[Reg.Num];
740       } else if (Reg.Group == RegGR) {
741         if (Reg.Num == 0)
742           return Error(Reg.StartLoc, "%r0 used in an address");
743         // If the are two registers, the first one is the index and the
744         // second is the base.
745         if (getLexer().is(AsmToken::Comma))
746           Index = Regs[Reg.Num];
747         else
748           Base = Regs[Reg.Num];
749       } else
750         return Error(Reg.StartLoc, "invalid address register");
751     } else {
752       // Parse the length.
753       if (getParser().parseExpression(Length))
754         return true;
755     }
756 
757     // Check whether there's a second register.  It's the base if so.
758     if (getLexer().is(AsmToken::Comma)) {
759       Parser.Lex();
760       Register Reg;
761       if (parseRegister(Reg, RegGR, Regs, RegKind))
762         return true;
763       Base = Reg.Num;
764     }
765 
766     // Consume the closing bracket.
767     if (getLexer().isNot(AsmToken::RParen))
768       return Error(Parser.getTok().getLoc(), "unexpected token in address");
769     Parser.Lex();
770   }
771   return false;
772 }
773 
774 // Parse a memory operand and add it to Operands.  The other arguments
775 // are as above.
776 SystemZAsmParser::OperandMatchResultTy
777 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
778                                const unsigned *Regs, RegisterKind RegKind) {
779   SMLoc StartLoc = Parser.getTok().getLoc();
780   unsigned Base, Index;
781   bool IsVector;
782   const MCExpr *Disp;
783   const MCExpr *Length;
784   if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
785     return MatchOperand_ParseFail;
786 
787   if (IsVector && MemKind != BDVMem) {
788     Error(StartLoc, "invalid use of vector addressing");
789     return MatchOperand_ParseFail;
790   }
791 
792   if (!IsVector && MemKind == BDVMem) {
793     Error(StartLoc, "vector index required in address");
794     return MatchOperand_ParseFail;
795   }
796 
797   if (Index && MemKind != BDXMem && MemKind != BDVMem) {
798     Error(StartLoc, "invalid use of indexed addressing");
799     return MatchOperand_ParseFail;
800   }
801 
802   if (Length && MemKind != BDLMem) {
803     Error(StartLoc, "invalid use of length addressing");
804     return MatchOperand_ParseFail;
805   }
806 
807   if (!Length && MemKind == BDLMem) {
808     Error(StartLoc, "missing length in address");
809     return MatchOperand_ParseFail;
810   }
811 
812   SMLoc EndLoc =
813     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
814   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
815                                                Index, Length, StartLoc,
816                                                EndLoc));
817   return MatchOperand_Success;
818 }
819 
820 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
821   StringRef IDVal = DirectiveID.getIdentifier();
822 
823   if (IDVal == ".insn")
824     return ParseDirectiveInsn(DirectiveID.getLoc());
825 
826   return true;
827 }
828 
829 /// ParseDirectiveInsn
830 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
831 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
832   MCAsmParser &Parser = getParser();
833 
834   // Expect instruction format as identifier.
835   StringRef Format;
836   SMLoc ErrorLoc = Parser.getTok().getLoc();
837   if (Parser.parseIdentifier(Format))
838     return Error(ErrorLoc, "expected instruction format");
839 
840   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
841 
842   // Find entry for this format in InsnMatchTable.
843   auto EntryRange =
844     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
845                      Format, CompareInsn());
846 
847   // If first == second, couldn't find a match in the table.
848   if (EntryRange.first == EntryRange.second)
849     return Error(ErrorLoc, "unrecognized format");
850 
851   struct InsnMatchEntry *Entry = EntryRange.first;
852 
853   // Format should match from equal_range.
854   assert(Entry->Format == Format);
855 
856   // Parse the following operands using the table's information.
857   for (int i = 0; i < Entry->NumOperands; i++) {
858     MatchClassKind Kind = Entry->OperandKinds[i];
859 
860     SMLoc StartLoc = Parser.getTok().getLoc();
861 
862     // Always expect commas as separators for operands.
863     if (getLexer().isNot(AsmToken::Comma))
864       return Error(StartLoc, "unexpected token in directive");
865     Lex();
866 
867     // Parse operands.
868     OperandMatchResultTy ResTy;
869     if (Kind == MCK_AnyReg)
870       ResTy = parseAnyReg(Operands);
871     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
872       ResTy = parseBDXAddr64(Operands);
873     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
874       ResTy = parseBDAddr64(Operands);
875     else if (Kind == MCK_PCRel32)
876       ResTy = parsePCRel32(Operands);
877     else if (Kind == MCK_PCRel16)
878       ResTy = parsePCRel16(Operands);
879     else {
880       // Only remaining operand kind is an immediate.
881       const MCExpr *Expr;
882       SMLoc StartLoc = Parser.getTok().getLoc();
883 
884       // Expect immediate expression.
885       if (Parser.parseExpression(Expr))
886         return Error(StartLoc, "unexpected token in directive");
887 
888       SMLoc EndLoc =
889         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
890 
891       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
892       ResTy = MatchOperand_Success;
893     }
894 
895     if (ResTy != MatchOperand_Success)
896       return true;
897   }
898 
899   // Build the instruction with the parsed operands.
900   MCInst Inst = MCInstBuilder(Entry->Opcode);
901 
902   for (size_t i = 0; i < Operands.size(); i++) {
903     MCParsedAsmOperand &Operand = *Operands[i];
904     MatchClassKind Kind = Entry->OperandKinds[i];
905 
906     // Verify operand.
907     unsigned Res = validateOperandClass(Operand, Kind);
908     if (Res != Match_Success)
909       return Error(Operand.getStartLoc(), "unexpected operand type");
910 
911     // Add operands to instruction.
912     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
913     if (ZOperand.isReg())
914       ZOperand.addRegOperands(Inst, 1);
915     else if (ZOperand.isMem(BDMem))
916       ZOperand.addBDAddrOperands(Inst, 2);
917     else if (ZOperand.isMem(BDXMem))
918       ZOperand.addBDXAddrOperands(Inst, 3);
919     else if (ZOperand.isImm())
920       ZOperand.addImmOperands(Inst, 1);
921     else
922       llvm_unreachable("unexpected operand type");
923   }
924 
925   // Emit as a regular instruction.
926   Parser.getStreamer().EmitInstruction(Inst, getSTI());
927 
928   return false;
929 }
930 
931 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
932                                      SMLoc &EndLoc) {
933   Register Reg;
934   if (parseRegister(Reg))
935     return true;
936   if (Reg.Group == RegGR)
937     RegNo = SystemZMC::GR64Regs[Reg.Num];
938   else if (Reg.Group == RegFP)
939     RegNo = SystemZMC::FP64Regs[Reg.Num];
940   else if (Reg.Group == RegV)
941     RegNo = SystemZMC::VR128Regs[Reg.Num];
942   else
943     // FIXME: Access registers aren't modelled as LLVM registers yet.
944     return Error(Reg.StartLoc, "invalid operand for instruction");
945   StartLoc = Reg.StartLoc;
946   EndLoc = Reg.EndLoc;
947   return false;
948 }
949 
950 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
951                                         StringRef Name, SMLoc NameLoc,
952                                         OperandVector &Operands) {
953   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
954 
955   // Read the remaining operands.
956   if (getLexer().isNot(AsmToken::EndOfStatement)) {
957     // Read the first operand.
958     if (parseOperand(Operands, Name)) {
959       Parser.eatToEndOfStatement();
960       return true;
961     }
962 
963     // Read any subsequent operands.
964     while (getLexer().is(AsmToken::Comma)) {
965       Parser.Lex();
966       if (parseOperand(Operands, Name)) {
967         Parser.eatToEndOfStatement();
968         return true;
969       }
970     }
971     if (getLexer().isNot(AsmToken::EndOfStatement)) {
972       SMLoc Loc = getLexer().getLoc();
973       Parser.eatToEndOfStatement();
974       return Error(Loc, "unexpected token in argument list");
975     }
976   }
977 
978   // Consume the EndOfStatement.
979   Parser.Lex();
980   return false;
981 }
982 
983 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
984                                     StringRef Mnemonic) {
985   // Check if the current operand has a custom associated parser, if so, try to
986   // custom parse the operand, or fallback to the general approach.
987   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
988   if (ResTy == MatchOperand_Success)
989     return false;
990 
991   // If there wasn't a custom match, try the generic matcher below. Otherwise,
992   // there was a match, but an error occurred, in which case, just return that
993   // the operand parsing failed.
994   if (ResTy == MatchOperand_ParseFail)
995     return true;
996 
997   // Check for a register.  All real register operands should have used
998   // a context-dependent parse routine, which gives the required register
999   // class.  The code is here to mop up other cases, like those where
1000   // the instruction isn't recognized.
1001   if (Parser.getTok().is(AsmToken::Percent)) {
1002     Register Reg;
1003     if (parseRegister(Reg))
1004       return true;
1005     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1006     return false;
1007   }
1008 
1009   // The only other type of operand is an immediate or address.  As above,
1010   // real address operands should have used a context-dependent parse routine,
1011   // so we treat any plain expression as an immediate.
1012   SMLoc StartLoc = Parser.getTok().getLoc();
1013   unsigned Base, Index;
1014   bool IsVector;
1015   const MCExpr *Expr, *Length;
1016   if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs,
1017                    ADDR64Reg))
1018     return true;
1019 
1020   SMLoc EndLoc =
1021     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1022   if (Base || Index || Length)
1023     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1024   else
1025     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1026   return false;
1027 }
1028 
1029 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1030                                                OperandVector &Operands,
1031                                                MCStreamer &Out,
1032                                                uint64_t &ErrorInfo,
1033                                                bool MatchingInlineAsm) {
1034   MCInst Inst;
1035   unsigned MatchResult;
1036 
1037   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1038                                      MatchingInlineAsm);
1039   switch (MatchResult) {
1040   case Match_Success:
1041     Inst.setLoc(IDLoc);
1042     Out.EmitInstruction(Inst, getSTI());
1043     return false;
1044 
1045   case Match_MissingFeature: {
1046     assert(ErrorInfo && "Unknown missing feature!");
1047     // Special case the error message for the very common case where only
1048     // a single subtarget feature is missing
1049     std::string Msg = "instruction requires:";
1050     uint64_t Mask = 1;
1051     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1052       if (ErrorInfo & Mask) {
1053         Msg += " ";
1054         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1055       }
1056       Mask <<= 1;
1057     }
1058     return Error(IDLoc, Msg);
1059   }
1060 
1061   case Match_InvalidOperand: {
1062     SMLoc ErrorLoc = IDLoc;
1063     if (ErrorInfo != ~0ULL) {
1064       if (ErrorInfo >= Operands.size())
1065         return Error(IDLoc, "too few operands for instruction");
1066 
1067       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1068       if (ErrorLoc == SMLoc())
1069         ErrorLoc = IDLoc;
1070     }
1071     return Error(ErrorLoc, "invalid operand for instruction");
1072   }
1073 
1074   case Match_MnemonicFail:
1075     return Error(IDLoc, "invalid instruction");
1076   }
1077 
1078   llvm_unreachable("Unexpected match type");
1079 }
1080 
1081 SystemZAsmParser::OperandMatchResultTy
1082 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
1083   if (Parser.getTok().isNot(AsmToken::Percent))
1084     return MatchOperand_NoMatch;
1085 
1086   Register Reg;
1087   if (parseRegister(Reg, RegAccess, nullptr))
1088     return MatchOperand_ParseFail;
1089 
1090   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
1091                                                      Reg.StartLoc,
1092                                                      Reg.EndLoc));
1093   return MatchOperand_Success;
1094 }
1095 
1096 SystemZAsmParser::OperandMatchResultTy
1097 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1098                              int64_t MaxVal, bool AllowTLS) {
1099   MCContext &Ctx = getContext();
1100   MCStreamer &Out = getStreamer();
1101   const MCExpr *Expr;
1102   SMLoc StartLoc = Parser.getTok().getLoc();
1103   if (getParser().parseExpression(Expr))
1104     return MatchOperand_NoMatch;
1105 
1106   // For consistency with the GNU assembler, treat immediates as offsets
1107   // from ".".
1108   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1109     int64_t Value = CE->getValue();
1110     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1111       Error(StartLoc, "offset out of range");
1112       return MatchOperand_ParseFail;
1113     }
1114     MCSymbol *Sym = Ctx.createTempSymbol();
1115     Out.EmitLabel(Sym);
1116     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1117                                                  Ctx);
1118     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1119   }
1120 
1121   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1122   const MCExpr *Sym = nullptr;
1123   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1124     Parser.Lex();
1125 
1126     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1127       Error(Parser.getTok().getLoc(), "unexpected token");
1128       return MatchOperand_ParseFail;
1129     }
1130 
1131     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1132     StringRef Name = Parser.getTok().getString();
1133     if (Name == "tls_gdcall")
1134       Kind = MCSymbolRefExpr::VK_TLSGD;
1135     else if (Name == "tls_ldcall")
1136       Kind = MCSymbolRefExpr::VK_TLSLDM;
1137     else {
1138       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1139       return MatchOperand_ParseFail;
1140     }
1141     Parser.Lex();
1142 
1143     if (Parser.getTok().isNot(AsmToken::Colon)) {
1144       Error(Parser.getTok().getLoc(), "unexpected token");
1145       return MatchOperand_ParseFail;
1146     }
1147     Parser.Lex();
1148 
1149     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1150       Error(Parser.getTok().getLoc(), "unexpected token");
1151       return MatchOperand_ParseFail;
1152     }
1153 
1154     StringRef Identifier = Parser.getTok().getString();
1155     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1156                                   Kind, Ctx);
1157     Parser.Lex();
1158   }
1159 
1160   SMLoc EndLoc =
1161     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1162 
1163   if (AllowTLS)
1164     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1165                                                     StartLoc, EndLoc));
1166   else
1167     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1168 
1169   return MatchOperand_Success;
1170 }
1171 
1172 // Force static initialization.
1173 extern "C" void LLVMInitializeSystemZAsmParser() {
1174   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
1175 }
1176