1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCInstBuilder.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 // Return true if Expr is in the range [MinValue, MaxValue].
25 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
26   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
27     int64_t Value = CE->getValue();
28     return Value >= MinValue && Value <= MaxValue;
29   }
30   return false;
31 }
32 
33 namespace {
34 enum RegisterKind {
35   GR32Reg,
36   GRH32Reg,
37   GR64Reg,
38   GR128Reg,
39   ADDR32Reg,
40   ADDR64Reg,
41   FP32Reg,
42   FP64Reg,
43   FP128Reg,
44   VR32Reg,
45   VR64Reg,
46   VR128Reg,
47   AR32Reg,
48 };
49 
50 enum MemoryKind {
51   BDMem,
52   BDXMem,
53   BDLMem,
54   BDRMem,
55   BDVMem
56 };
57 
58 class SystemZOperand : public MCParsedAsmOperand {
59 public:
60 private:
61   enum OperandKind {
62     KindInvalid,
63     KindToken,
64     KindReg,
65     KindImm,
66     KindImmTLS,
67     KindMem
68   };
69 
70   OperandKind Kind;
71   SMLoc StartLoc, EndLoc;
72 
73   // A string of length Length, starting at Data.
74   struct TokenOp {
75     const char *Data;
76     unsigned Length;
77   };
78 
79   // LLVM register Num, which has kind Kind.  In some ways it might be
80   // easier for this class to have a register bank (general, floating-point
81   // or access) and a raw register number (0-15).  This would postpone the
82   // interpretation of the operand to the add*() methods and avoid the need
83   // for context-dependent parsing.  However, we do things the current way
84   // because of the virtual getReg() method, which needs to distinguish
85   // between (say) %r0 used as a single register and %r0 used as a pair.
86   // Context-dependent parsing can also give us slightly better error
87   // messages when invalid pairs like %r1 are used.
88   struct RegOp {
89     RegisterKind Kind;
90     unsigned Num;
91   };
92 
93   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
94   // MemKind says what type of memory this is and RegKind says what type
95   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
96   // length for D(L,B)-style operands, otherwise it is null.
97   struct MemOp {
98     unsigned Base : 12;
99     unsigned Index : 12;
100     unsigned MemKind : 4;
101     unsigned RegKind : 4;
102     const MCExpr *Disp;
103     union {
104       const MCExpr *Imm;
105       unsigned Reg;
106     } Length;
107   };
108 
109   // Imm is an immediate operand, and Sym is an optional TLS symbol
110   // for use with a __tls_get_offset marker relocation.
111   struct ImmTLSOp {
112     const MCExpr *Imm;
113     const MCExpr *Sym;
114   };
115 
116   union {
117     TokenOp Token;
118     RegOp Reg;
119     const MCExpr *Imm;
120     ImmTLSOp ImmTLS;
121     MemOp Mem;
122   };
123 
124   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
125     // Add as immediates when possible.  Null MCExpr = 0.
126     if (!Expr)
127       Inst.addOperand(MCOperand::createImm(0));
128     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
129       Inst.addOperand(MCOperand::createImm(CE->getValue()));
130     else
131       Inst.addOperand(MCOperand::createExpr(Expr));
132   }
133 
134 public:
135   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
136       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
137 
138   // Create particular kinds of operand.
139   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
140                                                        SMLoc EndLoc) {
141     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
142   }
143   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
144     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
145     Op->Token.Data = Str.data();
146     Op->Token.Length = Str.size();
147     return Op;
148   }
149   static std::unique_ptr<SystemZOperand>
150   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
151     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
152     Op->Reg.Kind = Kind;
153     Op->Reg.Num = Num;
154     return Op;
155   }
156   static std::unique_ptr<SystemZOperand>
157   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
158     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
159     Op->Imm = Expr;
160     return Op;
161   }
162   static std::unique_ptr<SystemZOperand>
163   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
164             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
165             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
166     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
167     Op->Mem.MemKind = MemKind;
168     Op->Mem.RegKind = RegKind;
169     Op->Mem.Base = Base;
170     Op->Mem.Index = Index;
171     Op->Mem.Disp = Disp;
172     if (MemKind == BDLMem)
173       Op->Mem.Length.Imm = LengthImm;
174     if (MemKind == BDRMem)
175       Op->Mem.Length.Reg = LengthReg;
176     return Op;
177   }
178   static std::unique_ptr<SystemZOperand>
179   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
180                SMLoc StartLoc, SMLoc EndLoc) {
181     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
182     Op->ImmTLS.Imm = Imm;
183     Op->ImmTLS.Sym = Sym;
184     return Op;
185   }
186 
187   // Token operands
188   bool isToken() const override {
189     return Kind == KindToken;
190   }
191   StringRef getToken() const {
192     assert(Kind == KindToken && "Not a token");
193     return StringRef(Token.Data, Token.Length);
194   }
195 
196   // Register operands.
197   bool isReg() const override {
198     return Kind == KindReg;
199   }
200   bool isReg(RegisterKind RegKind) const {
201     return Kind == KindReg && Reg.Kind == RegKind;
202   }
203   unsigned getReg() const override {
204     assert(Kind == KindReg && "Not a register");
205     return Reg.Num;
206   }
207 
208   // Immediate operands.
209   bool isImm() const override {
210     return Kind == KindImm;
211   }
212   bool isImm(int64_t MinValue, int64_t MaxValue) const {
213     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
214   }
215   const MCExpr *getImm() const {
216     assert(Kind == KindImm && "Not an immediate");
217     return Imm;
218   }
219 
220   // Immediate operands with optional TLS symbol.
221   bool isImmTLS() const {
222     return Kind == KindImmTLS;
223   }
224 
225   // Memory operands.
226   bool isMem() const override {
227     return Kind == KindMem;
228   }
229   bool isMem(MemoryKind MemKind) const {
230     return (Kind == KindMem &&
231             (Mem.MemKind == MemKind ||
232              // A BDMem can be treated as a BDXMem in which the index
233              // register field is 0.
234              (Mem.MemKind == BDMem && MemKind == BDXMem)));
235   }
236   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
237     return isMem(MemKind) && Mem.RegKind == RegKind;
238   }
239   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
240     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
241   }
242   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
243     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
244   }
245   bool isMemDisp12Len8(RegisterKind RegKind) const {
246     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
247   }
248 
249   // Override MCParsedAsmOperand.
250   SMLoc getStartLoc() const override { return StartLoc; }
251   SMLoc getEndLoc() const override { return EndLoc; }
252   void print(raw_ostream &OS) const override;
253 
254   // Used by the TableGen code to add particular types of operand
255   // to an instruction.
256   void addRegOperands(MCInst &Inst, unsigned N) const {
257     assert(N == 1 && "Invalid number of operands");
258     Inst.addOperand(MCOperand::createReg(getReg()));
259   }
260   void addImmOperands(MCInst &Inst, unsigned N) const {
261     assert(N == 1 && "Invalid number of operands");
262     addExpr(Inst, getImm());
263   }
264   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
265     assert(N == 2 && "Invalid number of operands");
266     assert(isMem(BDMem) && "Invalid operand type");
267     Inst.addOperand(MCOperand::createReg(Mem.Base));
268     addExpr(Inst, Mem.Disp);
269   }
270   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
271     assert(N == 3 && "Invalid number of operands");
272     assert(isMem(BDXMem) && "Invalid operand type");
273     Inst.addOperand(MCOperand::createReg(Mem.Base));
274     addExpr(Inst, Mem.Disp);
275     Inst.addOperand(MCOperand::createReg(Mem.Index));
276   }
277   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
278     assert(N == 3 && "Invalid number of operands");
279     assert(isMem(BDLMem) && "Invalid operand type");
280     Inst.addOperand(MCOperand::createReg(Mem.Base));
281     addExpr(Inst, Mem.Disp);
282     addExpr(Inst, Mem.Length.Imm);
283   }
284   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
285     assert(N == 3 && "Invalid number of operands");
286     assert(isMem(BDRMem) && "Invalid operand type");
287     Inst.addOperand(MCOperand::createReg(Mem.Base));
288     addExpr(Inst, Mem.Disp);
289     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
290   }
291   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
292     assert(N == 3 && "Invalid number of operands");
293     assert(isMem(BDVMem) && "Invalid operand type");
294     Inst.addOperand(MCOperand::createReg(Mem.Base));
295     addExpr(Inst, Mem.Disp);
296     Inst.addOperand(MCOperand::createReg(Mem.Index));
297   }
298   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
299     assert(N == 2 && "Invalid number of operands");
300     assert(Kind == KindImmTLS && "Invalid operand type");
301     addExpr(Inst, ImmTLS.Imm);
302     if (ImmTLS.Sym)
303       addExpr(Inst, ImmTLS.Sym);
304   }
305 
306   // Used by the TableGen code to check for particular operand types.
307   bool isGR32() const { return isReg(GR32Reg); }
308   bool isGRH32() const { return isReg(GRH32Reg); }
309   bool isGRX32() const { return false; }
310   bool isGR64() const { return isReg(GR64Reg); }
311   bool isGR128() const { return isReg(GR128Reg); }
312   bool isADDR32() const { return isReg(ADDR32Reg); }
313   bool isADDR64() const { return isReg(ADDR64Reg); }
314   bool isADDR128() const { return false; }
315   bool isFP32() const { return isReg(FP32Reg); }
316   bool isFP64() const { return isReg(FP64Reg); }
317   bool isFP128() const { return isReg(FP128Reg); }
318   bool isVR32() const { return isReg(VR32Reg); }
319   bool isVR64() const { return isReg(VR64Reg); }
320   bool isVF128() const { return false; }
321   bool isVR128() const { return isReg(VR128Reg); }
322   bool isAR32() const { return isReg(AR32Reg); }
323   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
324   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
325   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
326   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
327   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
328   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
329   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
330   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
331   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
332   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
333   bool isU1Imm() const { return isImm(0, 1); }
334   bool isU2Imm() const { return isImm(0, 3); }
335   bool isU3Imm() const { return isImm(0, 7); }
336   bool isU4Imm() const { return isImm(0, 15); }
337   bool isU6Imm() const { return isImm(0, 63); }
338   bool isU8Imm() const { return isImm(0, 255); }
339   bool isS8Imm() const { return isImm(-128, 127); }
340   bool isU12Imm() const { return isImm(0, 4095); }
341   bool isU16Imm() const { return isImm(0, 65535); }
342   bool isS16Imm() const { return isImm(-32768, 32767); }
343   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
344   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
345   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
346 };
347 
348 class SystemZAsmParser : public MCTargetAsmParser {
349 #define GET_ASSEMBLER_HEADER
350 #include "SystemZGenAsmMatcher.inc"
351 
352 private:
353   MCAsmParser &Parser;
354   enum RegisterGroup {
355     RegGR,
356     RegFP,
357     RegV,
358     RegAR
359   };
360   struct Register {
361     RegisterGroup Group;
362     unsigned Num;
363     SMLoc StartLoc, EndLoc;
364   };
365 
366   bool parseRegister(Register &Reg);
367 
368   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
369                      bool IsAddress = false);
370 
371   OperandMatchResultTy parseRegister(OperandVector &Operands,
372                                      RegisterGroup Group, const unsigned *Regs,
373                                      RegisterKind Kind);
374 
375   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
376 
377   bool parseAddress(bool &HaveReg1, Register &Reg1,
378                     bool &HaveReg2, Register &Reg2,
379                     const MCExpr *&Disp, const MCExpr *&Length);
380   bool parseAddressRegister(Register &Reg);
381 
382   bool ParseDirectiveInsn(SMLoc L);
383 
384   OperandMatchResultTy parseAddress(OperandVector &Operands,
385                                     MemoryKind MemKind, const unsigned *Regs,
386                                     RegisterKind RegKind);
387 
388   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
389                                   int64_t MaxVal, bool AllowTLS);
390 
391   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
392 
393 public:
394   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
395                    const MCInstrInfo &MII,
396                    const MCTargetOptions &Options)
397     : MCTargetAsmParser(Options, sti), Parser(parser) {
398     MCAsmParserExtension::Initialize(Parser);
399 
400     // Alias the .word directive to .short.
401     parser.addAliasForDirective(".word", ".short");
402 
403     // Initialize the set of available features.
404     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
405   }
406 
407   // Override MCTargetAsmParser.
408   bool ParseDirective(AsmToken DirectiveID) override;
409   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
410   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
411                         SMLoc NameLoc, OperandVector &Operands) override;
412   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
413                                OperandVector &Operands, MCStreamer &Out,
414                                uint64_t &ErrorInfo,
415                                bool MatchingInlineAsm) override;
416 
417   // Used by the TableGen code to parse particular operand types.
418   OperandMatchResultTy parseGR32(OperandVector &Operands) {
419     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
420   }
421   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
422     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
423   }
424   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
425     llvm_unreachable("GRX32 should only be used for pseudo instructions");
426   }
427   OperandMatchResultTy parseGR64(OperandVector &Operands) {
428     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
429   }
430   OperandMatchResultTy parseGR128(OperandVector &Operands) {
431     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
432   }
433   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
434     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
435   }
436   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
437     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
438   }
439   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
440     llvm_unreachable("Shouldn't be used as an operand");
441   }
442   OperandMatchResultTy parseFP32(OperandVector &Operands) {
443     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
444   }
445   OperandMatchResultTy parseFP64(OperandVector &Operands) {
446     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
447   }
448   OperandMatchResultTy parseFP128(OperandVector &Operands) {
449     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
450   }
451   OperandMatchResultTy parseVR32(OperandVector &Operands) {
452     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
453   }
454   OperandMatchResultTy parseVR64(OperandVector &Operands) {
455     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
456   }
457   OperandMatchResultTy parseVF128(OperandVector &Operands) {
458     llvm_unreachable("Shouldn't be used as an operand");
459   }
460   OperandMatchResultTy parseVR128(OperandVector &Operands) {
461     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
462   }
463   OperandMatchResultTy parseAR32(OperandVector &Operands) {
464     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
465   }
466   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
467     return parseAnyRegister(Operands);
468   }
469   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
470     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
471   }
472   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
473     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
474   }
475   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
476     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
477   }
478   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
479     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
480   }
481   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
482     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
483   }
484   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
485     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
486   }
487   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
488     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
489   }
490   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
491     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
492   }
493   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
494     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
495   }
496   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
497     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
498   }
499   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
500     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
501   }
502   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
503     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
504   }
505 };
506 } // end anonymous namespace
507 
508 #define GET_REGISTER_MATCHER
509 #define GET_SUBTARGET_FEATURE_NAME
510 #define GET_MATCHER_IMPLEMENTATION
511 #include "SystemZGenAsmMatcher.inc"
512 
513 // Used for the .insn directives; contains information needed to parse the
514 // operands in the directive.
515 struct InsnMatchEntry {
516   StringRef Format;
517   uint64_t Opcode;
518   int32_t NumOperands;
519   MatchClassKind OperandKinds[5];
520 };
521 
522 // For equal_range comparison.
523 struct CompareInsn {
524   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
525     return LHS.Format < RHS;
526   }
527   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
528     return LHS < RHS.Format;
529   }
530   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
531     return LHS.Format < RHS.Format;
532   }
533 };
534 
535 // Table initializing information for parsing the .insn directive.
536 static struct InsnMatchEntry InsnMatchTable[] = {
537   /* Format, Opcode, NumOperands, OperandKinds */
538   { "e", SystemZ::InsnE, 1,
539     { MCK_U16Imm } },
540   { "ri", SystemZ::InsnRI, 3,
541     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
542   { "rie", SystemZ::InsnRIE, 4,
543     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
544   { "ril", SystemZ::InsnRIL, 3,
545     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
546   { "rilu", SystemZ::InsnRILU, 3,
547     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
548   { "ris", SystemZ::InsnRIS, 5,
549     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
550   { "rr", SystemZ::InsnRR, 3,
551     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
552   { "rre", SystemZ::InsnRRE, 3,
553     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
554   { "rrf", SystemZ::InsnRRF, 5,
555     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
556   { "rrs", SystemZ::InsnRRS, 5,
557     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
558   { "rs", SystemZ::InsnRS, 4,
559     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
560   { "rse", SystemZ::InsnRSE, 4,
561     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
562   { "rsi", SystemZ::InsnRSI, 4,
563     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
564   { "rsy", SystemZ::InsnRSY, 4,
565     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
566   { "rx", SystemZ::InsnRX, 3,
567     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
568   { "rxe", SystemZ::InsnRXE, 3,
569     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
570   { "rxf", SystemZ::InsnRXF, 4,
571     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
572   { "rxy", SystemZ::InsnRXY, 3,
573     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
574   { "s", SystemZ::InsnS, 2,
575     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
576   { "si", SystemZ::InsnSI, 3,
577     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
578   { "sil", SystemZ::InsnSIL, 3,
579     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
580   { "siy", SystemZ::InsnSIY, 3,
581     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
582   { "ss", SystemZ::InsnSS, 4,
583     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
584   { "sse", SystemZ::InsnSSE, 3,
585     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
586   { "ssf", SystemZ::InsnSSF, 4,
587     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
588 };
589 
590 void SystemZOperand::print(raw_ostream &OS) const {
591   llvm_unreachable("Not implemented");
592 }
593 
594 // Parse one register of the form %<prefix><number>.
595 bool SystemZAsmParser::parseRegister(Register &Reg) {
596   Reg.StartLoc = Parser.getTok().getLoc();
597 
598   // Eat the % prefix.
599   if (Parser.getTok().isNot(AsmToken::Percent))
600     return Error(Parser.getTok().getLoc(), "register expected");
601   Parser.Lex();
602 
603   // Expect a register name.
604   if (Parser.getTok().isNot(AsmToken::Identifier))
605     return Error(Reg.StartLoc, "invalid register");
606 
607   // Check that there's a prefix.
608   StringRef Name = Parser.getTok().getString();
609   if (Name.size() < 2)
610     return Error(Reg.StartLoc, "invalid register");
611   char Prefix = Name[0];
612 
613   // Treat the rest of the register name as a register number.
614   if (Name.substr(1).getAsInteger(10, Reg.Num))
615     return Error(Reg.StartLoc, "invalid register");
616 
617   // Look for valid combinations of prefix and number.
618   if (Prefix == 'r' && Reg.Num < 16)
619     Reg.Group = RegGR;
620   else if (Prefix == 'f' && Reg.Num < 16)
621     Reg.Group = RegFP;
622   else if (Prefix == 'v' && Reg.Num < 32)
623     Reg.Group = RegV;
624   else if (Prefix == 'a' && Reg.Num < 16)
625     Reg.Group = RegAR;
626   else
627     return Error(Reg.StartLoc, "invalid register");
628 
629   Reg.EndLoc = Parser.getTok().getLoc();
630   Parser.Lex();
631   return false;
632 }
633 
634 // Parse a register of group Group.  If Regs is nonnull, use it to map
635 // the raw register number to LLVM numbering, with zero entries
636 // indicating an invalid register.  IsAddress says whether the
637 // register appears in an address context. Allow FP Group if expecting
638 // RegV Group, since the f-prefix yields the FP group even while used
639 // with vector instructions.
640 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
641                                      const unsigned *Regs, bool IsAddress) {
642   if (parseRegister(Reg))
643     return true;
644   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
645     return Error(Reg.StartLoc, "invalid operand for instruction");
646   if (Regs && Regs[Reg.Num] == 0)
647     return Error(Reg.StartLoc, "invalid register pair");
648   if (Reg.Num == 0 && IsAddress)
649     return Error(Reg.StartLoc, "%r0 used in an address");
650   if (Regs)
651     Reg.Num = Regs[Reg.Num];
652   return false;
653 }
654 
655 // Parse a register and add it to Operands.  The other arguments are as above.
656 OperandMatchResultTy
657 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
658                                 const unsigned *Regs, RegisterKind Kind) {
659   if (Parser.getTok().isNot(AsmToken::Percent))
660     return MatchOperand_NoMatch;
661 
662   Register Reg;
663   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
664   if (parseRegister(Reg, Group, Regs, IsAddress))
665     return MatchOperand_ParseFail;
666 
667   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
668                                                Reg.StartLoc, Reg.EndLoc));
669   return MatchOperand_Success;
670 }
671 
672 // Parse any type of register (including integers) and add it to Operands.
673 OperandMatchResultTy
674 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
675   // Handle integer values.
676   if (Parser.getTok().is(AsmToken::Integer)) {
677     const MCExpr *Register;
678     SMLoc StartLoc = Parser.getTok().getLoc();
679     if (Parser.parseExpression(Register))
680       return MatchOperand_ParseFail;
681 
682     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
683       int64_t Value = CE->getValue();
684       if (Value < 0 || Value > 15) {
685         Error(StartLoc, "invalid register");
686         return MatchOperand_ParseFail;
687       }
688     }
689 
690     SMLoc EndLoc =
691       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
692 
693     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
694   }
695   else {
696     Register Reg;
697     if (parseRegister(Reg))
698       return MatchOperand_ParseFail;
699 
700     // Map to the correct register kind.
701     RegisterKind Kind;
702     unsigned RegNo;
703     if (Reg.Group == RegGR) {
704       Kind = GR64Reg;
705       RegNo = SystemZMC::GR64Regs[Reg.Num];
706     }
707     else if (Reg.Group == RegFP) {
708       Kind = FP64Reg;
709       RegNo = SystemZMC::FP64Regs[Reg.Num];
710     }
711     else if (Reg.Group == RegV) {
712       Kind = VR128Reg;
713       RegNo = SystemZMC::VR128Regs[Reg.Num];
714     }
715     else if (Reg.Group == RegAR) {
716       Kind = AR32Reg;
717       RegNo = SystemZMC::AR32Regs[Reg.Num];
718     }
719     else {
720       return MatchOperand_ParseFail;
721     }
722 
723     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
724                                                  Reg.StartLoc, Reg.EndLoc));
725   }
726   return MatchOperand_Success;
727 }
728 
729 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
730 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
731                                     bool &HaveReg2, Register &Reg2,
732                                     const MCExpr *&Disp,
733                                     const MCExpr *&Length) {
734   // Parse the displacement, which must always be present.
735   if (getParser().parseExpression(Disp))
736     return true;
737 
738   // Parse the optional base and index.
739   HaveReg1 = false;
740   HaveReg2 = false;
741   Length = nullptr;
742   if (getLexer().is(AsmToken::LParen)) {
743     Parser.Lex();
744 
745     if (getLexer().is(AsmToken::Percent)) {
746       // Parse the first register.
747       HaveReg1 = true;
748       if (parseRegister(Reg1))
749         return true;
750     } else {
751       // Parse the length.
752       if (getParser().parseExpression(Length))
753         return true;
754     }
755 
756     // Check whether there's a second register.
757     if (getLexer().is(AsmToken::Comma)) {
758       Parser.Lex();
759       HaveReg2 = true;
760       if (parseRegister(Reg2))
761         return true;
762     }
763 
764     // Consume the closing bracket.
765     if (getLexer().isNot(AsmToken::RParen))
766       return Error(Parser.getTok().getLoc(), "unexpected token in address");
767     Parser.Lex();
768   }
769   return false;
770 }
771 
772 // Verify that Reg is a valid address register (base or index).
773 bool
774 SystemZAsmParser::parseAddressRegister(Register &Reg) {
775   if (Reg.Group == RegV) {
776     Error(Reg.StartLoc, "invalid use of vector addressing");
777     return true;
778   } else if (Reg.Group != RegGR) {
779     Error(Reg.StartLoc, "invalid address register");
780     return true;
781   } else if (Reg.Num == 0) {
782     Error(Reg.StartLoc, "%r0 used in an address");
783     return true;
784   }
785   return false;
786 }
787 
788 // Parse a memory operand and add it to Operands.  The other arguments
789 // are as above.
790 OperandMatchResultTy
791 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
792                                const unsigned *Regs, RegisterKind RegKind) {
793   SMLoc StartLoc = Parser.getTok().getLoc();
794   unsigned Base = 0, Index = 0, LengthReg = 0;
795   Register Reg1, Reg2;
796   bool HaveReg1, HaveReg2;
797   const MCExpr *Disp;
798   const MCExpr *Length;
799   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
800     return MatchOperand_ParseFail;
801 
802   switch (MemKind) {
803   case BDMem:
804     // If we have Reg1, it must be an address register.
805     if (HaveReg1) {
806       if (parseAddressRegister(Reg1))
807         return MatchOperand_ParseFail;
808       Base = Regs[Reg1.Num];
809     }
810     // There must be no Reg2 or length.
811     if (Length) {
812       Error(StartLoc, "invalid use of length addressing");
813       return MatchOperand_ParseFail;
814     }
815     if (HaveReg2) {
816       Error(StartLoc, "invalid use of indexed addressing");
817       return MatchOperand_ParseFail;
818     }
819     break;
820   case BDXMem:
821     // If we have Reg1, it must be an address register.
822     if (HaveReg1) {
823       if (parseAddressRegister(Reg1))
824         return MatchOperand_ParseFail;
825       // If the are two registers, the first one is the index and the
826       // second is the base.
827       if (HaveReg2)
828         Index = Regs[Reg1.Num];
829       else
830         Base = Regs[Reg1.Num];
831     }
832     // If we have Reg2, it must be an address register.
833     if (HaveReg2) {
834       if (parseAddressRegister(Reg2))
835         return MatchOperand_ParseFail;
836       Base = Regs[Reg2.Num];
837     }
838     // There must be no length.
839     if (Length) {
840       Error(StartLoc, "invalid use of length addressing");
841       return MatchOperand_ParseFail;
842     }
843     break;
844   case BDLMem:
845     // If we have Reg2, it must be an address register.
846     if (HaveReg2) {
847       if (parseAddressRegister(Reg2))
848         return MatchOperand_ParseFail;
849       Base = Regs[Reg2.Num];
850     }
851     // We cannot support base+index addressing.
852     if (HaveReg1 && HaveReg2) {
853       Error(StartLoc, "invalid use of indexed addressing");
854       return MatchOperand_ParseFail;
855     }
856     // We must have a length.
857     if (!Length) {
858       Error(StartLoc, "missing length in address");
859       return MatchOperand_ParseFail;
860     }
861     break;
862   case BDRMem:
863     // We must have Reg1, and it must be a GPR.
864     if (!HaveReg1 || Reg1.Group != RegGR) {
865       Error(StartLoc, "invalid operand for instruction");
866       return MatchOperand_ParseFail;
867     }
868     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
869     // If we have Reg2, it must be an address register.
870     if (HaveReg2) {
871       if (parseAddressRegister(Reg2))
872         return MatchOperand_ParseFail;
873       Base = Regs[Reg2.Num];
874     }
875     // There must be no length.
876     if (Length) {
877       Error(StartLoc, "invalid use of length addressing");
878       return MatchOperand_ParseFail;
879     }
880     break;
881   case BDVMem:
882     // We must have Reg1, and it must be a vector register.
883     if (!HaveReg1 || Reg1.Group != RegV) {
884       Error(StartLoc, "vector index required in address");
885       return MatchOperand_ParseFail;
886     }
887     Index = SystemZMC::VR128Regs[Reg1.Num];
888     // If we have Reg2, it must be an address register.
889     if (HaveReg2) {
890       if (parseAddressRegister(Reg2))
891         return MatchOperand_ParseFail;
892       Base = Regs[Reg2.Num];
893     }
894     // There must be no length.
895     if (Length) {
896       Error(StartLoc, "invalid use of length addressing");
897       return MatchOperand_ParseFail;
898     }
899     break;
900   }
901 
902   SMLoc EndLoc =
903     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
904   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
905                                                Index, Length, LengthReg,
906                                                StartLoc, EndLoc));
907   return MatchOperand_Success;
908 }
909 
910 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
911   StringRef IDVal = DirectiveID.getIdentifier();
912 
913   if (IDVal == ".insn")
914     return ParseDirectiveInsn(DirectiveID.getLoc());
915 
916   return true;
917 }
918 
919 /// ParseDirectiveInsn
920 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
921 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
922   MCAsmParser &Parser = getParser();
923 
924   // Expect instruction format as identifier.
925   StringRef Format;
926   SMLoc ErrorLoc = Parser.getTok().getLoc();
927   if (Parser.parseIdentifier(Format))
928     return Error(ErrorLoc, "expected instruction format");
929 
930   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
931 
932   // Find entry for this format in InsnMatchTable.
933   auto EntryRange =
934     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
935                      Format, CompareInsn());
936 
937   // If first == second, couldn't find a match in the table.
938   if (EntryRange.first == EntryRange.second)
939     return Error(ErrorLoc, "unrecognized format");
940 
941   struct InsnMatchEntry *Entry = EntryRange.first;
942 
943   // Format should match from equal_range.
944   assert(Entry->Format == Format);
945 
946   // Parse the following operands using the table's information.
947   for (int i = 0; i < Entry->NumOperands; i++) {
948     MatchClassKind Kind = Entry->OperandKinds[i];
949 
950     SMLoc StartLoc = Parser.getTok().getLoc();
951 
952     // Always expect commas as separators for operands.
953     if (getLexer().isNot(AsmToken::Comma))
954       return Error(StartLoc, "unexpected token in directive");
955     Lex();
956 
957     // Parse operands.
958     OperandMatchResultTy ResTy;
959     if (Kind == MCK_AnyReg)
960       ResTy = parseAnyReg(Operands);
961     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
962       ResTy = parseBDXAddr64(Operands);
963     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
964       ResTy = parseBDAddr64(Operands);
965     else if (Kind == MCK_PCRel32)
966       ResTy = parsePCRel32(Operands);
967     else if (Kind == MCK_PCRel16)
968       ResTy = parsePCRel16(Operands);
969     else {
970       // Only remaining operand kind is an immediate.
971       const MCExpr *Expr;
972       SMLoc StartLoc = Parser.getTok().getLoc();
973 
974       // Expect immediate expression.
975       if (Parser.parseExpression(Expr))
976         return Error(StartLoc, "unexpected token in directive");
977 
978       SMLoc EndLoc =
979         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
980 
981       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
982       ResTy = MatchOperand_Success;
983     }
984 
985     if (ResTy != MatchOperand_Success)
986       return true;
987   }
988 
989   // Build the instruction with the parsed operands.
990   MCInst Inst = MCInstBuilder(Entry->Opcode);
991 
992   for (size_t i = 0; i < Operands.size(); i++) {
993     MCParsedAsmOperand &Operand = *Operands[i];
994     MatchClassKind Kind = Entry->OperandKinds[i];
995 
996     // Verify operand.
997     unsigned Res = validateOperandClass(Operand, Kind);
998     if (Res != Match_Success)
999       return Error(Operand.getStartLoc(), "unexpected operand type");
1000 
1001     // Add operands to instruction.
1002     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1003     if (ZOperand.isReg())
1004       ZOperand.addRegOperands(Inst, 1);
1005     else if (ZOperand.isMem(BDMem))
1006       ZOperand.addBDAddrOperands(Inst, 2);
1007     else if (ZOperand.isMem(BDXMem))
1008       ZOperand.addBDXAddrOperands(Inst, 3);
1009     else if (ZOperand.isImm())
1010       ZOperand.addImmOperands(Inst, 1);
1011     else
1012       llvm_unreachable("unexpected operand type");
1013   }
1014 
1015   // Emit as a regular instruction.
1016   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1017 
1018   return false;
1019 }
1020 
1021 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1022                                      SMLoc &EndLoc) {
1023   Register Reg;
1024   if (parseRegister(Reg))
1025     return true;
1026   if (Reg.Group == RegGR)
1027     RegNo = SystemZMC::GR64Regs[Reg.Num];
1028   else if (Reg.Group == RegFP)
1029     RegNo = SystemZMC::FP64Regs[Reg.Num];
1030   else if (Reg.Group == RegV)
1031     RegNo = SystemZMC::VR128Regs[Reg.Num];
1032   else if (Reg.Group == RegAR)
1033     RegNo = SystemZMC::AR32Regs[Reg.Num];
1034   StartLoc = Reg.StartLoc;
1035   EndLoc = Reg.EndLoc;
1036   return false;
1037 }
1038 
1039 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1040                                         StringRef Name, SMLoc NameLoc,
1041                                         OperandVector &Operands) {
1042   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1043 
1044   // Read the remaining operands.
1045   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1046     // Read the first operand.
1047     if (parseOperand(Operands, Name)) {
1048       return true;
1049     }
1050 
1051     // Read any subsequent operands.
1052     while (getLexer().is(AsmToken::Comma)) {
1053       Parser.Lex();
1054       if (parseOperand(Operands, Name)) {
1055         return true;
1056       }
1057     }
1058     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1059       SMLoc Loc = getLexer().getLoc();
1060       return Error(Loc, "unexpected token in argument list");
1061     }
1062   }
1063 
1064   // Consume the EndOfStatement.
1065   Parser.Lex();
1066   return false;
1067 }
1068 
1069 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1070                                     StringRef Mnemonic) {
1071   // Check if the current operand has a custom associated parser, if so, try to
1072   // custom parse the operand, or fallback to the general approach.  Force all
1073   // features to be available during the operand check, or else we will fail to
1074   // find the custom parser, and then we will later get an InvalidOperand error
1075   // instead of a MissingFeature errror.
1076   uint64_t AvailableFeatures = getAvailableFeatures();
1077   setAvailableFeatures(~(uint64_t)0);
1078   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1079   setAvailableFeatures(AvailableFeatures);
1080   if (ResTy == MatchOperand_Success)
1081     return false;
1082 
1083   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1084   // there was a match, but an error occurred, in which case, just return that
1085   // the operand parsing failed.
1086   if (ResTy == MatchOperand_ParseFail)
1087     return true;
1088 
1089   // Check for a register.  All real register operands should have used
1090   // a context-dependent parse routine, which gives the required register
1091   // class.  The code is here to mop up other cases, like those where
1092   // the instruction isn't recognized.
1093   if (Parser.getTok().is(AsmToken::Percent)) {
1094     Register Reg;
1095     if (parseRegister(Reg))
1096       return true;
1097     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1098     return false;
1099   }
1100 
1101   // The only other type of operand is an immediate or address.  As above,
1102   // real address operands should have used a context-dependent parse routine,
1103   // so we treat any plain expression as an immediate.
1104   SMLoc StartLoc = Parser.getTok().getLoc();
1105   Register Reg1, Reg2;
1106   bool HaveReg1, HaveReg2;
1107   const MCExpr *Expr;
1108   const MCExpr *Length;
1109   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1110     return true;
1111   // If the register combination is not valid for any instruction, reject it.
1112   // Otherwise, fall back to reporting an unrecognized instruction.
1113   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1114       && parseAddressRegister(Reg1))
1115     return true;
1116   if (HaveReg2 && parseAddressRegister(Reg2))
1117     return true;
1118 
1119   SMLoc EndLoc =
1120     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1121   if (HaveReg1 || HaveReg2 || Length)
1122     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1123   else
1124     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1125   return false;
1126 }
1127 
1128 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1129                                                OperandVector &Operands,
1130                                                MCStreamer &Out,
1131                                                uint64_t &ErrorInfo,
1132                                                bool MatchingInlineAsm) {
1133   MCInst Inst;
1134   unsigned MatchResult;
1135 
1136   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1137                                      MatchingInlineAsm);
1138   switch (MatchResult) {
1139   case Match_Success:
1140     Inst.setLoc(IDLoc);
1141     Out.EmitInstruction(Inst, getSTI());
1142     return false;
1143 
1144   case Match_MissingFeature: {
1145     assert(ErrorInfo && "Unknown missing feature!");
1146     // Special case the error message for the very common case where only
1147     // a single subtarget feature is missing
1148     std::string Msg = "instruction requires:";
1149     uint64_t Mask = 1;
1150     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1151       if (ErrorInfo & Mask) {
1152         Msg += " ";
1153         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1154       }
1155       Mask <<= 1;
1156     }
1157     return Error(IDLoc, Msg);
1158   }
1159 
1160   case Match_InvalidOperand: {
1161     SMLoc ErrorLoc = IDLoc;
1162     if (ErrorInfo != ~0ULL) {
1163       if (ErrorInfo >= Operands.size())
1164         return Error(IDLoc, "too few operands for instruction");
1165 
1166       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1167       if (ErrorLoc == SMLoc())
1168         ErrorLoc = IDLoc;
1169     }
1170     return Error(ErrorLoc, "invalid operand for instruction");
1171   }
1172 
1173   case Match_MnemonicFail:
1174     return Error(IDLoc, "invalid instruction");
1175   }
1176 
1177   llvm_unreachable("Unexpected match type");
1178 }
1179 
1180 OperandMatchResultTy
1181 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1182                              int64_t MaxVal, bool AllowTLS) {
1183   MCContext &Ctx = getContext();
1184   MCStreamer &Out = getStreamer();
1185   const MCExpr *Expr;
1186   SMLoc StartLoc = Parser.getTok().getLoc();
1187   if (getParser().parseExpression(Expr))
1188     return MatchOperand_NoMatch;
1189 
1190   // For consistency with the GNU assembler, treat immediates as offsets
1191   // from ".".
1192   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1193     int64_t Value = CE->getValue();
1194     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1195       Error(StartLoc, "offset out of range");
1196       return MatchOperand_ParseFail;
1197     }
1198     MCSymbol *Sym = Ctx.createTempSymbol();
1199     Out.EmitLabel(Sym);
1200     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1201                                                  Ctx);
1202     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1203   }
1204 
1205   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1206   const MCExpr *Sym = nullptr;
1207   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1208     Parser.Lex();
1209 
1210     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1211       Error(Parser.getTok().getLoc(), "unexpected token");
1212       return MatchOperand_ParseFail;
1213     }
1214 
1215     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1216     StringRef Name = Parser.getTok().getString();
1217     if (Name == "tls_gdcall")
1218       Kind = MCSymbolRefExpr::VK_TLSGD;
1219     else if (Name == "tls_ldcall")
1220       Kind = MCSymbolRefExpr::VK_TLSLDM;
1221     else {
1222       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1223       return MatchOperand_ParseFail;
1224     }
1225     Parser.Lex();
1226 
1227     if (Parser.getTok().isNot(AsmToken::Colon)) {
1228       Error(Parser.getTok().getLoc(), "unexpected token");
1229       return MatchOperand_ParseFail;
1230     }
1231     Parser.Lex();
1232 
1233     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1234       Error(Parser.getTok().getLoc(), "unexpected token");
1235       return MatchOperand_ParseFail;
1236     }
1237 
1238     StringRef Identifier = Parser.getTok().getString();
1239     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1240                                   Kind, Ctx);
1241     Parser.Lex();
1242   }
1243 
1244   SMLoc EndLoc =
1245     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1246 
1247   if (AllowTLS)
1248     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1249                                                     StartLoc, EndLoc));
1250   else
1251     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1252 
1253   return MatchOperand_Success;
1254 }
1255 
1256 // Force static initialization.
1257 extern "C" void LLVMInitializeSystemZAsmParser() {
1258   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1259 }
1260