1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
26     int64_t Value = CE->getValue();
27     return Value >= MinValue && Value <= MaxValue;
28   }
29   return false;
30 }
31 
32 namespace {
33 enum RegisterKind {
34   GR32Reg,
35   GRH32Reg,
36   GR64Reg,
37   GR128Reg,
38   ADDR32Reg,
39   ADDR64Reg,
40   FP32Reg,
41   FP64Reg,
42   FP128Reg,
43   VR32Reg,
44   VR64Reg,
45   VR128Reg
46 };
47 
48 enum MemoryKind {
49   BDMem,
50   BDXMem,
51   BDLMem,
52   BDVMem
53 };
54 
55 class SystemZOperand : public MCParsedAsmOperand {
56 public:
57 private:
58   enum OperandKind {
59     KindInvalid,
60     KindToken,
61     KindReg,
62     KindAccessReg,
63     KindImm,
64     KindImmTLS,
65     KindMem
66   };
67 
68   OperandKind Kind;
69   SMLoc StartLoc, EndLoc;
70 
71   // A string of length Length, starting at Data.
72   struct TokenOp {
73     const char *Data;
74     unsigned Length;
75   };
76 
77   // LLVM register Num, which has kind Kind.  In some ways it might be
78   // easier for this class to have a register bank (general, floating-point
79   // or access) and a raw register number (0-15).  This would postpone the
80   // interpretation of the operand to the add*() methods and avoid the need
81   // for context-dependent parsing.  However, we do things the current way
82   // because of the virtual getReg() method, which needs to distinguish
83   // between (say) %r0 used as a single register and %r0 used as a pair.
84   // Context-dependent parsing can also give us slightly better error
85   // messages when invalid pairs like %r1 are used.
86   struct RegOp {
87     RegisterKind Kind;
88     unsigned Num;
89   };
90 
91   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
92   // MemKind says what type of memory this is and RegKind says what type
93   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
94   // length for D(L,B)-style operands, otherwise it is null.
95   struct MemOp {
96     unsigned Base : 12;
97     unsigned Index : 12;
98     unsigned MemKind : 4;
99     unsigned RegKind : 4;
100     const MCExpr *Disp;
101     const MCExpr *Length;
102   };
103 
104   // Imm is an immediate operand, and Sym is an optional TLS symbol
105   // for use with a __tls_get_offset marker relocation.
106   struct ImmTLSOp {
107     const MCExpr *Imm;
108     const MCExpr *Sym;
109   };
110 
111   union {
112     TokenOp Token;
113     RegOp Reg;
114     unsigned AccessReg;
115     const MCExpr *Imm;
116     ImmTLSOp ImmTLS;
117     MemOp Mem;
118   };
119 
120   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
121     // Add as immediates when possible.  Null MCExpr = 0.
122     if (!Expr)
123       Inst.addOperand(MCOperand::createImm(0));
124     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
125       Inst.addOperand(MCOperand::createImm(CE->getValue()));
126     else
127       Inst.addOperand(MCOperand::createExpr(Expr));
128   }
129 
130 public:
131   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
132       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
133 
134   // Create particular kinds of operand.
135   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
136                                                        SMLoc EndLoc) {
137     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
138   }
139   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
140     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
141     Op->Token.Data = Str.data();
142     Op->Token.Length = Str.size();
143     return Op;
144   }
145   static std::unique_ptr<SystemZOperand>
146   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
147     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
148     Op->Reg.Kind = Kind;
149     Op->Reg.Num = Num;
150     return Op;
151   }
152   static std::unique_ptr<SystemZOperand>
153   createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
154     auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
155     Op->AccessReg = Num;
156     return Op;
157   }
158   static std::unique_ptr<SystemZOperand>
159   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
160     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
161     Op->Imm = Expr;
162     return Op;
163   }
164   static std::unique_ptr<SystemZOperand>
165   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
166             const MCExpr *Disp, unsigned Index, const MCExpr *Length,
167             SMLoc StartLoc, SMLoc EndLoc) {
168     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
169     Op->Mem.MemKind = MemKind;
170     Op->Mem.RegKind = RegKind;
171     Op->Mem.Base = Base;
172     Op->Mem.Index = Index;
173     Op->Mem.Disp = Disp;
174     Op->Mem.Length = Length;
175     return Op;
176   }
177   static std::unique_ptr<SystemZOperand>
178   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
179                SMLoc StartLoc, SMLoc EndLoc) {
180     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
181     Op->ImmTLS.Imm = Imm;
182     Op->ImmTLS.Sym = Sym;
183     return Op;
184   }
185 
186   // Token operands
187   bool isToken() const override {
188     return Kind == KindToken;
189   }
190   StringRef getToken() const {
191     assert(Kind == KindToken && "Not a token");
192     return StringRef(Token.Data, Token.Length);
193   }
194 
195   // Register operands.
196   bool isReg() const override {
197     return Kind == KindReg;
198   }
199   bool isReg(RegisterKind RegKind) const {
200     return Kind == KindReg && Reg.Kind == RegKind;
201   }
202   unsigned getReg() const override {
203     assert(Kind == KindReg && "Not a register");
204     return Reg.Num;
205   }
206 
207   // Access register operands.  Access registers aren't exposed to LLVM
208   // as registers.
209   bool isAccessReg() const {
210     return Kind == KindAccessReg;
211   }
212 
213   // Immediate operands.
214   bool isImm() const override {
215     return Kind == KindImm;
216   }
217   bool isImm(int64_t MinValue, int64_t MaxValue) const {
218     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
219   }
220   const MCExpr *getImm() const {
221     assert(Kind == KindImm && "Not an immediate");
222     return Imm;
223   }
224 
225   // Immediate operands with optional TLS symbol.
226   bool isImmTLS() const {
227     return Kind == KindImmTLS;
228   }
229 
230   // Memory operands.
231   bool isMem() const override {
232     return Kind == KindMem;
233   }
234   bool isMem(MemoryKind MemKind) const {
235     return (Kind == KindMem &&
236             (Mem.MemKind == MemKind ||
237              // A BDMem can be treated as a BDXMem in which the index
238              // register field is 0.
239              (Mem.MemKind == BDMem && MemKind == BDXMem)));
240   }
241   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
242     return isMem(MemKind) && Mem.RegKind == RegKind;
243   }
244   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
245     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
246   }
247   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
248     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
249   }
250   bool isMemDisp12Len8(RegisterKind RegKind) const {
251     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
252   }
253   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
254     assert(N == 3 && "Invalid number of operands");
255     assert(isMem(BDVMem) && "Invalid operand type");
256     Inst.addOperand(MCOperand::createReg(Mem.Base));
257     addExpr(Inst, Mem.Disp);
258     Inst.addOperand(MCOperand::createReg(Mem.Index));
259   }
260 
261   // Override MCParsedAsmOperand.
262   SMLoc getStartLoc() const override { return StartLoc; }
263   SMLoc getEndLoc() const override { return EndLoc; }
264   void print(raw_ostream &OS) const override;
265 
266   // Used by the TableGen code to add particular types of operand
267   // to an instruction.
268   void addRegOperands(MCInst &Inst, unsigned N) const {
269     assert(N == 1 && "Invalid number of operands");
270     Inst.addOperand(MCOperand::createReg(getReg()));
271   }
272   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
273     assert(N == 1 && "Invalid number of operands");
274     assert(Kind == KindAccessReg && "Invalid operand type");
275     Inst.addOperand(MCOperand::createImm(AccessReg));
276   }
277   void addImmOperands(MCInst &Inst, unsigned N) const {
278     assert(N == 1 && "Invalid number of operands");
279     addExpr(Inst, getImm());
280   }
281   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
282     assert(N == 2 && "Invalid number of operands");
283     assert(isMem(BDMem) && "Invalid operand type");
284     Inst.addOperand(MCOperand::createReg(Mem.Base));
285     addExpr(Inst, Mem.Disp);
286   }
287   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
288     assert(N == 3 && "Invalid number of operands");
289     assert(isMem(BDXMem) && "Invalid operand type");
290     Inst.addOperand(MCOperand::createReg(Mem.Base));
291     addExpr(Inst, Mem.Disp);
292     Inst.addOperand(MCOperand::createReg(Mem.Index));
293   }
294   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
295     assert(N == 3 && "Invalid number of operands");
296     assert(isMem(BDLMem) && "Invalid operand type");
297     Inst.addOperand(MCOperand::createReg(Mem.Base));
298     addExpr(Inst, Mem.Disp);
299     addExpr(Inst, Mem.Length);
300   }
301   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
302     assert(N == 2 && "Invalid number of operands");
303     assert(Kind == KindImmTLS && "Invalid operand type");
304     addExpr(Inst, ImmTLS.Imm);
305     if (ImmTLS.Sym)
306       addExpr(Inst, ImmTLS.Sym);
307   }
308 
309   // Used by the TableGen code to check for particular operand types.
310   bool isGR32() const { return isReg(GR32Reg); }
311   bool isGRH32() const { return isReg(GRH32Reg); }
312   bool isGRX32() const { return false; }
313   bool isGR64() const { return isReg(GR64Reg); }
314   bool isGR128() const { return isReg(GR128Reg); }
315   bool isADDR32() const { return isReg(ADDR32Reg); }
316   bool isADDR64() const { return isReg(ADDR64Reg); }
317   bool isADDR128() const { return false; }
318   bool isFP32() const { return isReg(FP32Reg); }
319   bool isFP64() const { return isReg(FP64Reg); }
320   bool isFP128() const { return isReg(FP128Reg); }
321   bool isVR32() const { return isReg(VR32Reg); }
322   bool isVR64() const { return isReg(VR64Reg); }
323   bool isVF128() const { return false; }
324   bool isVR128() const { return isReg(VR128Reg); }
325   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
326   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
327   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
328   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
329   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
330   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
331   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
332   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
333   bool isU1Imm() const { return isImm(0, 1); }
334   bool isU2Imm() const { return isImm(0, 3); }
335   bool isU3Imm() const { return isImm(0, 7); }
336   bool isU4Imm() const { return isImm(0, 15); }
337   bool isU6Imm() const { return isImm(0, 63); }
338   bool isU8Imm() const { return isImm(0, 255); }
339   bool isS8Imm() const { return isImm(-128, 127); }
340   bool isU12Imm() const { return isImm(0, 4095); }
341   bool isU16Imm() const { return isImm(0, 65535); }
342   bool isS16Imm() const { return isImm(-32768, 32767); }
343   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
344   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
345 };
346 
347 class SystemZAsmParser : public MCTargetAsmParser {
348 #define GET_ASSEMBLER_HEADER
349 #include "SystemZGenAsmMatcher.inc"
350 
351 private:
352   MCSubtargetInfo &STI;
353   MCAsmParser &Parser;
354   enum RegisterGroup {
355     RegGR,
356     RegFP,
357     RegV,
358     RegAccess
359   };
360   struct Register {
361     RegisterGroup Group;
362     unsigned Num;
363     SMLoc StartLoc, EndLoc;
364   };
365 
366   bool parseRegister(Register &Reg);
367 
368   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
369                      bool IsAddress = false);
370 
371   OperandMatchResultTy parseRegister(OperandVector &Operands,
372                                      RegisterGroup Group, const unsigned *Regs,
373                                      RegisterKind Kind);
374 
375   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
376                     unsigned &Index, bool &IsVector, const MCExpr *&Length,
377                     const unsigned *Regs, RegisterKind RegKind);
378 
379   OperandMatchResultTy parseAddress(OperandVector &Operands,
380                                     MemoryKind MemKind, const unsigned *Regs,
381                                     RegisterKind RegKind);
382 
383   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
384                                   int64_t MaxVal, bool AllowTLS);
385 
386   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
387 
388 public:
389   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
390                    const MCInstrInfo &MII,
391                    const MCTargetOptions &Options)
392       : MCTargetAsmParser(Options), STI(sti), Parser(parser) {
393     MCAsmParserExtension::Initialize(Parser);
394 
395     // Initialize the set of available features.
396     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
397   }
398 
399   // Override MCTargetAsmParser.
400   bool ParseDirective(AsmToken DirectiveID) override;
401   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
402   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
403                         SMLoc NameLoc, OperandVector &Operands) override;
404   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
405                                OperandVector &Operands, MCStreamer &Out,
406                                uint64_t &ErrorInfo,
407                                bool MatchingInlineAsm) override;
408 
409   // Used by the TableGen code to parse particular operand types.
410   OperandMatchResultTy parseGR32(OperandVector &Operands) {
411     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
412   }
413   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
414     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
415   }
416   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
417     llvm_unreachable("GRX32 should only be used for pseudo instructions");
418   }
419   OperandMatchResultTy parseGR64(OperandVector &Operands) {
420     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
421   }
422   OperandMatchResultTy parseGR128(OperandVector &Operands) {
423     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
424   }
425   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
426     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
427   }
428   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
429     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
430   }
431   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
432     llvm_unreachable("Shouldn't be used as an operand");
433   }
434   OperandMatchResultTy parseFP32(OperandVector &Operands) {
435     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
436   }
437   OperandMatchResultTy parseFP64(OperandVector &Operands) {
438     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
439   }
440   OperandMatchResultTy parseFP128(OperandVector &Operands) {
441     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
442   }
443   OperandMatchResultTy parseVR32(OperandVector &Operands) {
444     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
445   }
446   OperandMatchResultTy parseVR64(OperandVector &Operands) {
447     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
448   }
449   OperandMatchResultTy parseVF128(OperandVector &Operands) {
450     llvm_unreachable("Shouldn't be used as an operand");
451   }
452   OperandMatchResultTy parseVR128(OperandVector &Operands) {
453     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
454   }
455   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
456     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
457   }
458   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
459     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
460   }
461   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
462     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
463   }
464   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
465     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
466   }
467   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
468     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
469   }
470   OperandMatchResultTy parseAccessReg(OperandVector &Operands);
471   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
472     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
473   }
474   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
475     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
476   }
477   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
478     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
479   }
480   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
481     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
482   }
483 };
484 } // end anonymous namespace
485 
486 #define GET_REGISTER_MATCHER
487 #define GET_SUBTARGET_FEATURE_NAME
488 #define GET_MATCHER_IMPLEMENTATION
489 #include "SystemZGenAsmMatcher.inc"
490 
491 void SystemZOperand::print(raw_ostream &OS) const {
492   llvm_unreachable("Not implemented");
493 }
494 
495 // Parse one register of the form %<prefix><number>.
496 bool SystemZAsmParser::parseRegister(Register &Reg) {
497   Reg.StartLoc = Parser.getTok().getLoc();
498 
499   // Eat the % prefix.
500   if (Parser.getTok().isNot(AsmToken::Percent))
501     return Error(Parser.getTok().getLoc(), "register expected");
502   Parser.Lex();
503 
504   // Expect a register name.
505   if (Parser.getTok().isNot(AsmToken::Identifier))
506     return Error(Reg.StartLoc, "invalid register");
507 
508   // Check that there's a prefix.
509   StringRef Name = Parser.getTok().getString();
510   if (Name.size() < 2)
511     return Error(Reg.StartLoc, "invalid register");
512   char Prefix = Name[0];
513 
514   // Treat the rest of the register name as a register number.
515   if (Name.substr(1).getAsInteger(10, Reg.Num))
516     return Error(Reg.StartLoc, "invalid register");
517 
518   // Look for valid combinations of prefix and number.
519   if (Prefix == 'r' && Reg.Num < 16)
520     Reg.Group = RegGR;
521   else if (Prefix == 'f' && Reg.Num < 16)
522     Reg.Group = RegFP;
523   else if (Prefix == 'v' && Reg.Num < 32)
524     Reg.Group = RegV;
525   else if (Prefix == 'a' && Reg.Num < 16)
526     Reg.Group = RegAccess;
527   else
528     return Error(Reg.StartLoc, "invalid register");
529 
530   Reg.EndLoc = Parser.getTok().getLoc();
531   Parser.Lex();
532   return false;
533 }
534 
535 // Parse a register of group Group.  If Regs is nonnull, use it to map
536 // the raw register number to LLVM numbering, with zero entries indicating
537 // an invalid register.  IsAddress says whether the register appears in an
538 // address context.
539 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
540                                      const unsigned *Regs, bool IsAddress) {
541   if (parseRegister(Reg))
542     return true;
543   if (Reg.Group != Group)
544     return Error(Reg.StartLoc, "invalid operand for instruction");
545   if (Regs && Regs[Reg.Num] == 0)
546     return Error(Reg.StartLoc, "invalid register pair");
547   if (Reg.Num == 0 && IsAddress)
548     return Error(Reg.StartLoc, "%r0 used in an address");
549   if (Regs)
550     Reg.Num = Regs[Reg.Num];
551   return false;
552 }
553 
554 // Parse a register and add it to Operands.  The other arguments are as above.
555 SystemZAsmParser::OperandMatchResultTy
556 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
557                                 const unsigned *Regs, RegisterKind Kind) {
558   if (Parser.getTok().isNot(AsmToken::Percent))
559     return MatchOperand_NoMatch;
560 
561   Register Reg;
562   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
563   if (parseRegister(Reg, Group, Regs, IsAddress))
564     return MatchOperand_ParseFail;
565 
566   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
567                                                Reg.StartLoc, Reg.EndLoc));
568   return MatchOperand_Success;
569 }
570 
571 // Parse a memory operand into Base, Disp, Index and Length.
572 // Regs maps asm register numbers to LLVM register numbers and RegKind
573 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
574 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
575                                     unsigned &Index, bool &IsVector,
576                                     const MCExpr *&Length, const unsigned *Regs,
577                                     RegisterKind RegKind) {
578   // Parse the displacement, which must always be present.
579   if (getParser().parseExpression(Disp))
580     return true;
581 
582   // Parse the optional base and index.
583   Index = 0;
584   Base = 0;
585   IsVector = false;
586   Length = nullptr;
587   if (getLexer().is(AsmToken::LParen)) {
588     Parser.Lex();
589 
590     if (getLexer().is(AsmToken::Percent)) {
591       // Parse the first register and decide whether it's a base or an index.
592       Register Reg;
593       if (parseRegister(Reg))
594         return true;
595       if (Reg.Group == RegV) {
596         // A vector index register.  The base register is optional.
597         IsVector = true;
598         Index = SystemZMC::VR128Regs[Reg.Num];
599       } else if (Reg.Group == RegGR) {
600         if (Reg.Num == 0)
601           return Error(Reg.StartLoc, "%r0 used in an address");
602         // If the are two registers, the first one is the index and the
603         // second is the base.
604         if (getLexer().is(AsmToken::Comma))
605           Index = Regs[Reg.Num];
606         else
607           Base = Regs[Reg.Num];
608       } else
609         return Error(Reg.StartLoc, "invalid address register");
610     } else {
611       // Parse the length.
612       if (getParser().parseExpression(Length))
613         return true;
614     }
615 
616     // Check whether there's a second register.  It's the base if so.
617     if (getLexer().is(AsmToken::Comma)) {
618       Parser.Lex();
619       Register Reg;
620       if (parseRegister(Reg, RegGR, Regs, RegKind))
621         return true;
622       Base = Reg.Num;
623     }
624 
625     // Consume the closing bracket.
626     if (getLexer().isNot(AsmToken::RParen))
627       return Error(Parser.getTok().getLoc(), "unexpected token in address");
628     Parser.Lex();
629   }
630   return false;
631 }
632 
633 // Parse a memory operand and add it to Operands.  The other arguments
634 // are as above.
635 SystemZAsmParser::OperandMatchResultTy
636 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
637                                const unsigned *Regs, RegisterKind RegKind) {
638   SMLoc StartLoc = Parser.getTok().getLoc();
639   unsigned Base, Index;
640   bool IsVector;
641   const MCExpr *Disp;
642   const MCExpr *Length;
643   if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
644     return MatchOperand_ParseFail;
645 
646   if (IsVector && MemKind != BDVMem) {
647     Error(StartLoc, "invalid use of vector addressing");
648     return MatchOperand_ParseFail;
649   }
650 
651   if (!IsVector && MemKind == BDVMem) {
652     Error(StartLoc, "vector index required in address");
653     return MatchOperand_ParseFail;
654   }
655 
656   if (Index && MemKind != BDXMem && MemKind != BDVMem) {
657     Error(StartLoc, "invalid use of indexed addressing");
658     return MatchOperand_ParseFail;
659   }
660 
661   if (Length && MemKind != BDLMem) {
662     Error(StartLoc, "invalid use of length addressing");
663     return MatchOperand_ParseFail;
664   }
665 
666   if (!Length && MemKind == BDLMem) {
667     Error(StartLoc, "missing length in address");
668     return MatchOperand_ParseFail;
669   }
670 
671   SMLoc EndLoc =
672     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
673   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
674                                                Index, Length, StartLoc,
675                                                EndLoc));
676   return MatchOperand_Success;
677 }
678 
679 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
680   return true;
681 }
682 
683 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
684                                      SMLoc &EndLoc) {
685   Register Reg;
686   if (parseRegister(Reg))
687     return true;
688   if (Reg.Group == RegGR)
689     RegNo = SystemZMC::GR64Regs[Reg.Num];
690   else if (Reg.Group == RegFP)
691     RegNo = SystemZMC::FP64Regs[Reg.Num];
692   else if (Reg.Group == RegV)
693     RegNo = SystemZMC::VR128Regs[Reg.Num];
694   else
695     // FIXME: Access registers aren't modelled as LLVM registers yet.
696     return Error(Reg.StartLoc, "invalid operand for instruction");
697   StartLoc = Reg.StartLoc;
698   EndLoc = Reg.EndLoc;
699   return false;
700 }
701 
702 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
703                                         StringRef Name, SMLoc NameLoc,
704                                         OperandVector &Operands) {
705   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
706 
707   // Read the remaining operands.
708   if (getLexer().isNot(AsmToken::EndOfStatement)) {
709     // Read the first operand.
710     if (parseOperand(Operands, Name)) {
711       Parser.eatToEndOfStatement();
712       return true;
713     }
714 
715     // Read any subsequent operands.
716     while (getLexer().is(AsmToken::Comma)) {
717       Parser.Lex();
718       if (parseOperand(Operands, Name)) {
719         Parser.eatToEndOfStatement();
720         return true;
721       }
722     }
723     if (getLexer().isNot(AsmToken::EndOfStatement)) {
724       SMLoc Loc = getLexer().getLoc();
725       Parser.eatToEndOfStatement();
726       return Error(Loc, "unexpected token in argument list");
727     }
728   }
729 
730   // Consume the EndOfStatement.
731   Parser.Lex();
732   return false;
733 }
734 
735 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
736                                     StringRef Mnemonic) {
737   // Check if the current operand has a custom associated parser, if so, try to
738   // custom parse the operand, or fallback to the general approach.
739   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
740   if (ResTy == MatchOperand_Success)
741     return false;
742 
743   // If there wasn't a custom match, try the generic matcher below. Otherwise,
744   // there was a match, but an error occurred, in which case, just return that
745   // the operand parsing failed.
746   if (ResTy == MatchOperand_ParseFail)
747     return true;
748 
749   // Check for a register.  All real register operands should have used
750   // a context-dependent parse routine, which gives the required register
751   // class.  The code is here to mop up other cases, like those where
752   // the instruction isn't recognized.
753   if (Parser.getTok().is(AsmToken::Percent)) {
754     Register Reg;
755     if (parseRegister(Reg))
756       return true;
757     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
758     return false;
759   }
760 
761   // The only other type of operand is an immediate or address.  As above,
762   // real address operands should have used a context-dependent parse routine,
763   // so we treat any plain expression as an immediate.
764   SMLoc StartLoc = Parser.getTok().getLoc();
765   unsigned Base, Index;
766   bool IsVector;
767   const MCExpr *Expr, *Length;
768   if (parseAddress(Base, Expr, Index, IsVector, Length, SystemZMC::GR64Regs,
769                    ADDR64Reg))
770     return true;
771 
772   SMLoc EndLoc =
773     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
774   if (Base || Index || Length)
775     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
776   else
777     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
778   return false;
779 }
780 
781 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
782                                                OperandVector &Operands,
783                                                MCStreamer &Out,
784                                                uint64_t &ErrorInfo,
785                                                bool MatchingInlineAsm) {
786   MCInst Inst;
787   unsigned MatchResult;
788 
789   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
790                                      MatchingInlineAsm);
791   switch (MatchResult) {
792   case Match_Success:
793     Inst.setLoc(IDLoc);
794     Out.EmitInstruction(Inst, STI);
795     return false;
796 
797   case Match_MissingFeature: {
798     assert(ErrorInfo && "Unknown missing feature!");
799     // Special case the error message for the very common case where only
800     // a single subtarget feature is missing
801     std::string Msg = "instruction requires:";
802     uint64_t Mask = 1;
803     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
804       if (ErrorInfo & Mask) {
805         Msg += " ";
806         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
807       }
808       Mask <<= 1;
809     }
810     return Error(IDLoc, Msg);
811   }
812 
813   case Match_InvalidOperand: {
814     SMLoc ErrorLoc = IDLoc;
815     if (ErrorInfo != ~0ULL) {
816       if (ErrorInfo >= Operands.size())
817         return Error(IDLoc, "too few operands for instruction");
818 
819       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
820       if (ErrorLoc == SMLoc())
821         ErrorLoc = IDLoc;
822     }
823     return Error(ErrorLoc, "invalid operand for instruction");
824   }
825 
826   case Match_MnemonicFail:
827     return Error(IDLoc, "invalid instruction");
828   }
829 
830   llvm_unreachable("Unexpected match type");
831 }
832 
833 SystemZAsmParser::OperandMatchResultTy
834 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
835   if (Parser.getTok().isNot(AsmToken::Percent))
836     return MatchOperand_NoMatch;
837 
838   Register Reg;
839   if (parseRegister(Reg, RegAccess, nullptr))
840     return MatchOperand_ParseFail;
841 
842   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
843                                                      Reg.StartLoc,
844                                                      Reg.EndLoc));
845   return MatchOperand_Success;
846 }
847 
848 SystemZAsmParser::OperandMatchResultTy
849 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
850                              int64_t MaxVal, bool AllowTLS) {
851   MCContext &Ctx = getContext();
852   MCStreamer &Out = getStreamer();
853   const MCExpr *Expr;
854   SMLoc StartLoc = Parser.getTok().getLoc();
855   if (getParser().parseExpression(Expr))
856     return MatchOperand_NoMatch;
857 
858   // For consistency with the GNU assembler, treat immediates as offsets
859   // from ".".
860   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
861     int64_t Value = CE->getValue();
862     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
863       Error(StartLoc, "offset out of range");
864       return MatchOperand_ParseFail;
865     }
866     MCSymbol *Sym = Ctx.createTempSymbol();
867     Out.EmitLabel(Sym);
868     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
869                                                  Ctx);
870     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
871   }
872 
873   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
874   const MCExpr *Sym = nullptr;
875   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
876     Parser.Lex();
877 
878     if (Parser.getTok().isNot(AsmToken::Identifier)) {
879       Error(Parser.getTok().getLoc(), "unexpected token");
880       return MatchOperand_ParseFail;
881     }
882 
883     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
884     StringRef Name = Parser.getTok().getString();
885     if (Name == "tls_gdcall")
886       Kind = MCSymbolRefExpr::VK_TLSGD;
887     else if (Name == "tls_ldcall")
888       Kind = MCSymbolRefExpr::VK_TLSLDM;
889     else {
890       Error(Parser.getTok().getLoc(), "unknown TLS tag");
891       return MatchOperand_ParseFail;
892     }
893     Parser.Lex();
894 
895     if (Parser.getTok().isNot(AsmToken::Colon)) {
896       Error(Parser.getTok().getLoc(), "unexpected token");
897       return MatchOperand_ParseFail;
898     }
899     Parser.Lex();
900 
901     if (Parser.getTok().isNot(AsmToken::Identifier)) {
902       Error(Parser.getTok().getLoc(), "unexpected token");
903       return MatchOperand_ParseFail;
904     }
905 
906     StringRef Identifier = Parser.getTok().getString();
907     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
908                                   Kind, Ctx);
909     Parser.Lex();
910   }
911 
912   SMLoc EndLoc =
913     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
914 
915   if (AllowTLS)
916     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
917                                                     StartLoc, EndLoc));
918   else
919     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
920 
921   return MatchOperand_Success;
922 }
923 
924 // Force static initialization.
925 extern "C" void LLVMInitializeSystemZAsmParser() {
926   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
927 }
928