1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
26     int64_t Value = CE->getValue();
27     return Value >= MinValue && Value <= MaxValue;
28   }
29   return false;
30 }
31 
32 namespace {
33 enum RegisterKind {
34   GR32Reg,
35   GRH32Reg,
36   GR64Reg,
37   GR128Reg,
38   ADDR32Reg,
39   ADDR64Reg,
40   FP32Reg,
41   FP64Reg,
42   FP128Reg
43 };
44 
45 enum MemoryKind {
46   BDMem,
47   BDXMem,
48   BDLMem
49 };
50 
51 class SystemZOperand : public MCParsedAsmOperand {
52 public:
53 private:
54   enum OperandKind {
55     KindInvalid,
56     KindToken,
57     KindReg,
58     KindAccessReg,
59     KindImm,
60     KindMem
61   };
62 
63   OperandKind Kind;
64   SMLoc StartLoc, EndLoc;
65 
66   // A string of length Length, starting at Data.
67   struct TokenOp {
68     const char *Data;
69     unsigned Length;
70   };
71 
72   // LLVM register Num, which has kind Kind.  In some ways it might be
73   // easier for this class to have a register bank (general, floating-point
74   // or access) and a raw register number (0-15).  This would postpone the
75   // interpretation of the operand to the add*() methods and avoid the need
76   // for context-dependent parsing.  However, we do things the current way
77   // because of the virtual getReg() method, which needs to distinguish
78   // between (say) %r0 used as a single register and %r0 used as a pair.
79   // Context-dependent parsing can also give us slightly better error
80   // messages when invalid pairs like %r1 are used.
81   struct RegOp {
82     RegisterKind Kind;
83     unsigned Num;
84   };
85 
86   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
87   // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
88   // Length is the operand length for D(L,B)-style operands, otherwise
89   // it is null.
90   struct MemOp {
91     unsigned Base : 8;
92     unsigned Index : 8;
93     unsigned RegKind : 8;
94     unsigned Unused : 8;
95     const MCExpr *Disp;
96     const MCExpr *Length;
97   };
98 
99   union {
100     TokenOp Token;
101     RegOp Reg;
102     unsigned AccessReg;
103     const MCExpr *Imm;
104     MemOp Mem;
105   };
106 
107   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
108     : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
109   {}
110 
111   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
112     // Add as immediates when possible.  Null MCExpr = 0.
113     if (!Expr)
114       Inst.addOperand(MCOperand::CreateImm(0));
115     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
116       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
117     else
118       Inst.addOperand(MCOperand::CreateExpr(Expr));
119   }
120 
121 public:
122   // Create particular kinds of operand.
123   static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
124     return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
125   }
126   static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
127     SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
128     Op->Token.Data = Str.data();
129     Op->Token.Length = Str.size();
130     return Op;
131   }
132   static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
133                                    SMLoc StartLoc, SMLoc EndLoc) {
134     SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
135     Op->Reg.Kind = Kind;
136     Op->Reg.Num = Num;
137     return Op;
138   }
139   static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
140                                          SMLoc EndLoc) {
141     SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
142     Op->AccessReg = Num;
143     return Op;
144   }
145   static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
146                                    SMLoc EndLoc) {
147     SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
148     Op->Imm = Expr;
149     return Op;
150   }
151   static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
152                                    const MCExpr *Disp, unsigned Index,
153                                    const MCExpr *Length, SMLoc StartLoc,
154                                    SMLoc EndLoc) {
155     SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
156     Op->Mem.RegKind = RegKind;
157     Op->Mem.Base = Base;
158     Op->Mem.Index = Index;
159     Op->Mem.Disp = Disp;
160     Op->Mem.Length = Length;
161     return Op;
162   }
163 
164   // Token operands
165   bool isToken() const override {
166     return Kind == KindToken;
167   }
168   StringRef getToken() const {
169     assert(Kind == KindToken && "Not a token");
170     return StringRef(Token.Data, Token.Length);
171   }
172 
173   // Register operands.
174   bool isReg() const override {
175     return Kind == KindReg;
176   }
177   bool isReg(RegisterKind RegKind) const {
178     return Kind == KindReg && Reg.Kind == RegKind;
179   }
180   unsigned getReg() const override {
181     assert(Kind == KindReg && "Not a register");
182     return Reg.Num;
183   }
184 
185   // Access register operands.  Access registers aren't exposed to LLVM
186   // as registers.
187   bool isAccessReg() const {
188     return Kind == KindAccessReg;
189   }
190 
191   // Immediate operands.
192   bool isImm() const override {
193     return Kind == KindImm;
194   }
195   bool isImm(int64_t MinValue, int64_t MaxValue) const {
196     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
197   }
198   const MCExpr *getImm() const {
199     assert(Kind == KindImm && "Not an immediate");
200     return Imm;
201   }
202 
203   // Memory operands.
204   bool isMem() const override {
205     return Kind == KindMem;
206   }
207   bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
208     return (Kind == KindMem &&
209             Mem.RegKind == RegKind &&
210             (MemKind == BDXMem || !Mem.Index) &&
211             (MemKind == BDLMem) == (Mem.Length != nullptr));
212   }
213   bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
214     return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
215   }
216   bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
217     return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
218   }
219   bool isMemDisp12Len8(RegisterKind RegKind) const {
220     return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
221   }
222 
223   // Override MCParsedAsmOperand.
224   SMLoc getStartLoc() const override { return StartLoc; }
225   SMLoc getEndLoc() const override { return EndLoc; }
226   void print(raw_ostream &OS) const override;
227 
228   // Used by the TableGen code to add particular types of operand
229   // to an instruction.
230   void addRegOperands(MCInst &Inst, unsigned N) const {
231     assert(N == 1 && "Invalid number of operands");
232     Inst.addOperand(MCOperand::CreateReg(getReg()));
233   }
234   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
235     assert(N == 1 && "Invalid number of operands");
236     assert(Kind == KindAccessReg && "Invalid operand type");
237     Inst.addOperand(MCOperand::CreateImm(AccessReg));
238   }
239   void addImmOperands(MCInst &Inst, unsigned N) const {
240     assert(N == 1 && "Invalid number of operands");
241     addExpr(Inst, getImm());
242   }
243   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
244     assert(N == 2 && "Invalid number of operands");
245     assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
246     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
247     addExpr(Inst, Mem.Disp);
248   }
249   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
250     assert(N == 3 && "Invalid number of operands");
251     assert(Kind == KindMem && "Invalid operand type");
252     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
253     addExpr(Inst, Mem.Disp);
254     Inst.addOperand(MCOperand::CreateReg(Mem.Index));
255   }
256   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
257     assert(N == 3 && "Invalid number of operands");
258     assert(Kind == KindMem && "Invalid operand type");
259     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
260     addExpr(Inst, Mem.Disp);
261     addExpr(Inst, Mem.Length);
262   }
263 
264   // Used by the TableGen code to check for particular operand types.
265   bool isGR32() const { return isReg(GR32Reg); }
266   bool isGRH32() const { return isReg(GRH32Reg); }
267   bool isGRX32() const { return false; }
268   bool isGR64() const { return isReg(GR64Reg); }
269   bool isGR128() const { return isReg(GR128Reg); }
270   bool isADDR32() const { return isReg(ADDR32Reg); }
271   bool isADDR64() const { return isReg(ADDR64Reg); }
272   bool isADDR128() const { return false; }
273   bool isFP32() const { return isReg(FP32Reg); }
274   bool isFP64() const { return isReg(FP64Reg); }
275   bool isFP128() const { return isReg(FP128Reg); }
276   bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
277   bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
278   bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
279   bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
280   bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
281   bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
282   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
283   bool isU4Imm() const { return isImm(0, 15); }
284   bool isU6Imm() const { return isImm(0, 63); }
285   bool isU8Imm() const { return isImm(0, 255); }
286   bool isS8Imm() const { return isImm(-128, 127); }
287   bool isU16Imm() const { return isImm(0, 65535); }
288   bool isS16Imm() const { return isImm(-32768, 32767); }
289   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
290   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
291 };
292 
293 class SystemZAsmParser : public MCTargetAsmParser {
294 #define GET_ASSEMBLER_HEADER
295 #include "SystemZGenAsmMatcher.inc"
296 
297 private:
298   MCSubtargetInfo &STI;
299   MCAsmParser &Parser;
300   enum RegisterGroup {
301     RegGR,
302     RegFP,
303     RegAccess
304   };
305   struct Register {
306     RegisterGroup Group;
307     unsigned Num;
308     SMLoc StartLoc, EndLoc;
309   };
310 
311   bool parseRegister(Register &Reg);
312 
313   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
314                      bool IsAddress = false);
315 
316   OperandMatchResultTy
317   parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
318                 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
319 
320   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
321                     unsigned &Index, const MCExpr *&Length,
322                     const unsigned *Regs, RegisterKind RegKind);
323 
324   OperandMatchResultTy
325   parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
326                const unsigned *Regs, RegisterKind RegKind,
327                MemoryKind MemKind);
328 
329   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
330                     StringRef Mnemonic);
331 
332 public:
333   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
334                    const MCInstrInfo &MII,
335                    const MCTargetOptions &Options)
336       : MCTargetAsmParser(), STI(sti), Parser(parser) {
337     MCAsmParserExtension::Initialize(Parser);
338 
339     // Initialize the set of available features.
340     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
341   }
342 
343   // Override MCTargetAsmParser.
344   bool ParseDirective(AsmToken DirectiveID) override;
345   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
346   bool ParseInstruction(ParseInstructionInfo &Info,
347                         StringRef Name, SMLoc NameLoc,
348                         SmallVectorImpl<MCParsedAsmOperand*> &Operands)
349     override;
350   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
351                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
352                                MCStreamer &Out, unsigned &ErrorInfo,
353                                bool MatchingInlineAsm) override;
354 
355   // Used by the TableGen code to parse particular operand types.
356   OperandMatchResultTy
357   parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
358     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
359   }
360   OperandMatchResultTy
361   parseGRH32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
362     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
363   }
364   OperandMatchResultTy
365   parseGRX32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
366     llvm_unreachable("GRX32 should only be used for pseudo instructions");
367   }
368   OperandMatchResultTy
369   parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
370     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
371   }
372   OperandMatchResultTy
373   parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
374     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
375   }
376   OperandMatchResultTy
377   parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
378     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
379   }
380   OperandMatchResultTy
381   parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
382     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
383   }
384   OperandMatchResultTy
385   parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
386     llvm_unreachable("Shouldn't be used as an operand");
387   }
388   OperandMatchResultTy
389   parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
390     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
391   }
392   OperandMatchResultTy
393   parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
394     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
395   }
396   OperandMatchResultTy
397   parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
398     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
399   }
400   OperandMatchResultTy
401   parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
402     return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
403   }
404   OperandMatchResultTy
405   parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
406     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
407   }
408   OperandMatchResultTy
409   parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
410     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
411   }
412   OperandMatchResultTy
413   parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
414     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
415   }
416   OperandMatchResultTy
417   parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
418   OperandMatchResultTy
419   parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
420              int64_t MinVal, int64_t MaxVal);
421   OperandMatchResultTy
422   parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
423     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
424   }
425   OperandMatchResultTy
426   parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
427     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
428   }
429 };
430 } // end anonymous namespace
431 
432 #define GET_REGISTER_MATCHER
433 #define GET_SUBTARGET_FEATURE_NAME
434 #define GET_MATCHER_IMPLEMENTATION
435 #include "SystemZGenAsmMatcher.inc"
436 
437 void SystemZOperand::print(raw_ostream &OS) const {
438   llvm_unreachable("Not implemented");
439 }
440 
441 // Parse one register of the form %<prefix><number>.
442 bool SystemZAsmParser::parseRegister(Register &Reg) {
443   Reg.StartLoc = Parser.getTok().getLoc();
444 
445   // Eat the % prefix.
446   if (Parser.getTok().isNot(AsmToken::Percent))
447     return Error(Parser.getTok().getLoc(), "register expected");
448   Parser.Lex();
449 
450   // Expect a register name.
451   if (Parser.getTok().isNot(AsmToken::Identifier))
452     return Error(Reg.StartLoc, "invalid register");
453 
454   // Check that there's a prefix.
455   StringRef Name = Parser.getTok().getString();
456   if (Name.size() < 2)
457     return Error(Reg.StartLoc, "invalid register");
458   char Prefix = Name[0];
459 
460   // Treat the rest of the register name as a register number.
461   if (Name.substr(1).getAsInteger(10, Reg.Num))
462     return Error(Reg.StartLoc, "invalid register");
463 
464   // Look for valid combinations of prefix and number.
465   if (Prefix == 'r' && Reg.Num < 16)
466     Reg.Group = RegGR;
467   else if (Prefix == 'f' && Reg.Num < 16)
468     Reg.Group = RegFP;
469   else if (Prefix == 'a' && Reg.Num < 16)
470     Reg.Group = RegAccess;
471   else
472     return Error(Reg.StartLoc, "invalid register");
473 
474   Reg.EndLoc = Parser.getTok().getLoc();
475   Parser.Lex();
476   return false;
477 }
478 
479 // Parse a register of group Group.  If Regs is nonnull, use it to map
480 // the raw register number to LLVM numbering, with zero entries indicating
481 // an invalid register.  IsAddress says whether the register appears in an
482 // address context.
483 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
484                                      const unsigned *Regs, bool IsAddress) {
485   if (parseRegister(Reg))
486     return true;
487   if (Reg.Group != Group)
488     return Error(Reg.StartLoc, "invalid operand for instruction");
489   if (Regs && Regs[Reg.Num] == 0)
490     return Error(Reg.StartLoc, "invalid register pair");
491   if (Reg.Num == 0 && IsAddress)
492     return Error(Reg.StartLoc, "%r0 used in an address");
493   if (Regs)
494     Reg.Num = Regs[Reg.Num];
495   return false;
496 }
497 
498 // Parse a register and add it to Operands.  The other arguments are as above.
499 SystemZAsmParser::OperandMatchResultTy
500 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
501                                 RegisterGroup Group, const unsigned *Regs,
502                                 RegisterKind Kind) {
503   if (Parser.getTok().isNot(AsmToken::Percent))
504     return MatchOperand_NoMatch;
505 
506   Register Reg;
507   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
508   if (parseRegister(Reg, Group, Regs, IsAddress))
509     return MatchOperand_ParseFail;
510 
511   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
512                                                Reg.StartLoc, Reg.EndLoc));
513   return MatchOperand_Success;
514 }
515 
516 // Parse a memory operand into Base, Disp, Index and Length.
517 // Regs maps asm register numbers to LLVM register numbers and RegKind
518 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
519 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
520                                     unsigned &Index, const MCExpr *&Length,
521                                     const unsigned *Regs,
522                                     RegisterKind RegKind) {
523   // Parse the displacement, which must always be present.
524   if (getParser().parseExpression(Disp))
525     return true;
526 
527   // Parse the optional base and index.
528   Index = 0;
529   Base = 0;
530   Length = nullptr;
531   if (getLexer().is(AsmToken::LParen)) {
532     Parser.Lex();
533 
534     if (getLexer().is(AsmToken::Percent)) {
535       // Parse the first register and decide whether it's a base or an index.
536       Register Reg;
537       if (parseRegister(Reg, RegGR, Regs, RegKind))
538         return true;
539       if (getLexer().is(AsmToken::Comma))
540         Index = Reg.Num;
541       else
542         Base = Reg.Num;
543     } else {
544       // Parse the length.
545       if (getParser().parseExpression(Length))
546         return true;
547     }
548 
549     // Check whether there's a second register.  It's the base if so.
550     if (getLexer().is(AsmToken::Comma)) {
551       Parser.Lex();
552       Register Reg;
553       if (parseRegister(Reg, RegGR, Regs, RegKind))
554         return true;
555       Base = Reg.Num;
556     }
557 
558     // Consume the closing bracket.
559     if (getLexer().isNot(AsmToken::RParen))
560       return Error(Parser.getTok().getLoc(), "unexpected token in address");
561     Parser.Lex();
562   }
563   return false;
564 }
565 
566 // Parse a memory operand and add it to Operands.  The other arguments
567 // are as above.
568 SystemZAsmParser::OperandMatchResultTy
569 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
570                                const unsigned *Regs, RegisterKind RegKind,
571                                MemoryKind MemKind) {
572   SMLoc StartLoc = Parser.getTok().getLoc();
573   unsigned Base, Index;
574   const MCExpr *Disp;
575   const MCExpr *Length;
576   if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
577     return MatchOperand_ParseFail;
578 
579   if (Index && MemKind != BDXMem)
580     {
581       Error(StartLoc, "invalid use of indexed addressing");
582       return MatchOperand_ParseFail;
583     }
584 
585   if (Length && MemKind != BDLMem)
586     {
587       Error(StartLoc, "invalid use of length addressing");
588       return MatchOperand_ParseFail;
589     }
590 
591   if (!Length && MemKind == BDLMem)
592     {
593       Error(StartLoc, "missing length in address");
594       return MatchOperand_ParseFail;
595     }
596 
597   SMLoc EndLoc =
598     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
599   Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
600                                                Length, StartLoc, EndLoc));
601   return MatchOperand_Success;
602 }
603 
604 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
605   return true;
606 }
607 
608 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
609                                      SMLoc &EndLoc) {
610   Register Reg;
611   if (parseRegister(Reg))
612     return true;
613   if (Reg.Group == RegGR)
614     RegNo = SystemZMC::GR64Regs[Reg.Num];
615   else if (Reg.Group == RegFP)
616     RegNo = SystemZMC::FP64Regs[Reg.Num];
617   else
618     // FIXME: Access registers aren't modelled as LLVM registers yet.
619     return Error(Reg.StartLoc, "invalid operand for instruction");
620   StartLoc = Reg.StartLoc;
621   EndLoc = Reg.EndLoc;
622   return false;
623 }
624 
625 bool SystemZAsmParser::
626 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
627                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
628   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
629 
630   // Read the remaining operands.
631   if (getLexer().isNot(AsmToken::EndOfStatement)) {
632     // Read the first operand.
633     if (parseOperand(Operands, Name)) {
634       Parser.eatToEndOfStatement();
635       return true;
636     }
637 
638     // Read any subsequent operands.
639     while (getLexer().is(AsmToken::Comma)) {
640       Parser.Lex();
641       if (parseOperand(Operands, Name)) {
642         Parser.eatToEndOfStatement();
643         return true;
644       }
645     }
646     if (getLexer().isNot(AsmToken::EndOfStatement)) {
647       SMLoc Loc = getLexer().getLoc();
648       Parser.eatToEndOfStatement();
649       return Error(Loc, "unexpected token in argument list");
650     }
651   }
652 
653   // Consume the EndOfStatement.
654   Parser.Lex();
655   return false;
656 }
657 
658 bool SystemZAsmParser::
659 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
660              StringRef Mnemonic) {
661   // Check if the current operand has a custom associated parser, if so, try to
662   // custom parse the operand, or fallback to the general approach.
663   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
664   if (ResTy == MatchOperand_Success)
665     return false;
666 
667   // If there wasn't a custom match, try the generic matcher below. Otherwise,
668   // there was a match, but an error occurred, in which case, just return that
669   // the operand parsing failed.
670   if (ResTy == MatchOperand_ParseFail)
671     return true;
672 
673   // Check for a register.  All real register operands should have used
674   // a context-dependent parse routine, which gives the required register
675   // class.  The code is here to mop up other cases, like those where
676   // the instruction isn't recognized.
677   if (Parser.getTok().is(AsmToken::Percent)) {
678     Register Reg;
679     if (parseRegister(Reg))
680       return true;
681     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
682     return false;
683   }
684 
685   // The only other type of operand is an immediate or address.  As above,
686   // real address operands should have used a context-dependent parse routine,
687   // so we treat any plain expression as an immediate.
688   SMLoc StartLoc = Parser.getTok().getLoc();
689   unsigned Base, Index;
690   const MCExpr *Expr, *Length;
691   if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
692     return true;
693 
694   SMLoc EndLoc =
695     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
696   if (Base || Index || Length)
697     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
698   else
699     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
700   return false;
701 }
702 
703 bool SystemZAsmParser::
704 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
705                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
706                         MCStreamer &Out, unsigned &ErrorInfo,
707                         bool MatchingInlineAsm) {
708   MCInst Inst;
709   unsigned MatchResult;
710 
711   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
712                                      MatchingInlineAsm);
713   switch (MatchResult) {
714   default: break;
715   case Match_Success:
716     Inst.setLoc(IDLoc);
717     Out.EmitInstruction(Inst, STI);
718     return false;
719 
720   case Match_MissingFeature: {
721     assert(ErrorInfo && "Unknown missing feature!");
722     // Special case the error message for the very common case where only
723     // a single subtarget feature is missing
724     std::string Msg = "instruction requires:";
725     unsigned Mask = 1;
726     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
727       if (ErrorInfo & Mask) {
728         Msg += " ";
729         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
730       }
731       Mask <<= 1;
732     }
733     return Error(IDLoc, Msg);
734   }
735 
736   case Match_InvalidOperand: {
737     SMLoc ErrorLoc = IDLoc;
738     if (ErrorInfo != ~0U) {
739       if (ErrorInfo >= Operands.size())
740         return Error(IDLoc, "too few operands for instruction");
741 
742       ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
743       if (ErrorLoc == SMLoc())
744         ErrorLoc = IDLoc;
745     }
746     return Error(ErrorLoc, "invalid operand for instruction");
747   }
748 
749   case Match_MnemonicFail:
750     return Error(IDLoc, "invalid instruction");
751   }
752 
753   llvm_unreachable("Unexpected match type");
754 }
755 
756 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
757 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
758   if (Parser.getTok().isNot(AsmToken::Percent))
759     return MatchOperand_NoMatch;
760 
761   Register Reg;
762   if (parseRegister(Reg, RegAccess, nullptr))
763     return MatchOperand_ParseFail;
764 
765   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
766                                                      Reg.StartLoc,
767                                                      Reg.EndLoc));
768   return MatchOperand_Success;
769 }
770 
771 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
772 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
773            int64_t MinVal, int64_t MaxVal) {
774   MCContext &Ctx = getContext();
775   MCStreamer &Out = getStreamer();
776   const MCExpr *Expr;
777   SMLoc StartLoc = Parser.getTok().getLoc();
778   if (getParser().parseExpression(Expr))
779     return MatchOperand_NoMatch;
780 
781   // For consistency with the GNU assembler, treat immediates as offsets
782   // from ".".
783   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
784     int64_t Value = CE->getValue();
785     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
786       Error(StartLoc, "offset out of range");
787       return MatchOperand_ParseFail;
788     }
789     MCSymbol *Sym = Ctx.CreateTempSymbol();
790     Out.EmitLabel(Sym);
791     const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
792                                                  Ctx);
793     Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
794   }
795 
796   SMLoc EndLoc =
797     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
798   Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
799   return MatchOperand_Success;
800 }
801 
802 // Force static initialization.
803 extern "C" void LLVMInitializeSystemZAsmParser() {
804   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
805 }
806