1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/SMLoc.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <iterator>
34 #include <memory>
35 #include <string>
36 
37 using namespace llvm;
38 
39 // Return true if Expr is in the range [MinValue, MaxValue].
40 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
41   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
42     int64_t Value = CE->getValue();
43     return Value >= MinValue && Value <= MaxValue;
44   }
45   return false;
46 }
47 
48 namespace {
49 
50 enum RegisterKind {
51   GR32Reg,
52   GRH32Reg,
53   GR64Reg,
54   GR128Reg,
55   ADDR32Reg,
56   ADDR64Reg,
57   FP32Reg,
58   FP64Reg,
59   FP128Reg,
60   VR32Reg,
61   VR64Reg,
62   VR128Reg,
63   AR32Reg,
64   CR64Reg,
65 };
66 
67 enum MemoryKind {
68   BDMem,
69   BDXMem,
70   BDLMem,
71   BDRMem,
72   BDVMem
73 };
74 
75 class SystemZOperand : public MCParsedAsmOperand {
76 private:
77   enum OperandKind {
78     KindInvalid,
79     KindToken,
80     KindReg,
81     KindImm,
82     KindImmTLS,
83     KindMem
84   };
85 
86   OperandKind Kind;
87   SMLoc StartLoc, EndLoc;
88 
89   // A string of length Length, starting at Data.
90   struct TokenOp {
91     const char *Data;
92     unsigned Length;
93   };
94 
95   // LLVM register Num, which has kind Kind.  In some ways it might be
96   // easier for this class to have a register bank (general, floating-point
97   // or access) and a raw register number (0-15).  This would postpone the
98   // interpretation of the operand to the add*() methods and avoid the need
99   // for context-dependent parsing.  However, we do things the current way
100   // because of the virtual getReg() method, which needs to distinguish
101   // between (say) %r0 used as a single register and %r0 used as a pair.
102   // Context-dependent parsing can also give us slightly better error
103   // messages when invalid pairs like %r1 are used.
104   struct RegOp {
105     RegisterKind Kind;
106     unsigned Num;
107   };
108 
109   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
110   // MemKind says what type of memory this is and RegKind says what type
111   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
112   // length for D(L,B)-style operands, otherwise it is null.
113   struct MemOp {
114     unsigned Base : 12;
115     unsigned Index : 12;
116     unsigned MemKind : 4;
117     unsigned RegKind : 4;
118     const MCExpr *Disp;
119     union {
120       const MCExpr *Imm;
121       unsigned Reg;
122     } Length;
123   };
124 
125   // Imm is an immediate operand, and Sym is an optional TLS symbol
126   // for use with a __tls_get_offset marker relocation.
127   struct ImmTLSOp {
128     const MCExpr *Imm;
129     const MCExpr *Sym;
130   };
131 
132   union {
133     TokenOp Token;
134     RegOp Reg;
135     const MCExpr *Imm;
136     ImmTLSOp ImmTLS;
137     MemOp Mem;
138   };
139 
140   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
141     // Add as immediates when possible.  Null MCExpr = 0.
142     if (!Expr)
143       Inst.addOperand(MCOperand::createImm(0));
144     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
145       Inst.addOperand(MCOperand::createImm(CE->getValue()));
146     else
147       Inst.addOperand(MCOperand::createExpr(Expr));
148   }
149 
150 public:
151   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
152       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
153 
154   // Create particular kinds of operand.
155   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
156                                                        SMLoc EndLoc) {
157     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
158   }
159 
160   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
161     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
162     Op->Token.Data = Str.data();
163     Op->Token.Length = Str.size();
164     return Op;
165   }
166 
167   static std::unique_ptr<SystemZOperand>
168   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
169     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
170     Op->Reg.Kind = Kind;
171     Op->Reg.Num = Num;
172     return Op;
173   }
174 
175   static std::unique_ptr<SystemZOperand>
176   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
177     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
178     Op->Imm = Expr;
179     return Op;
180   }
181 
182   static std::unique_ptr<SystemZOperand>
183   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
184             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
185             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
186     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
187     Op->Mem.MemKind = MemKind;
188     Op->Mem.RegKind = RegKind;
189     Op->Mem.Base = Base;
190     Op->Mem.Index = Index;
191     Op->Mem.Disp = Disp;
192     if (MemKind == BDLMem)
193       Op->Mem.Length.Imm = LengthImm;
194     if (MemKind == BDRMem)
195       Op->Mem.Length.Reg = LengthReg;
196     return Op;
197   }
198 
199   static std::unique_ptr<SystemZOperand>
200   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
201                SMLoc StartLoc, SMLoc EndLoc) {
202     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
203     Op->ImmTLS.Imm = Imm;
204     Op->ImmTLS.Sym = Sym;
205     return Op;
206   }
207 
208   // Token operands
209   bool isToken() const override {
210     return Kind == KindToken;
211   }
212   StringRef getToken() const {
213     assert(Kind == KindToken && "Not a token");
214     return StringRef(Token.Data, Token.Length);
215   }
216 
217   // Register operands.
218   bool isReg() const override {
219     return Kind == KindReg;
220   }
221   bool isReg(RegisterKind RegKind) const {
222     return Kind == KindReg && Reg.Kind == RegKind;
223   }
224   unsigned getReg() const override {
225     assert(Kind == KindReg && "Not a register");
226     return Reg.Num;
227   }
228 
229   // Immediate operands.
230   bool isImm() const override {
231     return Kind == KindImm;
232   }
233   bool isImm(int64_t MinValue, int64_t MaxValue) const {
234     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
235   }
236   const MCExpr *getImm() const {
237     assert(Kind == KindImm && "Not an immediate");
238     return Imm;
239   }
240 
241   // Immediate operands with optional TLS symbol.
242   bool isImmTLS() const {
243     return Kind == KindImmTLS;
244   }
245 
246   const ImmTLSOp getImmTLS() const {
247     assert(Kind == KindImmTLS && "Not a TLS immediate");
248     return ImmTLS;
249   }
250 
251   // Memory operands.
252   bool isMem() const override {
253     return Kind == KindMem;
254   }
255   bool isMem(MemoryKind MemKind) const {
256     return (Kind == KindMem &&
257             (Mem.MemKind == MemKind ||
258              // A BDMem can be treated as a BDXMem in which the index
259              // register field is 0.
260              (Mem.MemKind == BDMem && MemKind == BDXMem)));
261   }
262   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
263     return isMem(MemKind) && Mem.RegKind == RegKind;
264   }
265   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
266     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
267   }
268   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
269     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
270   }
271   bool isMemDisp12Len4(RegisterKind RegKind) const {
272     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
273   }
274   bool isMemDisp12Len8(RegisterKind RegKind) const {
275     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
276   }
277 
278   const MemOp& getMem() const {
279     assert(Kind == KindMem && "Not a Mem operand");
280     return Mem;
281   }
282 
283   // Override MCParsedAsmOperand.
284   SMLoc getStartLoc() const override { return StartLoc; }
285   SMLoc getEndLoc() const override { return EndLoc; }
286   void print(raw_ostream &OS) const override;
287 
288   /// getLocRange - Get the range between the first and last token of this
289   /// operand.
290   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
291 
292   // Used by the TableGen code to add particular types of operand
293   // to an instruction.
294   void addRegOperands(MCInst &Inst, unsigned N) const {
295     assert(N == 1 && "Invalid number of operands");
296     Inst.addOperand(MCOperand::createReg(getReg()));
297   }
298   void addImmOperands(MCInst &Inst, unsigned N) const {
299     assert(N == 1 && "Invalid number of operands");
300     addExpr(Inst, getImm());
301   }
302   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
303     assert(N == 2 && "Invalid number of operands");
304     assert(isMem(BDMem) && "Invalid operand type");
305     Inst.addOperand(MCOperand::createReg(Mem.Base));
306     addExpr(Inst, Mem.Disp);
307   }
308   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
309     assert(N == 3 && "Invalid number of operands");
310     assert(isMem(BDXMem) && "Invalid operand type");
311     Inst.addOperand(MCOperand::createReg(Mem.Base));
312     addExpr(Inst, Mem.Disp);
313     Inst.addOperand(MCOperand::createReg(Mem.Index));
314   }
315   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
316     assert(N == 3 && "Invalid number of operands");
317     assert(isMem(BDLMem) && "Invalid operand type");
318     Inst.addOperand(MCOperand::createReg(Mem.Base));
319     addExpr(Inst, Mem.Disp);
320     addExpr(Inst, Mem.Length.Imm);
321   }
322   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
323     assert(N == 3 && "Invalid number of operands");
324     assert(isMem(BDRMem) && "Invalid operand type");
325     Inst.addOperand(MCOperand::createReg(Mem.Base));
326     addExpr(Inst, Mem.Disp);
327     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
328   }
329   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
330     assert(N == 3 && "Invalid number of operands");
331     assert(isMem(BDVMem) && "Invalid operand type");
332     Inst.addOperand(MCOperand::createReg(Mem.Base));
333     addExpr(Inst, Mem.Disp);
334     Inst.addOperand(MCOperand::createReg(Mem.Index));
335   }
336   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
337     assert(N == 2 && "Invalid number of operands");
338     assert(Kind == KindImmTLS && "Invalid operand type");
339     addExpr(Inst, ImmTLS.Imm);
340     if (ImmTLS.Sym)
341       addExpr(Inst, ImmTLS.Sym);
342   }
343 
344   // Used by the TableGen code to check for particular operand types.
345   bool isGR32() const { return isReg(GR32Reg); }
346   bool isGRH32() const { return isReg(GRH32Reg); }
347   bool isGRX32() const { return false; }
348   bool isGR64() const { return isReg(GR64Reg); }
349   bool isGR128() const { return isReg(GR128Reg); }
350   bool isADDR32() const { return isReg(ADDR32Reg); }
351   bool isADDR64() const { return isReg(ADDR64Reg); }
352   bool isADDR128() const { return false; }
353   bool isFP32() const { return isReg(FP32Reg); }
354   bool isFP64() const { return isReg(FP64Reg); }
355   bool isFP128() const { return isReg(FP128Reg); }
356   bool isVR32() const { return isReg(VR32Reg); }
357   bool isVR64() const { return isReg(VR64Reg); }
358   bool isVF128() const { return false; }
359   bool isVR128() const { return isReg(VR128Reg); }
360   bool isAR32() const { return isReg(AR32Reg); }
361   bool isCR64() const { return isReg(CR64Reg); }
362   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
363   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
364   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
365   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
366   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
367   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
368   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
369   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
370   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
371   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
372   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
373   bool isU1Imm() const { return isImm(0, 1); }
374   bool isU2Imm() const { return isImm(0, 3); }
375   bool isU3Imm() const { return isImm(0, 7); }
376   bool isU4Imm() const { return isImm(0, 15); }
377   bool isU6Imm() const { return isImm(0, 63); }
378   bool isU8Imm() const { return isImm(0, 255); }
379   bool isS8Imm() const { return isImm(-128, 127); }
380   bool isU12Imm() const { return isImm(0, 4095); }
381   bool isU16Imm() const { return isImm(0, 65535); }
382   bool isS16Imm() const { return isImm(-32768, 32767); }
383   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
384   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
385   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
386 };
387 
388 class SystemZAsmParser : public MCTargetAsmParser {
389 #define GET_ASSEMBLER_HEADER
390 #include "SystemZGenAsmMatcher.inc"
391 
392 private:
393   MCAsmParser &Parser;
394   enum RegisterGroup {
395     RegGR,
396     RegFP,
397     RegV,
398     RegAR,
399     RegCR
400   };
401   struct Register {
402     RegisterGroup Group;
403     unsigned Num;
404     SMLoc StartLoc, EndLoc;
405   };
406 
407   bool parseRegister(Register &Reg);
408 
409   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
410                      bool IsAddress = false);
411 
412   OperandMatchResultTy parseRegister(OperandVector &Operands,
413                                      RegisterGroup Group, const unsigned *Regs,
414                                      RegisterKind Kind);
415 
416   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
417 
418   bool parseAddress(bool &HaveReg1, Register &Reg1,
419                     bool &HaveReg2, Register &Reg2,
420                     const MCExpr *&Disp, const MCExpr *&Length);
421   bool parseAddressRegister(Register &Reg);
422 
423   bool ParseDirectiveInsn(SMLoc L);
424 
425   OperandMatchResultTy parseAddress(OperandVector &Operands,
426                                     MemoryKind MemKind, const unsigned *Regs,
427                                     RegisterKind RegKind);
428 
429   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
430                                   int64_t MaxVal, bool AllowTLS);
431 
432   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
433 
434 public:
435   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
436                    const MCInstrInfo &MII,
437                    const MCTargetOptions &Options)
438     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
439     MCAsmParserExtension::Initialize(Parser);
440 
441     // Alias the .word directive to .short.
442     parser.addAliasForDirective(".word", ".short");
443 
444     // Initialize the set of available features.
445     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
446   }
447 
448   // Override MCTargetAsmParser.
449   bool ParseDirective(AsmToken DirectiveID) override;
450   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
451   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
452                         SMLoc NameLoc, OperandVector &Operands) override;
453   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
454                                OperandVector &Operands, MCStreamer &Out,
455                                uint64_t &ErrorInfo,
456                                bool MatchingInlineAsm) override;
457 
458   // Used by the TableGen code to parse particular operand types.
459   OperandMatchResultTy parseGR32(OperandVector &Operands) {
460     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
461   }
462   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
463     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
464   }
465   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
466     llvm_unreachable("GRX32 should only be used for pseudo instructions");
467   }
468   OperandMatchResultTy parseGR64(OperandVector &Operands) {
469     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
470   }
471   OperandMatchResultTy parseGR128(OperandVector &Operands) {
472     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
473   }
474   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
475     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
476   }
477   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
478     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
479   }
480   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
481     llvm_unreachable("Shouldn't be used as an operand");
482   }
483   OperandMatchResultTy parseFP32(OperandVector &Operands) {
484     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
485   }
486   OperandMatchResultTy parseFP64(OperandVector &Operands) {
487     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
488   }
489   OperandMatchResultTy parseFP128(OperandVector &Operands) {
490     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
491   }
492   OperandMatchResultTy parseVR32(OperandVector &Operands) {
493     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
494   }
495   OperandMatchResultTy parseVR64(OperandVector &Operands) {
496     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
497   }
498   OperandMatchResultTy parseVF128(OperandVector &Operands) {
499     llvm_unreachable("Shouldn't be used as an operand");
500   }
501   OperandMatchResultTy parseVR128(OperandVector &Operands) {
502     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
503   }
504   OperandMatchResultTy parseAR32(OperandVector &Operands) {
505     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
506   }
507   OperandMatchResultTy parseCR64(OperandVector &Operands) {
508     return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
509   }
510   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
511     return parseAnyRegister(Operands);
512   }
513   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
514     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
515   }
516   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
517     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
518   }
519   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
520     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
521   }
522   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
523     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
524   }
525   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
526     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
527   }
528   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
529     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
530   }
531   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
532     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
533   }
534   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
535     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
536   }
537   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
538     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
539   }
540   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
541     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
542   }
543   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
544     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
545   }
546   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
547     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
548   }
549 };
550 
551 } // end anonymous namespace
552 
553 #define GET_REGISTER_MATCHER
554 #define GET_SUBTARGET_FEATURE_NAME
555 #define GET_MATCHER_IMPLEMENTATION
556 #define GET_MNEMONIC_SPELL_CHECKER
557 #include "SystemZGenAsmMatcher.inc"
558 
559 // Used for the .insn directives; contains information needed to parse the
560 // operands in the directive.
561 struct InsnMatchEntry {
562   StringRef Format;
563   uint64_t Opcode;
564   int32_t NumOperands;
565   MatchClassKind OperandKinds[5];
566 };
567 
568 // For equal_range comparison.
569 struct CompareInsn {
570   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
571     return LHS.Format < RHS;
572   }
573   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
574     return LHS < RHS.Format;
575   }
576   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
577     return LHS.Format < RHS.Format;
578   }
579 };
580 
581 // Table initializing information for parsing the .insn directive.
582 static struct InsnMatchEntry InsnMatchTable[] = {
583   /* Format, Opcode, NumOperands, OperandKinds */
584   { "e", SystemZ::InsnE, 1,
585     { MCK_U16Imm } },
586   { "ri", SystemZ::InsnRI, 3,
587     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
588   { "rie", SystemZ::InsnRIE, 4,
589     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
590   { "ril", SystemZ::InsnRIL, 3,
591     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
592   { "rilu", SystemZ::InsnRILU, 3,
593     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
594   { "ris", SystemZ::InsnRIS, 5,
595     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
596   { "rr", SystemZ::InsnRR, 3,
597     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
598   { "rre", SystemZ::InsnRRE, 3,
599     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
600   { "rrf", SystemZ::InsnRRF, 5,
601     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
602   { "rrs", SystemZ::InsnRRS, 5,
603     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
604   { "rs", SystemZ::InsnRS, 4,
605     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
606   { "rse", SystemZ::InsnRSE, 4,
607     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
608   { "rsi", SystemZ::InsnRSI, 4,
609     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
610   { "rsy", SystemZ::InsnRSY, 4,
611     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
612   { "rx", SystemZ::InsnRX, 3,
613     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
614   { "rxe", SystemZ::InsnRXE, 3,
615     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
616   { "rxf", SystemZ::InsnRXF, 4,
617     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
618   { "rxy", SystemZ::InsnRXY, 3,
619     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
620   { "s", SystemZ::InsnS, 2,
621     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
622   { "si", SystemZ::InsnSI, 3,
623     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
624   { "sil", SystemZ::InsnSIL, 3,
625     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
626   { "siy", SystemZ::InsnSIY, 3,
627     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
628   { "ss", SystemZ::InsnSS, 4,
629     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
630   { "sse", SystemZ::InsnSSE, 3,
631     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
632   { "ssf", SystemZ::InsnSSF, 4,
633     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
634 };
635 
636 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
637   if (!E)
638     return;
639   if (auto *CE = dyn_cast<MCConstantExpr>(E))
640     OS << *CE;
641   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
642     OS << *UE;
643   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
644     OS << *BE;
645   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
646     OS << *SRE;
647   else
648     OS << *E;
649 }
650 
651 void SystemZOperand::print(raw_ostream &OS) const {
652   switch (Kind) {
653   case KindToken:
654     OS << "Token:" << getToken();
655     break;
656   case KindReg:
657     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
658     break;
659   case KindImm:
660     OS << "Imm:";
661     printMCExpr(getImm(), OS);
662     break;
663   case KindImmTLS:
664     OS << "ImmTLS:";
665     printMCExpr(getImmTLS().Imm, OS);
666     if (getImmTLS().Sym) {
667       OS << ", ";
668       printMCExpr(getImmTLS().Sym, OS);
669     }
670     break;
671   case KindMem: {
672     const MemOp &Op = getMem();
673     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
674     if (Op.Base) {
675       OS << "(";
676       if (Op.MemKind == BDLMem)
677         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
678       else if (Op.MemKind == BDRMem)
679         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
680       if (Op.Index)
681         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
682       OS << SystemZInstPrinter::getRegisterName(Op.Base);
683       OS << ")";
684     }
685     break;
686   }
687   case KindInvalid:
688     break;
689   }
690 }
691 
692 // Parse one register of the form %<prefix><number>.
693 bool SystemZAsmParser::parseRegister(Register &Reg) {
694   Reg.StartLoc = Parser.getTok().getLoc();
695 
696   // Eat the % prefix.
697   if (Parser.getTok().isNot(AsmToken::Percent))
698     return Error(Parser.getTok().getLoc(), "register expected");
699   Parser.Lex();
700 
701   // Expect a register name.
702   if (Parser.getTok().isNot(AsmToken::Identifier))
703     return Error(Reg.StartLoc, "invalid register");
704 
705   // Check that there's a prefix.
706   StringRef Name = Parser.getTok().getString();
707   if (Name.size() < 2)
708     return Error(Reg.StartLoc, "invalid register");
709   char Prefix = Name[0];
710 
711   // Treat the rest of the register name as a register number.
712   if (Name.substr(1).getAsInteger(10, Reg.Num))
713     return Error(Reg.StartLoc, "invalid register");
714 
715   // Look for valid combinations of prefix and number.
716   if (Prefix == 'r' && Reg.Num < 16)
717     Reg.Group = RegGR;
718   else if (Prefix == 'f' && Reg.Num < 16)
719     Reg.Group = RegFP;
720   else if (Prefix == 'v' && Reg.Num < 32)
721     Reg.Group = RegV;
722   else if (Prefix == 'a' && Reg.Num < 16)
723     Reg.Group = RegAR;
724   else if (Prefix == 'c' && Reg.Num < 16)
725     Reg.Group = RegCR;
726   else
727     return Error(Reg.StartLoc, "invalid register");
728 
729   Reg.EndLoc = Parser.getTok().getLoc();
730   Parser.Lex();
731   return false;
732 }
733 
734 // Parse a register of group Group.  If Regs is nonnull, use it to map
735 // the raw register number to LLVM numbering, with zero entries
736 // indicating an invalid register.  IsAddress says whether the
737 // register appears in an address context. Allow FP Group if expecting
738 // RegV Group, since the f-prefix yields the FP group even while used
739 // with vector instructions.
740 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
741                                      const unsigned *Regs, bool IsAddress) {
742   if (parseRegister(Reg))
743     return true;
744   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
745     return Error(Reg.StartLoc, "invalid operand for instruction");
746   if (Regs && Regs[Reg.Num] == 0)
747     return Error(Reg.StartLoc, "invalid register pair");
748   if (Reg.Num == 0 && IsAddress)
749     return Error(Reg.StartLoc, "%r0 used in an address");
750   if (Regs)
751     Reg.Num = Regs[Reg.Num];
752   return false;
753 }
754 
755 // Parse a register and add it to Operands.  The other arguments are as above.
756 OperandMatchResultTy
757 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
758                                 const unsigned *Regs, RegisterKind Kind) {
759   if (Parser.getTok().isNot(AsmToken::Percent))
760     return MatchOperand_NoMatch;
761 
762   Register Reg;
763   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
764   if (parseRegister(Reg, Group, Regs, IsAddress))
765     return MatchOperand_ParseFail;
766 
767   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
768                                                Reg.StartLoc, Reg.EndLoc));
769   return MatchOperand_Success;
770 }
771 
772 // Parse any type of register (including integers) and add it to Operands.
773 OperandMatchResultTy
774 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
775   // Handle integer values.
776   if (Parser.getTok().is(AsmToken::Integer)) {
777     const MCExpr *Register;
778     SMLoc StartLoc = Parser.getTok().getLoc();
779     if (Parser.parseExpression(Register))
780       return MatchOperand_ParseFail;
781 
782     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
783       int64_t Value = CE->getValue();
784       if (Value < 0 || Value > 15) {
785         Error(StartLoc, "invalid register");
786         return MatchOperand_ParseFail;
787       }
788     }
789 
790     SMLoc EndLoc =
791       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
792 
793     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
794   }
795   else {
796     Register Reg;
797     if (parseRegister(Reg))
798       return MatchOperand_ParseFail;
799 
800     // Map to the correct register kind.
801     RegisterKind Kind;
802     unsigned RegNo;
803     if (Reg.Group == RegGR) {
804       Kind = GR64Reg;
805       RegNo = SystemZMC::GR64Regs[Reg.Num];
806     }
807     else if (Reg.Group == RegFP) {
808       Kind = FP64Reg;
809       RegNo = SystemZMC::FP64Regs[Reg.Num];
810     }
811     else if (Reg.Group == RegV) {
812       Kind = VR128Reg;
813       RegNo = SystemZMC::VR128Regs[Reg.Num];
814     }
815     else if (Reg.Group == RegAR) {
816       Kind = AR32Reg;
817       RegNo = SystemZMC::AR32Regs[Reg.Num];
818     }
819     else if (Reg.Group == RegCR) {
820       Kind = CR64Reg;
821       RegNo = SystemZMC::CR64Regs[Reg.Num];
822     }
823     else {
824       return MatchOperand_ParseFail;
825     }
826 
827     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
828                                                  Reg.StartLoc, Reg.EndLoc));
829   }
830   return MatchOperand_Success;
831 }
832 
833 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
834 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
835                                     bool &HaveReg2, Register &Reg2,
836                                     const MCExpr *&Disp,
837                                     const MCExpr *&Length) {
838   // Parse the displacement, which must always be present.
839   if (getParser().parseExpression(Disp))
840     return true;
841 
842   // Parse the optional base and index.
843   HaveReg1 = false;
844   HaveReg2 = false;
845   Length = nullptr;
846   if (getLexer().is(AsmToken::LParen)) {
847     Parser.Lex();
848 
849     if (getLexer().is(AsmToken::Percent)) {
850       // Parse the first register.
851       HaveReg1 = true;
852       if (parseRegister(Reg1))
853         return true;
854     } else {
855       // Parse the length.
856       if (getParser().parseExpression(Length))
857         return true;
858     }
859 
860     // Check whether there's a second register.
861     if (getLexer().is(AsmToken::Comma)) {
862       Parser.Lex();
863       HaveReg2 = true;
864       if (parseRegister(Reg2))
865         return true;
866     }
867 
868     // Consume the closing bracket.
869     if (getLexer().isNot(AsmToken::RParen))
870       return Error(Parser.getTok().getLoc(), "unexpected token in address");
871     Parser.Lex();
872   }
873   return false;
874 }
875 
876 // Verify that Reg is a valid address register (base or index).
877 bool
878 SystemZAsmParser::parseAddressRegister(Register &Reg) {
879   if (Reg.Group == RegV) {
880     Error(Reg.StartLoc, "invalid use of vector addressing");
881     return true;
882   } else if (Reg.Group != RegGR) {
883     Error(Reg.StartLoc, "invalid address register");
884     return true;
885   } else if (Reg.Num == 0) {
886     Error(Reg.StartLoc, "%r0 used in an address");
887     return true;
888   }
889   return false;
890 }
891 
892 // Parse a memory operand and add it to Operands.  The other arguments
893 // are as above.
894 OperandMatchResultTy
895 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
896                                const unsigned *Regs, RegisterKind RegKind) {
897   SMLoc StartLoc = Parser.getTok().getLoc();
898   unsigned Base = 0, Index = 0, LengthReg = 0;
899   Register Reg1, Reg2;
900   bool HaveReg1, HaveReg2;
901   const MCExpr *Disp;
902   const MCExpr *Length;
903   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
904     return MatchOperand_ParseFail;
905 
906   switch (MemKind) {
907   case BDMem:
908     // If we have Reg1, it must be an address register.
909     if (HaveReg1) {
910       if (parseAddressRegister(Reg1))
911         return MatchOperand_ParseFail;
912       Base = Regs[Reg1.Num];
913     }
914     // There must be no Reg2 or length.
915     if (Length) {
916       Error(StartLoc, "invalid use of length addressing");
917       return MatchOperand_ParseFail;
918     }
919     if (HaveReg2) {
920       Error(StartLoc, "invalid use of indexed addressing");
921       return MatchOperand_ParseFail;
922     }
923     break;
924   case BDXMem:
925     // If we have Reg1, it must be an address register.
926     if (HaveReg1) {
927       if (parseAddressRegister(Reg1))
928         return MatchOperand_ParseFail;
929       // If the are two registers, the first one is the index and the
930       // second is the base.
931       if (HaveReg2)
932         Index = Regs[Reg1.Num];
933       else
934         Base = Regs[Reg1.Num];
935     }
936     // If we have Reg2, it must be an address register.
937     if (HaveReg2) {
938       if (parseAddressRegister(Reg2))
939         return MatchOperand_ParseFail;
940       Base = Regs[Reg2.Num];
941     }
942     // There must be no length.
943     if (Length) {
944       Error(StartLoc, "invalid use of length addressing");
945       return MatchOperand_ParseFail;
946     }
947     break;
948   case BDLMem:
949     // If we have Reg2, it must be an address register.
950     if (HaveReg2) {
951       if (parseAddressRegister(Reg2))
952         return MatchOperand_ParseFail;
953       Base = Regs[Reg2.Num];
954     }
955     // We cannot support base+index addressing.
956     if (HaveReg1 && HaveReg2) {
957       Error(StartLoc, "invalid use of indexed addressing");
958       return MatchOperand_ParseFail;
959     }
960     // We must have a length.
961     if (!Length) {
962       Error(StartLoc, "missing length in address");
963       return MatchOperand_ParseFail;
964     }
965     break;
966   case BDRMem:
967     // We must have Reg1, and it must be a GPR.
968     if (!HaveReg1 || Reg1.Group != RegGR) {
969       Error(StartLoc, "invalid operand for instruction");
970       return MatchOperand_ParseFail;
971     }
972     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
973     // If we have Reg2, it must be an address register.
974     if (HaveReg2) {
975       if (parseAddressRegister(Reg2))
976         return MatchOperand_ParseFail;
977       Base = Regs[Reg2.Num];
978     }
979     // There must be no length.
980     if (Length) {
981       Error(StartLoc, "invalid use of length addressing");
982       return MatchOperand_ParseFail;
983     }
984     break;
985   case BDVMem:
986     // We must have Reg1, and it must be a vector register.
987     if (!HaveReg1 || Reg1.Group != RegV) {
988       Error(StartLoc, "vector index required in address");
989       return MatchOperand_ParseFail;
990     }
991     Index = SystemZMC::VR128Regs[Reg1.Num];
992     // If we have Reg2, it must be an address register.
993     if (HaveReg2) {
994       if (parseAddressRegister(Reg2))
995         return MatchOperand_ParseFail;
996       Base = Regs[Reg2.Num];
997     }
998     // There must be no length.
999     if (Length) {
1000       Error(StartLoc, "invalid use of length addressing");
1001       return MatchOperand_ParseFail;
1002     }
1003     break;
1004   }
1005 
1006   SMLoc EndLoc =
1007     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1008   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1009                                                Index, Length, LengthReg,
1010                                                StartLoc, EndLoc));
1011   return MatchOperand_Success;
1012 }
1013 
1014 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1015   StringRef IDVal = DirectiveID.getIdentifier();
1016 
1017   if (IDVal == ".insn")
1018     return ParseDirectiveInsn(DirectiveID.getLoc());
1019 
1020   return true;
1021 }
1022 
1023 /// ParseDirectiveInsn
1024 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1025 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1026   MCAsmParser &Parser = getParser();
1027 
1028   // Expect instruction format as identifier.
1029   StringRef Format;
1030   SMLoc ErrorLoc = Parser.getTok().getLoc();
1031   if (Parser.parseIdentifier(Format))
1032     return Error(ErrorLoc, "expected instruction format");
1033 
1034   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1035 
1036   // Find entry for this format in InsnMatchTable.
1037   auto EntryRange =
1038     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1039                      Format, CompareInsn());
1040 
1041   // If first == second, couldn't find a match in the table.
1042   if (EntryRange.first == EntryRange.second)
1043     return Error(ErrorLoc, "unrecognized format");
1044 
1045   struct InsnMatchEntry *Entry = EntryRange.first;
1046 
1047   // Format should match from equal_range.
1048   assert(Entry->Format == Format);
1049 
1050   // Parse the following operands using the table's information.
1051   for (int i = 0; i < Entry->NumOperands; i++) {
1052     MatchClassKind Kind = Entry->OperandKinds[i];
1053 
1054     SMLoc StartLoc = Parser.getTok().getLoc();
1055 
1056     // Always expect commas as separators for operands.
1057     if (getLexer().isNot(AsmToken::Comma))
1058       return Error(StartLoc, "unexpected token in directive");
1059     Lex();
1060 
1061     // Parse operands.
1062     OperandMatchResultTy ResTy;
1063     if (Kind == MCK_AnyReg)
1064       ResTy = parseAnyReg(Operands);
1065     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1066       ResTy = parseBDXAddr64(Operands);
1067     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1068       ResTy = parseBDAddr64(Operands);
1069     else if (Kind == MCK_PCRel32)
1070       ResTy = parsePCRel32(Operands);
1071     else if (Kind == MCK_PCRel16)
1072       ResTy = parsePCRel16(Operands);
1073     else {
1074       // Only remaining operand kind is an immediate.
1075       const MCExpr *Expr;
1076       SMLoc StartLoc = Parser.getTok().getLoc();
1077 
1078       // Expect immediate expression.
1079       if (Parser.parseExpression(Expr))
1080         return Error(StartLoc, "unexpected token in directive");
1081 
1082       SMLoc EndLoc =
1083         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1084 
1085       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1086       ResTy = MatchOperand_Success;
1087     }
1088 
1089     if (ResTy != MatchOperand_Success)
1090       return true;
1091   }
1092 
1093   // Build the instruction with the parsed operands.
1094   MCInst Inst = MCInstBuilder(Entry->Opcode);
1095 
1096   for (size_t i = 0; i < Operands.size(); i++) {
1097     MCParsedAsmOperand &Operand = *Operands[i];
1098     MatchClassKind Kind = Entry->OperandKinds[i];
1099 
1100     // Verify operand.
1101     unsigned Res = validateOperandClass(Operand, Kind);
1102     if (Res != Match_Success)
1103       return Error(Operand.getStartLoc(), "unexpected operand type");
1104 
1105     // Add operands to instruction.
1106     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1107     if (ZOperand.isReg())
1108       ZOperand.addRegOperands(Inst, 1);
1109     else if (ZOperand.isMem(BDMem))
1110       ZOperand.addBDAddrOperands(Inst, 2);
1111     else if (ZOperand.isMem(BDXMem))
1112       ZOperand.addBDXAddrOperands(Inst, 3);
1113     else if (ZOperand.isImm())
1114       ZOperand.addImmOperands(Inst, 1);
1115     else
1116       llvm_unreachable("unexpected operand type");
1117   }
1118 
1119   // Emit as a regular instruction.
1120   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1121 
1122   return false;
1123 }
1124 
1125 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1126                                      SMLoc &EndLoc) {
1127   Register Reg;
1128   if (parseRegister(Reg))
1129     return true;
1130   if (Reg.Group == RegGR)
1131     RegNo = SystemZMC::GR64Regs[Reg.Num];
1132   else if (Reg.Group == RegFP)
1133     RegNo = SystemZMC::FP64Regs[Reg.Num];
1134   else if (Reg.Group == RegV)
1135     RegNo = SystemZMC::VR128Regs[Reg.Num];
1136   else if (Reg.Group == RegAR)
1137     RegNo = SystemZMC::AR32Regs[Reg.Num];
1138   else if (Reg.Group == RegCR)
1139     RegNo = SystemZMC::CR64Regs[Reg.Num];
1140   StartLoc = Reg.StartLoc;
1141   EndLoc = Reg.EndLoc;
1142   return false;
1143 }
1144 
1145 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1146                                         StringRef Name, SMLoc NameLoc,
1147                                         OperandVector &Operands) {
1148   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1149 
1150   // Read the remaining operands.
1151   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1152     // Read the first operand.
1153     if (parseOperand(Operands, Name)) {
1154       return true;
1155     }
1156 
1157     // Read any subsequent operands.
1158     while (getLexer().is(AsmToken::Comma)) {
1159       Parser.Lex();
1160       if (parseOperand(Operands, Name)) {
1161         return true;
1162       }
1163     }
1164     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1165       SMLoc Loc = getLexer().getLoc();
1166       return Error(Loc, "unexpected token in argument list");
1167     }
1168   }
1169 
1170   // Consume the EndOfStatement.
1171   Parser.Lex();
1172   return false;
1173 }
1174 
1175 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1176                                     StringRef Mnemonic) {
1177   // Check if the current operand has a custom associated parser, if so, try to
1178   // custom parse the operand, or fallback to the general approach.  Force all
1179   // features to be available during the operand check, or else we will fail to
1180   // find the custom parser, and then we will later get an InvalidOperand error
1181   // instead of a MissingFeature errror.
1182   FeatureBitset AvailableFeatures = getAvailableFeatures();
1183   FeatureBitset All;
1184   All.set();
1185   setAvailableFeatures(All);
1186   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1187   setAvailableFeatures(AvailableFeatures);
1188   if (ResTy == MatchOperand_Success)
1189     return false;
1190 
1191   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1192   // there was a match, but an error occurred, in which case, just return that
1193   // the operand parsing failed.
1194   if (ResTy == MatchOperand_ParseFail)
1195     return true;
1196 
1197   // Check for a register.  All real register operands should have used
1198   // a context-dependent parse routine, which gives the required register
1199   // class.  The code is here to mop up other cases, like those where
1200   // the instruction isn't recognized.
1201   if (Parser.getTok().is(AsmToken::Percent)) {
1202     Register Reg;
1203     if (parseRegister(Reg))
1204       return true;
1205     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1206     return false;
1207   }
1208 
1209   // The only other type of operand is an immediate or address.  As above,
1210   // real address operands should have used a context-dependent parse routine,
1211   // so we treat any plain expression as an immediate.
1212   SMLoc StartLoc = Parser.getTok().getLoc();
1213   Register Reg1, Reg2;
1214   bool HaveReg1, HaveReg2;
1215   const MCExpr *Expr;
1216   const MCExpr *Length;
1217   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1218     return true;
1219   // If the register combination is not valid for any instruction, reject it.
1220   // Otherwise, fall back to reporting an unrecognized instruction.
1221   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1222       && parseAddressRegister(Reg1))
1223     return true;
1224   if (HaveReg2 && parseAddressRegister(Reg2))
1225     return true;
1226 
1227   SMLoc EndLoc =
1228     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1229   if (HaveReg1 || HaveReg2 || Length)
1230     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1231   else
1232     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1233   return false;
1234 }
1235 
1236 static std::string SystemZMnemonicSpellCheck(StringRef S,
1237                                              const FeatureBitset &FBS,
1238                                              unsigned VariantID = 0);
1239 
1240 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1241                                                OperandVector &Operands,
1242                                                MCStreamer &Out,
1243                                                uint64_t &ErrorInfo,
1244                                                bool MatchingInlineAsm) {
1245   MCInst Inst;
1246   unsigned MatchResult;
1247 
1248   FeatureBitset MissingFeatures;
1249   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1250                                      MissingFeatures, MatchingInlineAsm);
1251   switch (MatchResult) {
1252   case Match_Success:
1253     Inst.setLoc(IDLoc);
1254     Out.EmitInstruction(Inst, getSTI());
1255     return false;
1256 
1257   case Match_MissingFeature: {
1258     assert(MissingFeatures.any() && "Unknown missing feature!");
1259     // Special case the error message for the very common case where only
1260     // a single subtarget feature is missing
1261     std::string Msg = "instruction requires:";
1262     for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1263       if (MissingFeatures[I]) {
1264         Msg += " ";
1265         Msg += getSubtargetFeatureName(I);
1266       }
1267     }
1268     return Error(IDLoc, Msg);
1269   }
1270 
1271   case Match_InvalidOperand: {
1272     SMLoc ErrorLoc = IDLoc;
1273     if (ErrorInfo != ~0ULL) {
1274       if (ErrorInfo >= Operands.size())
1275         return Error(IDLoc, "too few operands for instruction");
1276 
1277       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1278       if (ErrorLoc == SMLoc())
1279         ErrorLoc = IDLoc;
1280     }
1281     return Error(ErrorLoc, "invalid operand for instruction");
1282   }
1283 
1284   case Match_MnemonicFail: {
1285     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1286     std::string Suggestion = SystemZMnemonicSpellCheck(
1287       ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1288     return Error(IDLoc, "invalid instruction" + Suggestion,
1289                  ((SystemZOperand &)*Operands[0]).getLocRange());
1290   }
1291   }
1292 
1293   llvm_unreachable("Unexpected match type");
1294 }
1295 
1296 OperandMatchResultTy
1297 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1298                              int64_t MaxVal, bool AllowTLS) {
1299   MCContext &Ctx = getContext();
1300   MCStreamer &Out = getStreamer();
1301   const MCExpr *Expr;
1302   SMLoc StartLoc = Parser.getTok().getLoc();
1303   if (getParser().parseExpression(Expr))
1304     return MatchOperand_NoMatch;
1305 
1306   // For consistency with the GNU assembler, treat immediates as offsets
1307   // from ".".
1308   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1309     int64_t Value = CE->getValue();
1310     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1311       Error(StartLoc, "offset out of range");
1312       return MatchOperand_ParseFail;
1313     }
1314     MCSymbol *Sym = Ctx.createTempSymbol();
1315     Out.EmitLabel(Sym);
1316     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1317                                                  Ctx);
1318     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1319   }
1320 
1321   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1322   const MCExpr *Sym = nullptr;
1323   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1324     Parser.Lex();
1325 
1326     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1327       Error(Parser.getTok().getLoc(), "unexpected token");
1328       return MatchOperand_ParseFail;
1329     }
1330 
1331     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1332     StringRef Name = Parser.getTok().getString();
1333     if (Name == "tls_gdcall")
1334       Kind = MCSymbolRefExpr::VK_TLSGD;
1335     else if (Name == "tls_ldcall")
1336       Kind = MCSymbolRefExpr::VK_TLSLDM;
1337     else {
1338       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1339       return MatchOperand_ParseFail;
1340     }
1341     Parser.Lex();
1342 
1343     if (Parser.getTok().isNot(AsmToken::Colon)) {
1344       Error(Parser.getTok().getLoc(), "unexpected token");
1345       return MatchOperand_ParseFail;
1346     }
1347     Parser.Lex();
1348 
1349     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1350       Error(Parser.getTok().getLoc(), "unexpected token");
1351       return MatchOperand_ParseFail;
1352     }
1353 
1354     StringRef Identifier = Parser.getTok().getString();
1355     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1356                                   Kind, Ctx);
1357     Parser.Lex();
1358   }
1359 
1360   SMLoc EndLoc =
1361     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1362 
1363   if (AllowTLS)
1364     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1365                                                     StartLoc, EndLoc));
1366   else
1367     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1368 
1369   return MatchOperand_Success;
1370 }
1371 
1372 // Force static initialization.
1373 extern "C" void LLVMInitializeSystemZAsmParser() {
1374   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1375 }
1376