1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/SMLoc.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <iterator>
34 #include <memory>
35 #include <string>
36 
37 using namespace llvm;
38 
39 // Return true if Expr is in the range [MinValue, MaxValue].
40 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
41   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
42     int64_t Value = CE->getValue();
43     return Value >= MinValue && Value <= MaxValue;
44   }
45   return false;
46 }
47 
48 namespace {
49 
50 enum RegisterKind {
51   GR32Reg,
52   GRH32Reg,
53   GR64Reg,
54   GR128Reg,
55   ADDR32Reg,
56   ADDR64Reg,
57   FP32Reg,
58   FP64Reg,
59   FP128Reg,
60   VR32Reg,
61   VR64Reg,
62   VR128Reg,
63   AR32Reg,
64 };
65 
66 enum MemoryKind {
67   BDMem,
68   BDXMem,
69   BDLMem,
70   BDRMem,
71   BDVMem
72 };
73 
74 class SystemZOperand : public MCParsedAsmOperand {
75 private:
76   enum OperandKind {
77     KindInvalid,
78     KindToken,
79     KindReg,
80     KindImm,
81     KindImmTLS,
82     KindMem
83   };
84 
85   OperandKind Kind;
86   SMLoc StartLoc, EndLoc;
87 
88   // A string of length Length, starting at Data.
89   struct TokenOp {
90     const char *Data;
91     unsigned Length;
92   };
93 
94   // LLVM register Num, which has kind Kind.  In some ways it might be
95   // easier for this class to have a register bank (general, floating-point
96   // or access) and a raw register number (0-15).  This would postpone the
97   // interpretation of the operand to the add*() methods and avoid the need
98   // for context-dependent parsing.  However, we do things the current way
99   // because of the virtual getReg() method, which needs to distinguish
100   // between (say) %r0 used as a single register and %r0 used as a pair.
101   // Context-dependent parsing can also give us slightly better error
102   // messages when invalid pairs like %r1 are used.
103   struct RegOp {
104     RegisterKind Kind;
105     unsigned Num;
106   };
107 
108   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
109   // MemKind says what type of memory this is and RegKind says what type
110   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
111   // length for D(L,B)-style operands, otherwise it is null.
112   struct MemOp {
113     unsigned Base : 12;
114     unsigned Index : 12;
115     unsigned MemKind : 4;
116     unsigned RegKind : 4;
117     const MCExpr *Disp;
118     union {
119       const MCExpr *Imm;
120       unsigned Reg;
121     } Length;
122   };
123 
124   // Imm is an immediate operand, and Sym is an optional TLS symbol
125   // for use with a __tls_get_offset marker relocation.
126   struct ImmTLSOp {
127     const MCExpr *Imm;
128     const MCExpr *Sym;
129   };
130 
131   union {
132     TokenOp Token;
133     RegOp Reg;
134     const MCExpr *Imm;
135     ImmTLSOp ImmTLS;
136     MemOp Mem;
137   };
138 
139   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
140     // Add as immediates when possible.  Null MCExpr = 0.
141     if (!Expr)
142       Inst.addOperand(MCOperand::createImm(0));
143     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
144       Inst.addOperand(MCOperand::createImm(CE->getValue()));
145     else
146       Inst.addOperand(MCOperand::createExpr(Expr));
147   }
148 
149 public:
150   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
151       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
152 
153   // Create particular kinds of operand.
154   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
155                                                        SMLoc EndLoc) {
156     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
157   }
158 
159   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
160     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
161     Op->Token.Data = Str.data();
162     Op->Token.Length = Str.size();
163     return Op;
164   }
165 
166   static std::unique_ptr<SystemZOperand>
167   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
168     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
169     Op->Reg.Kind = Kind;
170     Op->Reg.Num = Num;
171     return Op;
172   }
173 
174   static std::unique_ptr<SystemZOperand>
175   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
176     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
177     Op->Imm = Expr;
178     return Op;
179   }
180 
181   static std::unique_ptr<SystemZOperand>
182   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
183             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
184             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
185     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
186     Op->Mem.MemKind = MemKind;
187     Op->Mem.RegKind = RegKind;
188     Op->Mem.Base = Base;
189     Op->Mem.Index = Index;
190     Op->Mem.Disp = Disp;
191     if (MemKind == BDLMem)
192       Op->Mem.Length.Imm = LengthImm;
193     if (MemKind == BDRMem)
194       Op->Mem.Length.Reg = LengthReg;
195     return Op;
196   }
197 
198   static std::unique_ptr<SystemZOperand>
199   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
200                SMLoc StartLoc, SMLoc EndLoc) {
201     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
202     Op->ImmTLS.Imm = Imm;
203     Op->ImmTLS.Sym = Sym;
204     return Op;
205   }
206 
207   // Token operands
208   bool isToken() const override {
209     return Kind == KindToken;
210   }
211   StringRef getToken() const {
212     assert(Kind == KindToken && "Not a token");
213     return StringRef(Token.Data, Token.Length);
214   }
215 
216   // Register operands.
217   bool isReg() const override {
218     return Kind == KindReg;
219   }
220   bool isReg(RegisterKind RegKind) const {
221     return Kind == KindReg && Reg.Kind == RegKind;
222   }
223   unsigned getReg() const override {
224     assert(Kind == KindReg && "Not a register");
225     return Reg.Num;
226   }
227 
228   // Immediate operands.
229   bool isImm() const override {
230     return Kind == KindImm;
231   }
232   bool isImm(int64_t MinValue, int64_t MaxValue) const {
233     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
234   }
235   const MCExpr *getImm() const {
236     assert(Kind == KindImm && "Not an immediate");
237     return Imm;
238   }
239 
240   // Immediate operands with optional TLS symbol.
241   bool isImmTLS() const {
242     return Kind == KindImmTLS;
243   }
244 
245   // Memory operands.
246   bool isMem() const override {
247     return Kind == KindMem;
248   }
249   bool isMem(MemoryKind MemKind) const {
250     return (Kind == KindMem &&
251             (Mem.MemKind == MemKind ||
252              // A BDMem can be treated as a BDXMem in which the index
253              // register field is 0.
254              (Mem.MemKind == BDMem && MemKind == BDXMem)));
255   }
256   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
257     return isMem(MemKind) && Mem.RegKind == RegKind;
258   }
259   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
260     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
261   }
262   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
263     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
264   }
265   bool isMemDisp12Len8(RegisterKind RegKind) const {
266     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
267   }
268 
269   // Override MCParsedAsmOperand.
270   SMLoc getStartLoc() const override { return StartLoc; }
271   SMLoc getEndLoc() const override { return EndLoc; }
272   void print(raw_ostream &OS) const override;
273 
274   // Used by the TableGen code to add particular types of operand
275   // to an instruction.
276   void addRegOperands(MCInst &Inst, unsigned N) const {
277     assert(N == 1 && "Invalid number of operands");
278     Inst.addOperand(MCOperand::createReg(getReg()));
279   }
280   void addImmOperands(MCInst &Inst, unsigned N) const {
281     assert(N == 1 && "Invalid number of operands");
282     addExpr(Inst, getImm());
283   }
284   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
285     assert(N == 2 && "Invalid number of operands");
286     assert(isMem(BDMem) && "Invalid operand type");
287     Inst.addOperand(MCOperand::createReg(Mem.Base));
288     addExpr(Inst, Mem.Disp);
289   }
290   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
291     assert(N == 3 && "Invalid number of operands");
292     assert(isMem(BDXMem) && "Invalid operand type");
293     Inst.addOperand(MCOperand::createReg(Mem.Base));
294     addExpr(Inst, Mem.Disp);
295     Inst.addOperand(MCOperand::createReg(Mem.Index));
296   }
297   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
298     assert(N == 3 && "Invalid number of operands");
299     assert(isMem(BDLMem) && "Invalid operand type");
300     Inst.addOperand(MCOperand::createReg(Mem.Base));
301     addExpr(Inst, Mem.Disp);
302     addExpr(Inst, Mem.Length.Imm);
303   }
304   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
305     assert(N == 3 && "Invalid number of operands");
306     assert(isMem(BDRMem) && "Invalid operand type");
307     Inst.addOperand(MCOperand::createReg(Mem.Base));
308     addExpr(Inst, Mem.Disp);
309     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
310   }
311   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
312     assert(N == 3 && "Invalid number of operands");
313     assert(isMem(BDVMem) && "Invalid operand type");
314     Inst.addOperand(MCOperand::createReg(Mem.Base));
315     addExpr(Inst, Mem.Disp);
316     Inst.addOperand(MCOperand::createReg(Mem.Index));
317   }
318   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
319     assert(N == 2 && "Invalid number of operands");
320     assert(Kind == KindImmTLS && "Invalid operand type");
321     addExpr(Inst, ImmTLS.Imm);
322     if (ImmTLS.Sym)
323       addExpr(Inst, ImmTLS.Sym);
324   }
325 
326   // Used by the TableGen code to check for particular operand types.
327   bool isGR32() const { return isReg(GR32Reg); }
328   bool isGRH32() const { return isReg(GRH32Reg); }
329   bool isGRX32() const { return false; }
330   bool isGR64() const { return isReg(GR64Reg); }
331   bool isGR128() const { return isReg(GR128Reg); }
332   bool isADDR32() const { return isReg(ADDR32Reg); }
333   bool isADDR64() const { return isReg(ADDR64Reg); }
334   bool isADDR128() const { return false; }
335   bool isFP32() const { return isReg(FP32Reg); }
336   bool isFP64() const { return isReg(FP64Reg); }
337   bool isFP128() const { return isReg(FP128Reg); }
338   bool isVR32() const { return isReg(VR32Reg); }
339   bool isVR64() const { return isReg(VR64Reg); }
340   bool isVF128() const { return false; }
341   bool isVR128() const { return isReg(VR128Reg); }
342   bool isAR32() const { return isReg(AR32Reg); }
343   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
344   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
345   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
346   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
347   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
348   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
349   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
350   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
351   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
352   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
353   bool isU1Imm() const { return isImm(0, 1); }
354   bool isU2Imm() const { return isImm(0, 3); }
355   bool isU3Imm() const { return isImm(0, 7); }
356   bool isU4Imm() const { return isImm(0, 15); }
357   bool isU6Imm() const { return isImm(0, 63); }
358   bool isU8Imm() const { return isImm(0, 255); }
359   bool isS8Imm() const { return isImm(-128, 127); }
360   bool isU12Imm() const { return isImm(0, 4095); }
361   bool isU16Imm() const { return isImm(0, 65535); }
362   bool isS16Imm() const { return isImm(-32768, 32767); }
363   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
364   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
365   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
366 };
367 
368 class SystemZAsmParser : public MCTargetAsmParser {
369 #define GET_ASSEMBLER_HEADER
370 #include "SystemZGenAsmMatcher.inc"
371 
372 private:
373   MCAsmParser &Parser;
374   enum RegisterGroup {
375     RegGR,
376     RegFP,
377     RegV,
378     RegAR
379   };
380   struct Register {
381     RegisterGroup Group;
382     unsigned Num;
383     SMLoc StartLoc, EndLoc;
384   };
385 
386   bool parseRegister(Register &Reg);
387 
388   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
389                      bool IsAddress = false);
390 
391   OperandMatchResultTy parseRegister(OperandVector &Operands,
392                                      RegisterGroup Group, const unsigned *Regs,
393                                      RegisterKind Kind);
394 
395   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
396 
397   bool parseAddress(bool &HaveReg1, Register &Reg1,
398                     bool &HaveReg2, Register &Reg2,
399                     const MCExpr *&Disp, const MCExpr *&Length);
400   bool parseAddressRegister(Register &Reg);
401 
402   bool ParseDirectiveInsn(SMLoc L);
403 
404   OperandMatchResultTy parseAddress(OperandVector &Operands,
405                                     MemoryKind MemKind, const unsigned *Regs,
406                                     RegisterKind RegKind);
407 
408   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
409                                   int64_t MaxVal, bool AllowTLS);
410 
411   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
412 
413 public:
414   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
415                    const MCInstrInfo &MII,
416                    const MCTargetOptions &Options)
417     : MCTargetAsmParser(Options, sti), Parser(parser) {
418     MCAsmParserExtension::Initialize(Parser);
419 
420     // Alias the .word directive to .short.
421     parser.addAliasForDirective(".word", ".short");
422 
423     // Initialize the set of available features.
424     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
425   }
426 
427   // Override MCTargetAsmParser.
428   bool ParseDirective(AsmToken DirectiveID) override;
429   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
430   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
431                         SMLoc NameLoc, OperandVector &Operands) override;
432   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
433                                OperandVector &Operands, MCStreamer &Out,
434                                uint64_t &ErrorInfo,
435                                bool MatchingInlineAsm) override;
436 
437   // Used by the TableGen code to parse particular operand types.
438   OperandMatchResultTy parseGR32(OperandVector &Operands) {
439     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
440   }
441   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
442     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
443   }
444   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
445     llvm_unreachable("GRX32 should only be used for pseudo instructions");
446   }
447   OperandMatchResultTy parseGR64(OperandVector &Operands) {
448     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
449   }
450   OperandMatchResultTy parseGR128(OperandVector &Operands) {
451     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
452   }
453   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
454     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
455   }
456   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
457     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
458   }
459   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
460     llvm_unreachable("Shouldn't be used as an operand");
461   }
462   OperandMatchResultTy parseFP32(OperandVector &Operands) {
463     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
464   }
465   OperandMatchResultTy parseFP64(OperandVector &Operands) {
466     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
467   }
468   OperandMatchResultTy parseFP128(OperandVector &Operands) {
469     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
470   }
471   OperandMatchResultTy parseVR32(OperandVector &Operands) {
472     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
473   }
474   OperandMatchResultTy parseVR64(OperandVector &Operands) {
475     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
476   }
477   OperandMatchResultTy parseVF128(OperandVector &Operands) {
478     llvm_unreachable("Shouldn't be used as an operand");
479   }
480   OperandMatchResultTy parseVR128(OperandVector &Operands) {
481     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
482   }
483   OperandMatchResultTy parseAR32(OperandVector &Operands) {
484     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
485   }
486   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
487     return parseAnyRegister(Operands);
488   }
489   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
490     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
491   }
492   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
493     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
494   }
495   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
496     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
497   }
498   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
499     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
500   }
501   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
502     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
503   }
504   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
505     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
506   }
507   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
508     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
509   }
510   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
511     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
512   }
513   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
514     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
515   }
516   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
517     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
518   }
519   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
520     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
521   }
522   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
523     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
524   }
525 };
526 
527 } // end anonymous namespace
528 
529 #define GET_REGISTER_MATCHER
530 #define GET_SUBTARGET_FEATURE_NAME
531 #define GET_MATCHER_IMPLEMENTATION
532 #include "SystemZGenAsmMatcher.inc"
533 
534 // Used for the .insn directives; contains information needed to parse the
535 // operands in the directive.
536 struct InsnMatchEntry {
537   StringRef Format;
538   uint64_t Opcode;
539   int32_t NumOperands;
540   MatchClassKind OperandKinds[5];
541 };
542 
543 // For equal_range comparison.
544 struct CompareInsn {
545   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
546     return LHS.Format < RHS;
547   }
548   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
549     return LHS < RHS.Format;
550   }
551   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
552     return LHS.Format < RHS.Format;
553   }
554 };
555 
556 // Table initializing information for parsing the .insn directive.
557 static struct InsnMatchEntry InsnMatchTable[] = {
558   /* Format, Opcode, NumOperands, OperandKinds */
559   { "e", SystemZ::InsnE, 1,
560     { MCK_U16Imm } },
561   { "ri", SystemZ::InsnRI, 3,
562     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
563   { "rie", SystemZ::InsnRIE, 4,
564     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
565   { "ril", SystemZ::InsnRIL, 3,
566     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
567   { "rilu", SystemZ::InsnRILU, 3,
568     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
569   { "ris", SystemZ::InsnRIS, 5,
570     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
571   { "rr", SystemZ::InsnRR, 3,
572     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
573   { "rre", SystemZ::InsnRRE, 3,
574     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
575   { "rrf", SystemZ::InsnRRF, 5,
576     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
577   { "rrs", SystemZ::InsnRRS, 5,
578     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
579   { "rs", SystemZ::InsnRS, 4,
580     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
581   { "rse", SystemZ::InsnRSE, 4,
582     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
583   { "rsi", SystemZ::InsnRSI, 4,
584     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
585   { "rsy", SystemZ::InsnRSY, 4,
586     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
587   { "rx", SystemZ::InsnRX, 3,
588     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
589   { "rxe", SystemZ::InsnRXE, 3,
590     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
591   { "rxf", SystemZ::InsnRXF, 4,
592     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
593   { "rxy", SystemZ::InsnRXY, 3,
594     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
595   { "s", SystemZ::InsnS, 2,
596     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
597   { "si", SystemZ::InsnSI, 3,
598     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
599   { "sil", SystemZ::InsnSIL, 3,
600     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
601   { "siy", SystemZ::InsnSIY, 3,
602     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
603   { "ss", SystemZ::InsnSS, 4,
604     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
605   { "sse", SystemZ::InsnSSE, 3,
606     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
607   { "ssf", SystemZ::InsnSSF, 4,
608     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
609 };
610 
611 void SystemZOperand::print(raw_ostream &OS) const {
612   llvm_unreachable("Not implemented");
613 }
614 
615 // Parse one register of the form %<prefix><number>.
616 bool SystemZAsmParser::parseRegister(Register &Reg) {
617   Reg.StartLoc = Parser.getTok().getLoc();
618 
619   // Eat the % prefix.
620   if (Parser.getTok().isNot(AsmToken::Percent))
621     return Error(Parser.getTok().getLoc(), "register expected");
622   Parser.Lex();
623 
624   // Expect a register name.
625   if (Parser.getTok().isNot(AsmToken::Identifier))
626     return Error(Reg.StartLoc, "invalid register");
627 
628   // Check that there's a prefix.
629   StringRef Name = Parser.getTok().getString();
630   if (Name.size() < 2)
631     return Error(Reg.StartLoc, "invalid register");
632   char Prefix = Name[0];
633 
634   // Treat the rest of the register name as a register number.
635   if (Name.substr(1).getAsInteger(10, Reg.Num))
636     return Error(Reg.StartLoc, "invalid register");
637 
638   // Look for valid combinations of prefix and number.
639   if (Prefix == 'r' && Reg.Num < 16)
640     Reg.Group = RegGR;
641   else if (Prefix == 'f' && Reg.Num < 16)
642     Reg.Group = RegFP;
643   else if (Prefix == 'v' && Reg.Num < 32)
644     Reg.Group = RegV;
645   else if (Prefix == 'a' && Reg.Num < 16)
646     Reg.Group = RegAR;
647   else
648     return Error(Reg.StartLoc, "invalid register");
649 
650   Reg.EndLoc = Parser.getTok().getLoc();
651   Parser.Lex();
652   return false;
653 }
654 
655 // Parse a register of group Group.  If Regs is nonnull, use it to map
656 // the raw register number to LLVM numbering, with zero entries
657 // indicating an invalid register.  IsAddress says whether the
658 // register appears in an address context. Allow FP Group if expecting
659 // RegV Group, since the f-prefix yields the FP group even while used
660 // with vector instructions.
661 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
662                                      const unsigned *Regs, bool IsAddress) {
663   if (parseRegister(Reg))
664     return true;
665   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
666     return Error(Reg.StartLoc, "invalid operand for instruction");
667   if (Regs && Regs[Reg.Num] == 0)
668     return Error(Reg.StartLoc, "invalid register pair");
669   if (Reg.Num == 0 && IsAddress)
670     return Error(Reg.StartLoc, "%r0 used in an address");
671   if (Regs)
672     Reg.Num = Regs[Reg.Num];
673   return false;
674 }
675 
676 // Parse a register and add it to Operands.  The other arguments are as above.
677 OperandMatchResultTy
678 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
679                                 const unsigned *Regs, RegisterKind Kind) {
680   if (Parser.getTok().isNot(AsmToken::Percent))
681     return MatchOperand_NoMatch;
682 
683   Register Reg;
684   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
685   if (parseRegister(Reg, Group, Regs, IsAddress))
686     return MatchOperand_ParseFail;
687 
688   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
689                                                Reg.StartLoc, Reg.EndLoc));
690   return MatchOperand_Success;
691 }
692 
693 // Parse any type of register (including integers) and add it to Operands.
694 OperandMatchResultTy
695 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
696   // Handle integer values.
697   if (Parser.getTok().is(AsmToken::Integer)) {
698     const MCExpr *Register;
699     SMLoc StartLoc = Parser.getTok().getLoc();
700     if (Parser.parseExpression(Register))
701       return MatchOperand_ParseFail;
702 
703     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
704       int64_t Value = CE->getValue();
705       if (Value < 0 || Value > 15) {
706         Error(StartLoc, "invalid register");
707         return MatchOperand_ParseFail;
708       }
709     }
710 
711     SMLoc EndLoc =
712       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
713 
714     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
715   }
716   else {
717     Register Reg;
718     if (parseRegister(Reg))
719       return MatchOperand_ParseFail;
720 
721     // Map to the correct register kind.
722     RegisterKind Kind;
723     unsigned RegNo;
724     if (Reg.Group == RegGR) {
725       Kind = GR64Reg;
726       RegNo = SystemZMC::GR64Regs[Reg.Num];
727     }
728     else if (Reg.Group == RegFP) {
729       Kind = FP64Reg;
730       RegNo = SystemZMC::FP64Regs[Reg.Num];
731     }
732     else if (Reg.Group == RegV) {
733       Kind = VR128Reg;
734       RegNo = SystemZMC::VR128Regs[Reg.Num];
735     }
736     else if (Reg.Group == RegAR) {
737       Kind = AR32Reg;
738       RegNo = SystemZMC::AR32Regs[Reg.Num];
739     }
740     else {
741       return MatchOperand_ParseFail;
742     }
743 
744     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
745                                                  Reg.StartLoc, Reg.EndLoc));
746   }
747   return MatchOperand_Success;
748 }
749 
750 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
751 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
752                                     bool &HaveReg2, Register &Reg2,
753                                     const MCExpr *&Disp,
754                                     const MCExpr *&Length) {
755   // Parse the displacement, which must always be present.
756   if (getParser().parseExpression(Disp))
757     return true;
758 
759   // Parse the optional base and index.
760   HaveReg1 = false;
761   HaveReg2 = false;
762   Length = nullptr;
763   if (getLexer().is(AsmToken::LParen)) {
764     Parser.Lex();
765 
766     if (getLexer().is(AsmToken::Percent)) {
767       // Parse the first register.
768       HaveReg1 = true;
769       if (parseRegister(Reg1))
770         return true;
771     } else {
772       // Parse the length.
773       if (getParser().parseExpression(Length))
774         return true;
775     }
776 
777     // Check whether there's a second register.
778     if (getLexer().is(AsmToken::Comma)) {
779       Parser.Lex();
780       HaveReg2 = true;
781       if (parseRegister(Reg2))
782         return true;
783     }
784 
785     // Consume the closing bracket.
786     if (getLexer().isNot(AsmToken::RParen))
787       return Error(Parser.getTok().getLoc(), "unexpected token in address");
788     Parser.Lex();
789   }
790   return false;
791 }
792 
793 // Verify that Reg is a valid address register (base or index).
794 bool
795 SystemZAsmParser::parseAddressRegister(Register &Reg) {
796   if (Reg.Group == RegV) {
797     Error(Reg.StartLoc, "invalid use of vector addressing");
798     return true;
799   } else if (Reg.Group != RegGR) {
800     Error(Reg.StartLoc, "invalid address register");
801     return true;
802   } else if (Reg.Num == 0) {
803     Error(Reg.StartLoc, "%r0 used in an address");
804     return true;
805   }
806   return false;
807 }
808 
809 // Parse a memory operand and add it to Operands.  The other arguments
810 // are as above.
811 OperandMatchResultTy
812 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
813                                const unsigned *Regs, RegisterKind RegKind) {
814   SMLoc StartLoc = Parser.getTok().getLoc();
815   unsigned Base = 0, Index = 0, LengthReg = 0;
816   Register Reg1, Reg2;
817   bool HaveReg1, HaveReg2;
818   const MCExpr *Disp;
819   const MCExpr *Length;
820   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
821     return MatchOperand_ParseFail;
822 
823   switch (MemKind) {
824   case BDMem:
825     // If we have Reg1, it must be an address register.
826     if (HaveReg1) {
827       if (parseAddressRegister(Reg1))
828         return MatchOperand_ParseFail;
829       Base = Regs[Reg1.Num];
830     }
831     // There must be no Reg2 or length.
832     if (Length) {
833       Error(StartLoc, "invalid use of length addressing");
834       return MatchOperand_ParseFail;
835     }
836     if (HaveReg2) {
837       Error(StartLoc, "invalid use of indexed addressing");
838       return MatchOperand_ParseFail;
839     }
840     break;
841   case BDXMem:
842     // If we have Reg1, it must be an address register.
843     if (HaveReg1) {
844       if (parseAddressRegister(Reg1))
845         return MatchOperand_ParseFail;
846       // If the are two registers, the first one is the index and the
847       // second is the base.
848       if (HaveReg2)
849         Index = Regs[Reg1.Num];
850       else
851         Base = Regs[Reg1.Num];
852     }
853     // If we have Reg2, it must be an address register.
854     if (HaveReg2) {
855       if (parseAddressRegister(Reg2))
856         return MatchOperand_ParseFail;
857       Base = Regs[Reg2.Num];
858     }
859     // There must be no length.
860     if (Length) {
861       Error(StartLoc, "invalid use of length addressing");
862       return MatchOperand_ParseFail;
863     }
864     break;
865   case BDLMem:
866     // If we have Reg2, it must be an address register.
867     if (HaveReg2) {
868       if (parseAddressRegister(Reg2))
869         return MatchOperand_ParseFail;
870       Base = Regs[Reg2.Num];
871     }
872     // We cannot support base+index addressing.
873     if (HaveReg1 && HaveReg2) {
874       Error(StartLoc, "invalid use of indexed addressing");
875       return MatchOperand_ParseFail;
876     }
877     // We must have a length.
878     if (!Length) {
879       Error(StartLoc, "missing length in address");
880       return MatchOperand_ParseFail;
881     }
882     break;
883   case BDRMem:
884     // We must have Reg1, and it must be a GPR.
885     if (!HaveReg1 || Reg1.Group != RegGR) {
886       Error(StartLoc, "invalid operand for instruction");
887       return MatchOperand_ParseFail;
888     }
889     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
890     // If we have Reg2, it must be an address register.
891     if (HaveReg2) {
892       if (parseAddressRegister(Reg2))
893         return MatchOperand_ParseFail;
894       Base = Regs[Reg2.Num];
895     }
896     // There must be no length.
897     if (Length) {
898       Error(StartLoc, "invalid use of length addressing");
899       return MatchOperand_ParseFail;
900     }
901     break;
902   case BDVMem:
903     // We must have Reg1, and it must be a vector register.
904     if (!HaveReg1 || Reg1.Group != RegV) {
905       Error(StartLoc, "vector index required in address");
906       return MatchOperand_ParseFail;
907     }
908     Index = SystemZMC::VR128Regs[Reg1.Num];
909     // If we have Reg2, it must be an address register.
910     if (HaveReg2) {
911       if (parseAddressRegister(Reg2))
912         return MatchOperand_ParseFail;
913       Base = Regs[Reg2.Num];
914     }
915     // There must be no length.
916     if (Length) {
917       Error(StartLoc, "invalid use of length addressing");
918       return MatchOperand_ParseFail;
919     }
920     break;
921   }
922 
923   SMLoc EndLoc =
924     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
925   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
926                                                Index, Length, LengthReg,
927                                                StartLoc, EndLoc));
928   return MatchOperand_Success;
929 }
930 
931 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
932   StringRef IDVal = DirectiveID.getIdentifier();
933 
934   if (IDVal == ".insn")
935     return ParseDirectiveInsn(DirectiveID.getLoc());
936 
937   return true;
938 }
939 
940 /// ParseDirectiveInsn
941 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
942 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
943   MCAsmParser &Parser = getParser();
944 
945   // Expect instruction format as identifier.
946   StringRef Format;
947   SMLoc ErrorLoc = Parser.getTok().getLoc();
948   if (Parser.parseIdentifier(Format))
949     return Error(ErrorLoc, "expected instruction format");
950 
951   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
952 
953   // Find entry for this format in InsnMatchTable.
954   auto EntryRange =
955     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
956                      Format, CompareInsn());
957 
958   // If first == second, couldn't find a match in the table.
959   if (EntryRange.first == EntryRange.second)
960     return Error(ErrorLoc, "unrecognized format");
961 
962   struct InsnMatchEntry *Entry = EntryRange.first;
963 
964   // Format should match from equal_range.
965   assert(Entry->Format == Format);
966 
967   // Parse the following operands using the table's information.
968   for (int i = 0; i < Entry->NumOperands; i++) {
969     MatchClassKind Kind = Entry->OperandKinds[i];
970 
971     SMLoc StartLoc = Parser.getTok().getLoc();
972 
973     // Always expect commas as separators for operands.
974     if (getLexer().isNot(AsmToken::Comma))
975       return Error(StartLoc, "unexpected token in directive");
976     Lex();
977 
978     // Parse operands.
979     OperandMatchResultTy ResTy;
980     if (Kind == MCK_AnyReg)
981       ResTy = parseAnyReg(Operands);
982     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
983       ResTy = parseBDXAddr64(Operands);
984     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
985       ResTy = parseBDAddr64(Operands);
986     else if (Kind == MCK_PCRel32)
987       ResTy = parsePCRel32(Operands);
988     else if (Kind == MCK_PCRel16)
989       ResTy = parsePCRel16(Operands);
990     else {
991       // Only remaining operand kind is an immediate.
992       const MCExpr *Expr;
993       SMLoc StartLoc = Parser.getTok().getLoc();
994 
995       // Expect immediate expression.
996       if (Parser.parseExpression(Expr))
997         return Error(StartLoc, "unexpected token in directive");
998 
999       SMLoc EndLoc =
1000         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1001 
1002       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1003       ResTy = MatchOperand_Success;
1004     }
1005 
1006     if (ResTy != MatchOperand_Success)
1007       return true;
1008   }
1009 
1010   // Build the instruction with the parsed operands.
1011   MCInst Inst = MCInstBuilder(Entry->Opcode);
1012 
1013   for (size_t i = 0; i < Operands.size(); i++) {
1014     MCParsedAsmOperand &Operand = *Operands[i];
1015     MatchClassKind Kind = Entry->OperandKinds[i];
1016 
1017     // Verify operand.
1018     unsigned Res = validateOperandClass(Operand, Kind);
1019     if (Res != Match_Success)
1020       return Error(Operand.getStartLoc(), "unexpected operand type");
1021 
1022     // Add operands to instruction.
1023     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1024     if (ZOperand.isReg())
1025       ZOperand.addRegOperands(Inst, 1);
1026     else if (ZOperand.isMem(BDMem))
1027       ZOperand.addBDAddrOperands(Inst, 2);
1028     else if (ZOperand.isMem(BDXMem))
1029       ZOperand.addBDXAddrOperands(Inst, 3);
1030     else if (ZOperand.isImm())
1031       ZOperand.addImmOperands(Inst, 1);
1032     else
1033       llvm_unreachable("unexpected operand type");
1034   }
1035 
1036   // Emit as a regular instruction.
1037   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1038 
1039   return false;
1040 }
1041 
1042 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1043                                      SMLoc &EndLoc) {
1044   Register Reg;
1045   if (parseRegister(Reg))
1046     return true;
1047   if (Reg.Group == RegGR)
1048     RegNo = SystemZMC::GR64Regs[Reg.Num];
1049   else if (Reg.Group == RegFP)
1050     RegNo = SystemZMC::FP64Regs[Reg.Num];
1051   else if (Reg.Group == RegV)
1052     RegNo = SystemZMC::VR128Regs[Reg.Num];
1053   else if (Reg.Group == RegAR)
1054     RegNo = SystemZMC::AR32Regs[Reg.Num];
1055   StartLoc = Reg.StartLoc;
1056   EndLoc = Reg.EndLoc;
1057   return false;
1058 }
1059 
1060 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1061                                         StringRef Name, SMLoc NameLoc,
1062                                         OperandVector &Operands) {
1063   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1064 
1065   // Read the remaining operands.
1066   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1067     // Read the first operand.
1068     if (parseOperand(Operands, Name)) {
1069       return true;
1070     }
1071 
1072     // Read any subsequent operands.
1073     while (getLexer().is(AsmToken::Comma)) {
1074       Parser.Lex();
1075       if (parseOperand(Operands, Name)) {
1076         return true;
1077       }
1078     }
1079     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1080       SMLoc Loc = getLexer().getLoc();
1081       return Error(Loc, "unexpected token in argument list");
1082     }
1083   }
1084 
1085   // Consume the EndOfStatement.
1086   Parser.Lex();
1087   return false;
1088 }
1089 
1090 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1091                                     StringRef Mnemonic) {
1092   // Check if the current operand has a custom associated parser, if so, try to
1093   // custom parse the operand, or fallback to the general approach.  Force all
1094   // features to be available during the operand check, or else we will fail to
1095   // find the custom parser, and then we will later get an InvalidOperand error
1096   // instead of a MissingFeature errror.
1097   uint64_t AvailableFeatures = getAvailableFeatures();
1098   setAvailableFeatures(~(uint64_t)0);
1099   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1100   setAvailableFeatures(AvailableFeatures);
1101   if (ResTy == MatchOperand_Success)
1102     return false;
1103 
1104   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1105   // there was a match, but an error occurred, in which case, just return that
1106   // the operand parsing failed.
1107   if (ResTy == MatchOperand_ParseFail)
1108     return true;
1109 
1110   // Check for a register.  All real register operands should have used
1111   // a context-dependent parse routine, which gives the required register
1112   // class.  The code is here to mop up other cases, like those where
1113   // the instruction isn't recognized.
1114   if (Parser.getTok().is(AsmToken::Percent)) {
1115     Register Reg;
1116     if (parseRegister(Reg))
1117       return true;
1118     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1119     return false;
1120   }
1121 
1122   // The only other type of operand is an immediate or address.  As above,
1123   // real address operands should have used a context-dependent parse routine,
1124   // so we treat any plain expression as an immediate.
1125   SMLoc StartLoc = Parser.getTok().getLoc();
1126   Register Reg1, Reg2;
1127   bool HaveReg1, HaveReg2;
1128   const MCExpr *Expr;
1129   const MCExpr *Length;
1130   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1131     return true;
1132   // If the register combination is not valid for any instruction, reject it.
1133   // Otherwise, fall back to reporting an unrecognized instruction.
1134   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1135       && parseAddressRegister(Reg1))
1136     return true;
1137   if (HaveReg2 && parseAddressRegister(Reg2))
1138     return true;
1139 
1140   SMLoc EndLoc =
1141     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1142   if (HaveReg1 || HaveReg2 || Length)
1143     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1144   else
1145     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1146   return false;
1147 }
1148 
1149 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1150                                                OperandVector &Operands,
1151                                                MCStreamer &Out,
1152                                                uint64_t &ErrorInfo,
1153                                                bool MatchingInlineAsm) {
1154   MCInst Inst;
1155   unsigned MatchResult;
1156 
1157   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1158                                      MatchingInlineAsm);
1159   switch (MatchResult) {
1160   case Match_Success:
1161     Inst.setLoc(IDLoc);
1162     Out.EmitInstruction(Inst, getSTI());
1163     return false;
1164 
1165   case Match_MissingFeature: {
1166     assert(ErrorInfo && "Unknown missing feature!");
1167     // Special case the error message for the very common case where only
1168     // a single subtarget feature is missing
1169     std::string Msg = "instruction requires:";
1170     uint64_t Mask = 1;
1171     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1172       if (ErrorInfo & Mask) {
1173         Msg += " ";
1174         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1175       }
1176       Mask <<= 1;
1177     }
1178     return Error(IDLoc, Msg);
1179   }
1180 
1181   case Match_InvalidOperand: {
1182     SMLoc ErrorLoc = IDLoc;
1183     if (ErrorInfo != ~0ULL) {
1184       if (ErrorInfo >= Operands.size())
1185         return Error(IDLoc, "too few operands for instruction");
1186 
1187       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1188       if (ErrorLoc == SMLoc())
1189         ErrorLoc = IDLoc;
1190     }
1191     return Error(ErrorLoc, "invalid operand for instruction");
1192   }
1193 
1194   case Match_MnemonicFail:
1195     return Error(IDLoc, "invalid instruction");
1196   }
1197 
1198   llvm_unreachable("Unexpected match type");
1199 }
1200 
1201 OperandMatchResultTy
1202 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1203                              int64_t MaxVal, bool AllowTLS) {
1204   MCContext &Ctx = getContext();
1205   MCStreamer &Out = getStreamer();
1206   const MCExpr *Expr;
1207   SMLoc StartLoc = Parser.getTok().getLoc();
1208   if (getParser().parseExpression(Expr))
1209     return MatchOperand_NoMatch;
1210 
1211   // For consistency with the GNU assembler, treat immediates as offsets
1212   // from ".".
1213   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1214     int64_t Value = CE->getValue();
1215     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1216       Error(StartLoc, "offset out of range");
1217       return MatchOperand_ParseFail;
1218     }
1219     MCSymbol *Sym = Ctx.createTempSymbol();
1220     Out.EmitLabel(Sym);
1221     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1222                                                  Ctx);
1223     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1224   }
1225 
1226   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1227   const MCExpr *Sym = nullptr;
1228   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1229     Parser.Lex();
1230 
1231     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1232       Error(Parser.getTok().getLoc(), "unexpected token");
1233       return MatchOperand_ParseFail;
1234     }
1235 
1236     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1237     StringRef Name = Parser.getTok().getString();
1238     if (Name == "tls_gdcall")
1239       Kind = MCSymbolRefExpr::VK_TLSGD;
1240     else if (Name == "tls_ldcall")
1241       Kind = MCSymbolRefExpr::VK_TLSLDM;
1242     else {
1243       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1244       return MatchOperand_ParseFail;
1245     }
1246     Parser.Lex();
1247 
1248     if (Parser.getTok().isNot(AsmToken::Colon)) {
1249       Error(Parser.getTok().getLoc(), "unexpected token");
1250       return MatchOperand_ParseFail;
1251     }
1252     Parser.Lex();
1253 
1254     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1255       Error(Parser.getTok().getLoc(), "unexpected token");
1256       return MatchOperand_ParseFail;
1257     }
1258 
1259     StringRef Identifier = Parser.getTok().getString();
1260     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1261                                   Kind, Ctx);
1262     Parser.Lex();
1263   }
1264 
1265   SMLoc EndLoc =
1266     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1267 
1268   if (AllowTLS)
1269     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1270                                                     StartLoc, EndLoc));
1271   else
1272     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1273 
1274   return MatchOperand_Success;
1275 }
1276 
1277 // Force static initialization.
1278 extern "C" void LLVMInitializeSystemZAsmParser() {
1279   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1280 }
1281