1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "InstPrinter/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/SMLoc.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <iterator>
34 #include <memory>
35 #include <string>
36 
37 using namespace llvm;
38 
39 // Return true if Expr is in the range [MinValue, MaxValue].
40 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
41   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
42     int64_t Value = CE->getValue();
43     return Value >= MinValue && Value <= MaxValue;
44   }
45   return false;
46 }
47 
48 namespace {
49 
50 enum RegisterKind {
51   GR32Reg,
52   GRH32Reg,
53   GR64Reg,
54   GR128Reg,
55   ADDR32Reg,
56   ADDR64Reg,
57   FP32Reg,
58   FP64Reg,
59   FP128Reg,
60   VR32Reg,
61   VR64Reg,
62   VR128Reg,
63   AR32Reg,
64   CR64Reg,
65 };
66 
67 enum MemoryKind {
68   BDMem,
69   BDXMem,
70   BDLMem,
71   BDRMem,
72   BDVMem
73 };
74 
75 class SystemZOperand : public MCParsedAsmOperand {
76 private:
77   enum OperandKind {
78     KindInvalid,
79     KindToken,
80     KindReg,
81     KindImm,
82     KindImmTLS,
83     KindMem
84   };
85 
86   OperandKind Kind;
87   SMLoc StartLoc, EndLoc;
88 
89   // A string of length Length, starting at Data.
90   struct TokenOp {
91     const char *Data;
92     unsigned Length;
93   };
94 
95   // LLVM register Num, which has kind Kind.  In some ways it might be
96   // easier for this class to have a register bank (general, floating-point
97   // or access) and a raw register number (0-15).  This would postpone the
98   // interpretation of the operand to the add*() methods and avoid the need
99   // for context-dependent parsing.  However, we do things the current way
100   // because of the virtual getReg() method, which needs to distinguish
101   // between (say) %r0 used as a single register and %r0 used as a pair.
102   // Context-dependent parsing can also give us slightly better error
103   // messages when invalid pairs like %r1 are used.
104   struct RegOp {
105     RegisterKind Kind;
106     unsigned Num;
107   };
108 
109   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
110   // MemKind says what type of memory this is and RegKind says what type
111   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
112   // length for D(L,B)-style operands, otherwise it is null.
113   struct MemOp {
114     unsigned Base : 12;
115     unsigned Index : 12;
116     unsigned MemKind : 4;
117     unsigned RegKind : 4;
118     const MCExpr *Disp;
119     union {
120       const MCExpr *Imm;
121       unsigned Reg;
122     } Length;
123   };
124 
125   // Imm is an immediate operand, and Sym is an optional TLS symbol
126   // for use with a __tls_get_offset marker relocation.
127   struct ImmTLSOp {
128     const MCExpr *Imm;
129     const MCExpr *Sym;
130   };
131 
132   union {
133     TokenOp Token;
134     RegOp Reg;
135     const MCExpr *Imm;
136     ImmTLSOp ImmTLS;
137     MemOp Mem;
138   };
139 
140   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
141     // Add as immediates when possible.  Null MCExpr = 0.
142     if (!Expr)
143       Inst.addOperand(MCOperand::createImm(0));
144     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
145       Inst.addOperand(MCOperand::createImm(CE->getValue()));
146     else
147       Inst.addOperand(MCOperand::createExpr(Expr));
148   }
149 
150 public:
151   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
152       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
153 
154   // Create particular kinds of operand.
155   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
156                                                        SMLoc EndLoc) {
157     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
158   }
159 
160   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
161     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
162     Op->Token.Data = Str.data();
163     Op->Token.Length = Str.size();
164     return Op;
165   }
166 
167   static std::unique_ptr<SystemZOperand>
168   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
169     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
170     Op->Reg.Kind = Kind;
171     Op->Reg.Num = Num;
172     return Op;
173   }
174 
175   static std::unique_ptr<SystemZOperand>
176   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
177     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
178     Op->Imm = Expr;
179     return Op;
180   }
181 
182   static std::unique_ptr<SystemZOperand>
183   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
184             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
185             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
186     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
187     Op->Mem.MemKind = MemKind;
188     Op->Mem.RegKind = RegKind;
189     Op->Mem.Base = Base;
190     Op->Mem.Index = Index;
191     Op->Mem.Disp = Disp;
192     if (MemKind == BDLMem)
193       Op->Mem.Length.Imm = LengthImm;
194     if (MemKind == BDRMem)
195       Op->Mem.Length.Reg = LengthReg;
196     return Op;
197   }
198 
199   static std::unique_ptr<SystemZOperand>
200   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
201                SMLoc StartLoc, SMLoc EndLoc) {
202     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
203     Op->ImmTLS.Imm = Imm;
204     Op->ImmTLS.Sym = Sym;
205     return Op;
206   }
207 
208   // Token operands
209   bool isToken() const override {
210     return Kind == KindToken;
211   }
212   StringRef getToken() const {
213     assert(Kind == KindToken && "Not a token");
214     return StringRef(Token.Data, Token.Length);
215   }
216 
217   // Register operands.
218   bool isReg() const override {
219     return Kind == KindReg;
220   }
221   bool isReg(RegisterKind RegKind) const {
222     return Kind == KindReg && Reg.Kind == RegKind;
223   }
224   unsigned getReg() const override {
225     assert(Kind == KindReg && "Not a register");
226     return Reg.Num;
227   }
228 
229   // Immediate operands.
230   bool isImm() const override {
231     return Kind == KindImm;
232   }
233   bool isImm(int64_t MinValue, int64_t MaxValue) const {
234     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
235   }
236   const MCExpr *getImm() const {
237     assert(Kind == KindImm && "Not an immediate");
238     return Imm;
239   }
240 
241   // Immediate operands with optional TLS symbol.
242   bool isImmTLS() const {
243     return Kind == KindImmTLS;
244   }
245 
246   const ImmTLSOp getImmTLS() const {
247     assert(Kind == KindImmTLS && "Not a TLS immediate");
248     return ImmTLS;
249   }
250 
251   // Memory operands.
252   bool isMem() const override {
253     return Kind == KindMem;
254   }
255   bool isMem(MemoryKind MemKind) const {
256     return (Kind == KindMem &&
257             (Mem.MemKind == MemKind ||
258              // A BDMem can be treated as a BDXMem in which the index
259              // register field is 0.
260              (Mem.MemKind == BDMem && MemKind == BDXMem)));
261   }
262   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
263     return isMem(MemKind) && Mem.RegKind == RegKind;
264   }
265   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
266     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
267   }
268   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
269     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
270   }
271   bool isMemDisp12Len4(RegisterKind RegKind) const {
272     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
273   }
274   bool isMemDisp12Len8(RegisterKind RegKind) const {
275     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
276   }
277 
278   const MemOp& getMem() const {
279     assert(Kind == KindMem && "Not a Mem operand");
280     return Mem;
281   }
282 
283   // Override MCParsedAsmOperand.
284   SMLoc getStartLoc() const override { return StartLoc; }
285   SMLoc getEndLoc() const override { return EndLoc; }
286   void print(raw_ostream &OS) const override;
287 
288   /// getLocRange - Get the range between the first and last token of this
289   /// operand.
290   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
291 
292   // Used by the TableGen code to add particular types of operand
293   // to an instruction.
294   void addRegOperands(MCInst &Inst, unsigned N) const {
295     assert(N == 1 && "Invalid number of operands");
296     Inst.addOperand(MCOperand::createReg(getReg()));
297   }
298   void addImmOperands(MCInst &Inst, unsigned N) const {
299     assert(N == 1 && "Invalid number of operands");
300     addExpr(Inst, getImm());
301   }
302   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
303     assert(N == 2 && "Invalid number of operands");
304     assert(isMem(BDMem) && "Invalid operand type");
305     Inst.addOperand(MCOperand::createReg(Mem.Base));
306     addExpr(Inst, Mem.Disp);
307   }
308   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
309     assert(N == 3 && "Invalid number of operands");
310     assert(isMem(BDXMem) && "Invalid operand type");
311     Inst.addOperand(MCOperand::createReg(Mem.Base));
312     addExpr(Inst, Mem.Disp);
313     Inst.addOperand(MCOperand::createReg(Mem.Index));
314   }
315   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
316     assert(N == 3 && "Invalid number of operands");
317     assert(isMem(BDLMem) && "Invalid operand type");
318     Inst.addOperand(MCOperand::createReg(Mem.Base));
319     addExpr(Inst, Mem.Disp);
320     addExpr(Inst, Mem.Length.Imm);
321   }
322   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
323     assert(N == 3 && "Invalid number of operands");
324     assert(isMem(BDRMem) && "Invalid operand type");
325     Inst.addOperand(MCOperand::createReg(Mem.Base));
326     addExpr(Inst, Mem.Disp);
327     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
328   }
329   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
330     assert(N == 3 && "Invalid number of operands");
331     assert(isMem(BDVMem) && "Invalid operand type");
332     Inst.addOperand(MCOperand::createReg(Mem.Base));
333     addExpr(Inst, Mem.Disp);
334     Inst.addOperand(MCOperand::createReg(Mem.Index));
335   }
336   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
337     assert(N == 2 && "Invalid number of operands");
338     assert(Kind == KindImmTLS && "Invalid operand type");
339     addExpr(Inst, ImmTLS.Imm);
340     if (ImmTLS.Sym)
341       addExpr(Inst, ImmTLS.Sym);
342   }
343 
344   // Used by the TableGen code to check for particular operand types.
345   bool isGR32() const { return isReg(GR32Reg); }
346   bool isGRH32() const { return isReg(GRH32Reg); }
347   bool isGRX32() const { return false; }
348   bool isGR64() const { return isReg(GR64Reg); }
349   bool isGR128() const { return isReg(GR128Reg); }
350   bool isADDR32() const { return isReg(ADDR32Reg); }
351   bool isADDR64() const { return isReg(ADDR64Reg); }
352   bool isADDR128() const { return false; }
353   bool isFP32() const { return isReg(FP32Reg); }
354   bool isFP64() const { return isReg(FP64Reg); }
355   bool isFP128() const { return isReg(FP128Reg); }
356   bool isVR32() const { return isReg(VR32Reg); }
357   bool isVR64() const { return isReg(VR64Reg); }
358   bool isVF128() const { return false; }
359   bool isVR128() const { return isReg(VR128Reg); }
360   bool isAR32() const { return isReg(AR32Reg); }
361   bool isCR64() const { return isReg(CR64Reg); }
362   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
363   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
364   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
365   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
366   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
367   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
368   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
369   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
370   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
371   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
372   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
373   bool isU1Imm() const { return isImm(0, 1); }
374   bool isU2Imm() const { return isImm(0, 3); }
375   bool isU3Imm() const { return isImm(0, 7); }
376   bool isU4Imm() const { return isImm(0, 15); }
377   bool isU6Imm() const { return isImm(0, 63); }
378   bool isU8Imm() const { return isImm(0, 255); }
379   bool isS8Imm() const { return isImm(-128, 127); }
380   bool isU12Imm() const { return isImm(0, 4095); }
381   bool isU16Imm() const { return isImm(0, 65535); }
382   bool isS16Imm() const { return isImm(-32768, 32767); }
383   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
384   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
385   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
386 };
387 
388 class SystemZAsmParser : public MCTargetAsmParser {
389 #define GET_ASSEMBLER_HEADER
390 #include "SystemZGenAsmMatcher.inc"
391 
392 private:
393   MCAsmParser &Parser;
394   enum RegisterGroup {
395     RegGR,
396     RegFP,
397     RegV,
398     RegAR,
399     RegCR
400   };
401   struct Register {
402     RegisterGroup Group;
403     unsigned Num;
404     SMLoc StartLoc, EndLoc;
405   };
406 
407   bool parseRegister(Register &Reg);
408 
409   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
410                      bool IsAddress = false);
411 
412   OperandMatchResultTy parseRegister(OperandVector &Operands,
413                                      RegisterGroup Group, const unsigned *Regs,
414                                      RegisterKind Kind);
415 
416   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
417 
418   bool parseAddress(bool &HaveReg1, Register &Reg1,
419                     bool &HaveReg2, Register &Reg2,
420                     const MCExpr *&Disp, const MCExpr *&Length);
421   bool parseAddressRegister(Register &Reg);
422 
423   bool ParseDirectiveInsn(SMLoc L);
424 
425   OperandMatchResultTy parseAddress(OperandVector &Operands,
426                                     MemoryKind MemKind, const unsigned *Regs,
427                                     RegisterKind RegKind);
428 
429   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
430                                   int64_t MaxVal, bool AllowTLS);
431 
432   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
433 
434 public:
435   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
436                    const MCInstrInfo &MII,
437                    const MCTargetOptions &Options)
438     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
439     MCAsmParserExtension::Initialize(Parser);
440 
441     // Alias the .word directive to .short.
442     parser.addAliasForDirective(".word", ".short");
443 
444     // Initialize the set of available features.
445     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
446   }
447 
448   // Override MCTargetAsmParser.
449   bool ParseDirective(AsmToken DirectiveID) override;
450   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
451   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
452                         SMLoc NameLoc, OperandVector &Operands) override;
453   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
454                                OperandVector &Operands, MCStreamer &Out,
455                                uint64_t &ErrorInfo,
456                                bool MatchingInlineAsm) override;
457 
458   // Used by the TableGen code to parse particular operand types.
459   OperandMatchResultTy parseGR32(OperandVector &Operands) {
460     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
461   }
462   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
463     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
464   }
465   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
466     llvm_unreachable("GRX32 should only be used for pseudo instructions");
467   }
468   OperandMatchResultTy parseGR64(OperandVector &Operands) {
469     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
470   }
471   OperandMatchResultTy parseGR128(OperandVector &Operands) {
472     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
473   }
474   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
475     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
476   }
477   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
478     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
479   }
480   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
481     llvm_unreachable("Shouldn't be used as an operand");
482   }
483   OperandMatchResultTy parseFP32(OperandVector &Operands) {
484     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
485   }
486   OperandMatchResultTy parseFP64(OperandVector &Operands) {
487     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
488   }
489   OperandMatchResultTy parseFP128(OperandVector &Operands) {
490     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
491   }
492   OperandMatchResultTy parseVR32(OperandVector &Operands) {
493     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
494   }
495   OperandMatchResultTy parseVR64(OperandVector &Operands) {
496     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
497   }
498   OperandMatchResultTy parseVF128(OperandVector &Operands) {
499     llvm_unreachable("Shouldn't be used as an operand");
500   }
501   OperandMatchResultTy parseVR128(OperandVector &Operands) {
502     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
503   }
504   OperandMatchResultTy parseAR32(OperandVector &Operands) {
505     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
506   }
507   OperandMatchResultTy parseCR64(OperandVector &Operands) {
508     return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
509   }
510   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
511     return parseAnyRegister(Operands);
512   }
513   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
514     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
515   }
516   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
517     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
518   }
519   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
520     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
521   }
522   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
523     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
524   }
525   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
526     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
527   }
528   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
529     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
530   }
531   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
532     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
533   }
534   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
535     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
536   }
537   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
538     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
539   }
540   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
541     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
542   }
543   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
544     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
545   }
546   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
547     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
548   }
549 };
550 
551 } // end anonymous namespace
552 
553 #define GET_REGISTER_MATCHER
554 #define GET_SUBTARGET_FEATURE_NAME
555 #define GET_MATCHER_IMPLEMENTATION
556 #define GET_MNEMONIC_SPELL_CHECKER
557 #include "SystemZGenAsmMatcher.inc"
558 
559 // Used for the .insn directives; contains information needed to parse the
560 // operands in the directive.
561 struct InsnMatchEntry {
562   StringRef Format;
563   uint64_t Opcode;
564   int32_t NumOperands;
565   MatchClassKind OperandKinds[5];
566 };
567 
568 // For equal_range comparison.
569 struct CompareInsn {
570   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
571     return LHS.Format < RHS;
572   }
573   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
574     return LHS < RHS.Format;
575   }
576   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
577     return LHS.Format < RHS.Format;
578   }
579 };
580 
581 // Table initializing information for parsing the .insn directive.
582 static struct InsnMatchEntry InsnMatchTable[] = {
583   /* Format, Opcode, NumOperands, OperandKinds */
584   { "e", SystemZ::InsnE, 1,
585     { MCK_U16Imm } },
586   { "ri", SystemZ::InsnRI, 3,
587     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
588   { "rie", SystemZ::InsnRIE, 4,
589     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
590   { "ril", SystemZ::InsnRIL, 3,
591     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
592   { "rilu", SystemZ::InsnRILU, 3,
593     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
594   { "ris", SystemZ::InsnRIS, 5,
595     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
596   { "rr", SystemZ::InsnRR, 3,
597     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
598   { "rre", SystemZ::InsnRRE, 3,
599     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
600   { "rrf", SystemZ::InsnRRF, 5,
601     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
602   { "rrs", SystemZ::InsnRRS, 5,
603     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
604   { "rs", SystemZ::InsnRS, 4,
605     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
606   { "rse", SystemZ::InsnRSE, 4,
607     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
608   { "rsi", SystemZ::InsnRSI, 4,
609     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
610   { "rsy", SystemZ::InsnRSY, 4,
611     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
612   { "rx", SystemZ::InsnRX, 3,
613     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
614   { "rxe", SystemZ::InsnRXE, 3,
615     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
616   { "rxf", SystemZ::InsnRXF, 4,
617     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
618   { "rxy", SystemZ::InsnRXY, 3,
619     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
620   { "s", SystemZ::InsnS, 2,
621     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
622   { "si", SystemZ::InsnSI, 3,
623     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
624   { "sil", SystemZ::InsnSIL, 3,
625     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
626   { "siy", SystemZ::InsnSIY, 3,
627     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
628   { "ss", SystemZ::InsnSS, 4,
629     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
630   { "sse", SystemZ::InsnSSE, 3,
631     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
632   { "ssf", SystemZ::InsnSSF, 4,
633     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
634 };
635 
636 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
637   if (!E)
638     return;
639   if (auto *CE = dyn_cast<MCConstantExpr>(E))
640     OS << *CE;
641   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
642     OS << *UE;
643   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
644     OS << *BE;
645   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
646     OS << *SRE;
647   else
648     OS << *E;
649 }
650 
651 void SystemZOperand::print(raw_ostream &OS) const {
652   switch (Kind) {
653     break;
654   case KindToken:
655     OS << "Token:" << getToken();
656     break;
657   case KindReg:
658     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
659     break;
660   case KindImm:
661     OS << "Imm:";
662     printMCExpr(getImm(), OS);
663     break;
664   case KindImmTLS:
665     OS << "ImmTLS:";
666     printMCExpr(getImmTLS().Imm, OS);
667     if (getImmTLS().Sym) {
668       OS << ", ";
669       printMCExpr(getImmTLS().Sym, OS);
670     }
671     break;
672   case KindMem: {
673     const MemOp &Op = getMem();
674     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
675     if (Op.Base) {
676       OS << "(";
677       if (Op.MemKind == BDLMem)
678         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
679       else if (Op.MemKind == BDRMem)
680         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
681       if (Op.Index)
682         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
683       OS << SystemZInstPrinter::getRegisterName(Op.Base);
684       OS << ")";
685     }
686     break;
687   }
688   case KindInvalid:
689     break;
690   }
691 }
692 
693 // Parse one register of the form %<prefix><number>.
694 bool SystemZAsmParser::parseRegister(Register &Reg) {
695   Reg.StartLoc = Parser.getTok().getLoc();
696 
697   // Eat the % prefix.
698   if (Parser.getTok().isNot(AsmToken::Percent))
699     return Error(Parser.getTok().getLoc(), "register expected");
700   Parser.Lex();
701 
702   // Expect a register name.
703   if (Parser.getTok().isNot(AsmToken::Identifier))
704     return Error(Reg.StartLoc, "invalid register");
705 
706   // Check that there's a prefix.
707   StringRef Name = Parser.getTok().getString();
708   if (Name.size() < 2)
709     return Error(Reg.StartLoc, "invalid register");
710   char Prefix = Name[0];
711 
712   // Treat the rest of the register name as a register number.
713   if (Name.substr(1).getAsInteger(10, Reg.Num))
714     return Error(Reg.StartLoc, "invalid register");
715 
716   // Look for valid combinations of prefix and number.
717   if (Prefix == 'r' && Reg.Num < 16)
718     Reg.Group = RegGR;
719   else if (Prefix == 'f' && Reg.Num < 16)
720     Reg.Group = RegFP;
721   else if (Prefix == 'v' && Reg.Num < 32)
722     Reg.Group = RegV;
723   else if (Prefix == 'a' && Reg.Num < 16)
724     Reg.Group = RegAR;
725   else if (Prefix == 'c' && Reg.Num < 16)
726     Reg.Group = RegCR;
727   else
728     return Error(Reg.StartLoc, "invalid register");
729 
730   Reg.EndLoc = Parser.getTok().getLoc();
731   Parser.Lex();
732   return false;
733 }
734 
735 // Parse a register of group Group.  If Regs is nonnull, use it to map
736 // the raw register number to LLVM numbering, with zero entries
737 // indicating an invalid register.  IsAddress says whether the
738 // register appears in an address context. Allow FP Group if expecting
739 // RegV Group, since the f-prefix yields the FP group even while used
740 // with vector instructions.
741 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
742                                      const unsigned *Regs, bool IsAddress) {
743   if (parseRegister(Reg))
744     return true;
745   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
746     return Error(Reg.StartLoc, "invalid operand for instruction");
747   if (Regs && Regs[Reg.Num] == 0)
748     return Error(Reg.StartLoc, "invalid register pair");
749   if (Reg.Num == 0 && IsAddress)
750     return Error(Reg.StartLoc, "%r0 used in an address");
751   if (Regs)
752     Reg.Num = Regs[Reg.Num];
753   return false;
754 }
755 
756 // Parse a register and add it to Operands.  The other arguments are as above.
757 OperandMatchResultTy
758 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
759                                 const unsigned *Regs, RegisterKind Kind) {
760   if (Parser.getTok().isNot(AsmToken::Percent))
761     return MatchOperand_NoMatch;
762 
763   Register Reg;
764   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
765   if (parseRegister(Reg, Group, Regs, IsAddress))
766     return MatchOperand_ParseFail;
767 
768   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
769                                                Reg.StartLoc, Reg.EndLoc));
770   return MatchOperand_Success;
771 }
772 
773 // Parse any type of register (including integers) and add it to Operands.
774 OperandMatchResultTy
775 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
776   // Handle integer values.
777   if (Parser.getTok().is(AsmToken::Integer)) {
778     const MCExpr *Register;
779     SMLoc StartLoc = Parser.getTok().getLoc();
780     if (Parser.parseExpression(Register))
781       return MatchOperand_ParseFail;
782 
783     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
784       int64_t Value = CE->getValue();
785       if (Value < 0 || Value > 15) {
786         Error(StartLoc, "invalid register");
787         return MatchOperand_ParseFail;
788       }
789     }
790 
791     SMLoc EndLoc =
792       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
793 
794     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
795   }
796   else {
797     Register Reg;
798     if (parseRegister(Reg))
799       return MatchOperand_ParseFail;
800 
801     // Map to the correct register kind.
802     RegisterKind Kind;
803     unsigned RegNo;
804     if (Reg.Group == RegGR) {
805       Kind = GR64Reg;
806       RegNo = SystemZMC::GR64Regs[Reg.Num];
807     }
808     else if (Reg.Group == RegFP) {
809       Kind = FP64Reg;
810       RegNo = SystemZMC::FP64Regs[Reg.Num];
811     }
812     else if (Reg.Group == RegV) {
813       Kind = VR128Reg;
814       RegNo = SystemZMC::VR128Regs[Reg.Num];
815     }
816     else if (Reg.Group == RegAR) {
817       Kind = AR32Reg;
818       RegNo = SystemZMC::AR32Regs[Reg.Num];
819     }
820     else if (Reg.Group == RegCR) {
821       Kind = CR64Reg;
822       RegNo = SystemZMC::CR64Regs[Reg.Num];
823     }
824     else {
825       return MatchOperand_ParseFail;
826     }
827 
828     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
829                                                  Reg.StartLoc, Reg.EndLoc));
830   }
831   return MatchOperand_Success;
832 }
833 
834 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
836                                     bool &HaveReg2, Register &Reg2,
837                                     const MCExpr *&Disp,
838                                     const MCExpr *&Length) {
839   // Parse the displacement, which must always be present.
840   if (getParser().parseExpression(Disp))
841     return true;
842 
843   // Parse the optional base and index.
844   HaveReg1 = false;
845   HaveReg2 = false;
846   Length = nullptr;
847   if (getLexer().is(AsmToken::LParen)) {
848     Parser.Lex();
849 
850     if (getLexer().is(AsmToken::Percent)) {
851       // Parse the first register.
852       HaveReg1 = true;
853       if (parseRegister(Reg1))
854         return true;
855     } else {
856       // Parse the length.
857       if (getParser().parseExpression(Length))
858         return true;
859     }
860 
861     // Check whether there's a second register.
862     if (getLexer().is(AsmToken::Comma)) {
863       Parser.Lex();
864       HaveReg2 = true;
865       if (parseRegister(Reg2))
866         return true;
867     }
868 
869     // Consume the closing bracket.
870     if (getLexer().isNot(AsmToken::RParen))
871       return Error(Parser.getTok().getLoc(), "unexpected token in address");
872     Parser.Lex();
873   }
874   return false;
875 }
876 
877 // Verify that Reg is a valid address register (base or index).
878 bool
879 SystemZAsmParser::parseAddressRegister(Register &Reg) {
880   if (Reg.Group == RegV) {
881     Error(Reg.StartLoc, "invalid use of vector addressing");
882     return true;
883   } else if (Reg.Group != RegGR) {
884     Error(Reg.StartLoc, "invalid address register");
885     return true;
886   } else if (Reg.Num == 0) {
887     Error(Reg.StartLoc, "%r0 used in an address");
888     return true;
889   }
890   return false;
891 }
892 
893 // Parse a memory operand and add it to Operands.  The other arguments
894 // are as above.
895 OperandMatchResultTy
896 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
897                                const unsigned *Regs, RegisterKind RegKind) {
898   SMLoc StartLoc = Parser.getTok().getLoc();
899   unsigned Base = 0, Index = 0, LengthReg = 0;
900   Register Reg1, Reg2;
901   bool HaveReg1, HaveReg2;
902   const MCExpr *Disp;
903   const MCExpr *Length;
904   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
905     return MatchOperand_ParseFail;
906 
907   switch (MemKind) {
908   case BDMem:
909     // If we have Reg1, it must be an address register.
910     if (HaveReg1) {
911       if (parseAddressRegister(Reg1))
912         return MatchOperand_ParseFail;
913       Base = Regs[Reg1.Num];
914     }
915     // There must be no Reg2 or length.
916     if (Length) {
917       Error(StartLoc, "invalid use of length addressing");
918       return MatchOperand_ParseFail;
919     }
920     if (HaveReg2) {
921       Error(StartLoc, "invalid use of indexed addressing");
922       return MatchOperand_ParseFail;
923     }
924     break;
925   case BDXMem:
926     // If we have Reg1, it must be an address register.
927     if (HaveReg1) {
928       if (parseAddressRegister(Reg1))
929         return MatchOperand_ParseFail;
930       // If the are two registers, the first one is the index and the
931       // second is the base.
932       if (HaveReg2)
933         Index = Regs[Reg1.Num];
934       else
935         Base = Regs[Reg1.Num];
936     }
937     // If we have Reg2, it must be an address register.
938     if (HaveReg2) {
939       if (parseAddressRegister(Reg2))
940         return MatchOperand_ParseFail;
941       Base = Regs[Reg2.Num];
942     }
943     // There must be no length.
944     if (Length) {
945       Error(StartLoc, "invalid use of length addressing");
946       return MatchOperand_ParseFail;
947     }
948     break;
949   case BDLMem:
950     // If we have Reg2, it must be an address register.
951     if (HaveReg2) {
952       if (parseAddressRegister(Reg2))
953         return MatchOperand_ParseFail;
954       Base = Regs[Reg2.Num];
955     }
956     // We cannot support base+index addressing.
957     if (HaveReg1 && HaveReg2) {
958       Error(StartLoc, "invalid use of indexed addressing");
959       return MatchOperand_ParseFail;
960     }
961     // We must have a length.
962     if (!Length) {
963       Error(StartLoc, "missing length in address");
964       return MatchOperand_ParseFail;
965     }
966     break;
967   case BDRMem:
968     // We must have Reg1, and it must be a GPR.
969     if (!HaveReg1 || Reg1.Group != RegGR) {
970       Error(StartLoc, "invalid operand for instruction");
971       return MatchOperand_ParseFail;
972     }
973     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
974     // If we have Reg2, it must be an address register.
975     if (HaveReg2) {
976       if (parseAddressRegister(Reg2))
977         return MatchOperand_ParseFail;
978       Base = Regs[Reg2.Num];
979     }
980     // There must be no length.
981     if (Length) {
982       Error(StartLoc, "invalid use of length addressing");
983       return MatchOperand_ParseFail;
984     }
985     break;
986   case BDVMem:
987     // We must have Reg1, and it must be a vector register.
988     if (!HaveReg1 || Reg1.Group != RegV) {
989       Error(StartLoc, "vector index required in address");
990       return MatchOperand_ParseFail;
991     }
992     Index = SystemZMC::VR128Regs[Reg1.Num];
993     // If we have Reg2, it must be an address register.
994     if (HaveReg2) {
995       if (parseAddressRegister(Reg2))
996         return MatchOperand_ParseFail;
997       Base = Regs[Reg2.Num];
998     }
999     // There must be no length.
1000     if (Length) {
1001       Error(StartLoc, "invalid use of length addressing");
1002       return MatchOperand_ParseFail;
1003     }
1004     break;
1005   }
1006 
1007   SMLoc EndLoc =
1008     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1009   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1010                                                Index, Length, LengthReg,
1011                                                StartLoc, EndLoc));
1012   return MatchOperand_Success;
1013 }
1014 
1015 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1016   StringRef IDVal = DirectiveID.getIdentifier();
1017 
1018   if (IDVal == ".insn")
1019     return ParseDirectiveInsn(DirectiveID.getLoc());
1020 
1021   return true;
1022 }
1023 
1024 /// ParseDirectiveInsn
1025 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1026 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1027   MCAsmParser &Parser = getParser();
1028 
1029   // Expect instruction format as identifier.
1030   StringRef Format;
1031   SMLoc ErrorLoc = Parser.getTok().getLoc();
1032   if (Parser.parseIdentifier(Format))
1033     return Error(ErrorLoc, "expected instruction format");
1034 
1035   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1036 
1037   // Find entry for this format in InsnMatchTable.
1038   auto EntryRange =
1039     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1040                      Format, CompareInsn());
1041 
1042   // If first == second, couldn't find a match in the table.
1043   if (EntryRange.first == EntryRange.second)
1044     return Error(ErrorLoc, "unrecognized format");
1045 
1046   struct InsnMatchEntry *Entry = EntryRange.first;
1047 
1048   // Format should match from equal_range.
1049   assert(Entry->Format == Format);
1050 
1051   // Parse the following operands using the table's information.
1052   for (int i = 0; i < Entry->NumOperands; i++) {
1053     MatchClassKind Kind = Entry->OperandKinds[i];
1054 
1055     SMLoc StartLoc = Parser.getTok().getLoc();
1056 
1057     // Always expect commas as separators for operands.
1058     if (getLexer().isNot(AsmToken::Comma))
1059       return Error(StartLoc, "unexpected token in directive");
1060     Lex();
1061 
1062     // Parse operands.
1063     OperandMatchResultTy ResTy;
1064     if (Kind == MCK_AnyReg)
1065       ResTy = parseAnyReg(Operands);
1066     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1067       ResTy = parseBDXAddr64(Operands);
1068     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1069       ResTy = parseBDAddr64(Operands);
1070     else if (Kind == MCK_PCRel32)
1071       ResTy = parsePCRel32(Operands);
1072     else if (Kind == MCK_PCRel16)
1073       ResTy = parsePCRel16(Operands);
1074     else {
1075       // Only remaining operand kind is an immediate.
1076       const MCExpr *Expr;
1077       SMLoc StartLoc = Parser.getTok().getLoc();
1078 
1079       // Expect immediate expression.
1080       if (Parser.parseExpression(Expr))
1081         return Error(StartLoc, "unexpected token in directive");
1082 
1083       SMLoc EndLoc =
1084         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1085 
1086       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1087       ResTy = MatchOperand_Success;
1088     }
1089 
1090     if (ResTy != MatchOperand_Success)
1091       return true;
1092   }
1093 
1094   // Build the instruction with the parsed operands.
1095   MCInst Inst = MCInstBuilder(Entry->Opcode);
1096 
1097   for (size_t i = 0; i < Operands.size(); i++) {
1098     MCParsedAsmOperand &Operand = *Operands[i];
1099     MatchClassKind Kind = Entry->OperandKinds[i];
1100 
1101     // Verify operand.
1102     unsigned Res = validateOperandClass(Operand, Kind);
1103     if (Res != Match_Success)
1104       return Error(Operand.getStartLoc(), "unexpected operand type");
1105 
1106     // Add operands to instruction.
1107     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1108     if (ZOperand.isReg())
1109       ZOperand.addRegOperands(Inst, 1);
1110     else if (ZOperand.isMem(BDMem))
1111       ZOperand.addBDAddrOperands(Inst, 2);
1112     else if (ZOperand.isMem(BDXMem))
1113       ZOperand.addBDXAddrOperands(Inst, 3);
1114     else if (ZOperand.isImm())
1115       ZOperand.addImmOperands(Inst, 1);
1116     else
1117       llvm_unreachable("unexpected operand type");
1118   }
1119 
1120   // Emit as a regular instruction.
1121   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1122 
1123   return false;
1124 }
1125 
1126 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1127                                      SMLoc &EndLoc) {
1128   Register Reg;
1129   if (parseRegister(Reg))
1130     return true;
1131   if (Reg.Group == RegGR)
1132     RegNo = SystemZMC::GR64Regs[Reg.Num];
1133   else if (Reg.Group == RegFP)
1134     RegNo = SystemZMC::FP64Regs[Reg.Num];
1135   else if (Reg.Group == RegV)
1136     RegNo = SystemZMC::VR128Regs[Reg.Num];
1137   else if (Reg.Group == RegAR)
1138     RegNo = SystemZMC::AR32Regs[Reg.Num];
1139   else if (Reg.Group == RegCR)
1140     RegNo = SystemZMC::CR64Regs[Reg.Num];
1141   StartLoc = Reg.StartLoc;
1142   EndLoc = Reg.EndLoc;
1143   return false;
1144 }
1145 
1146 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1147                                         StringRef Name, SMLoc NameLoc,
1148                                         OperandVector &Operands) {
1149   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1150 
1151   // Read the remaining operands.
1152   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1153     // Read the first operand.
1154     if (parseOperand(Operands, Name)) {
1155       return true;
1156     }
1157 
1158     // Read any subsequent operands.
1159     while (getLexer().is(AsmToken::Comma)) {
1160       Parser.Lex();
1161       if (parseOperand(Operands, Name)) {
1162         return true;
1163       }
1164     }
1165     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1166       SMLoc Loc = getLexer().getLoc();
1167       return Error(Loc, "unexpected token in argument list");
1168     }
1169   }
1170 
1171   // Consume the EndOfStatement.
1172   Parser.Lex();
1173   return false;
1174 }
1175 
1176 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1177                                     StringRef Mnemonic) {
1178   // Check if the current operand has a custom associated parser, if so, try to
1179   // custom parse the operand, or fallback to the general approach.  Force all
1180   // features to be available during the operand check, or else we will fail to
1181   // find the custom parser, and then we will later get an InvalidOperand error
1182   // instead of a MissingFeature errror.
1183   uint64_t AvailableFeatures = getAvailableFeatures();
1184   setAvailableFeatures(~(uint64_t)0);
1185   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1186   setAvailableFeatures(AvailableFeatures);
1187   if (ResTy == MatchOperand_Success)
1188     return false;
1189 
1190   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1191   // there was a match, but an error occurred, in which case, just return that
1192   // the operand parsing failed.
1193   if (ResTy == MatchOperand_ParseFail)
1194     return true;
1195 
1196   // Check for a register.  All real register operands should have used
1197   // a context-dependent parse routine, which gives the required register
1198   // class.  The code is here to mop up other cases, like those where
1199   // the instruction isn't recognized.
1200   if (Parser.getTok().is(AsmToken::Percent)) {
1201     Register Reg;
1202     if (parseRegister(Reg))
1203       return true;
1204     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1205     return false;
1206   }
1207 
1208   // The only other type of operand is an immediate or address.  As above,
1209   // real address operands should have used a context-dependent parse routine,
1210   // so we treat any plain expression as an immediate.
1211   SMLoc StartLoc = Parser.getTok().getLoc();
1212   Register Reg1, Reg2;
1213   bool HaveReg1, HaveReg2;
1214   const MCExpr *Expr;
1215   const MCExpr *Length;
1216   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1217     return true;
1218   // If the register combination is not valid for any instruction, reject it.
1219   // Otherwise, fall back to reporting an unrecognized instruction.
1220   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1221       && parseAddressRegister(Reg1))
1222     return true;
1223   if (HaveReg2 && parseAddressRegister(Reg2))
1224     return true;
1225 
1226   SMLoc EndLoc =
1227     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1228   if (HaveReg1 || HaveReg2 || Length)
1229     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1230   else
1231     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1232   return false;
1233 }
1234 
1235 static std::string SystemZMnemonicSpellCheck(StringRef S, uint64_t FBS,
1236                                              unsigned VariantID = 0);
1237 
1238 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1239                                                OperandVector &Operands,
1240                                                MCStreamer &Out,
1241                                                uint64_t &ErrorInfo,
1242                                                bool MatchingInlineAsm) {
1243   MCInst Inst;
1244   unsigned MatchResult;
1245 
1246   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1247                                      MatchingInlineAsm);
1248   switch (MatchResult) {
1249   case Match_Success:
1250     Inst.setLoc(IDLoc);
1251     Out.EmitInstruction(Inst, getSTI());
1252     return false;
1253 
1254   case Match_MissingFeature: {
1255     assert(ErrorInfo && "Unknown missing feature!");
1256     // Special case the error message for the very common case where only
1257     // a single subtarget feature is missing
1258     std::string Msg = "instruction requires:";
1259     uint64_t Mask = 1;
1260     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1261       if (ErrorInfo & Mask) {
1262         Msg += " ";
1263         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1264       }
1265       Mask <<= 1;
1266     }
1267     return Error(IDLoc, Msg);
1268   }
1269 
1270   case Match_InvalidOperand: {
1271     SMLoc ErrorLoc = IDLoc;
1272     if (ErrorInfo != ~0ULL) {
1273       if (ErrorInfo >= Operands.size())
1274         return Error(IDLoc, "too few operands for instruction");
1275 
1276       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1277       if (ErrorLoc == SMLoc())
1278         ErrorLoc = IDLoc;
1279     }
1280     return Error(ErrorLoc, "invalid operand for instruction");
1281   }
1282 
1283   case Match_MnemonicFail: {
1284     uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1285     std::string Suggestion = SystemZMnemonicSpellCheck(
1286       ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1287     return Error(IDLoc, "invalid instruction" + Suggestion,
1288                  ((SystemZOperand &)*Operands[0]).getLocRange());
1289   }
1290   }
1291 
1292   llvm_unreachable("Unexpected match type");
1293 }
1294 
1295 OperandMatchResultTy
1296 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1297                              int64_t MaxVal, bool AllowTLS) {
1298   MCContext &Ctx = getContext();
1299   MCStreamer &Out = getStreamer();
1300   const MCExpr *Expr;
1301   SMLoc StartLoc = Parser.getTok().getLoc();
1302   if (getParser().parseExpression(Expr))
1303     return MatchOperand_NoMatch;
1304 
1305   // For consistency with the GNU assembler, treat immediates as offsets
1306   // from ".".
1307   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1308     int64_t Value = CE->getValue();
1309     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1310       Error(StartLoc, "offset out of range");
1311       return MatchOperand_ParseFail;
1312     }
1313     MCSymbol *Sym = Ctx.createTempSymbol();
1314     Out.EmitLabel(Sym);
1315     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1316                                                  Ctx);
1317     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1318   }
1319 
1320   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1321   const MCExpr *Sym = nullptr;
1322   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1323     Parser.Lex();
1324 
1325     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1326       Error(Parser.getTok().getLoc(), "unexpected token");
1327       return MatchOperand_ParseFail;
1328     }
1329 
1330     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1331     StringRef Name = Parser.getTok().getString();
1332     if (Name == "tls_gdcall")
1333       Kind = MCSymbolRefExpr::VK_TLSGD;
1334     else if (Name == "tls_ldcall")
1335       Kind = MCSymbolRefExpr::VK_TLSLDM;
1336     else {
1337       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1338       return MatchOperand_ParseFail;
1339     }
1340     Parser.Lex();
1341 
1342     if (Parser.getTok().isNot(AsmToken::Colon)) {
1343       Error(Parser.getTok().getLoc(), "unexpected token");
1344       return MatchOperand_ParseFail;
1345     }
1346     Parser.Lex();
1347 
1348     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1349       Error(Parser.getTok().getLoc(), "unexpected token");
1350       return MatchOperand_ParseFail;
1351     }
1352 
1353     StringRef Identifier = Parser.getTok().getString();
1354     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1355                                   Kind, Ctx);
1356     Parser.Lex();
1357   }
1358 
1359   SMLoc EndLoc =
1360     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1361 
1362   if (AllowTLS)
1363     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1364                                                     StartLoc, EndLoc));
1365   else
1366     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1367 
1368   return MatchOperand_Success;
1369 }
1370 
1371 // Force static initialization.
1372 extern "C" void LLVMInitializeSystemZAsmParser() {
1373   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1374 }
1375