1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/SMLoc.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <iterator>
34 #include <memory>
35 #include <string>
36 
37 using namespace llvm;
38 
39 // Return true if Expr is in the range [MinValue, MaxValue].
40 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
41   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
42     int64_t Value = CE->getValue();
43     return Value >= MinValue && Value <= MaxValue;
44   }
45   return false;
46 }
47 
48 namespace {
49 
50 enum RegisterKind {
51   GR32Reg,
52   GRH32Reg,
53   GR64Reg,
54   GR128Reg,
55   ADDR32Reg,
56   ADDR64Reg,
57   FP32Reg,
58   FP64Reg,
59   FP128Reg,
60   VR32Reg,
61   VR64Reg,
62   VR128Reg,
63   AR32Reg,
64 };
65 
66 enum MemoryKind {
67   BDMem,
68   BDXMem,
69   BDLMem,
70   BDRMem,
71   BDVMem
72 };
73 
74 class SystemZOperand : public MCParsedAsmOperand {
75 private:
76   enum OperandKind {
77     KindInvalid,
78     KindToken,
79     KindReg,
80     KindImm,
81     KindImmTLS,
82     KindMem
83   };
84 
85   OperandKind Kind;
86   SMLoc StartLoc, EndLoc;
87 
88   // A string of length Length, starting at Data.
89   struct TokenOp {
90     const char *Data;
91     unsigned Length;
92   };
93 
94   // LLVM register Num, which has kind Kind.  In some ways it might be
95   // easier for this class to have a register bank (general, floating-point
96   // or access) and a raw register number (0-15).  This would postpone the
97   // interpretation of the operand to the add*() methods and avoid the need
98   // for context-dependent parsing.  However, we do things the current way
99   // because of the virtual getReg() method, which needs to distinguish
100   // between (say) %r0 used as a single register and %r0 used as a pair.
101   // Context-dependent parsing can also give us slightly better error
102   // messages when invalid pairs like %r1 are used.
103   struct RegOp {
104     RegisterKind Kind;
105     unsigned Num;
106   };
107 
108   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
109   // MemKind says what type of memory this is and RegKind says what type
110   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
111   // length for D(L,B)-style operands, otherwise it is null.
112   struct MemOp {
113     unsigned Base : 12;
114     unsigned Index : 12;
115     unsigned MemKind : 4;
116     unsigned RegKind : 4;
117     const MCExpr *Disp;
118     union {
119       const MCExpr *Imm;
120       unsigned Reg;
121     } Length;
122   };
123 
124   // Imm is an immediate operand, and Sym is an optional TLS symbol
125   // for use with a __tls_get_offset marker relocation.
126   struct ImmTLSOp {
127     const MCExpr *Imm;
128     const MCExpr *Sym;
129   };
130 
131   union {
132     TokenOp Token;
133     RegOp Reg;
134     const MCExpr *Imm;
135     ImmTLSOp ImmTLS;
136     MemOp Mem;
137   };
138 
139   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
140     // Add as immediates when possible.  Null MCExpr = 0.
141     if (!Expr)
142       Inst.addOperand(MCOperand::createImm(0));
143     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
144       Inst.addOperand(MCOperand::createImm(CE->getValue()));
145     else
146       Inst.addOperand(MCOperand::createExpr(Expr));
147   }
148 
149 public:
150   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
151       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
152 
153   // Create particular kinds of operand.
154   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
155                                                        SMLoc EndLoc) {
156     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
157   }
158 
159   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
160     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
161     Op->Token.Data = Str.data();
162     Op->Token.Length = Str.size();
163     return Op;
164   }
165 
166   static std::unique_ptr<SystemZOperand>
167   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
168     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
169     Op->Reg.Kind = Kind;
170     Op->Reg.Num = Num;
171     return Op;
172   }
173 
174   static std::unique_ptr<SystemZOperand>
175   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
176     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
177     Op->Imm = Expr;
178     return Op;
179   }
180 
181   static std::unique_ptr<SystemZOperand>
182   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
183             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
184             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
185     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
186     Op->Mem.MemKind = MemKind;
187     Op->Mem.RegKind = RegKind;
188     Op->Mem.Base = Base;
189     Op->Mem.Index = Index;
190     Op->Mem.Disp = Disp;
191     if (MemKind == BDLMem)
192       Op->Mem.Length.Imm = LengthImm;
193     if (MemKind == BDRMem)
194       Op->Mem.Length.Reg = LengthReg;
195     return Op;
196   }
197 
198   static std::unique_ptr<SystemZOperand>
199   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
200                SMLoc StartLoc, SMLoc EndLoc) {
201     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
202     Op->ImmTLS.Imm = Imm;
203     Op->ImmTLS.Sym = Sym;
204     return Op;
205   }
206 
207   // Token operands
208   bool isToken() const override {
209     return Kind == KindToken;
210   }
211   StringRef getToken() const {
212     assert(Kind == KindToken && "Not a token");
213     return StringRef(Token.Data, Token.Length);
214   }
215 
216   // Register operands.
217   bool isReg() const override {
218     return Kind == KindReg;
219   }
220   bool isReg(RegisterKind RegKind) const {
221     return Kind == KindReg && Reg.Kind == RegKind;
222   }
223   unsigned getReg() const override {
224     assert(Kind == KindReg && "Not a register");
225     return Reg.Num;
226   }
227 
228   // Immediate operands.
229   bool isImm() const override {
230     return Kind == KindImm;
231   }
232   bool isImm(int64_t MinValue, int64_t MaxValue) const {
233     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
234   }
235   const MCExpr *getImm() const {
236     assert(Kind == KindImm && "Not an immediate");
237     return Imm;
238   }
239 
240   // Immediate operands with optional TLS symbol.
241   bool isImmTLS() const {
242     return Kind == KindImmTLS;
243   }
244 
245   // Memory operands.
246   bool isMem() const override {
247     return Kind == KindMem;
248   }
249   bool isMem(MemoryKind MemKind) const {
250     return (Kind == KindMem &&
251             (Mem.MemKind == MemKind ||
252              // A BDMem can be treated as a BDXMem in which the index
253              // register field is 0.
254              (Mem.MemKind == BDMem && MemKind == BDXMem)));
255   }
256   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
257     return isMem(MemKind) && Mem.RegKind == RegKind;
258   }
259   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
260     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
261   }
262   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
263     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
264   }
265   bool isMemDisp12Len4(RegisterKind RegKind) const {
266     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
267   }
268   bool isMemDisp12Len8(RegisterKind RegKind) const {
269     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
270   }
271 
272   // Override MCParsedAsmOperand.
273   SMLoc getStartLoc() const override { return StartLoc; }
274   SMLoc getEndLoc() const override { return EndLoc; }
275   void print(raw_ostream &OS) const override;
276 
277   // Used by the TableGen code to add particular types of operand
278   // to an instruction.
279   void addRegOperands(MCInst &Inst, unsigned N) const {
280     assert(N == 1 && "Invalid number of operands");
281     Inst.addOperand(MCOperand::createReg(getReg()));
282   }
283   void addImmOperands(MCInst &Inst, unsigned N) const {
284     assert(N == 1 && "Invalid number of operands");
285     addExpr(Inst, getImm());
286   }
287   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
288     assert(N == 2 && "Invalid number of operands");
289     assert(isMem(BDMem) && "Invalid operand type");
290     Inst.addOperand(MCOperand::createReg(Mem.Base));
291     addExpr(Inst, Mem.Disp);
292   }
293   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
294     assert(N == 3 && "Invalid number of operands");
295     assert(isMem(BDXMem) && "Invalid operand type");
296     Inst.addOperand(MCOperand::createReg(Mem.Base));
297     addExpr(Inst, Mem.Disp);
298     Inst.addOperand(MCOperand::createReg(Mem.Index));
299   }
300   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
301     assert(N == 3 && "Invalid number of operands");
302     assert(isMem(BDLMem) && "Invalid operand type");
303     Inst.addOperand(MCOperand::createReg(Mem.Base));
304     addExpr(Inst, Mem.Disp);
305     addExpr(Inst, Mem.Length.Imm);
306   }
307   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
308     assert(N == 3 && "Invalid number of operands");
309     assert(isMem(BDRMem) && "Invalid operand type");
310     Inst.addOperand(MCOperand::createReg(Mem.Base));
311     addExpr(Inst, Mem.Disp);
312     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
313   }
314   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
315     assert(N == 3 && "Invalid number of operands");
316     assert(isMem(BDVMem) && "Invalid operand type");
317     Inst.addOperand(MCOperand::createReg(Mem.Base));
318     addExpr(Inst, Mem.Disp);
319     Inst.addOperand(MCOperand::createReg(Mem.Index));
320   }
321   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
322     assert(N == 2 && "Invalid number of operands");
323     assert(Kind == KindImmTLS && "Invalid operand type");
324     addExpr(Inst, ImmTLS.Imm);
325     if (ImmTLS.Sym)
326       addExpr(Inst, ImmTLS.Sym);
327   }
328 
329   // Used by the TableGen code to check for particular operand types.
330   bool isGR32() const { return isReg(GR32Reg); }
331   bool isGRH32() const { return isReg(GRH32Reg); }
332   bool isGRX32() const { return false; }
333   bool isGR64() const { return isReg(GR64Reg); }
334   bool isGR128() const { return isReg(GR128Reg); }
335   bool isADDR32() const { return isReg(ADDR32Reg); }
336   bool isADDR64() const { return isReg(ADDR64Reg); }
337   bool isADDR128() const { return false; }
338   bool isFP32() const { return isReg(FP32Reg); }
339   bool isFP64() const { return isReg(FP64Reg); }
340   bool isFP128() const { return isReg(FP128Reg); }
341   bool isVR32() const { return isReg(VR32Reg); }
342   bool isVR64() const { return isReg(VR64Reg); }
343   bool isVF128() const { return false; }
344   bool isVR128() const { return isReg(VR128Reg); }
345   bool isAR32() const { return isReg(AR32Reg); }
346   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
347   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
348   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
349   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
350   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
351   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
352   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
353   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
354   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
355   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
356   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
357   bool isU1Imm() const { return isImm(0, 1); }
358   bool isU2Imm() const { return isImm(0, 3); }
359   bool isU3Imm() const { return isImm(0, 7); }
360   bool isU4Imm() const { return isImm(0, 15); }
361   bool isU6Imm() const { return isImm(0, 63); }
362   bool isU8Imm() const { return isImm(0, 255); }
363   bool isS8Imm() const { return isImm(-128, 127); }
364   bool isU12Imm() const { return isImm(0, 4095); }
365   bool isU16Imm() const { return isImm(0, 65535); }
366   bool isS16Imm() const { return isImm(-32768, 32767); }
367   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
368   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
369   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
370 };
371 
372 class SystemZAsmParser : public MCTargetAsmParser {
373 #define GET_ASSEMBLER_HEADER
374 #include "SystemZGenAsmMatcher.inc"
375 
376 private:
377   MCAsmParser &Parser;
378   enum RegisterGroup {
379     RegGR,
380     RegFP,
381     RegV,
382     RegAR
383   };
384   struct Register {
385     RegisterGroup Group;
386     unsigned Num;
387     SMLoc StartLoc, EndLoc;
388   };
389 
390   bool parseRegister(Register &Reg);
391 
392   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
393                      bool IsAddress = false);
394 
395   OperandMatchResultTy parseRegister(OperandVector &Operands,
396                                      RegisterGroup Group, const unsigned *Regs,
397                                      RegisterKind Kind);
398 
399   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
400 
401   bool parseAddress(bool &HaveReg1, Register &Reg1,
402                     bool &HaveReg2, Register &Reg2,
403                     const MCExpr *&Disp, const MCExpr *&Length);
404   bool parseAddressRegister(Register &Reg);
405 
406   bool ParseDirectiveInsn(SMLoc L);
407 
408   OperandMatchResultTy parseAddress(OperandVector &Operands,
409                                     MemoryKind MemKind, const unsigned *Regs,
410                                     RegisterKind RegKind);
411 
412   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
413                                   int64_t MaxVal, bool AllowTLS);
414 
415   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
416 
417 public:
418   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
419                    const MCInstrInfo &MII,
420                    const MCTargetOptions &Options)
421     : MCTargetAsmParser(Options, sti), Parser(parser) {
422     MCAsmParserExtension::Initialize(Parser);
423 
424     // Alias the .word directive to .short.
425     parser.addAliasForDirective(".word", ".short");
426 
427     // Initialize the set of available features.
428     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
429   }
430 
431   // Override MCTargetAsmParser.
432   bool ParseDirective(AsmToken DirectiveID) override;
433   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
434   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
435                         SMLoc NameLoc, OperandVector &Operands) override;
436   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
437                                OperandVector &Operands, MCStreamer &Out,
438                                uint64_t &ErrorInfo,
439                                bool MatchingInlineAsm) override;
440 
441   // Used by the TableGen code to parse particular operand types.
442   OperandMatchResultTy parseGR32(OperandVector &Operands) {
443     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
444   }
445   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
446     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
447   }
448   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
449     llvm_unreachable("GRX32 should only be used for pseudo instructions");
450   }
451   OperandMatchResultTy parseGR64(OperandVector &Operands) {
452     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
453   }
454   OperandMatchResultTy parseGR128(OperandVector &Operands) {
455     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
456   }
457   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
458     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
459   }
460   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
461     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
462   }
463   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
464     llvm_unreachable("Shouldn't be used as an operand");
465   }
466   OperandMatchResultTy parseFP32(OperandVector &Operands) {
467     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
468   }
469   OperandMatchResultTy parseFP64(OperandVector &Operands) {
470     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
471   }
472   OperandMatchResultTy parseFP128(OperandVector &Operands) {
473     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
474   }
475   OperandMatchResultTy parseVR32(OperandVector &Operands) {
476     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
477   }
478   OperandMatchResultTy parseVR64(OperandVector &Operands) {
479     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
480   }
481   OperandMatchResultTy parseVF128(OperandVector &Operands) {
482     llvm_unreachable("Shouldn't be used as an operand");
483   }
484   OperandMatchResultTy parseVR128(OperandVector &Operands) {
485     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
486   }
487   OperandMatchResultTy parseAR32(OperandVector &Operands) {
488     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
489   }
490   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
491     return parseAnyRegister(Operands);
492   }
493   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
494     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
495   }
496   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
497     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
498   }
499   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
500     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
501   }
502   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
503     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
504   }
505   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
506     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
507   }
508   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
509     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
510   }
511   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
512     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
513   }
514   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
515     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
516   }
517   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
518     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
519   }
520   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
521     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
522   }
523   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
524     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
525   }
526   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
527     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
528   }
529 };
530 
531 } // end anonymous namespace
532 
533 #define GET_REGISTER_MATCHER
534 #define GET_SUBTARGET_FEATURE_NAME
535 #define GET_MATCHER_IMPLEMENTATION
536 #include "SystemZGenAsmMatcher.inc"
537 
538 // Used for the .insn directives; contains information needed to parse the
539 // operands in the directive.
540 struct InsnMatchEntry {
541   StringRef Format;
542   uint64_t Opcode;
543   int32_t NumOperands;
544   MatchClassKind OperandKinds[5];
545 };
546 
547 // For equal_range comparison.
548 struct CompareInsn {
549   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
550     return LHS.Format < RHS;
551   }
552   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
553     return LHS < RHS.Format;
554   }
555   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
556     return LHS.Format < RHS.Format;
557   }
558 };
559 
560 // Table initializing information for parsing the .insn directive.
561 static struct InsnMatchEntry InsnMatchTable[] = {
562   /* Format, Opcode, NumOperands, OperandKinds */
563   { "e", SystemZ::InsnE, 1,
564     { MCK_U16Imm } },
565   { "ri", SystemZ::InsnRI, 3,
566     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
567   { "rie", SystemZ::InsnRIE, 4,
568     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
569   { "ril", SystemZ::InsnRIL, 3,
570     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
571   { "rilu", SystemZ::InsnRILU, 3,
572     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
573   { "ris", SystemZ::InsnRIS, 5,
574     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
575   { "rr", SystemZ::InsnRR, 3,
576     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
577   { "rre", SystemZ::InsnRRE, 3,
578     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
579   { "rrf", SystemZ::InsnRRF, 5,
580     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
581   { "rrs", SystemZ::InsnRRS, 5,
582     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
583   { "rs", SystemZ::InsnRS, 4,
584     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
585   { "rse", SystemZ::InsnRSE, 4,
586     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
587   { "rsi", SystemZ::InsnRSI, 4,
588     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
589   { "rsy", SystemZ::InsnRSY, 4,
590     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
591   { "rx", SystemZ::InsnRX, 3,
592     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
593   { "rxe", SystemZ::InsnRXE, 3,
594     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
595   { "rxf", SystemZ::InsnRXF, 4,
596     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
597   { "rxy", SystemZ::InsnRXY, 3,
598     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
599   { "s", SystemZ::InsnS, 2,
600     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
601   { "si", SystemZ::InsnSI, 3,
602     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
603   { "sil", SystemZ::InsnSIL, 3,
604     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
605   { "siy", SystemZ::InsnSIY, 3,
606     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
607   { "ss", SystemZ::InsnSS, 4,
608     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
609   { "sse", SystemZ::InsnSSE, 3,
610     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
611   { "ssf", SystemZ::InsnSSF, 4,
612     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
613 };
614 
615 void SystemZOperand::print(raw_ostream &OS) const {
616   llvm_unreachable("Not implemented");
617 }
618 
619 // Parse one register of the form %<prefix><number>.
620 bool SystemZAsmParser::parseRegister(Register &Reg) {
621   Reg.StartLoc = Parser.getTok().getLoc();
622 
623   // Eat the % prefix.
624   if (Parser.getTok().isNot(AsmToken::Percent))
625     return Error(Parser.getTok().getLoc(), "register expected");
626   Parser.Lex();
627 
628   // Expect a register name.
629   if (Parser.getTok().isNot(AsmToken::Identifier))
630     return Error(Reg.StartLoc, "invalid register");
631 
632   // Check that there's a prefix.
633   StringRef Name = Parser.getTok().getString();
634   if (Name.size() < 2)
635     return Error(Reg.StartLoc, "invalid register");
636   char Prefix = Name[0];
637 
638   // Treat the rest of the register name as a register number.
639   if (Name.substr(1).getAsInteger(10, Reg.Num))
640     return Error(Reg.StartLoc, "invalid register");
641 
642   // Look for valid combinations of prefix and number.
643   if (Prefix == 'r' && Reg.Num < 16)
644     Reg.Group = RegGR;
645   else if (Prefix == 'f' && Reg.Num < 16)
646     Reg.Group = RegFP;
647   else if (Prefix == 'v' && Reg.Num < 32)
648     Reg.Group = RegV;
649   else if (Prefix == 'a' && Reg.Num < 16)
650     Reg.Group = RegAR;
651   else
652     return Error(Reg.StartLoc, "invalid register");
653 
654   Reg.EndLoc = Parser.getTok().getLoc();
655   Parser.Lex();
656   return false;
657 }
658 
659 // Parse a register of group Group.  If Regs is nonnull, use it to map
660 // the raw register number to LLVM numbering, with zero entries
661 // indicating an invalid register.  IsAddress says whether the
662 // register appears in an address context. Allow FP Group if expecting
663 // RegV Group, since the f-prefix yields the FP group even while used
664 // with vector instructions.
665 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
666                                      const unsigned *Regs, bool IsAddress) {
667   if (parseRegister(Reg))
668     return true;
669   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
670     return Error(Reg.StartLoc, "invalid operand for instruction");
671   if (Regs && Regs[Reg.Num] == 0)
672     return Error(Reg.StartLoc, "invalid register pair");
673   if (Reg.Num == 0 && IsAddress)
674     return Error(Reg.StartLoc, "%r0 used in an address");
675   if (Regs)
676     Reg.Num = Regs[Reg.Num];
677   return false;
678 }
679 
680 // Parse a register and add it to Operands.  The other arguments are as above.
681 OperandMatchResultTy
682 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
683                                 const unsigned *Regs, RegisterKind Kind) {
684   if (Parser.getTok().isNot(AsmToken::Percent))
685     return MatchOperand_NoMatch;
686 
687   Register Reg;
688   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
689   if (parseRegister(Reg, Group, Regs, IsAddress))
690     return MatchOperand_ParseFail;
691 
692   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
693                                                Reg.StartLoc, Reg.EndLoc));
694   return MatchOperand_Success;
695 }
696 
697 // Parse any type of register (including integers) and add it to Operands.
698 OperandMatchResultTy
699 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
700   // Handle integer values.
701   if (Parser.getTok().is(AsmToken::Integer)) {
702     const MCExpr *Register;
703     SMLoc StartLoc = Parser.getTok().getLoc();
704     if (Parser.parseExpression(Register))
705       return MatchOperand_ParseFail;
706 
707     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
708       int64_t Value = CE->getValue();
709       if (Value < 0 || Value > 15) {
710         Error(StartLoc, "invalid register");
711         return MatchOperand_ParseFail;
712       }
713     }
714 
715     SMLoc EndLoc =
716       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
717 
718     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
719   }
720   else {
721     Register Reg;
722     if (parseRegister(Reg))
723       return MatchOperand_ParseFail;
724 
725     // Map to the correct register kind.
726     RegisterKind Kind;
727     unsigned RegNo;
728     if (Reg.Group == RegGR) {
729       Kind = GR64Reg;
730       RegNo = SystemZMC::GR64Regs[Reg.Num];
731     }
732     else if (Reg.Group == RegFP) {
733       Kind = FP64Reg;
734       RegNo = SystemZMC::FP64Regs[Reg.Num];
735     }
736     else if (Reg.Group == RegV) {
737       Kind = VR128Reg;
738       RegNo = SystemZMC::VR128Regs[Reg.Num];
739     }
740     else if (Reg.Group == RegAR) {
741       Kind = AR32Reg;
742       RegNo = SystemZMC::AR32Regs[Reg.Num];
743     }
744     else {
745       return MatchOperand_ParseFail;
746     }
747 
748     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
749                                                  Reg.StartLoc, Reg.EndLoc));
750   }
751   return MatchOperand_Success;
752 }
753 
754 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
755 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
756                                     bool &HaveReg2, Register &Reg2,
757                                     const MCExpr *&Disp,
758                                     const MCExpr *&Length) {
759   // Parse the displacement, which must always be present.
760   if (getParser().parseExpression(Disp))
761     return true;
762 
763   // Parse the optional base and index.
764   HaveReg1 = false;
765   HaveReg2 = false;
766   Length = nullptr;
767   if (getLexer().is(AsmToken::LParen)) {
768     Parser.Lex();
769 
770     if (getLexer().is(AsmToken::Percent)) {
771       // Parse the first register.
772       HaveReg1 = true;
773       if (parseRegister(Reg1))
774         return true;
775     } else {
776       // Parse the length.
777       if (getParser().parseExpression(Length))
778         return true;
779     }
780 
781     // Check whether there's a second register.
782     if (getLexer().is(AsmToken::Comma)) {
783       Parser.Lex();
784       HaveReg2 = true;
785       if (parseRegister(Reg2))
786         return true;
787     }
788 
789     // Consume the closing bracket.
790     if (getLexer().isNot(AsmToken::RParen))
791       return Error(Parser.getTok().getLoc(), "unexpected token in address");
792     Parser.Lex();
793   }
794   return false;
795 }
796 
797 // Verify that Reg is a valid address register (base or index).
798 bool
799 SystemZAsmParser::parseAddressRegister(Register &Reg) {
800   if (Reg.Group == RegV) {
801     Error(Reg.StartLoc, "invalid use of vector addressing");
802     return true;
803   } else if (Reg.Group != RegGR) {
804     Error(Reg.StartLoc, "invalid address register");
805     return true;
806   } else if (Reg.Num == 0) {
807     Error(Reg.StartLoc, "%r0 used in an address");
808     return true;
809   }
810   return false;
811 }
812 
813 // Parse a memory operand and add it to Operands.  The other arguments
814 // are as above.
815 OperandMatchResultTy
816 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
817                                const unsigned *Regs, RegisterKind RegKind) {
818   SMLoc StartLoc = Parser.getTok().getLoc();
819   unsigned Base = 0, Index = 0, LengthReg = 0;
820   Register Reg1, Reg2;
821   bool HaveReg1, HaveReg2;
822   const MCExpr *Disp;
823   const MCExpr *Length;
824   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
825     return MatchOperand_ParseFail;
826 
827   switch (MemKind) {
828   case BDMem:
829     // If we have Reg1, it must be an address register.
830     if (HaveReg1) {
831       if (parseAddressRegister(Reg1))
832         return MatchOperand_ParseFail;
833       Base = Regs[Reg1.Num];
834     }
835     // There must be no Reg2 or length.
836     if (Length) {
837       Error(StartLoc, "invalid use of length addressing");
838       return MatchOperand_ParseFail;
839     }
840     if (HaveReg2) {
841       Error(StartLoc, "invalid use of indexed addressing");
842       return MatchOperand_ParseFail;
843     }
844     break;
845   case BDXMem:
846     // If we have Reg1, it must be an address register.
847     if (HaveReg1) {
848       if (parseAddressRegister(Reg1))
849         return MatchOperand_ParseFail;
850       // If the are two registers, the first one is the index and the
851       // second is the base.
852       if (HaveReg2)
853         Index = Regs[Reg1.Num];
854       else
855         Base = Regs[Reg1.Num];
856     }
857     // If we have Reg2, it must be an address register.
858     if (HaveReg2) {
859       if (parseAddressRegister(Reg2))
860         return MatchOperand_ParseFail;
861       Base = Regs[Reg2.Num];
862     }
863     // There must be no length.
864     if (Length) {
865       Error(StartLoc, "invalid use of length addressing");
866       return MatchOperand_ParseFail;
867     }
868     break;
869   case BDLMem:
870     // If we have Reg2, it must be an address register.
871     if (HaveReg2) {
872       if (parseAddressRegister(Reg2))
873         return MatchOperand_ParseFail;
874       Base = Regs[Reg2.Num];
875     }
876     // We cannot support base+index addressing.
877     if (HaveReg1 && HaveReg2) {
878       Error(StartLoc, "invalid use of indexed addressing");
879       return MatchOperand_ParseFail;
880     }
881     // We must have a length.
882     if (!Length) {
883       Error(StartLoc, "missing length in address");
884       return MatchOperand_ParseFail;
885     }
886     break;
887   case BDRMem:
888     // We must have Reg1, and it must be a GPR.
889     if (!HaveReg1 || Reg1.Group != RegGR) {
890       Error(StartLoc, "invalid operand for instruction");
891       return MatchOperand_ParseFail;
892     }
893     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
894     // If we have Reg2, it must be an address register.
895     if (HaveReg2) {
896       if (parseAddressRegister(Reg2))
897         return MatchOperand_ParseFail;
898       Base = Regs[Reg2.Num];
899     }
900     // There must be no length.
901     if (Length) {
902       Error(StartLoc, "invalid use of length addressing");
903       return MatchOperand_ParseFail;
904     }
905     break;
906   case BDVMem:
907     // We must have Reg1, and it must be a vector register.
908     if (!HaveReg1 || Reg1.Group != RegV) {
909       Error(StartLoc, "vector index required in address");
910       return MatchOperand_ParseFail;
911     }
912     Index = SystemZMC::VR128Regs[Reg1.Num];
913     // If we have Reg2, it must be an address register.
914     if (HaveReg2) {
915       if (parseAddressRegister(Reg2))
916         return MatchOperand_ParseFail;
917       Base = Regs[Reg2.Num];
918     }
919     // There must be no length.
920     if (Length) {
921       Error(StartLoc, "invalid use of length addressing");
922       return MatchOperand_ParseFail;
923     }
924     break;
925   }
926 
927   SMLoc EndLoc =
928     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
929   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
930                                                Index, Length, LengthReg,
931                                                StartLoc, EndLoc));
932   return MatchOperand_Success;
933 }
934 
935 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
936   StringRef IDVal = DirectiveID.getIdentifier();
937 
938   if (IDVal == ".insn")
939     return ParseDirectiveInsn(DirectiveID.getLoc());
940 
941   return true;
942 }
943 
944 /// ParseDirectiveInsn
945 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
946 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
947   MCAsmParser &Parser = getParser();
948 
949   // Expect instruction format as identifier.
950   StringRef Format;
951   SMLoc ErrorLoc = Parser.getTok().getLoc();
952   if (Parser.parseIdentifier(Format))
953     return Error(ErrorLoc, "expected instruction format");
954 
955   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
956 
957   // Find entry for this format in InsnMatchTable.
958   auto EntryRange =
959     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
960                      Format, CompareInsn());
961 
962   // If first == second, couldn't find a match in the table.
963   if (EntryRange.first == EntryRange.second)
964     return Error(ErrorLoc, "unrecognized format");
965 
966   struct InsnMatchEntry *Entry = EntryRange.first;
967 
968   // Format should match from equal_range.
969   assert(Entry->Format == Format);
970 
971   // Parse the following operands using the table's information.
972   for (int i = 0; i < Entry->NumOperands; i++) {
973     MatchClassKind Kind = Entry->OperandKinds[i];
974 
975     SMLoc StartLoc = Parser.getTok().getLoc();
976 
977     // Always expect commas as separators for operands.
978     if (getLexer().isNot(AsmToken::Comma))
979       return Error(StartLoc, "unexpected token in directive");
980     Lex();
981 
982     // Parse operands.
983     OperandMatchResultTy ResTy;
984     if (Kind == MCK_AnyReg)
985       ResTy = parseAnyReg(Operands);
986     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
987       ResTy = parseBDXAddr64(Operands);
988     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
989       ResTy = parseBDAddr64(Operands);
990     else if (Kind == MCK_PCRel32)
991       ResTy = parsePCRel32(Operands);
992     else if (Kind == MCK_PCRel16)
993       ResTy = parsePCRel16(Operands);
994     else {
995       // Only remaining operand kind is an immediate.
996       const MCExpr *Expr;
997       SMLoc StartLoc = Parser.getTok().getLoc();
998 
999       // Expect immediate expression.
1000       if (Parser.parseExpression(Expr))
1001         return Error(StartLoc, "unexpected token in directive");
1002 
1003       SMLoc EndLoc =
1004         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1005 
1006       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1007       ResTy = MatchOperand_Success;
1008     }
1009 
1010     if (ResTy != MatchOperand_Success)
1011       return true;
1012   }
1013 
1014   // Build the instruction with the parsed operands.
1015   MCInst Inst = MCInstBuilder(Entry->Opcode);
1016 
1017   for (size_t i = 0; i < Operands.size(); i++) {
1018     MCParsedAsmOperand &Operand = *Operands[i];
1019     MatchClassKind Kind = Entry->OperandKinds[i];
1020 
1021     // Verify operand.
1022     unsigned Res = validateOperandClass(Operand, Kind);
1023     if (Res != Match_Success)
1024       return Error(Operand.getStartLoc(), "unexpected operand type");
1025 
1026     // Add operands to instruction.
1027     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1028     if (ZOperand.isReg())
1029       ZOperand.addRegOperands(Inst, 1);
1030     else if (ZOperand.isMem(BDMem))
1031       ZOperand.addBDAddrOperands(Inst, 2);
1032     else if (ZOperand.isMem(BDXMem))
1033       ZOperand.addBDXAddrOperands(Inst, 3);
1034     else if (ZOperand.isImm())
1035       ZOperand.addImmOperands(Inst, 1);
1036     else
1037       llvm_unreachable("unexpected operand type");
1038   }
1039 
1040   // Emit as a regular instruction.
1041   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1042 
1043   return false;
1044 }
1045 
1046 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1047                                      SMLoc &EndLoc) {
1048   Register Reg;
1049   if (parseRegister(Reg))
1050     return true;
1051   if (Reg.Group == RegGR)
1052     RegNo = SystemZMC::GR64Regs[Reg.Num];
1053   else if (Reg.Group == RegFP)
1054     RegNo = SystemZMC::FP64Regs[Reg.Num];
1055   else if (Reg.Group == RegV)
1056     RegNo = SystemZMC::VR128Regs[Reg.Num];
1057   else if (Reg.Group == RegAR)
1058     RegNo = SystemZMC::AR32Regs[Reg.Num];
1059   StartLoc = Reg.StartLoc;
1060   EndLoc = Reg.EndLoc;
1061   return false;
1062 }
1063 
1064 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1065                                         StringRef Name, SMLoc NameLoc,
1066                                         OperandVector &Operands) {
1067   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1068 
1069   // Read the remaining operands.
1070   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1071     // Read the first operand.
1072     if (parseOperand(Operands, Name)) {
1073       return true;
1074     }
1075 
1076     // Read any subsequent operands.
1077     while (getLexer().is(AsmToken::Comma)) {
1078       Parser.Lex();
1079       if (parseOperand(Operands, Name)) {
1080         return true;
1081       }
1082     }
1083     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1084       SMLoc Loc = getLexer().getLoc();
1085       return Error(Loc, "unexpected token in argument list");
1086     }
1087   }
1088 
1089   // Consume the EndOfStatement.
1090   Parser.Lex();
1091   return false;
1092 }
1093 
1094 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1095                                     StringRef Mnemonic) {
1096   // Check if the current operand has a custom associated parser, if so, try to
1097   // custom parse the operand, or fallback to the general approach.  Force all
1098   // features to be available during the operand check, or else we will fail to
1099   // find the custom parser, and then we will later get an InvalidOperand error
1100   // instead of a MissingFeature errror.
1101   uint64_t AvailableFeatures = getAvailableFeatures();
1102   setAvailableFeatures(~(uint64_t)0);
1103   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1104   setAvailableFeatures(AvailableFeatures);
1105   if (ResTy == MatchOperand_Success)
1106     return false;
1107 
1108   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1109   // there was a match, but an error occurred, in which case, just return that
1110   // the operand parsing failed.
1111   if (ResTy == MatchOperand_ParseFail)
1112     return true;
1113 
1114   // Check for a register.  All real register operands should have used
1115   // a context-dependent parse routine, which gives the required register
1116   // class.  The code is here to mop up other cases, like those where
1117   // the instruction isn't recognized.
1118   if (Parser.getTok().is(AsmToken::Percent)) {
1119     Register Reg;
1120     if (parseRegister(Reg))
1121       return true;
1122     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1123     return false;
1124   }
1125 
1126   // The only other type of operand is an immediate or address.  As above,
1127   // real address operands should have used a context-dependent parse routine,
1128   // so we treat any plain expression as an immediate.
1129   SMLoc StartLoc = Parser.getTok().getLoc();
1130   Register Reg1, Reg2;
1131   bool HaveReg1, HaveReg2;
1132   const MCExpr *Expr;
1133   const MCExpr *Length;
1134   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1135     return true;
1136   // If the register combination is not valid for any instruction, reject it.
1137   // Otherwise, fall back to reporting an unrecognized instruction.
1138   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1139       && parseAddressRegister(Reg1))
1140     return true;
1141   if (HaveReg2 && parseAddressRegister(Reg2))
1142     return true;
1143 
1144   SMLoc EndLoc =
1145     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1146   if (HaveReg1 || HaveReg2 || Length)
1147     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1148   else
1149     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1150   return false;
1151 }
1152 
1153 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1154                                                OperandVector &Operands,
1155                                                MCStreamer &Out,
1156                                                uint64_t &ErrorInfo,
1157                                                bool MatchingInlineAsm) {
1158   MCInst Inst;
1159   unsigned MatchResult;
1160 
1161   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1162                                      MatchingInlineAsm);
1163   switch (MatchResult) {
1164   case Match_Success:
1165     Inst.setLoc(IDLoc);
1166     Out.EmitInstruction(Inst, getSTI());
1167     return false;
1168 
1169   case Match_MissingFeature: {
1170     assert(ErrorInfo && "Unknown missing feature!");
1171     // Special case the error message for the very common case where only
1172     // a single subtarget feature is missing
1173     std::string Msg = "instruction requires:";
1174     uint64_t Mask = 1;
1175     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1176       if (ErrorInfo & Mask) {
1177         Msg += " ";
1178         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1179       }
1180       Mask <<= 1;
1181     }
1182     return Error(IDLoc, Msg);
1183   }
1184 
1185   case Match_InvalidOperand: {
1186     SMLoc ErrorLoc = IDLoc;
1187     if (ErrorInfo != ~0ULL) {
1188       if (ErrorInfo >= Operands.size())
1189         return Error(IDLoc, "too few operands for instruction");
1190 
1191       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1192       if (ErrorLoc == SMLoc())
1193         ErrorLoc = IDLoc;
1194     }
1195     return Error(ErrorLoc, "invalid operand for instruction");
1196   }
1197 
1198   case Match_MnemonicFail:
1199     return Error(IDLoc, "invalid instruction");
1200   }
1201 
1202   llvm_unreachable("Unexpected match type");
1203 }
1204 
1205 OperandMatchResultTy
1206 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1207                              int64_t MaxVal, bool AllowTLS) {
1208   MCContext &Ctx = getContext();
1209   MCStreamer &Out = getStreamer();
1210   const MCExpr *Expr;
1211   SMLoc StartLoc = Parser.getTok().getLoc();
1212   if (getParser().parseExpression(Expr))
1213     return MatchOperand_NoMatch;
1214 
1215   // For consistency with the GNU assembler, treat immediates as offsets
1216   // from ".".
1217   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1218     int64_t Value = CE->getValue();
1219     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1220       Error(StartLoc, "offset out of range");
1221       return MatchOperand_ParseFail;
1222     }
1223     MCSymbol *Sym = Ctx.createTempSymbol();
1224     Out.EmitLabel(Sym);
1225     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1226                                                  Ctx);
1227     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1228   }
1229 
1230   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1231   const MCExpr *Sym = nullptr;
1232   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1233     Parser.Lex();
1234 
1235     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1236       Error(Parser.getTok().getLoc(), "unexpected token");
1237       return MatchOperand_ParseFail;
1238     }
1239 
1240     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1241     StringRef Name = Parser.getTok().getString();
1242     if (Name == "tls_gdcall")
1243       Kind = MCSymbolRefExpr::VK_TLSGD;
1244     else if (Name == "tls_ldcall")
1245       Kind = MCSymbolRefExpr::VK_TLSLDM;
1246     else {
1247       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1248       return MatchOperand_ParseFail;
1249     }
1250     Parser.Lex();
1251 
1252     if (Parser.getTok().isNot(AsmToken::Colon)) {
1253       Error(Parser.getTok().getLoc(), "unexpected token");
1254       return MatchOperand_ParseFail;
1255     }
1256     Parser.Lex();
1257 
1258     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1259       Error(Parser.getTok().getLoc(), "unexpected token");
1260       return MatchOperand_ParseFail;
1261     }
1262 
1263     StringRef Identifier = Parser.getTok().getString();
1264     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1265                                   Kind, Ctx);
1266     Parser.Lex();
1267   }
1268 
1269   SMLoc EndLoc =
1270     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1271 
1272   if (AllowTLS)
1273     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1274                                                     StartLoc, EndLoc));
1275   else
1276     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1277 
1278   return MatchOperand_Success;
1279 }
1280 
1281 // Force static initialization.
1282 extern "C" void LLVMInitializeSystemZAsmParser() {
1283   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1284 }
1285