1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
26     int64_t Value = CE->getValue();
27     return Value >= MinValue && Value <= MaxValue;
28   }
29   return false;
30 }
31 
32 namespace {
33 enum RegisterKind {
34   GR32Reg,
35   GRH32Reg,
36   GR64Reg,
37   GR128Reg,
38   ADDR32Reg,
39   ADDR64Reg,
40   FP32Reg,
41   FP64Reg,
42   FP128Reg
43 };
44 
45 enum MemoryKind {
46   BDMem,
47   BDXMem,
48   BDLMem
49 };
50 
51 class SystemZOperand : public MCParsedAsmOperand {
52 public:
53 private:
54   enum OperandKind {
55     KindInvalid,
56     KindToken,
57     KindReg,
58     KindAccessReg,
59     KindImm,
60     KindImmTLS,
61     KindMem
62   };
63 
64   OperandKind Kind;
65   SMLoc StartLoc, EndLoc;
66 
67   // A string of length Length, starting at Data.
68   struct TokenOp {
69     const char *Data;
70     unsigned Length;
71   };
72 
73   // LLVM register Num, which has kind Kind.  In some ways it might be
74   // easier for this class to have a register bank (general, floating-point
75   // or access) and a raw register number (0-15).  This would postpone the
76   // interpretation of the operand to the add*() methods and avoid the need
77   // for context-dependent parsing.  However, we do things the current way
78   // because of the virtual getReg() method, which needs to distinguish
79   // between (say) %r0 used as a single register and %r0 used as a pair.
80   // Context-dependent parsing can also give us slightly better error
81   // messages when invalid pairs like %r1 are used.
82   struct RegOp {
83     RegisterKind Kind;
84     unsigned Num;
85   };
86 
87   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
88   // MemKind says what type of memory this is and RegKind says what type
89   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
90   // length for D(L,B)-style operands, otherwise it is null.
91   struct MemOp {
92     unsigned Base : 8;
93     unsigned Index : 8;
94     unsigned MemKind : 8;
95     unsigned RegKind : 8;
96     const MCExpr *Disp;
97     const MCExpr *Length;
98   };
99 
100   // Imm is an immediate operand, and Sym is an optional TLS symbol
101   // for use with a __tls_get_offset marker relocation.
102   struct ImmTLSOp {
103     const MCExpr *Imm;
104     const MCExpr *Sym;
105   };
106 
107   union {
108     TokenOp Token;
109     RegOp Reg;
110     unsigned AccessReg;
111     const MCExpr *Imm;
112     ImmTLSOp ImmTLS;
113     MemOp Mem;
114   };
115 
116   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
117     // Add as immediates when possible.  Null MCExpr = 0.
118     if (!Expr)
119       Inst.addOperand(MCOperand::CreateImm(0));
120     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
121       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
122     else
123       Inst.addOperand(MCOperand::CreateExpr(Expr));
124   }
125 
126 public:
127   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
128       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
129 
130   // Create particular kinds of operand.
131   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
132                                                        SMLoc EndLoc) {
133     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
134   }
135   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
136     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
137     Op->Token.Data = Str.data();
138     Op->Token.Length = Str.size();
139     return Op;
140   }
141   static std::unique_ptr<SystemZOperand>
142   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
143     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
144     Op->Reg.Kind = Kind;
145     Op->Reg.Num = Num;
146     return Op;
147   }
148   static std::unique_ptr<SystemZOperand>
149   createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
150     auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
151     Op->AccessReg = Num;
152     return Op;
153   }
154   static std::unique_ptr<SystemZOperand>
155   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
156     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
157     Op->Imm = Expr;
158     return Op;
159   }
160   static std::unique_ptr<SystemZOperand>
161   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
162             const MCExpr *Disp, unsigned Index, const MCExpr *Length,
163             SMLoc StartLoc, SMLoc EndLoc) {
164     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
165     Op->Mem.MemKind = MemKind;
166     Op->Mem.RegKind = RegKind;
167     Op->Mem.Base = Base;
168     Op->Mem.Index = Index;
169     Op->Mem.Disp = Disp;
170     Op->Mem.Length = Length;
171     return Op;
172   }
173   static std::unique_ptr<SystemZOperand>
174   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
175                SMLoc StartLoc, SMLoc EndLoc) {
176     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
177     Op->ImmTLS.Imm = Imm;
178     Op->ImmTLS.Sym = Sym;
179     return Op;
180   }
181 
182   // Token operands
183   bool isToken() const override {
184     return Kind == KindToken;
185   }
186   StringRef getToken() const {
187     assert(Kind == KindToken && "Not a token");
188     return StringRef(Token.Data, Token.Length);
189   }
190 
191   // Register operands.
192   bool isReg() const override {
193     return Kind == KindReg;
194   }
195   bool isReg(RegisterKind RegKind) const {
196     return Kind == KindReg && Reg.Kind == RegKind;
197   }
198   unsigned getReg() const override {
199     assert(Kind == KindReg && "Not a register");
200     return Reg.Num;
201   }
202 
203   // Access register operands.  Access registers aren't exposed to LLVM
204   // as registers.
205   bool isAccessReg() const {
206     return Kind == KindAccessReg;
207   }
208 
209   // Immediate operands.
210   bool isImm() const override {
211     return Kind == KindImm;
212   }
213   bool isImm(int64_t MinValue, int64_t MaxValue) const {
214     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
215   }
216   const MCExpr *getImm() const {
217     assert(Kind == KindImm && "Not an immediate");
218     return Imm;
219   }
220 
221   // Immediate operands with optional TLS symbol.
222   bool isImmTLS() const {
223     return Kind == KindImmTLS;
224   }
225 
226   // Memory operands.
227   bool isMem() const override {
228     return Kind == KindMem;
229   }
230   bool isMem(MemoryKind MemKind) const {
231     return (Kind == KindMem &&
232             (Mem.MemKind == MemKind ||
233              // A BDMem can be treated as a BDXMem in which the index
234              // register field is 0.
235              (Mem.MemKind == BDMem && MemKind == BDXMem)));
236   }
237   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
238     return isMem(MemKind) && Mem.RegKind == RegKind;
239   }
240   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
241     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
242   }
243   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
244     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
245   }
246   bool isMemDisp12Len8(RegisterKind RegKind) const {
247     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
248   }
249 
250   // Override MCParsedAsmOperand.
251   SMLoc getStartLoc() const override { return StartLoc; }
252   SMLoc getEndLoc() const override { return EndLoc; }
253   void print(raw_ostream &OS) const override;
254 
255   // Used by the TableGen code to add particular types of operand
256   // to an instruction.
257   void addRegOperands(MCInst &Inst, unsigned N) const {
258     assert(N == 1 && "Invalid number of operands");
259     Inst.addOperand(MCOperand::CreateReg(getReg()));
260   }
261   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
262     assert(N == 1 && "Invalid number of operands");
263     assert(Kind == KindAccessReg && "Invalid operand type");
264     Inst.addOperand(MCOperand::CreateImm(AccessReg));
265   }
266   void addImmOperands(MCInst &Inst, unsigned N) const {
267     assert(N == 1 && "Invalid number of operands");
268     addExpr(Inst, getImm());
269   }
270   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
271     assert(N == 2 && "Invalid number of operands");
272     assert(isMem(BDMem) && "Invalid operand type");
273     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
274     addExpr(Inst, Mem.Disp);
275   }
276   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
277     assert(N == 3 && "Invalid number of operands");
278     assert(isMem(BDXMem) && "Invalid operand type");
279     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
280     addExpr(Inst, Mem.Disp);
281     Inst.addOperand(MCOperand::CreateReg(Mem.Index));
282   }
283   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
284     assert(N == 3 && "Invalid number of operands");
285     assert(isMem(BDLMem) && "Invalid operand type");
286     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
287     addExpr(Inst, Mem.Disp);
288     addExpr(Inst, Mem.Length);
289   }
290   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
291     assert(N == 2 && "Invalid number of operands");
292     assert(Kind == KindImmTLS && "Invalid operand type");
293     addExpr(Inst, ImmTLS.Imm);
294     if (ImmTLS.Sym)
295       addExpr(Inst, ImmTLS.Sym);
296   }
297 
298   // Used by the TableGen code to check for particular operand types.
299   bool isGR32() const { return isReg(GR32Reg); }
300   bool isGRH32() const { return isReg(GRH32Reg); }
301   bool isGRX32() const { return false; }
302   bool isGR64() const { return isReg(GR64Reg); }
303   bool isGR128() const { return isReg(GR128Reg); }
304   bool isADDR32() const { return isReg(ADDR32Reg); }
305   bool isADDR64() const { return isReg(ADDR64Reg); }
306   bool isADDR128() const { return false; }
307   bool isFP32() const { return isReg(FP32Reg); }
308   bool isFP64() const { return isReg(FP64Reg); }
309   bool isFP128() const { return isReg(FP128Reg); }
310   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
311   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
312   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
313   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
314   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
315   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
316   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
317   bool isU4Imm() const { return isImm(0, 15); }
318   bool isU6Imm() const { return isImm(0, 63); }
319   bool isU8Imm() const { return isImm(0, 255); }
320   bool isS8Imm() const { return isImm(-128, 127); }
321   bool isU16Imm() const { return isImm(0, 65535); }
322   bool isS16Imm() const { return isImm(-32768, 32767); }
323   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
324   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
325 };
326 
327 class SystemZAsmParser : public MCTargetAsmParser {
328 #define GET_ASSEMBLER_HEADER
329 #include "SystemZGenAsmMatcher.inc"
330 
331 private:
332   MCSubtargetInfo &STI;
333   MCAsmParser &Parser;
334   enum RegisterGroup {
335     RegGR,
336     RegFP,
337     RegAccess
338   };
339   struct Register {
340     RegisterGroup Group;
341     unsigned Num;
342     SMLoc StartLoc, EndLoc;
343   };
344 
345   bool parseRegister(Register &Reg);
346 
347   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
348                      bool IsAddress = false);
349 
350   OperandMatchResultTy parseRegister(OperandVector &Operands,
351                                      RegisterGroup Group, const unsigned *Regs,
352                                      RegisterKind Kind);
353 
354   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
355                     unsigned &Index, const MCExpr *&Length,
356                     const unsigned *Regs, RegisterKind RegKind);
357 
358   OperandMatchResultTy parseAddress(OperandVector &Operands,
359                                     MemoryKind MemKind, const unsigned *Regs,
360                                     RegisterKind RegKind);
361 
362   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
363                                   int64_t MaxVal, bool AllowTLS);
364 
365   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
366 
367 public:
368   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
369                    const MCInstrInfo &MII,
370                    const MCTargetOptions &Options)
371       : MCTargetAsmParser(), STI(sti), Parser(parser) {
372     MCAsmParserExtension::Initialize(Parser);
373 
374     // Initialize the set of available features.
375     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
376   }
377 
378   // Override MCTargetAsmParser.
379   bool ParseDirective(AsmToken DirectiveID) override;
380   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
381   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
382                         SMLoc NameLoc, OperandVector &Operands) override;
383   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
384                                OperandVector &Operands, MCStreamer &Out,
385                                uint64_t &ErrorInfo,
386                                bool MatchingInlineAsm) override;
387 
388   // Used by the TableGen code to parse particular operand types.
389   OperandMatchResultTy parseGR32(OperandVector &Operands) {
390     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
391   }
392   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
393     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
394   }
395   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
396     llvm_unreachable("GRX32 should only be used for pseudo instructions");
397   }
398   OperandMatchResultTy parseGR64(OperandVector &Operands) {
399     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
400   }
401   OperandMatchResultTy parseGR128(OperandVector &Operands) {
402     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
403   }
404   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
405     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
406   }
407   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
408     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
409   }
410   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
411     llvm_unreachable("Shouldn't be used as an operand");
412   }
413   OperandMatchResultTy parseFP32(OperandVector &Operands) {
414     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
415   }
416   OperandMatchResultTy parseFP64(OperandVector &Operands) {
417     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
418   }
419   OperandMatchResultTy parseFP128(OperandVector &Operands) {
420     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
421   }
422   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
423     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
424   }
425   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
426     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
427   }
428   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
429     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
430   }
431   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
432     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
433   }
434   OperandMatchResultTy parseAccessReg(OperandVector &Operands);
435   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
436     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
437   }
438   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
439     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
440   }
441   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
442     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
443   }
444   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
445     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
446   }
447 };
448 } // end anonymous namespace
449 
450 #define GET_REGISTER_MATCHER
451 #define GET_SUBTARGET_FEATURE_NAME
452 #define GET_MATCHER_IMPLEMENTATION
453 #include "SystemZGenAsmMatcher.inc"
454 
455 void SystemZOperand::print(raw_ostream &OS) const {
456   llvm_unreachable("Not implemented");
457 }
458 
459 // Parse one register of the form %<prefix><number>.
460 bool SystemZAsmParser::parseRegister(Register &Reg) {
461   Reg.StartLoc = Parser.getTok().getLoc();
462 
463   // Eat the % prefix.
464   if (Parser.getTok().isNot(AsmToken::Percent))
465     return Error(Parser.getTok().getLoc(), "register expected");
466   Parser.Lex();
467 
468   // Expect a register name.
469   if (Parser.getTok().isNot(AsmToken::Identifier))
470     return Error(Reg.StartLoc, "invalid register");
471 
472   // Check that there's a prefix.
473   StringRef Name = Parser.getTok().getString();
474   if (Name.size() < 2)
475     return Error(Reg.StartLoc, "invalid register");
476   char Prefix = Name[0];
477 
478   // Treat the rest of the register name as a register number.
479   if (Name.substr(1).getAsInteger(10, Reg.Num))
480     return Error(Reg.StartLoc, "invalid register");
481 
482   // Look for valid combinations of prefix and number.
483   if (Prefix == 'r' && Reg.Num < 16)
484     Reg.Group = RegGR;
485   else if (Prefix == 'f' && Reg.Num < 16)
486     Reg.Group = RegFP;
487   else if (Prefix == 'a' && Reg.Num < 16)
488     Reg.Group = RegAccess;
489   else
490     return Error(Reg.StartLoc, "invalid register");
491 
492   Reg.EndLoc = Parser.getTok().getLoc();
493   Parser.Lex();
494   return false;
495 }
496 
497 // Parse a register of group Group.  If Regs is nonnull, use it to map
498 // the raw register number to LLVM numbering, with zero entries indicating
499 // an invalid register.  IsAddress says whether the register appears in an
500 // address context.
501 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
502                                      const unsigned *Regs, bool IsAddress) {
503   if (parseRegister(Reg))
504     return true;
505   if (Reg.Group != Group)
506     return Error(Reg.StartLoc, "invalid operand for instruction");
507   if (Regs && Regs[Reg.Num] == 0)
508     return Error(Reg.StartLoc, "invalid register pair");
509   if (Reg.Num == 0 && IsAddress)
510     return Error(Reg.StartLoc, "%r0 used in an address");
511   if (Regs)
512     Reg.Num = Regs[Reg.Num];
513   return false;
514 }
515 
516 // Parse a register and add it to Operands.  The other arguments are as above.
517 SystemZAsmParser::OperandMatchResultTy
518 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
519                                 const unsigned *Regs, RegisterKind Kind) {
520   if (Parser.getTok().isNot(AsmToken::Percent))
521     return MatchOperand_NoMatch;
522 
523   Register Reg;
524   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
525   if (parseRegister(Reg, Group, Regs, IsAddress))
526     return MatchOperand_ParseFail;
527 
528   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
529                                                Reg.StartLoc, Reg.EndLoc));
530   return MatchOperand_Success;
531 }
532 
533 // Parse a memory operand into Base, Disp, Index and Length.
534 // Regs maps asm register numbers to LLVM register numbers and RegKind
535 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
536 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
537                                     unsigned &Index, const MCExpr *&Length,
538                                     const unsigned *Regs,
539                                     RegisterKind RegKind) {
540   // Parse the displacement, which must always be present.
541   if (getParser().parseExpression(Disp))
542     return true;
543 
544   // Parse the optional base and index.
545   Index = 0;
546   Base = 0;
547   Length = nullptr;
548   if (getLexer().is(AsmToken::LParen)) {
549     Parser.Lex();
550 
551     if (getLexer().is(AsmToken::Percent)) {
552       // Parse the first register and decide whether it's a base or an index.
553       Register Reg;
554       if (parseRegister(Reg, RegGR, Regs, RegKind))
555         return true;
556       if (getLexer().is(AsmToken::Comma))
557         Index = Reg.Num;
558       else
559         Base = Reg.Num;
560     } else {
561       // Parse the length.
562       if (getParser().parseExpression(Length))
563         return true;
564     }
565 
566     // Check whether there's a second register.  It's the base if so.
567     if (getLexer().is(AsmToken::Comma)) {
568       Parser.Lex();
569       Register Reg;
570       if (parseRegister(Reg, RegGR, Regs, RegKind))
571         return true;
572       Base = Reg.Num;
573     }
574 
575     // Consume the closing bracket.
576     if (getLexer().isNot(AsmToken::RParen))
577       return Error(Parser.getTok().getLoc(), "unexpected token in address");
578     Parser.Lex();
579   }
580   return false;
581 }
582 
583 // Parse a memory operand and add it to Operands.  The other arguments
584 // are as above.
585 SystemZAsmParser::OperandMatchResultTy
586 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
587                                const unsigned *Regs, RegisterKind RegKind) {
588   SMLoc StartLoc = Parser.getTok().getLoc();
589   unsigned Base, Index;
590   const MCExpr *Disp;
591   const MCExpr *Length;
592   if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
593     return MatchOperand_ParseFail;
594 
595   if (Index && MemKind != BDXMem)
596     {
597       Error(StartLoc, "invalid use of indexed addressing");
598       return MatchOperand_ParseFail;
599     }
600 
601   if (Length && MemKind != BDLMem)
602     {
603       Error(StartLoc, "invalid use of length addressing");
604       return MatchOperand_ParseFail;
605     }
606 
607   if (!Length && MemKind == BDLMem)
608     {
609       Error(StartLoc, "missing length in address");
610       return MatchOperand_ParseFail;
611     }
612 
613   SMLoc EndLoc =
614     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
615   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
616                                                Index, Length, StartLoc,
617                                                EndLoc));
618   return MatchOperand_Success;
619 }
620 
621 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
622   return true;
623 }
624 
625 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
626                                      SMLoc &EndLoc) {
627   Register Reg;
628   if (parseRegister(Reg))
629     return true;
630   if (Reg.Group == RegGR)
631     RegNo = SystemZMC::GR64Regs[Reg.Num];
632   else if (Reg.Group == RegFP)
633     RegNo = SystemZMC::FP64Regs[Reg.Num];
634   else
635     // FIXME: Access registers aren't modelled as LLVM registers yet.
636     return Error(Reg.StartLoc, "invalid operand for instruction");
637   StartLoc = Reg.StartLoc;
638   EndLoc = Reg.EndLoc;
639   return false;
640 }
641 
642 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
643                                         StringRef Name, SMLoc NameLoc,
644                                         OperandVector &Operands) {
645   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
646 
647   // Read the remaining operands.
648   if (getLexer().isNot(AsmToken::EndOfStatement)) {
649     // Read the first operand.
650     if (parseOperand(Operands, Name)) {
651       Parser.eatToEndOfStatement();
652       return true;
653     }
654 
655     // Read any subsequent operands.
656     while (getLexer().is(AsmToken::Comma)) {
657       Parser.Lex();
658       if (parseOperand(Operands, Name)) {
659         Parser.eatToEndOfStatement();
660         return true;
661       }
662     }
663     if (getLexer().isNot(AsmToken::EndOfStatement)) {
664       SMLoc Loc = getLexer().getLoc();
665       Parser.eatToEndOfStatement();
666       return Error(Loc, "unexpected token in argument list");
667     }
668   }
669 
670   // Consume the EndOfStatement.
671   Parser.Lex();
672   return false;
673 }
674 
675 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
676                                     StringRef Mnemonic) {
677   // Check if the current operand has a custom associated parser, if so, try to
678   // custom parse the operand, or fallback to the general approach.
679   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
680   if (ResTy == MatchOperand_Success)
681     return false;
682 
683   // If there wasn't a custom match, try the generic matcher below. Otherwise,
684   // there was a match, but an error occurred, in which case, just return that
685   // the operand parsing failed.
686   if (ResTy == MatchOperand_ParseFail)
687     return true;
688 
689   // Check for a register.  All real register operands should have used
690   // a context-dependent parse routine, which gives the required register
691   // class.  The code is here to mop up other cases, like those where
692   // the instruction isn't recognized.
693   if (Parser.getTok().is(AsmToken::Percent)) {
694     Register Reg;
695     if (parseRegister(Reg))
696       return true;
697     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
698     return false;
699   }
700 
701   // The only other type of operand is an immediate or address.  As above,
702   // real address operands should have used a context-dependent parse routine,
703   // so we treat any plain expression as an immediate.
704   SMLoc StartLoc = Parser.getTok().getLoc();
705   unsigned Base, Index;
706   const MCExpr *Expr, *Length;
707   if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
708     return true;
709 
710   SMLoc EndLoc =
711     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
712   if (Base || Index || Length)
713     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
714   else
715     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
716   return false;
717 }
718 
719 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
720                                                OperandVector &Operands,
721                                                MCStreamer &Out,
722                                                uint64_t &ErrorInfo,
723                                                bool MatchingInlineAsm) {
724   MCInst Inst;
725   unsigned MatchResult;
726 
727   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
728                                      MatchingInlineAsm);
729   switch (MatchResult) {
730   case Match_Success:
731     Inst.setLoc(IDLoc);
732     Out.EmitInstruction(Inst, STI);
733     return false;
734 
735   case Match_MissingFeature: {
736     assert(ErrorInfo && "Unknown missing feature!");
737     // Special case the error message for the very common case where only
738     // a single subtarget feature is missing
739     std::string Msg = "instruction requires:";
740     uint64_t Mask = 1;
741     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
742       if (ErrorInfo & Mask) {
743         Msg += " ";
744         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
745       }
746       Mask <<= 1;
747     }
748     return Error(IDLoc, Msg);
749   }
750 
751   case Match_InvalidOperand: {
752     SMLoc ErrorLoc = IDLoc;
753     if (ErrorInfo != ~0ULL) {
754       if (ErrorInfo >= Operands.size())
755         return Error(IDLoc, "too few operands for instruction");
756 
757       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
758       if (ErrorLoc == SMLoc())
759         ErrorLoc = IDLoc;
760     }
761     return Error(ErrorLoc, "invalid operand for instruction");
762   }
763 
764   case Match_MnemonicFail:
765     return Error(IDLoc, "invalid instruction");
766   }
767 
768   llvm_unreachable("Unexpected match type");
769 }
770 
771 SystemZAsmParser::OperandMatchResultTy
772 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
773   if (Parser.getTok().isNot(AsmToken::Percent))
774     return MatchOperand_NoMatch;
775 
776   Register Reg;
777   if (parseRegister(Reg, RegAccess, nullptr))
778     return MatchOperand_ParseFail;
779 
780   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
781                                                      Reg.StartLoc,
782                                                      Reg.EndLoc));
783   return MatchOperand_Success;
784 }
785 
786 SystemZAsmParser::OperandMatchResultTy
787 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
788                              int64_t MaxVal, bool AllowTLS) {
789   MCContext &Ctx = getContext();
790   MCStreamer &Out = getStreamer();
791   const MCExpr *Expr;
792   SMLoc StartLoc = Parser.getTok().getLoc();
793   if (getParser().parseExpression(Expr))
794     return MatchOperand_NoMatch;
795 
796   // For consistency with the GNU assembler, treat immediates as offsets
797   // from ".".
798   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
799     int64_t Value = CE->getValue();
800     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
801       Error(StartLoc, "offset out of range");
802       return MatchOperand_ParseFail;
803     }
804     MCSymbol *Sym = Ctx.CreateTempSymbol();
805     Out.EmitLabel(Sym);
806     const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
807                                                  Ctx);
808     Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
809   }
810 
811   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
812   const MCExpr *Sym = nullptr;
813   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
814     Parser.Lex();
815 
816     if (Parser.getTok().isNot(AsmToken::Identifier)) {
817       Error(Parser.getTok().getLoc(), "unexpected token");
818       return MatchOperand_ParseFail;
819     }
820 
821     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
822     StringRef Name = Parser.getTok().getString();
823     if (Name == "tls_gdcall")
824       Kind = MCSymbolRefExpr::VK_TLSGD;
825     else if (Name == "tls_ldcall")
826       Kind = MCSymbolRefExpr::VK_TLSLDM;
827     else {
828       Error(Parser.getTok().getLoc(), "unknown TLS tag");
829       return MatchOperand_ParseFail;
830     }
831     Parser.Lex();
832 
833     if (Parser.getTok().isNot(AsmToken::Colon)) {
834       Error(Parser.getTok().getLoc(), "unexpected token");
835       return MatchOperand_ParseFail;
836     }
837     Parser.Lex();
838 
839     if (Parser.getTok().isNot(AsmToken::Identifier)) {
840       Error(Parser.getTok().getLoc(), "unexpected token");
841       return MatchOperand_ParseFail;
842     }
843 
844     StringRef Identifier = Parser.getTok().getString();
845     Sym = MCSymbolRefExpr::Create(Ctx.GetOrCreateSymbol(Identifier),
846                                   Kind, Ctx);
847     Parser.Lex();
848   }
849 
850   SMLoc EndLoc =
851     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
852 
853   if (AllowTLS)
854     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
855                                                     StartLoc, EndLoc));
856   else
857     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
858 
859   return MatchOperand_Success;
860 }
861 
862 // Force static initialization.
863 extern "C" void LLVMInitializeSystemZAsmParser() {
864   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
865 }
866