1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/SMLoc.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstddef>
32 #include <cstdint>
33 #include <iterator>
34 #include <memory>
35 #include <string>
36 
37 using namespace llvm;
38 
39 // Return true if Expr is in the range [MinValue, MaxValue].
40 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
41   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
42     int64_t Value = CE->getValue();
43     return Value >= MinValue && Value <= MaxValue;
44   }
45   return false;
46 }
47 
48 namespace {
49 
50 enum RegisterKind {
51   GR32Reg,
52   GRH32Reg,
53   GR64Reg,
54   GR128Reg,
55   ADDR32Reg,
56   ADDR64Reg,
57   FP32Reg,
58   FP64Reg,
59   FP128Reg,
60   VR32Reg,
61   VR64Reg,
62   VR128Reg,
63   AR32Reg,
64   CR64Reg,
65 };
66 
67 enum MemoryKind {
68   BDMem,
69   BDXMem,
70   BDLMem,
71   BDRMem,
72   BDVMem
73 };
74 
75 class SystemZOperand : public MCParsedAsmOperand {
76 private:
77   enum OperandKind {
78     KindInvalid,
79     KindToken,
80     KindReg,
81     KindImm,
82     KindImmTLS,
83     KindMem
84   };
85 
86   OperandKind Kind;
87   SMLoc StartLoc, EndLoc;
88 
89   // A string of length Length, starting at Data.
90   struct TokenOp {
91     const char *Data;
92     unsigned Length;
93   };
94 
95   // LLVM register Num, which has kind Kind.  In some ways it might be
96   // easier for this class to have a register bank (general, floating-point
97   // or access) and a raw register number (0-15).  This would postpone the
98   // interpretation of the operand to the add*() methods and avoid the need
99   // for context-dependent parsing.  However, we do things the current way
100   // because of the virtual getReg() method, which needs to distinguish
101   // between (say) %r0 used as a single register and %r0 used as a pair.
102   // Context-dependent parsing can also give us slightly better error
103   // messages when invalid pairs like %r1 are used.
104   struct RegOp {
105     RegisterKind Kind;
106     unsigned Num;
107   };
108 
109   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
110   // MemKind says what type of memory this is and RegKind says what type
111   // the base register has (ADDR32Reg or ADDR64Reg).  Length is the operand
112   // length for D(L,B)-style operands, otherwise it is null.
113   struct MemOp {
114     unsigned Base : 12;
115     unsigned Index : 12;
116     unsigned MemKind : 4;
117     unsigned RegKind : 4;
118     const MCExpr *Disp;
119     union {
120       const MCExpr *Imm;
121       unsigned Reg;
122     } Length;
123   };
124 
125   // Imm is an immediate operand, and Sym is an optional TLS symbol
126   // for use with a __tls_get_offset marker relocation.
127   struct ImmTLSOp {
128     const MCExpr *Imm;
129     const MCExpr *Sym;
130   };
131 
132   union {
133     TokenOp Token;
134     RegOp Reg;
135     const MCExpr *Imm;
136     ImmTLSOp ImmTLS;
137     MemOp Mem;
138   };
139 
140   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
141     // Add as immediates when possible.  Null MCExpr = 0.
142     if (!Expr)
143       Inst.addOperand(MCOperand::createImm(0));
144     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
145       Inst.addOperand(MCOperand::createImm(CE->getValue()));
146     else
147       Inst.addOperand(MCOperand::createExpr(Expr));
148   }
149 
150 public:
151   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
152       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
153 
154   // Create particular kinds of operand.
155   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
156                                                        SMLoc EndLoc) {
157     return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
158   }
159 
160   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
161     auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
162     Op->Token.Data = Str.data();
163     Op->Token.Length = Str.size();
164     return Op;
165   }
166 
167   static std::unique_ptr<SystemZOperand>
168   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
169     auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
170     Op->Reg.Kind = Kind;
171     Op->Reg.Num = Num;
172     return Op;
173   }
174 
175   static std::unique_ptr<SystemZOperand>
176   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
177     auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
178     Op->Imm = Expr;
179     return Op;
180   }
181 
182   static std::unique_ptr<SystemZOperand>
183   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
184             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
185             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
186     auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
187     Op->Mem.MemKind = MemKind;
188     Op->Mem.RegKind = RegKind;
189     Op->Mem.Base = Base;
190     Op->Mem.Index = Index;
191     Op->Mem.Disp = Disp;
192     if (MemKind == BDLMem)
193       Op->Mem.Length.Imm = LengthImm;
194     if (MemKind == BDRMem)
195       Op->Mem.Length.Reg = LengthReg;
196     return Op;
197   }
198 
199   static std::unique_ptr<SystemZOperand>
200   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
201                SMLoc StartLoc, SMLoc EndLoc) {
202     auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
203     Op->ImmTLS.Imm = Imm;
204     Op->ImmTLS.Sym = Sym;
205     return Op;
206   }
207 
208   // Token operands
209   bool isToken() const override {
210     return Kind == KindToken;
211   }
212   StringRef getToken() const {
213     assert(Kind == KindToken && "Not a token");
214     return StringRef(Token.Data, Token.Length);
215   }
216 
217   // Register operands.
218   bool isReg() const override {
219     return Kind == KindReg;
220   }
221   bool isReg(RegisterKind RegKind) const {
222     return Kind == KindReg && Reg.Kind == RegKind;
223   }
224   unsigned getReg() const override {
225     assert(Kind == KindReg && "Not a register");
226     return Reg.Num;
227   }
228 
229   // Immediate operands.
230   bool isImm() const override {
231     return Kind == KindImm;
232   }
233   bool isImm(int64_t MinValue, int64_t MaxValue) const {
234     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
235   }
236   const MCExpr *getImm() const {
237     assert(Kind == KindImm && "Not an immediate");
238     return Imm;
239   }
240 
241   // Immediate operands with optional TLS symbol.
242   bool isImmTLS() const {
243     return Kind == KindImmTLS;
244   }
245 
246   // Memory operands.
247   bool isMem() const override {
248     return Kind == KindMem;
249   }
250   bool isMem(MemoryKind MemKind) const {
251     return (Kind == KindMem &&
252             (Mem.MemKind == MemKind ||
253              // A BDMem can be treated as a BDXMem in which the index
254              // register field is 0.
255              (Mem.MemKind == BDMem && MemKind == BDXMem)));
256   }
257   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
258     return isMem(MemKind) && Mem.RegKind == RegKind;
259   }
260   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
261     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
262   }
263   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
264     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
265   }
266   bool isMemDisp12Len4(RegisterKind RegKind) const {
267     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
268   }
269   bool isMemDisp12Len8(RegisterKind RegKind) const {
270     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
271   }
272 
273   // Override MCParsedAsmOperand.
274   SMLoc getStartLoc() const override { return StartLoc; }
275   SMLoc getEndLoc() const override { return EndLoc; }
276   void print(raw_ostream &OS) const override;
277 
278   // Used by the TableGen code to add particular types of operand
279   // to an instruction.
280   void addRegOperands(MCInst &Inst, unsigned N) const {
281     assert(N == 1 && "Invalid number of operands");
282     Inst.addOperand(MCOperand::createReg(getReg()));
283   }
284   void addImmOperands(MCInst &Inst, unsigned N) const {
285     assert(N == 1 && "Invalid number of operands");
286     addExpr(Inst, getImm());
287   }
288   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
289     assert(N == 2 && "Invalid number of operands");
290     assert(isMem(BDMem) && "Invalid operand type");
291     Inst.addOperand(MCOperand::createReg(Mem.Base));
292     addExpr(Inst, Mem.Disp);
293   }
294   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
295     assert(N == 3 && "Invalid number of operands");
296     assert(isMem(BDXMem) && "Invalid operand type");
297     Inst.addOperand(MCOperand::createReg(Mem.Base));
298     addExpr(Inst, Mem.Disp);
299     Inst.addOperand(MCOperand::createReg(Mem.Index));
300   }
301   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
302     assert(N == 3 && "Invalid number of operands");
303     assert(isMem(BDLMem) && "Invalid operand type");
304     Inst.addOperand(MCOperand::createReg(Mem.Base));
305     addExpr(Inst, Mem.Disp);
306     addExpr(Inst, Mem.Length.Imm);
307   }
308   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
309     assert(N == 3 && "Invalid number of operands");
310     assert(isMem(BDRMem) && "Invalid operand type");
311     Inst.addOperand(MCOperand::createReg(Mem.Base));
312     addExpr(Inst, Mem.Disp);
313     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
314   }
315   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
316     assert(N == 3 && "Invalid number of operands");
317     assert(isMem(BDVMem) && "Invalid operand type");
318     Inst.addOperand(MCOperand::createReg(Mem.Base));
319     addExpr(Inst, Mem.Disp);
320     Inst.addOperand(MCOperand::createReg(Mem.Index));
321   }
322   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
323     assert(N == 2 && "Invalid number of operands");
324     assert(Kind == KindImmTLS && "Invalid operand type");
325     addExpr(Inst, ImmTLS.Imm);
326     if (ImmTLS.Sym)
327       addExpr(Inst, ImmTLS.Sym);
328   }
329 
330   // Used by the TableGen code to check for particular operand types.
331   bool isGR32() const { return isReg(GR32Reg); }
332   bool isGRH32() const { return isReg(GRH32Reg); }
333   bool isGRX32() const { return false; }
334   bool isGR64() const { return isReg(GR64Reg); }
335   bool isGR128() const { return isReg(GR128Reg); }
336   bool isADDR32() const { return isReg(ADDR32Reg); }
337   bool isADDR64() const { return isReg(ADDR64Reg); }
338   bool isADDR128() const { return false; }
339   bool isFP32() const { return isReg(FP32Reg); }
340   bool isFP64() const { return isReg(FP64Reg); }
341   bool isFP128() const { return isReg(FP128Reg); }
342   bool isVR32() const { return isReg(VR32Reg); }
343   bool isVR64() const { return isReg(VR64Reg); }
344   bool isVF128() const { return false; }
345   bool isVR128() const { return isReg(VR128Reg); }
346   bool isAR32() const { return isReg(AR32Reg); }
347   bool isCR64() const { return isReg(CR64Reg); }
348   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
349   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
350   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
351   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
352   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
353   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
354   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
355   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
356   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
357   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
358   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
359   bool isU1Imm() const { return isImm(0, 1); }
360   bool isU2Imm() const { return isImm(0, 3); }
361   bool isU3Imm() const { return isImm(0, 7); }
362   bool isU4Imm() const { return isImm(0, 15); }
363   bool isU6Imm() const { return isImm(0, 63); }
364   bool isU8Imm() const { return isImm(0, 255); }
365   bool isS8Imm() const { return isImm(-128, 127); }
366   bool isU12Imm() const { return isImm(0, 4095); }
367   bool isU16Imm() const { return isImm(0, 65535); }
368   bool isS16Imm() const { return isImm(-32768, 32767); }
369   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
370   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
371   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
372 };
373 
374 class SystemZAsmParser : public MCTargetAsmParser {
375 #define GET_ASSEMBLER_HEADER
376 #include "SystemZGenAsmMatcher.inc"
377 
378 private:
379   MCAsmParser &Parser;
380   enum RegisterGroup {
381     RegGR,
382     RegFP,
383     RegV,
384     RegAR,
385     RegCR
386   };
387   struct Register {
388     RegisterGroup Group;
389     unsigned Num;
390     SMLoc StartLoc, EndLoc;
391   };
392 
393   bool parseRegister(Register &Reg);
394 
395   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
396                      bool IsAddress = false);
397 
398   OperandMatchResultTy parseRegister(OperandVector &Operands,
399                                      RegisterGroup Group, const unsigned *Regs,
400                                      RegisterKind Kind);
401 
402   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
403 
404   bool parseAddress(bool &HaveReg1, Register &Reg1,
405                     bool &HaveReg2, Register &Reg2,
406                     const MCExpr *&Disp, const MCExpr *&Length);
407   bool parseAddressRegister(Register &Reg);
408 
409   bool ParseDirectiveInsn(SMLoc L);
410 
411   OperandMatchResultTy parseAddress(OperandVector &Operands,
412                                     MemoryKind MemKind, const unsigned *Regs,
413                                     RegisterKind RegKind);
414 
415   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
416                                   int64_t MaxVal, bool AllowTLS);
417 
418   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
419 
420 public:
421   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
422                    const MCInstrInfo &MII,
423                    const MCTargetOptions &Options)
424     : MCTargetAsmParser(Options, sti), Parser(parser) {
425     MCAsmParserExtension::Initialize(Parser);
426 
427     // Alias the .word directive to .short.
428     parser.addAliasForDirective(".word", ".short");
429 
430     // Initialize the set of available features.
431     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
432   }
433 
434   // Override MCTargetAsmParser.
435   bool ParseDirective(AsmToken DirectiveID) override;
436   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
437   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
438                         SMLoc NameLoc, OperandVector &Operands) override;
439   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
440                                OperandVector &Operands, MCStreamer &Out,
441                                uint64_t &ErrorInfo,
442                                bool MatchingInlineAsm) override;
443 
444   // Used by the TableGen code to parse particular operand types.
445   OperandMatchResultTy parseGR32(OperandVector &Operands) {
446     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
447   }
448   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
449     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
450   }
451   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
452     llvm_unreachable("GRX32 should only be used for pseudo instructions");
453   }
454   OperandMatchResultTy parseGR64(OperandVector &Operands) {
455     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
456   }
457   OperandMatchResultTy parseGR128(OperandVector &Operands) {
458     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
459   }
460   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
461     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
462   }
463   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
464     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
465   }
466   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
467     llvm_unreachable("Shouldn't be used as an operand");
468   }
469   OperandMatchResultTy parseFP32(OperandVector &Operands) {
470     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
471   }
472   OperandMatchResultTy parseFP64(OperandVector &Operands) {
473     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
474   }
475   OperandMatchResultTy parseFP128(OperandVector &Operands) {
476     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
477   }
478   OperandMatchResultTy parseVR32(OperandVector &Operands) {
479     return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
480   }
481   OperandMatchResultTy parseVR64(OperandVector &Operands) {
482     return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
483   }
484   OperandMatchResultTy parseVF128(OperandVector &Operands) {
485     llvm_unreachable("Shouldn't be used as an operand");
486   }
487   OperandMatchResultTy parseVR128(OperandVector &Operands) {
488     return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
489   }
490   OperandMatchResultTy parseAR32(OperandVector &Operands) {
491     return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
492   }
493   OperandMatchResultTy parseCR64(OperandVector &Operands) {
494     return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
495   }
496   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
497     return parseAnyRegister(Operands);
498   }
499   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
500     return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
501   }
502   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
503     return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
504   }
505   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
506     return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
507   }
508   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
509     return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
510   }
511   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
512     return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
513   }
514   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
515     return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
516   }
517   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
518     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
519   }
520   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
521     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
522   }
523   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
524     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
525   }
526   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
527     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
528   }
529   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
530     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
531   }
532   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
533     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
534   }
535 };
536 
537 } // end anonymous namespace
538 
539 #define GET_REGISTER_MATCHER
540 #define GET_SUBTARGET_FEATURE_NAME
541 #define GET_MATCHER_IMPLEMENTATION
542 #include "SystemZGenAsmMatcher.inc"
543 
544 // Used for the .insn directives; contains information needed to parse the
545 // operands in the directive.
546 struct InsnMatchEntry {
547   StringRef Format;
548   uint64_t Opcode;
549   int32_t NumOperands;
550   MatchClassKind OperandKinds[5];
551 };
552 
553 // For equal_range comparison.
554 struct CompareInsn {
555   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
556     return LHS.Format < RHS;
557   }
558   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
559     return LHS < RHS.Format;
560   }
561   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
562     return LHS.Format < RHS.Format;
563   }
564 };
565 
566 // Table initializing information for parsing the .insn directive.
567 static struct InsnMatchEntry InsnMatchTable[] = {
568   /* Format, Opcode, NumOperands, OperandKinds */
569   { "e", SystemZ::InsnE, 1,
570     { MCK_U16Imm } },
571   { "ri", SystemZ::InsnRI, 3,
572     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
573   { "rie", SystemZ::InsnRIE, 4,
574     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
575   { "ril", SystemZ::InsnRIL, 3,
576     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
577   { "rilu", SystemZ::InsnRILU, 3,
578     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
579   { "ris", SystemZ::InsnRIS, 5,
580     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
581   { "rr", SystemZ::InsnRR, 3,
582     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
583   { "rre", SystemZ::InsnRRE, 3,
584     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
585   { "rrf", SystemZ::InsnRRF, 5,
586     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
587   { "rrs", SystemZ::InsnRRS, 5,
588     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
589   { "rs", SystemZ::InsnRS, 4,
590     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
591   { "rse", SystemZ::InsnRSE, 4,
592     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
593   { "rsi", SystemZ::InsnRSI, 4,
594     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
595   { "rsy", SystemZ::InsnRSY, 4,
596     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
597   { "rx", SystemZ::InsnRX, 3,
598     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
599   { "rxe", SystemZ::InsnRXE, 3,
600     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
601   { "rxf", SystemZ::InsnRXF, 4,
602     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
603   { "rxy", SystemZ::InsnRXY, 3,
604     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
605   { "s", SystemZ::InsnS, 2,
606     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
607   { "si", SystemZ::InsnSI, 3,
608     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
609   { "sil", SystemZ::InsnSIL, 3,
610     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
611   { "siy", SystemZ::InsnSIY, 3,
612     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
613   { "ss", SystemZ::InsnSS, 4,
614     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
615   { "sse", SystemZ::InsnSSE, 3,
616     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
617   { "ssf", SystemZ::InsnSSF, 4,
618     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
619 };
620 
621 void SystemZOperand::print(raw_ostream &OS) const {
622   llvm_unreachable("Not implemented");
623 }
624 
625 // Parse one register of the form %<prefix><number>.
626 bool SystemZAsmParser::parseRegister(Register &Reg) {
627   Reg.StartLoc = Parser.getTok().getLoc();
628 
629   // Eat the % prefix.
630   if (Parser.getTok().isNot(AsmToken::Percent))
631     return Error(Parser.getTok().getLoc(), "register expected");
632   Parser.Lex();
633 
634   // Expect a register name.
635   if (Parser.getTok().isNot(AsmToken::Identifier))
636     return Error(Reg.StartLoc, "invalid register");
637 
638   // Check that there's a prefix.
639   StringRef Name = Parser.getTok().getString();
640   if (Name.size() < 2)
641     return Error(Reg.StartLoc, "invalid register");
642   char Prefix = Name[0];
643 
644   // Treat the rest of the register name as a register number.
645   if (Name.substr(1).getAsInteger(10, Reg.Num))
646     return Error(Reg.StartLoc, "invalid register");
647 
648   // Look for valid combinations of prefix and number.
649   if (Prefix == 'r' && Reg.Num < 16)
650     Reg.Group = RegGR;
651   else if (Prefix == 'f' && Reg.Num < 16)
652     Reg.Group = RegFP;
653   else if (Prefix == 'v' && Reg.Num < 32)
654     Reg.Group = RegV;
655   else if (Prefix == 'a' && Reg.Num < 16)
656     Reg.Group = RegAR;
657   else if (Prefix == 'c' && Reg.Num < 16)
658     Reg.Group = RegCR;
659   else
660     return Error(Reg.StartLoc, "invalid register");
661 
662   Reg.EndLoc = Parser.getTok().getLoc();
663   Parser.Lex();
664   return false;
665 }
666 
667 // Parse a register of group Group.  If Regs is nonnull, use it to map
668 // the raw register number to LLVM numbering, with zero entries
669 // indicating an invalid register.  IsAddress says whether the
670 // register appears in an address context. Allow FP Group if expecting
671 // RegV Group, since the f-prefix yields the FP group even while used
672 // with vector instructions.
673 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
674                                      const unsigned *Regs, bool IsAddress) {
675   if (parseRegister(Reg))
676     return true;
677   if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
678     return Error(Reg.StartLoc, "invalid operand for instruction");
679   if (Regs && Regs[Reg.Num] == 0)
680     return Error(Reg.StartLoc, "invalid register pair");
681   if (Reg.Num == 0 && IsAddress)
682     return Error(Reg.StartLoc, "%r0 used in an address");
683   if (Regs)
684     Reg.Num = Regs[Reg.Num];
685   return false;
686 }
687 
688 // Parse a register and add it to Operands.  The other arguments are as above.
689 OperandMatchResultTy
690 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
691                                 const unsigned *Regs, RegisterKind Kind) {
692   if (Parser.getTok().isNot(AsmToken::Percent))
693     return MatchOperand_NoMatch;
694 
695   Register Reg;
696   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
697   if (parseRegister(Reg, Group, Regs, IsAddress))
698     return MatchOperand_ParseFail;
699 
700   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
701                                                Reg.StartLoc, Reg.EndLoc));
702   return MatchOperand_Success;
703 }
704 
705 // Parse any type of register (including integers) and add it to Operands.
706 OperandMatchResultTy
707 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
708   // Handle integer values.
709   if (Parser.getTok().is(AsmToken::Integer)) {
710     const MCExpr *Register;
711     SMLoc StartLoc = Parser.getTok().getLoc();
712     if (Parser.parseExpression(Register))
713       return MatchOperand_ParseFail;
714 
715     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
716       int64_t Value = CE->getValue();
717       if (Value < 0 || Value > 15) {
718         Error(StartLoc, "invalid register");
719         return MatchOperand_ParseFail;
720       }
721     }
722 
723     SMLoc EndLoc =
724       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
725 
726     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
727   }
728   else {
729     Register Reg;
730     if (parseRegister(Reg))
731       return MatchOperand_ParseFail;
732 
733     // Map to the correct register kind.
734     RegisterKind Kind;
735     unsigned RegNo;
736     if (Reg.Group == RegGR) {
737       Kind = GR64Reg;
738       RegNo = SystemZMC::GR64Regs[Reg.Num];
739     }
740     else if (Reg.Group == RegFP) {
741       Kind = FP64Reg;
742       RegNo = SystemZMC::FP64Regs[Reg.Num];
743     }
744     else if (Reg.Group == RegV) {
745       Kind = VR128Reg;
746       RegNo = SystemZMC::VR128Regs[Reg.Num];
747     }
748     else if (Reg.Group == RegAR) {
749       Kind = AR32Reg;
750       RegNo = SystemZMC::AR32Regs[Reg.Num];
751     }
752     else if (Reg.Group == RegCR) {
753       Kind = CR64Reg;
754       RegNo = SystemZMC::CR64Regs[Reg.Num];
755     }
756     else {
757       return MatchOperand_ParseFail;
758     }
759 
760     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
761                                                  Reg.StartLoc, Reg.EndLoc));
762   }
763   return MatchOperand_Success;
764 }
765 
766 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
767 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
768                                     bool &HaveReg2, Register &Reg2,
769                                     const MCExpr *&Disp,
770                                     const MCExpr *&Length) {
771   // Parse the displacement, which must always be present.
772   if (getParser().parseExpression(Disp))
773     return true;
774 
775   // Parse the optional base and index.
776   HaveReg1 = false;
777   HaveReg2 = false;
778   Length = nullptr;
779   if (getLexer().is(AsmToken::LParen)) {
780     Parser.Lex();
781 
782     if (getLexer().is(AsmToken::Percent)) {
783       // Parse the first register.
784       HaveReg1 = true;
785       if (parseRegister(Reg1))
786         return true;
787     } else {
788       // Parse the length.
789       if (getParser().parseExpression(Length))
790         return true;
791     }
792 
793     // Check whether there's a second register.
794     if (getLexer().is(AsmToken::Comma)) {
795       Parser.Lex();
796       HaveReg2 = true;
797       if (parseRegister(Reg2))
798         return true;
799     }
800 
801     // Consume the closing bracket.
802     if (getLexer().isNot(AsmToken::RParen))
803       return Error(Parser.getTok().getLoc(), "unexpected token in address");
804     Parser.Lex();
805   }
806   return false;
807 }
808 
809 // Verify that Reg is a valid address register (base or index).
810 bool
811 SystemZAsmParser::parseAddressRegister(Register &Reg) {
812   if (Reg.Group == RegV) {
813     Error(Reg.StartLoc, "invalid use of vector addressing");
814     return true;
815   } else if (Reg.Group != RegGR) {
816     Error(Reg.StartLoc, "invalid address register");
817     return true;
818   } else if (Reg.Num == 0) {
819     Error(Reg.StartLoc, "%r0 used in an address");
820     return true;
821   }
822   return false;
823 }
824 
825 // Parse a memory operand and add it to Operands.  The other arguments
826 // are as above.
827 OperandMatchResultTy
828 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
829                                const unsigned *Regs, RegisterKind RegKind) {
830   SMLoc StartLoc = Parser.getTok().getLoc();
831   unsigned Base = 0, Index = 0, LengthReg = 0;
832   Register Reg1, Reg2;
833   bool HaveReg1, HaveReg2;
834   const MCExpr *Disp;
835   const MCExpr *Length;
836   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
837     return MatchOperand_ParseFail;
838 
839   switch (MemKind) {
840   case BDMem:
841     // If we have Reg1, it must be an address register.
842     if (HaveReg1) {
843       if (parseAddressRegister(Reg1))
844         return MatchOperand_ParseFail;
845       Base = Regs[Reg1.Num];
846     }
847     // There must be no Reg2 or length.
848     if (Length) {
849       Error(StartLoc, "invalid use of length addressing");
850       return MatchOperand_ParseFail;
851     }
852     if (HaveReg2) {
853       Error(StartLoc, "invalid use of indexed addressing");
854       return MatchOperand_ParseFail;
855     }
856     break;
857   case BDXMem:
858     // If we have Reg1, it must be an address register.
859     if (HaveReg1) {
860       if (parseAddressRegister(Reg1))
861         return MatchOperand_ParseFail;
862       // If the are two registers, the first one is the index and the
863       // second is the base.
864       if (HaveReg2)
865         Index = Regs[Reg1.Num];
866       else
867         Base = Regs[Reg1.Num];
868     }
869     // If we have Reg2, it must be an address register.
870     if (HaveReg2) {
871       if (parseAddressRegister(Reg2))
872         return MatchOperand_ParseFail;
873       Base = Regs[Reg2.Num];
874     }
875     // There must be no length.
876     if (Length) {
877       Error(StartLoc, "invalid use of length addressing");
878       return MatchOperand_ParseFail;
879     }
880     break;
881   case BDLMem:
882     // If we have Reg2, it must be an address register.
883     if (HaveReg2) {
884       if (parseAddressRegister(Reg2))
885         return MatchOperand_ParseFail;
886       Base = Regs[Reg2.Num];
887     }
888     // We cannot support base+index addressing.
889     if (HaveReg1 && HaveReg2) {
890       Error(StartLoc, "invalid use of indexed addressing");
891       return MatchOperand_ParseFail;
892     }
893     // We must have a length.
894     if (!Length) {
895       Error(StartLoc, "missing length in address");
896       return MatchOperand_ParseFail;
897     }
898     break;
899   case BDRMem:
900     // We must have Reg1, and it must be a GPR.
901     if (!HaveReg1 || Reg1.Group != RegGR) {
902       Error(StartLoc, "invalid operand for instruction");
903       return MatchOperand_ParseFail;
904     }
905     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
906     // If we have Reg2, it must be an address register.
907     if (HaveReg2) {
908       if (parseAddressRegister(Reg2))
909         return MatchOperand_ParseFail;
910       Base = Regs[Reg2.Num];
911     }
912     // There must be no length.
913     if (Length) {
914       Error(StartLoc, "invalid use of length addressing");
915       return MatchOperand_ParseFail;
916     }
917     break;
918   case BDVMem:
919     // We must have Reg1, and it must be a vector register.
920     if (!HaveReg1 || Reg1.Group != RegV) {
921       Error(StartLoc, "vector index required in address");
922       return MatchOperand_ParseFail;
923     }
924     Index = SystemZMC::VR128Regs[Reg1.Num];
925     // If we have Reg2, it must be an address register.
926     if (HaveReg2) {
927       if (parseAddressRegister(Reg2))
928         return MatchOperand_ParseFail;
929       Base = Regs[Reg2.Num];
930     }
931     // There must be no length.
932     if (Length) {
933       Error(StartLoc, "invalid use of length addressing");
934       return MatchOperand_ParseFail;
935     }
936     break;
937   }
938 
939   SMLoc EndLoc =
940     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
941   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
942                                                Index, Length, LengthReg,
943                                                StartLoc, EndLoc));
944   return MatchOperand_Success;
945 }
946 
947 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
948   StringRef IDVal = DirectiveID.getIdentifier();
949 
950   if (IDVal == ".insn")
951     return ParseDirectiveInsn(DirectiveID.getLoc());
952 
953   return true;
954 }
955 
956 /// ParseDirectiveInsn
957 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
958 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
959   MCAsmParser &Parser = getParser();
960 
961   // Expect instruction format as identifier.
962   StringRef Format;
963   SMLoc ErrorLoc = Parser.getTok().getLoc();
964   if (Parser.parseIdentifier(Format))
965     return Error(ErrorLoc, "expected instruction format");
966 
967   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
968 
969   // Find entry for this format in InsnMatchTable.
970   auto EntryRange =
971     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
972                      Format, CompareInsn());
973 
974   // If first == second, couldn't find a match in the table.
975   if (EntryRange.first == EntryRange.second)
976     return Error(ErrorLoc, "unrecognized format");
977 
978   struct InsnMatchEntry *Entry = EntryRange.first;
979 
980   // Format should match from equal_range.
981   assert(Entry->Format == Format);
982 
983   // Parse the following operands using the table's information.
984   for (int i = 0; i < Entry->NumOperands; i++) {
985     MatchClassKind Kind = Entry->OperandKinds[i];
986 
987     SMLoc StartLoc = Parser.getTok().getLoc();
988 
989     // Always expect commas as separators for operands.
990     if (getLexer().isNot(AsmToken::Comma))
991       return Error(StartLoc, "unexpected token in directive");
992     Lex();
993 
994     // Parse operands.
995     OperandMatchResultTy ResTy;
996     if (Kind == MCK_AnyReg)
997       ResTy = parseAnyReg(Operands);
998     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
999       ResTy = parseBDXAddr64(Operands);
1000     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1001       ResTy = parseBDAddr64(Operands);
1002     else if (Kind == MCK_PCRel32)
1003       ResTy = parsePCRel32(Operands);
1004     else if (Kind == MCK_PCRel16)
1005       ResTy = parsePCRel16(Operands);
1006     else {
1007       // Only remaining operand kind is an immediate.
1008       const MCExpr *Expr;
1009       SMLoc StartLoc = Parser.getTok().getLoc();
1010 
1011       // Expect immediate expression.
1012       if (Parser.parseExpression(Expr))
1013         return Error(StartLoc, "unexpected token in directive");
1014 
1015       SMLoc EndLoc =
1016         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1017 
1018       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1019       ResTy = MatchOperand_Success;
1020     }
1021 
1022     if (ResTy != MatchOperand_Success)
1023       return true;
1024   }
1025 
1026   // Build the instruction with the parsed operands.
1027   MCInst Inst = MCInstBuilder(Entry->Opcode);
1028 
1029   for (size_t i = 0; i < Operands.size(); i++) {
1030     MCParsedAsmOperand &Operand = *Operands[i];
1031     MatchClassKind Kind = Entry->OperandKinds[i];
1032 
1033     // Verify operand.
1034     unsigned Res = validateOperandClass(Operand, Kind);
1035     if (Res != Match_Success)
1036       return Error(Operand.getStartLoc(), "unexpected operand type");
1037 
1038     // Add operands to instruction.
1039     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1040     if (ZOperand.isReg())
1041       ZOperand.addRegOperands(Inst, 1);
1042     else if (ZOperand.isMem(BDMem))
1043       ZOperand.addBDAddrOperands(Inst, 2);
1044     else if (ZOperand.isMem(BDXMem))
1045       ZOperand.addBDXAddrOperands(Inst, 3);
1046     else if (ZOperand.isImm())
1047       ZOperand.addImmOperands(Inst, 1);
1048     else
1049       llvm_unreachable("unexpected operand type");
1050   }
1051 
1052   // Emit as a regular instruction.
1053   Parser.getStreamer().EmitInstruction(Inst, getSTI());
1054 
1055   return false;
1056 }
1057 
1058 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1059                                      SMLoc &EndLoc) {
1060   Register Reg;
1061   if (parseRegister(Reg))
1062     return true;
1063   if (Reg.Group == RegGR)
1064     RegNo = SystemZMC::GR64Regs[Reg.Num];
1065   else if (Reg.Group == RegFP)
1066     RegNo = SystemZMC::FP64Regs[Reg.Num];
1067   else if (Reg.Group == RegV)
1068     RegNo = SystemZMC::VR128Regs[Reg.Num];
1069   else if (Reg.Group == RegAR)
1070     RegNo = SystemZMC::AR32Regs[Reg.Num];
1071   else if (Reg.Group == RegCR)
1072     RegNo = SystemZMC::CR64Regs[Reg.Num];
1073   StartLoc = Reg.StartLoc;
1074   EndLoc = Reg.EndLoc;
1075   return false;
1076 }
1077 
1078 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1079                                         StringRef Name, SMLoc NameLoc,
1080                                         OperandVector &Operands) {
1081   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1082 
1083   // Read the remaining operands.
1084   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1085     // Read the first operand.
1086     if (parseOperand(Operands, Name)) {
1087       return true;
1088     }
1089 
1090     // Read any subsequent operands.
1091     while (getLexer().is(AsmToken::Comma)) {
1092       Parser.Lex();
1093       if (parseOperand(Operands, Name)) {
1094         return true;
1095       }
1096     }
1097     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1098       SMLoc Loc = getLexer().getLoc();
1099       return Error(Loc, "unexpected token in argument list");
1100     }
1101   }
1102 
1103   // Consume the EndOfStatement.
1104   Parser.Lex();
1105   return false;
1106 }
1107 
1108 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1109                                     StringRef Mnemonic) {
1110   // Check if the current operand has a custom associated parser, if so, try to
1111   // custom parse the operand, or fallback to the general approach.  Force all
1112   // features to be available during the operand check, or else we will fail to
1113   // find the custom parser, and then we will later get an InvalidOperand error
1114   // instead of a MissingFeature errror.
1115   uint64_t AvailableFeatures = getAvailableFeatures();
1116   setAvailableFeatures(~(uint64_t)0);
1117   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1118   setAvailableFeatures(AvailableFeatures);
1119   if (ResTy == MatchOperand_Success)
1120     return false;
1121 
1122   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1123   // there was a match, but an error occurred, in which case, just return that
1124   // the operand parsing failed.
1125   if (ResTy == MatchOperand_ParseFail)
1126     return true;
1127 
1128   // Check for a register.  All real register operands should have used
1129   // a context-dependent parse routine, which gives the required register
1130   // class.  The code is here to mop up other cases, like those where
1131   // the instruction isn't recognized.
1132   if (Parser.getTok().is(AsmToken::Percent)) {
1133     Register Reg;
1134     if (parseRegister(Reg))
1135       return true;
1136     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1137     return false;
1138   }
1139 
1140   // The only other type of operand is an immediate or address.  As above,
1141   // real address operands should have used a context-dependent parse routine,
1142   // so we treat any plain expression as an immediate.
1143   SMLoc StartLoc = Parser.getTok().getLoc();
1144   Register Reg1, Reg2;
1145   bool HaveReg1, HaveReg2;
1146   const MCExpr *Expr;
1147   const MCExpr *Length;
1148   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1149     return true;
1150   // If the register combination is not valid for any instruction, reject it.
1151   // Otherwise, fall back to reporting an unrecognized instruction.
1152   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1153       && parseAddressRegister(Reg1))
1154     return true;
1155   if (HaveReg2 && parseAddressRegister(Reg2))
1156     return true;
1157 
1158   SMLoc EndLoc =
1159     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1160   if (HaveReg1 || HaveReg2 || Length)
1161     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1162   else
1163     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1164   return false;
1165 }
1166 
1167 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1168                                                OperandVector &Operands,
1169                                                MCStreamer &Out,
1170                                                uint64_t &ErrorInfo,
1171                                                bool MatchingInlineAsm) {
1172   MCInst Inst;
1173   unsigned MatchResult;
1174 
1175   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1176                                      MatchingInlineAsm);
1177   switch (MatchResult) {
1178   case Match_Success:
1179     Inst.setLoc(IDLoc);
1180     Out.EmitInstruction(Inst, getSTI());
1181     return false;
1182 
1183   case Match_MissingFeature: {
1184     assert(ErrorInfo && "Unknown missing feature!");
1185     // Special case the error message for the very common case where only
1186     // a single subtarget feature is missing
1187     std::string Msg = "instruction requires:";
1188     uint64_t Mask = 1;
1189     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
1190       if (ErrorInfo & Mask) {
1191         Msg += " ";
1192         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
1193       }
1194       Mask <<= 1;
1195     }
1196     return Error(IDLoc, Msg);
1197   }
1198 
1199   case Match_InvalidOperand: {
1200     SMLoc ErrorLoc = IDLoc;
1201     if (ErrorInfo != ~0ULL) {
1202       if (ErrorInfo >= Operands.size())
1203         return Error(IDLoc, "too few operands for instruction");
1204 
1205       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1206       if (ErrorLoc == SMLoc())
1207         ErrorLoc = IDLoc;
1208     }
1209     return Error(ErrorLoc, "invalid operand for instruction");
1210   }
1211 
1212   case Match_MnemonicFail:
1213     return Error(IDLoc, "invalid instruction");
1214   }
1215 
1216   llvm_unreachable("Unexpected match type");
1217 }
1218 
1219 OperandMatchResultTy
1220 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1221                              int64_t MaxVal, bool AllowTLS) {
1222   MCContext &Ctx = getContext();
1223   MCStreamer &Out = getStreamer();
1224   const MCExpr *Expr;
1225   SMLoc StartLoc = Parser.getTok().getLoc();
1226   if (getParser().parseExpression(Expr))
1227     return MatchOperand_NoMatch;
1228 
1229   // For consistency with the GNU assembler, treat immediates as offsets
1230   // from ".".
1231   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1232     int64_t Value = CE->getValue();
1233     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1234       Error(StartLoc, "offset out of range");
1235       return MatchOperand_ParseFail;
1236     }
1237     MCSymbol *Sym = Ctx.createTempSymbol();
1238     Out.EmitLabel(Sym);
1239     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1240                                                  Ctx);
1241     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1242   }
1243 
1244   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1245   const MCExpr *Sym = nullptr;
1246   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1247     Parser.Lex();
1248 
1249     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1250       Error(Parser.getTok().getLoc(), "unexpected token");
1251       return MatchOperand_ParseFail;
1252     }
1253 
1254     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1255     StringRef Name = Parser.getTok().getString();
1256     if (Name == "tls_gdcall")
1257       Kind = MCSymbolRefExpr::VK_TLSGD;
1258     else if (Name == "tls_ldcall")
1259       Kind = MCSymbolRefExpr::VK_TLSLDM;
1260     else {
1261       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1262       return MatchOperand_ParseFail;
1263     }
1264     Parser.Lex();
1265 
1266     if (Parser.getTok().isNot(AsmToken::Colon)) {
1267       Error(Parser.getTok().getLoc(), "unexpected token");
1268       return MatchOperand_ParseFail;
1269     }
1270     Parser.Lex();
1271 
1272     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1273       Error(Parser.getTok().getLoc(), "unexpected token");
1274       return MatchOperand_ParseFail;
1275     }
1276 
1277     StringRef Identifier = Parser.getTok().getString();
1278     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1279                                   Kind, Ctx);
1280     Parser.Lex();
1281   }
1282 
1283   SMLoc EndLoc =
1284     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1285 
1286   if (AllowTLS)
1287     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1288                                                     StartLoc, EndLoc));
1289   else
1290     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1291 
1292   return MatchOperand_Success;
1293 }
1294 
1295 // Force static initialization.
1296 extern "C" void LLVMInitializeSystemZAsmParser() {
1297   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1298 }
1299