1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "TargetInfo/SystemZTargetInfo.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/Casting.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/SMLoc.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <iterator>
35 #include <memory>
36 #include <string>
37 
38 using namespace llvm;
39 
40 // Return true if Expr is in the range [MinValue, MaxValue].
41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43     int64_t Value = CE->getValue();
44     return Value >= MinValue && Value <= MaxValue;
45   }
46   return false;
47 }
48 
49 namespace {
50 
51 enum RegisterKind {
52   GR32Reg,
53   GRH32Reg,
54   GR64Reg,
55   GR128Reg,
56   FP32Reg,
57   FP64Reg,
58   FP128Reg,
59   VR32Reg,
60   VR64Reg,
61   VR128Reg,
62   AR32Reg,
63   CR64Reg,
64 };
65 
66 enum MemoryKind {
67   BDMem,
68   BDXMem,
69   BDLMem,
70   BDRMem,
71   BDVMem
72 };
73 
74 class SystemZOperand : public MCParsedAsmOperand {
75 private:
76   enum OperandKind {
77     KindInvalid,
78     KindToken,
79     KindReg,
80     KindImm,
81     KindImmTLS,
82     KindMem
83   };
84 
85   OperandKind Kind;
86   SMLoc StartLoc, EndLoc;
87 
88   // A string of length Length, starting at Data.
89   struct TokenOp {
90     const char *Data;
91     unsigned Length;
92   };
93 
94   // LLVM register Num, which has kind Kind.  In some ways it might be
95   // easier for this class to have a register bank (general, floating-point
96   // or access) and a raw register number (0-15).  This would postpone the
97   // interpretation of the operand to the add*() methods and avoid the need
98   // for context-dependent parsing.  However, we do things the current way
99   // because of the virtual getReg() method, which needs to distinguish
100   // between (say) %r0 used as a single register and %r0 used as a pair.
101   // Context-dependent parsing can also give us slightly better error
102   // messages when invalid pairs like %r1 are used.
103   struct RegOp {
104     RegisterKind Kind;
105     unsigned Num;
106   };
107 
108   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
109   // MemKind says what type of memory this is and RegKind says what type
110   // the base register has (GR32Reg or GR64Reg).  Length is the operand
111   // length for D(L,B)-style operands, otherwise it is null.
112   struct MemOp {
113     unsigned Base : 12;
114     unsigned Index : 12;
115     unsigned MemKind : 4;
116     unsigned RegKind : 4;
117     const MCExpr *Disp;
118     union {
119       const MCExpr *Imm;
120       unsigned Reg;
121     } Length;
122   };
123 
124   // Imm is an immediate operand, and Sym is an optional TLS symbol
125   // for use with a __tls_get_offset marker relocation.
126   struct ImmTLSOp {
127     const MCExpr *Imm;
128     const MCExpr *Sym;
129   };
130 
131   union {
132     TokenOp Token;
133     RegOp Reg;
134     const MCExpr *Imm;
135     ImmTLSOp ImmTLS;
136     MemOp Mem;
137   };
138 
139   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
140     // Add as immediates when possible.  Null MCExpr = 0.
141     if (!Expr)
142       Inst.addOperand(MCOperand::createImm(0));
143     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
144       Inst.addOperand(MCOperand::createImm(CE->getValue()));
145     else
146       Inst.addOperand(MCOperand::createExpr(Expr));
147   }
148 
149 public:
150   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
151       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
152 
153   // Create particular kinds of operand.
154   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
155                                                        SMLoc EndLoc) {
156     return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
157   }
158 
159   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
160     auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
161     Op->Token.Data = Str.data();
162     Op->Token.Length = Str.size();
163     return Op;
164   }
165 
166   static std::unique_ptr<SystemZOperand>
167   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
168     auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
169     Op->Reg.Kind = Kind;
170     Op->Reg.Num = Num;
171     return Op;
172   }
173 
174   static std::unique_ptr<SystemZOperand>
175   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
176     auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
177     Op->Imm = Expr;
178     return Op;
179   }
180 
181   static std::unique_ptr<SystemZOperand>
182   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
183             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
184             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
185     auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
186     Op->Mem.MemKind = MemKind;
187     Op->Mem.RegKind = RegKind;
188     Op->Mem.Base = Base;
189     Op->Mem.Index = Index;
190     Op->Mem.Disp = Disp;
191     if (MemKind == BDLMem)
192       Op->Mem.Length.Imm = LengthImm;
193     if (MemKind == BDRMem)
194       Op->Mem.Length.Reg = LengthReg;
195     return Op;
196   }
197 
198   static std::unique_ptr<SystemZOperand>
199   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
200                SMLoc StartLoc, SMLoc EndLoc) {
201     auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
202     Op->ImmTLS.Imm = Imm;
203     Op->ImmTLS.Sym = Sym;
204     return Op;
205   }
206 
207   // Token operands
208   bool isToken() const override {
209     return Kind == KindToken;
210   }
211   StringRef getToken() const {
212     assert(Kind == KindToken && "Not a token");
213     return StringRef(Token.Data, Token.Length);
214   }
215 
216   // Register operands.
217   bool isReg() const override {
218     return Kind == KindReg;
219   }
220   bool isReg(RegisterKind RegKind) const {
221     return Kind == KindReg && Reg.Kind == RegKind;
222   }
223   unsigned getReg() const override {
224     assert(Kind == KindReg && "Not a register");
225     return Reg.Num;
226   }
227 
228   // Immediate operands.
229   bool isImm() const override {
230     return Kind == KindImm;
231   }
232   bool isImm(int64_t MinValue, int64_t MaxValue) const {
233     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
234   }
235   const MCExpr *getImm() const {
236     assert(Kind == KindImm && "Not an immediate");
237     return Imm;
238   }
239 
240   // Immediate operands with optional TLS symbol.
241   bool isImmTLS() const {
242     return Kind == KindImmTLS;
243   }
244 
245   const ImmTLSOp getImmTLS() const {
246     assert(Kind == KindImmTLS && "Not a TLS immediate");
247     return ImmTLS;
248   }
249 
250   // Memory operands.
251   bool isMem() const override {
252     return Kind == KindMem;
253   }
254   bool isMem(MemoryKind MemKind) const {
255     return (Kind == KindMem &&
256             (Mem.MemKind == MemKind ||
257              // A BDMem can be treated as a BDXMem in which the index
258              // register field is 0.
259              (Mem.MemKind == BDMem && MemKind == BDXMem)));
260   }
261   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
262     return isMem(MemKind) && Mem.RegKind == RegKind;
263   }
264   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
265     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
266   }
267   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
268     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
269   }
270   bool isMemDisp12Len4(RegisterKind RegKind) const {
271     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
272   }
273   bool isMemDisp12Len8(RegisterKind RegKind) const {
274     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
275   }
276 
277   const MemOp& getMem() const {
278     assert(Kind == KindMem && "Not a Mem operand");
279     return Mem;
280   }
281 
282   // Override MCParsedAsmOperand.
283   SMLoc getStartLoc() const override { return StartLoc; }
284   SMLoc getEndLoc() const override { return EndLoc; }
285   void print(raw_ostream &OS) const override;
286 
287   /// getLocRange - Get the range between the first and last token of this
288   /// operand.
289   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
290 
291   // Used by the TableGen code to add particular types of operand
292   // to an instruction.
293   void addRegOperands(MCInst &Inst, unsigned N) const {
294     assert(N == 1 && "Invalid number of operands");
295     Inst.addOperand(MCOperand::createReg(getReg()));
296   }
297   void addImmOperands(MCInst &Inst, unsigned N) const {
298     assert(N == 1 && "Invalid number of operands");
299     addExpr(Inst, getImm());
300   }
301   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
302     assert(N == 2 && "Invalid number of operands");
303     assert(isMem(BDMem) && "Invalid operand type");
304     Inst.addOperand(MCOperand::createReg(Mem.Base));
305     addExpr(Inst, Mem.Disp);
306   }
307   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
308     assert(N == 3 && "Invalid number of operands");
309     assert(isMem(BDXMem) && "Invalid operand type");
310     Inst.addOperand(MCOperand::createReg(Mem.Base));
311     addExpr(Inst, Mem.Disp);
312     Inst.addOperand(MCOperand::createReg(Mem.Index));
313   }
314   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
315     assert(N == 3 && "Invalid number of operands");
316     assert(isMem(BDLMem) && "Invalid operand type");
317     Inst.addOperand(MCOperand::createReg(Mem.Base));
318     addExpr(Inst, Mem.Disp);
319     addExpr(Inst, Mem.Length.Imm);
320   }
321   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
322     assert(N == 3 && "Invalid number of operands");
323     assert(isMem(BDRMem) && "Invalid operand type");
324     Inst.addOperand(MCOperand::createReg(Mem.Base));
325     addExpr(Inst, Mem.Disp);
326     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
327   }
328   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
329     assert(N == 3 && "Invalid number of operands");
330     assert(isMem(BDVMem) && "Invalid operand type");
331     Inst.addOperand(MCOperand::createReg(Mem.Base));
332     addExpr(Inst, Mem.Disp);
333     Inst.addOperand(MCOperand::createReg(Mem.Index));
334   }
335   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
336     assert(N == 2 && "Invalid number of operands");
337     assert(Kind == KindImmTLS && "Invalid operand type");
338     addExpr(Inst, ImmTLS.Imm);
339     if (ImmTLS.Sym)
340       addExpr(Inst, ImmTLS.Sym);
341   }
342 
343   // Used by the TableGen code to check for particular operand types.
344   bool isGR32() const { return isReg(GR32Reg); }
345   bool isGRH32() const { return isReg(GRH32Reg); }
346   bool isGRX32() const { return false; }
347   bool isGR64() const { return isReg(GR64Reg); }
348   bool isGR128() const { return isReg(GR128Reg); }
349   bool isADDR32() const { return isReg(GR32Reg); }
350   bool isADDR64() const { return isReg(GR64Reg); }
351   bool isADDR128() const { return false; }
352   bool isFP32() const { return isReg(FP32Reg); }
353   bool isFP64() const { return isReg(FP64Reg); }
354   bool isFP128() const { return isReg(FP128Reg); }
355   bool isVR32() const { return isReg(VR32Reg); }
356   bool isVR64() const { return isReg(VR64Reg); }
357   bool isVF128() const { return false; }
358   bool isVR128() const { return isReg(VR128Reg); }
359   bool isAR32() const { return isReg(AR32Reg); }
360   bool isCR64() const { return isReg(CR64Reg); }
361   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
362   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
363   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
364   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
365   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
366   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
367   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
368   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
369   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
370   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
371   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
372   bool isU1Imm() const { return isImm(0, 1); }
373   bool isU2Imm() const { return isImm(0, 3); }
374   bool isU3Imm() const { return isImm(0, 7); }
375   bool isU4Imm() const { return isImm(0, 15); }
376   bool isU6Imm() const { return isImm(0, 63); }
377   bool isU8Imm() const { return isImm(0, 255); }
378   bool isS8Imm() const { return isImm(-128, 127); }
379   bool isU12Imm() const { return isImm(0, 4095); }
380   bool isU16Imm() const { return isImm(0, 65535); }
381   bool isS16Imm() const { return isImm(-32768, 32767); }
382   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
383   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
384   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
385 };
386 
387 class SystemZAsmParser : public MCTargetAsmParser {
388 #define GET_ASSEMBLER_HEADER
389 #include "SystemZGenAsmMatcher.inc"
390 
391 private:
392   MCAsmParser &Parser;
393   enum RegisterGroup {
394     RegGR,
395     RegFP,
396     RegV,
397     RegAR,
398     RegCR
399   };
400   struct Register {
401     RegisterGroup Group;
402     unsigned Num;
403     SMLoc StartLoc, EndLoc;
404   };
405 
406   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
407 
408   bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
409 
410   OperandMatchResultTy parseRegister(OperandVector &Operands,
411                                      RegisterKind Kind);
412 
413   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
414 
415   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
416                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
417                     bool HasLength = false, bool HasVectorIndex = false);
418   bool parseAddressRegister(Register &Reg);
419 
420   bool ParseDirectiveInsn(SMLoc L);
421 
422   OperandMatchResultTy parseAddress(OperandVector &Operands,
423                                     MemoryKind MemKind,
424                                     RegisterKind RegKind);
425 
426   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
427                                   int64_t MaxVal, bool AllowTLS);
428 
429   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
430 
431 public:
432   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
433                    const MCInstrInfo &MII,
434                    const MCTargetOptions &Options)
435     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
436     MCAsmParserExtension::Initialize(Parser);
437 
438     // Alias the .word directive to .short.
439     parser.addAliasForDirective(".word", ".short");
440 
441     // Initialize the set of available features.
442     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
443   }
444 
445   // Override MCTargetAsmParser.
446   bool ParseDirective(AsmToken DirectiveID) override;
447   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
448   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
449                      bool RestoreOnFailure);
450   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
451                                         SMLoc &EndLoc) override;
452   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453                         SMLoc NameLoc, OperandVector &Operands) override;
454   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455                                OperandVector &Operands, MCStreamer &Out,
456                                uint64_t &ErrorInfo,
457                                bool MatchingInlineAsm) override;
458 
459   // Used by the TableGen code to parse particular operand types.
460   OperandMatchResultTy parseGR32(OperandVector &Operands) {
461     return parseRegister(Operands, GR32Reg);
462   }
463   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464     return parseRegister(Operands, GRH32Reg);
465   }
466   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467     llvm_unreachable("GRX32 should only be used for pseudo instructions");
468   }
469   OperandMatchResultTy parseGR64(OperandVector &Operands) {
470     return parseRegister(Operands, GR64Reg);
471   }
472   OperandMatchResultTy parseGR128(OperandVector &Operands) {
473     return parseRegister(Operands, GR128Reg);
474   }
475   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476     // For the AsmParser, we will accept %r0 for ADDR32 as well.
477     return parseRegister(Operands, GR32Reg);
478   }
479   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
480     // For the AsmParser, we will accept %r0 for ADDR64 as well.
481     return parseRegister(Operands, GR64Reg);
482   }
483   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
484     llvm_unreachable("Shouldn't be used as an operand");
485   }
486   OperandMatchResultTy parseFP32(OperandVector &Operands) {
487     return parseRegister(Operands, FP32Reg);
488   }
489   OperandMatchResultTy parseFP64(OperandVector &Operands) {
490     return parseRegister(Operands, FP64Reg);
491   }
492   OperandMatchResultTy parseFP128(OperandVector &Operands) {
493     return parseRegister(Operands, FP128Reg);
494   }
495   OperandMatchResultTy parseVR32(OperandVector &Operands) {
496     return parseRegister(Operands, VR32Reg);
497   }
498   OperandMatchResultTy parseVR64(OperandVector &Operands) {
499     return parseRegister(Operands, VR64Reg);
500   }
501   OperandMatchResultTy parseVF128(OperandVector &Operands) {
502     llvm_unreachable("Shouldn't be used as an operand");
503   }
504   OperandMatchResultTy parseVR128(OperandVector &Operands) {
505     return parseRegister(Operands, VR128Reg);
506   }
507   OperandMatchResultTy parseAR32(OperandVector &Operands) {
508     return parseRegister(Operands, AR32Reg);
509   }
510   OperandMatchResultTy parseCR64(OperandVector &Operands) {
511     return parseRegister(Operands, CR64Reg);
512   }
513   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
514     return parseAnyRegister(Operands);
515   }
516   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
517     return parseAddress(Operands, BDMem, GR32Reg);
518   }
519   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
520     return parseAddress(Operands, BDMem, GR64Reg);
521   }
522   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
523     return parseAddress(Operands, BDXMem, GR64Reg);
524   }
525   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
526     return parseAddress(Operands, BDLMem, GR64Reg);
527   }
528   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
529     return parseAddress(Operands, BDRMem, GR64Reg);
530   }
531   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
532     return parseAddress(Operands, BDVMem, GR64Reg);
533   }
534   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
535     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
536   }
537   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
538     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
539   }
540   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
541     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
542   }
543   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
544     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
545   }
546   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
547     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
548   }
549   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
550     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
551   }
552 };
553 
554 } // end anonymous namespace
555 
556 #define GET_REGISTER_MATCHER
557 #define GET_SUBTARGET_FEATURE_NAME
558 #define GET_MATCHER_IMPLEMENTATION
559 #define GET_MNEMONIC_SPELL_CHECKER
560 #include "SystemZGenAsmMatcher.inc"
561 
562 // Used for the .insn directives; contains information needed to parse the
563 // operands in the directive.
564 struct InsnMatchEntry {
565   StringRef Format;
566   uint64_t Opcode;
567   int32_t NumOperands;
568   MatchClassKind OperandKinds[7];
569 };
570 
571 // For equal_range comparison.
572 struct CompareInsn {
573   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
574     return LHS.Format < RHS;
575   }
576   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
577     return LHS < RHS.Format;
578   }
579   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
580     return LHS.Format < RHS.Format;
581   }
582 };
583 
584 // Table initializing information for parsing the .insn directive.
585 static struct InsnMatchEntry InsnMatchTable[] = {
586   /* Format, Opcode, NumOperands, OperandKinds */
587   { "e", SystemZ::InsnE, 1,
588     { MCK_U16Imm } },
589   { "ri", SystemZ::InsnRI, 3,
590     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
591   { "rie", SystemZ::InsnRIE, 4,
592     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
593   { "ril", SystemZ::InsnRIL, 3,
594     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
595   { "rilu", SystemZ::InsnRILU, 3,
596     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
597   { "ris", SystemZ::InsnRIS, 5,
598     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
599   { "rr", SystemZ::InsnRR, 3,
600     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
601   { "rre", SystemZ::InsnRRE, 3,
602     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
603   { "rrf", SystemZ::InsnRRF, 5,
604     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
605   { "rrs", SystemZ::InsnRRS, 5,
606     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
607   { "rs", SystemZ::InsnRS, 4,
608     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609   { "rse", SystemZ::InsnRSE, 4,
610     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
611   { "rsi", SystemZ::InsnRSI, 4,
612     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
613   { "rsy", SystemZ::InsnRSY, 4,
614     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
615   { "rx", SystemZ::InsnRX, 3,
616     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617   { "rxe", SystemZ::InsnRXE, 3,
618     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619   { "rxf", SystemZ::InsnRXF, 4,
620     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
621   { "rxy", SystemZ::InsnRXY, 3,
622     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
623   { "s", SystemZ::InsnS, 2,
624     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
625   { "si", SystemZ::InsnSI, 3,
626     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
627   { "sil", SystemZ::InsnSIL, 3,
628     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
629   { "siy", SystemZ::InsnSIY, 3,
630     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
631   { "ss", SystemZ::InsnSS, 4,
632     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
633   { "sse", SystemZ::InsnSSE, 3,
634     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
635   { "ssf", SystemZ::InsnSSF, 4,
636     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
637   { "vri", SystemZ::InsnVRI, 6,
638     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
639   { "vrr", SystemZ::InsnVRR, 7,
640     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_U4Imm,
641       MCK_U4Imm } },
642   { "vrs", SystemZ::InsnVRS, 5,
643     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U4Imm } },
644   { "vrv", SystemZ::InsnVRV, 4,
645     { MCK_U48Imm, MCK_AnyReg, MCK_BDVAddr64Disp12, MCK_U4Imm } },
646   { "vrx", SystemZ::InsnVRX, 4,
647     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12, MCK_U4Imm } },
648   { "vsi", SystemZ::InsnVSI, 4,
649     { MCK_U48Imm, MCK_AnyReg, MCK_BDAddr64Disp12, MCK_U8Imm } }
650 };
651 
652 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
653   if (!E)
654     return;
655   if (auto *CE = dyn_cast<MCConstantExpr>(E))
656     OS << *CE;
657   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
658     OS << *UE;
659   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
660     OS << *BE;
661   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
662     OS << *SRE;
663   else
664     OS << *E;
665 }
666 
667 void SystemZOperand::print(raw_ostream &OS) const {
668   switch (Kind) {
669   case KindToken:
670     OS << "Token:" << getToken();
671     break;
672   case KindReg:
673     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
674     break;
675   case KindImm:
676     OS << "Imm:";
677     printMCExpr(getImm(), OS);
678     break;
679   case KindImmTLS:
680     OS << "ImmTLS:";
681     printMCExpr(getImmTLS().Imm, OS);
682     if (getImmTLS().Sym) {
683       OS << ", ";
684       printMCExpr(getImmTLS().Sym, OS);
685     }
686     break;
687   case KindMem: {
688     const MemOp &Op = getMem();
689     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
690     if (Op.Base) {
691       OS << "(";
692       if (Op.MemKind == BDLMem)
693         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
694       else if (Op.MemKind == BDRMem)
695         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
696       if (Op.Index)
697         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
698       OS << SystemZInstPrinter::getRegisterName(Op.Base);
699       OS << ")";
700     }
701     break;
702   }
703   case KindInvalid:
704     break;
705   }
706 }
707 
708 // Parse one register of the form %<prefix><number>.
709 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
710   Reg.StartLoc = Parser.getTok().getLoc();
711 
712   // Eat the % prefix.
713   if (Parser.getTok().isNot(AsmToken::Percent))
714     return Error(Parser.getTok().getLoc(), "register expected");
715   const AsmToken &PercentTok = Parser.getTok();
716   Parser.Lex();
717 
718   // Expect a register name.
719   if (Parser.getTok().isNot(AsmToken::Identifier)) {
720     if (RestoreOnFailure)
721       getLexer().UnLex(PercentTok);
722     return Error(Reg.StartLoc, "invalid register");
723   }
724 
725   // Check that there's a prefix.
726   StringRef Name = Parser.getTok().getString();
727   if (Name.size() < 2) {
728     if (RestoreOnFailure)
729       getLexer().UnLex(PercentTok);
730     return Error(Reg.StartLoc, "invalid register");
731   }
732   char Prefix = Name[0];
733 
734   // Treat the rest of the register name as a register number.
735   if (Name.substr(1).getAsInteger(10, Reg.Num)) {
736     if (RestoreOnFailure)
737       getLexer().UnLex(PercentTok);
738     return Error(Reg.StartLoc, "invalid register");
739   }
740 
741   // Look for valid combinations of prefix and number.
742   if (Prefix == 'r' && Reg.Num < 16)
743     Reg.Group = RegGR;
744   else if (Prefix == 'f' && Reg.Num < 16)
745     Reg.Group = RegFP;
746   else if (Prefix == 'v' && Reg.Num < 32)
747     Reg.Group = RegV;
748   else if (Prefix == 'a' && Reg.Num < 16)
749     Reg.Group = RegAR;
750   else if (Prefix == 'c' && Reg.Num < 16)
751     Reg.Group = RegCR;
752   else {
753     if (RestoreOnFailure)
754       getLexer().UnLex(PercentTok);
755     return Error(Reg.StartLoc, "invalid register");
756   }
757 
758   Reg.EndLoc = Parser.getTok().getLoc();
759   Parser.Lex();
760   return false;
761 }
762 
763 // Parse a register of kind Kind and add it to Operands.
764 OperandMatchResultTy
765 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
766   Register Reg;
767   RegisterGroup Group;
768   switch (Kind) {
769   case GR32Reg:
770   case GRH32Reg:
771   case GR64Reg:
772   case GR128Reg:
773     Group = RegGR;
774     break;
775   case FP32Reg:
776   case FP64Reg:
777   case FP128Reg:
778     Group = RegFP;
779     break;
780   case VR32Reg:
781   case VR64Reg:
782   case VR128Reg:
783     Group = RegV;
784     break;
785   case AR32Reg:
786     Group = RegAR;
787     break;
788   case CR64Reg:
789     Group = RegCR;
790     break;
791   }
792 
793   // Handle register names of the form %<prefix><number>
794   if (Parser.getTok().is(AsmToken::Percent)) {
795     if (parseRegister(Reg))
796       return MatchOperand_ParseFail;
797 
798     // Check the parsed register group "Reg.Group" with the expected "Group"
799     // Have to error out if user specified wrong prefix.
800     switch (Group) {
801     case RegGR:
802     case RegFP:
803     case RegAR:
804     case RegCR:
805       if (Group != Reg.Group) {
806         Error(Reg.StartLoc, "invalid operand for instruction");
807         return MatchOperand_ParseFail;
808       }
809       break;
810     case RegV:
811       if (Reg.Group != RegV && Reg.Group != RegFP) {
812         Error(Reg.StartLoc, "invalid operand for instruction");
813         return MatchOperand_ParseFail;
814       }
815       break;
816     }
817   } else if (Parser.getTok().is(AsmToken::Integer)) {
818     if (parseIntegerRegister(Reg, Group))
819       return MatchOperand_ParseFail;
820   }
821   // Otherwise we didn't match a register operand.
822   else
823     return MatchOperand_NoMatch;
824 
825   // Determine the LLVM register number according to Kind.
826   const unsigned *Regs;
827   switch (Kind) {
828   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
829   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
830   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
831   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
832   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
833   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
834   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
835   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
836   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
837   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
838   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
839   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
840   }
841   if (Regs[Reg.Num] == 0) {
842     Error(Reg.StartLoc, "invalid register pair");
843     return MatchOperand_ParseFail;
844   }
845 
846   Operands.push_back(
847       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
848   return MatchOperand_Success;
849 }
850 
851 // Parse any type of register (including integers) and add it to Operands.
852 OperandMatchResultTy
853 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
854   // Handle integer values.
855   if (Parser.getTok().is(AsmToken::Integer)) {
856     const MCExpr *Register;
857     SMLoc StartLoc = Parser.getTok().getLoc();
858     if (Parser.parseExpression(Register))
859       return MatchOperand_ParseFail;
860 
861     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
862       int64_t Value = CE->getValue();
863       if (Value < 0 || Value > 15) {
864         Error(StartLoc, "invalid register");
865         return MatchOperand_ParseFail;
866       }
867     }
868 
869     SMLoc EndLoc =
870       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
871 
872     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
873   }
874   else {
875     Register Reg;
876     if (parseRegister(Reg))
877       return MatchOperand_ParseFail;
878 
879     // Map to the correct register kind.
880     RegisterKind Kind;
881     unsigned RegNo;
882     if (Reg.Group == RegGR) {
883       Kind = GR64Reg;
884       RegNo = SystemZMC::GR64Regs[Reg.Num];
885     }
886     else if (Reg.Group == RegFP) {
887       Kind = FP64Reg;
888       RegNo = SystemZMC::FP64Regs[Reg.Num];
889     }
890     else if (Reg.Group == RegV) {
891       Kind = VR128Reg;
892       RegNo = SystemZMC::VR128Regs[Reg.Num];
893     }
894     else if (Reg.Group == RegAR) {
895       Kind = AR32Reg;
896       RegNo = SystemZMC::AR32Regs[Reg.Num];
897     }
898     else if (Reg.Group == RegCR) {
899       Kind = CR64Reg;
900       RegNo = SystemZMC::CR64Regs[Reg.Num];
901     }
902     else {
903       return MatchOperand_ParseFail;
904     }
905 
906     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
907                                                  Reg.StartLoc, Reg.EndLoc));
908   }
909   return MatchOperand_Success;
910 }
911 
912 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
913                                             RegisterGroup Group) {
914   Reg.StartLoc = Parser.getTok().getLoc();
915   // We have an integer token
916   const MCExpr *Register;
917   if (Parser.parseExpression(Register))
918     return true;
919 
920   const auto *CE = dyn_cast<MCConstantExpr>(Register);
921   if (!CE)
922     return true;
923 
924   int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
925   int64_t Value = CE->getValue();
926   if (Value < 0 || Value > MaxRegNum) {
927     Error(Parser.getTok().getLoc(), "invalid register");
928     return true;
929   }
930 
931   // Assign the Register Number
932   Reg.Num = (unsigned)Value;
933   Reg.Group = Group;
934   Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
935 
936   // At this point, successfully parsed an integer register.
937   return false;
938 }
939 
940 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
941 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
942                                     bool &HaveReg2, Register &Reg2,
943                                     const MCExpr *&Disp, const MCExpr *&Length,
944                                     bool HasLength, bool HasVectorIndex) {
945   // Parse the displacement, which must always be present.
946   if (getParser().parseExpression(Disp))
947     return true;
948 
949   // Parse the optional base and index.
950   HaveReg1 = false;
951   HaveReg2 = false;
952   Length = nullptr;
953 
954   // If we have a scenario as below:
955   //   vgef %v0, 0(0), 0
956   // This is an example of a "BDVMem" instruction type.
957   //
958   // So when we parse this as an integer register, the register group
959   // needs to be tied to "RegV". Usually when the prefix is passed in
960   // as %<prefix><reg-number> its easy to check which group it should belong to
961   // However, if we're passing in just the integer there's no real way to
962   // "check" what register group it should belong to.
963   //
964   // When the user passes in the register as an integer, the user assumes that
965   // the compiler is responsible for substituting it as the right kind of
966   // register. Whereas, when the user specifies a "prefix", the onus is on
967   // the user to make sure they pass in the right kind of register.
968   //
969   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
970   // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
971   // (i.e. insn is of type BDVMem) is true.
972   RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
973 
974   if (getLexer().is(AsmToken::LParen)) {
975     Parser.Lex();
976 
977     if (getLexer().is(AsmToken::Percent)) {
978       // Parse the first register.
979       HaveReg1 = true;
980       if (parseRegister(Reg1))
981         return true;
982     }
983     // So if we have an integer as the first token in ([tok1], ..), it could:
984     // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
985     // instructions)
986     // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
987     else if (getLexer().is(AsmToken::Integer)) {
988       if (HasLength) {
989         // Instruction has a "Length" field, safe to parse the first token as
990         // the "Length" field
991         if (getParser().parseExpression(Length))
992           return true;
993       } else {
994         // Otherwise, if the instruction has no "Length" field, parse the
995         // token as a "Register". We don't have to worry about whether the
996         // instruction is invalid here, because the caller will take care of
997         // error reporting.
998         HaveReg1 = true;
999         if (parseIntegerRegister(Reg1, RegGroup))
1000           return true;
1001       }
1002     } else {
1003       // If its not an integer or a percent token, then if the instruction
1004       // is reported to have a "Length" then, parse it as "Length".
1005       if (HasLength) {
1006         if (getParser().parseExpression(Length))
1007           return true;
1008       }
1009     }
1010 
1011     // Check whether there's a second register.
1012     if (getLexer().is(AsmToken::Comma)) {
1013       Parser.Lex();
1014       HaveReg2 = true;
1015 
1016       if (getLexer().is(AsmToken::Integer)) {
1017         if (parseIntegerRegister(Reg2, RegGR))
1018           return true;
1019       } else {
1020         if (parseRegister(Reg2))
1021           return true;
1022       }
1023     }
1024 
1025     // Consume the closing bracket.
1026     if (getLexer().isNot(AsmToken::RParen))
1027       return Error(Parser.getTok().getLoc(), "unexpected token in address");
1028     Parser.Lex();
1029   }
1030   return false;
1031 }
1032 
1033 // Verify that Reg is a valid address register (base or index).
1034 bool
1035 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1036   if (Reg.Group == RegV) {
1037     Error(Reg.StartLoc, "invalid use of vector addressing");
1038     return true;
1039   } else if (Reg.Group != RegGR) {
1040     Error(Reg.StartLoc, "invalid address register");
1041     return true;
1042   }
1043   return false;
1044 }
1045 
1046 // Parse a memory operand and add it to Operands.  The other arguments
1047 // are as above.
1048 OperandMatchResultTy
1049 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1050                                RegisterKind RegKind) {
1051   SMLoc StartLoc = Parser.getTok().getLoc();
1052   unsigned Base = 0, Index = 0, LengthReg = 0;
1053   Register Reg1, Reg2;
1054   bool HaveReg1, HaveReg2;
1055   const MCExpr *Disp;
1056   const MCExpr *Length;
1057 
1058   bool HasLength = (MemKind == BDLMem) ? true : false;
1059   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1060   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1061                    HasVectorIndex))
1062     return MatchOperand_ParseFail;
1063 
1064   const unsigned *Regs;
1065   switch (RegKind) {
1066   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1067   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1068   default: llvm_unreachable("invalid RegKind");
1069   }
1070 
1071   switch (MemKind) {
1072   case BDMem:
1073     // If we have Reg1, it must be an address register.
1074     if (HaveReg1) {
1075       if (parseAddressRegister(Reg1))
1076         return MatchOperand_ParseFail;
1077       Base = Regs[Reg1.Num];
1078     }
1079     // There must be no Reg2.
1080     if (HaveReg2) {
1081       Error(StartLoc, "invalid use of indexed addressing");
1082       return MatchOperand_ParseFail;
1083     }
1084     break;
1085   case BDXMem:
1086     // If we have Reg1, it must be an address register.
1087     if (HaveReg1) {
1088       if (parseAddressRegister(Reg1))
1089         return MatchOperand_ParseFail;
1090       // If the are two registers, the first one is the index and the
1091       // second is the base.
1092       if (HaveReg2)
1093         Index = Regs[Reg1.Num];
1094       else
1095         Base = Regs[Reg1.Num];
1096     }
1097     // If we have Reg2, it must be an address register.
1098     if (HaveReg2) {
1099       if (parseAddressRegister(Reg2))
1100         return MatchOperand_ParseFail;
1101       Base = Regs[Reg2.Num];
1102     }
1103     break;
1104   case BDLMem:
1105     // If we have Reg2, it must be an address register.
1106     if (HaveReg2) {
1107       if (parseAddressRegister(Reg2))
1108         return MatchOperand_ParseFail;
1109       Base = Regs[Reg2.Num];
1110     }
1111     // We cannot support base+index addressing.
1112     if (HaveReg1 && HaveReg2) {
1113       Error(StartLoc, "invalid use of indexed addressing");
1114       return MatchOperand_ParseFail;
1115     }
1116     // We must have a length.
1117     if (!Length) {
1118       Error(StartLoc, "missing length in address");
1119       return MatchOperand_ParseFail;
1120     }
1121     break;
1122   case BDRMem:
1123     // We must have Reg1, and it must be a GPR.
1124     if (!HaveReg1 || Reg1.Group != RegGR) {
1125       Error(StartLoc, "invalid operand for instruction");
1126       return MatchOperand_ParseFail;
1127     }
1128     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1129     // If we have Reg2, it must be an address register.
1130     if (HaveReg2) {
1131       if (parseAddressRegister(Reg2))
1132         return MatchOperand_ParseFail;
1133       Base = Regs[Reg2.Num];
1134     }
1135     break;
1136   case BDVMem:
1137     // We must have Reg1, and it must be a vector register.
1138     if (!HaveReg1 || Reg1.Group != RegV) {
1139       Error(StartLoc, "vector index required in address");
1140       return MatchOperand_ParseFail;
1141     }
1142     Index = SystemZMC::VR128Regs[Reg1.Num];
1143     // If we have Reg2, it must be an address register.
1144     if (HaveReg2) {
1145       if (parseAddressRegister(Reg2))
1146         return MatchOperand_ParseFail;
1147       Base = Regs[Reg2.Num];
1148     }
1149     break;
1150   }
1151 
1152   SMLoc EndLoc =
1153       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1154   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1155                                                Index, Length, LengthReg,
1156                                                StartLoc, EndLoc));
1157   return MatchOperand_Success;
1158 }
1159 
1160 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1161   StringRef IDVal = DirectiveID.getIdentifier();
1162 
1163   if (IDVal == ".insn")
1164     return ParseDirectiveInsn(DirectiveID.getLoc());
1165 
1166   return true;
1167 }
1168 
1169 /// ParseDirectiveInsn
1170 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1171 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1172   MCAsmParser &Parser = getParser();
1173 
1174   // Expect instruction format as identifier.
1175   StringRef Format;
1176   SMLoc ErrorLoc = Parser.getTok().getLoc();
1177   if (Parser.parseIdentifier(Format))
1178     return Error(ErrorLoc, "expected instruction format");
1179 
1180   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1181 
1182   // Find entry for this format in InsnMatchTable.
1183   auto EntryRange =
1184     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1185                      Format, CompareInsn());
1186 
1187   // If first == second, couldn't find a match in the table.
1188   if (EntryRange.first == EntryRange.second)
1189     return Error(ErrorLoc, "unrecognized format");
1190 
1191   struct InsnMatchEntry *Entry = EntryRange.first;
1192 
1193   // Format should match from equal_range.
1194   assert(Entry->Format == Format);
1195 
1196   // Parse the following operands using the table's information.
1197   for (int i = 0; i < Entry->NumOperands; i++) {
1198     MatchClassKind Kind = Entry->OperandKinds[i];
1199 
1200     SMLoc StartLoc = Parser.getTok().getLoc();
1201 
1202     // Always expect commas as separators for operands.
1203     if (getLexer().isNot(AsmToken::Comma))
1204       return Error(StartLoc, "unexpected token in directive");
1205     Lex();
1206 
1207     // Parse operands.
1208     OperandMatchResultTy ResTy;
1209     if (Kind == MCK_AnyReg)
1210       ResTy = parseAnyReg(Operands);
1211     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1212       ResTy = parseBDXAddr64(Operands);
1213     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1214       ResTy = parseBDAddr64(Operands);
1215     else if (Kind == MCK_BDVAddr64Disp12)
1216       ResTy = parseBDVAddr64(Operands);
1217     else if (Kind == MCK_PCRel32)
1218       ResTy = parsePCRel32(Operands);
1219     else if (Kind == MCK_PCRel16)
1220       ResTy = parsePCRel16(Operands);
1221     else {
1222       // Only remaining operand kind is an immediate.
1223       const MCExpr *Expr;
1224       SMLoc StartLoc = Parser.getTok().getLoc();
1225 
1226       // Expect immediate expression.
1227       if (Parser.parseExpression(Expr))
1228         return Error(StartLoc, "unexpected token in directive");
1229 
1230       SMLoc EndLoc =
1231         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1232 
1233       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1234       ResTy = MatchOperand_Success;
1235     }
1236 
1237     if (ResTy != MatchOperand_Success)
1238       return true;
1239   }
1240 
1241   // Build the instruction with the parsed operands.
1242   MCInst Inst = MCInstBuilder(Entry->Opcode);
1243 
1244   for (size_t i = 0; i < Operands.size(); i++) {
1245     MCParsedAsmOperand &Operand = *Operands[i];
1246     MatchClassKind Kind = Entry->OperandKinds[i];
1247 
1248     // Verify operand.
1249     unsigned Res = validateOperandClass(Operand, Kind);
1250     if (Res != Match_Success)
1251       return Error(Operand.getStartLoc(), "unexpected operand type");
1252 
1253     // Add operands to instruction.
1254     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1255     if (ZOperand.isReg())
1256       ZOperand.addRegOperands(Inst, 1);
1257     else if (ZOperand.isMem(BDMem))
1258       ZOperand.addBDAddrOperands(Inst, 2);
1259     else if (ZOperand.isMem(BDXMem))
1260       ZOperand.addBDXAddrOperands(Inst, 3);
1261     else if (ZOperand.isMem(BDVMem))
1262       ZOperand.addBDVAddrOperands(Inst, 3);
1263     else if (ZOperand.isImm())
1264       ZOperand.addImmOperands(Inst, 1);
1265     else
1266       llvm_unreachable("unexpected operand type");
1267   }
1268 
1269   // Emit as a regular instruction.
1270   Parser.getStreamer().emitInstruction(Inst, getSTI());
1271 
1272   return false;
1273 }
1274 
1275 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1276                                      SMLoc &EndLoc, bool RestoreOnFailure) {
1277   Register Reg;
1278   if (parseRegister(Reg, RestoreOnFailure))
1279     return true;
1280   if (Reg.Group == RegGR)
1281     RegNo = SystemZMC::GR64Regs[Reg.Num];
1282   else if (Reg.Group == RegFP)
1283     RegNo = SystemZMC::FP64Regs[Reg.Num];
1284   else if (Reg.Group == RegV)
1285     RegNo = SystemZMC::VR128Regs[Reg.Num];
1286   else if (Reg.Group == RegAR)
1287     RegNo = SystemZMC::AR32Regs[Reg.Num];
1288   else if (Reg.Group == RegCR)
1289     RegNo = SystemZMC::CR64Regs[Reg.Num];
1290   StartLoc = Reg.StartLoc;
1291   EndLoc = Reg.EndLoc;
1292   return false;
1293 }
1294 
1295 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1296                                      SMLoc &EndLoc) {
1297   return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1298 }
1299 
1300 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1301                                                         SMLoc &StartLoc,
1302                                                         SMLoc &EndLoc) {
1303   bool Result =
1304       ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1305   bool PendingErrors = getParser().hasPendingError();
1306   getParser().clearPendingErrors();
1307   if (PendingErrors)
1308     return MatchOperand_ParseFail;
1309   if (Result)
1310     return MatchOperand_NoMatch;
1311   return MatchOperand_Success;
1312 }
1313 
1314 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1315                                         StringRef Name, SMLoc NameLoc,
1316                                         OperandVector &Operands) {
1317   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1318 
1319   // Read the remaining operands.
1320   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1321     // Read the first operand.
1322     if (parseOperand(Operands, Name)) {
1323       return true;
1324     }
1325 
1326     // Read any subsequent operands.
1327     while (getLexer().is(AsmToken::Comma)) {
1328       Parser.Lex();
1329       if (parseOperand(Operands, Name)) {
1330         return true;
1331       }
1332     }
1333     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1334       SMLoc Loc = getLexer().getLoc();
1335       return Error(Loc, "unexpected token in argument list");
1336     }
1337   }
1338 
1339   // Consume the EndOfStatement.
1340   Parser.Lex();
1341   return false;
1342 }
1343 
1344 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1345                                     StringRef Mnemonic) {
1346   // Check if the current operand has a custom associated parser, if so, try to
1347   // custom parse the operand, or fallback to the general approach.  Force all
1348   // features to be available during the operand check, or else we will fail to
1349   // find the custom parser, and then we will later get an InvalidOperand error
1350   // instead of a MissingFeature errror.
1351   FeatureBitset AvailableFeatures = getAvailableFeatures();
1352   FeatureBitset All;
1353   All.set();
1354   setAvailableFeatures(All);
1355   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1356   setAvailableFeatures(AvailableFeatures);
1357   if (ResTy == MatchOperand_Success)
1358     return false;
1359 
1360   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1361   // there was a match, but an error occurred, in which case, just return that
1362   // the operand parsing failed.
1363   if (ResTy == MatchOperand_ParseFail)
1364     return true;
1365 
1366   // Check for a register.  All real register operands should have used
1367   // a context-dependent parse routine, which gives the required register
1368   // class.  The code is here to mop up other cases, like those where
1369   // the instruction isn't recognized.
1370   if (Parser.getTok().is(AsmToken::Percent)) {
1371     Register Reg;
1372     if (parseRegister(Reg))
1373       return true;
1374     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1375     return false;
1376   }
1377 
1378   // The only other type of operand is an immediate or address.  As above,
1379   // real address operands should have used a context-dependent parse routine,
1380   // so we treat any plain expression as an immediate.
1381   SMLoc StartLoc = Parser.getTok().getLoc();
1382   Register Reg1, Reg2;
1383   bool HaveReg1, HaveReg2;
1384   const MCExpr *Expr;
1385   const MCExpr *Length;
1386   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1387                    /*HasLength*/ true, /*HasVectorIndex*/ true))
1388     return true;
1389   // If the register combination is not valid for any instruction, reject it.
1390   // Otherwise, fall back to reporting an unrecognized instruction.
1391   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1392       && parseAddressRegister(Reg1))
1393     return true;
1394   if (HaveReg2 && parseAddressRegister(Reg2))
1395     return true;
1396 
1397   SMLoc EndLoc =
1398     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1399   if (HaveReg1 || HaveReg2 || Length)
1400     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1401   else
1402     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1403   return false;
1404 }
1405 
1406 static std::string SystemZMnemonicSpellCheck(StringRef S,
1407                                              const FeatureBitset &FBS,
1408                                              unsigned VariantID = 0);
1409 
1410 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1411                                                OperandVector &Operands,
1412                                                MCStreamer &Out,
1413                                                uint64_t &ErrorInfo,
1414                                                bool MatchingInlineAsm) {
1415   MCInst Inst;
1416   unsigned MatchResult;
1417 
1418   FeatureBitset MissingFeatures;
1419   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1420                                      MissingFeatures, MatchingInlineAsm);
1421   switch (MatchResult) {
1422   case Match_Success:
1423     Inst.setLoc(IDLoc);
1424     Out.emitInstruction(Inst, getSTI());
1425     return false;
1426 
1427   case Match_MissingFeature: {
1428     assert(MissingFeatures.any() && "Unknown missing feature!");
1429     // Special case the error message for the very common case where only
1430     // a single subtarget feature is missing
1431     std::string Msg = "instruction requires:";
1432     for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1433       if (MissingFeatures[I]) {
1434         Msg += " ";
1435         Msg += getSubtargetFeatureName(I);
1436       }
1437     }
1438     return Error(IDLoc, Msg);
1439   }
1440 
1441   case Match_InvalidOperand: {
1442     SMLoc ErrorLoc = IDLoc;
1443     if (ErrorInfo != ~0ULL) {
1444       if (ErrorInfo >= Operands.size())
1445         return Error(IDLoc, "too few operands for instruction");
1446 
1447       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1448       if (ErrorLoc == SMLoc())
1449         ErrorLoc = IDLoc;
1450     }
1451     return Error(ErrorLoc, "invalid operand for instruction");
1452   }
1453 
1454   case Match_MnemonicFail: {
1455     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1456     std::string Suggestion = SystemZMnemonicSpellCheck(
1457       ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1458     return Error(IDLoc, "invalid instruction" + Suggestion,
1459                  ((SystemZOperand &)*Operands[0]).getLocRange());
1460   }
1461   }
1462 
1463   llvm_unreachable("Unexpected match type");
1464 }
1465 
1466 OperandMatchResultTy
1467 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1468                              int64_t MaxVal, bool AllowTLS) {
1469   MCContext &Ctx = getContext();
1470   MCStreamer &Out = getStreamer();
1471   const MCExpr *Expr;
1472   SMLoc StartLoc = Parser.getTok().getLoc();
1473   if (getParser().parseExpression(Expr))
1474     return MatchOperand_NoMatch;
1475 
1476   auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1477     if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1478       int64_t Value = CE->getValue();
1479       if ((Value & 1) || Value < MinVal || Value > MaxVal)
1480         return true;
1481     }
1482     return false;
1483   };
1484 
1485   // For consistency with the GNU assembler, treat immediates as offsets
1486   // from ".".
1487   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1488     if (isOutOfRangeConstant(CE)) {
1489       Error(StartLoc, "offset out of range");
1490       return MatchOperand_ParseFail;
1491     }
1492     int64_t Value = CE->getValue();
1493     MCSymbol *Sym = Ctx.createTempSymbol();
1494     Out.emitLabel(Sym);
1495     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1496                                                  Ctx);
1497     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1498   }
1499 
1500   // For consistency with the GNU assembler, conservatively assume that a
1501   // constant offset must by itself be within the given size range.
1502   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1503     if (isOutOfRangeConstant(BE->getLHS()) ||
1504         isOutOfRangeConstant(BE->getRHS())) {
1505       Error(StartLoc, "offset out of range");
1506       return MatchOperand_ParseFail;
1507     }
1508 
1509   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1510   const MCExpr *Sym = nullptr;
1511   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1512     Parser.Lex();
1513 
1514     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1515       Error(Parser.getTok().getLoc(), "unexpected token");
1516       return MatchOperand_ParseFail;
1517     }
1518 
1519     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1520     StringRef Name = Parser.getTok().getString();
1521     if (Name == "tls_gdcall")
1522       Kind = MCSymbolRefExpr::VK_TLSGD;
1523     else if (Name == "tls_ldcall")
1524       Kind = MCSymbolRefExpr::VK_TLSLDM;
1525     else {
1526       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1527       return MatchOperand_ParseFail;
1528     }
1529     Parser.Lex();
1530 
1531     if (Parser.getTok().isNot(AsmToken::Colon)) {
1532       Error(Parser.getTok().getLoc(), "unexpected token");
1533       return MatchOperand_ParseFail;
1534     }
1535     Parser.Lex();
1536 
1537     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1538       Error(Parser.getTok().getLoc(), "unexpected token");
1539       return MatchOperand_ParseFail;
1540     }
1541 
1542     StringRef Identifier = Parser.getTok().getString();
1543     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1544                                   Kind, Ctx);
1545     Parser.Lex();
1546   }
1547 
1548   SMLoc EndLoc =
1549     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1550 
1551   if (AllowTLS)
1552     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1553                                                     StartLoc, EndLoc));
1554   else
1555     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1556 
1557   return MatchOperand_Success;
1558 }
1559 
1560 // Force static initialization.
1561 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1562   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1563 }
1564