1 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines an instruction selector for the RISCV target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCV.h" 15 #include "MCTargetDesc/RISCVMCTargetDesc.h" 16 #include "RISCVTargetMachine.h" 17 #include "llvm/CodeGen/SelectionDAGISel.h" 18 #include "llvm/Support/Debug.h" 19 #include "llvm/Support/MathExtras.h" 20 #include "llvm/Support/raw_ostream.h" 21 using namespace llvm; 22 23 #define DEBUG_TYPE "riscv-isel" 24 25 // RISCV-specific code to select RISCV machine instructions for 26 // SelectionDAG operations. 27 namespace { 28 class RISCVDAGToDAGISel final : public SelectionDAGISel { 29 public: 30 explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) 31 : SelectionDAGISel(TargetMachine) {} 32 33 StringRef getPassName() const override { 34 return "RISCV DAG->DAG Pattern Instruction Selection"; 35 } 36 37 void Select(SDNode *Node) override; 38 39 // Include the pieces autogenerated from the target description. 40 #include "RISCVGenDAGISel.inc" 41 }; 42 } 43 44 void RISCVDAGToDAGISel::Select(SDNode *Node) { 45 // Dump information about the Node being selected. 46 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << "\n"); 47 48 // If we have a custom node, we have already selected 49 if (Node->isMachineOpcode()) { 50 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n"); 51 Node->setNodeId(-1); 52 return; 53 } 54 55 // Select the default instruction. 56 SelectCode(Node); 57 } 58 59 // This pass converts a legalized DAG into a RISCV-specific DAG, ready 60 // for instruction scheduling. 61 FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) { 62 return new RISCVDAGToDAGISel(TM); 63 } 64