1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// This file provides RISCV-specific target descriptions. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVMCTargetDesc.h" 15 #include "InstPrinter/RISCVInstPrinter.h" 16 #include "RISCVMCAsmInfo.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/MC/MCStreamer.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 #define GET_INSTRINFO_MC_DESC 27 #include "RISCVGenInstrInfo.inc" 28 29 #define GET_REGINFO_MC_DESC 30 #include "RISCVGenRegisterInfo.inc" 31 32 using namespace llvm; 33 34 static MCInstrInfo *createRISCVMCInstrInfo() { 35 MCInstrInfo *X = new MCInstrInfo(); 36 InitRISCVMCInstrInfo(X); 37 return X; 38 } 39 40 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { 41 MCRegisterInfo *X = new MCRegisterInfo(); 42 InitRISCVMCRegisterInfo(X, RISCV::X1_32); 43 return X; 44 } 45 46 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, 47 const Triple &TT) { 48 return new RISCVMCAsmInfo(TT); 49 } 50 51 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, 52 unsigned SyntaxVariant, 53 const MCAsmInfo &MAI, 54 const MCInstrInfo &MII, 55 const MCRegisterInfo &MRI) { 56 return new RISCVInstPrinter(MAI, MII, MRI); 57 } 58 59 extern "C" void LLVMInitializeRISCVTargetMC() { 60 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { 61 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); 62 TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); 63 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); 64 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); 65 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); 66 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); 67 } 68 } 69