1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVELFStreamer.h"
15 #include "RISCVInstPrinter.h"
16 #include "RISCVMCAsmInfo.h"
17 #include "RISCVTargetStreamer.h"
18 #include "TargetInfo/RISCVTargetInfo.h"
19 #include "Utils/RISCVBaseInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/Register.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCInstrAnalysis.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/TargetRegistry.h"
30 
31 #define GET_INSTRINFO_MC_DESC
32 #include "RISCVGenInstrInfo.inc"
33 
34 #define GET_REGINFO_MC_DESC
35 #include "RISCVGenRegisterInfo.inc"
36 
37 #define GET_SUBTARGETINFO_MC_DESC
38 #include "RISCVGenSubtargetInfo.inc"
39 
40 using namespace llvm;
41 
42 static MCInstrInfo *createRISCVMCInstrInfo() {
43   MCInstrInfo *X = new MCInstrInfo();
44   InitRISCVMCInstrInfo(X);
45   return X;
46 }
47 
48 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
49   MCRegisterInfo *X = new MCRegisterInfo();
50   InitRISCVMCRegisterInfo(X, RISCV::X1);
51   return X;
52 }
53 
54 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
55                                        const Triple &TT,
56                                        const MCTargetOptions &Options) {
57   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
58 
59   Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
60   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
61   MAI->addInitialFrameState(Inst);
62 
63   return MAI;
64 }
65 
66 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
67                                                    StringRef CPU, StringRef FS) {
68   std::string CPUName = std::string(CPU);
69   if (CPUName.empty())
70     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
71   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
72 }
73 
74 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
75                                                unsigned SyntaxVariant,
76                                                const MCAsmInfo &MAI,
77                                                const MCInstrInfo &MII,
78                                                const MCRegisterInfo &MRI) {
79   return new RISCVInstPrinter(MAI, MII, MRI);
80 }
81 
82 static MCTargetStreamer *
83 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
84   const Triple &TT = STI.getTargetTriple();
85   if (TT.isOSBinFormatELF())
86     return new RISCVTargetELFStreamer(S, STI);
87   return nullptr;
88 }
89 
90 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
91                                                       formatted_raw_ostream &OS,
92                                                       MCInstPrinter *InstPrint,
93                                                       bool isVerboseAsm) {
94   return new RISCVTargetAsmStreamer(S, OS);
95 }
96 
97 namespace {
98 
99 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
100 public:
101   explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
102       : MCInstrAnalysis(Info) {}
103 
104   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
105                       uint64_t &Target) const override {
106     if (isConditionalBranch(Inst)) {
107       int64_t Imm;
108       if (Size == 2)
109         Imm = Inst.getOperand(1).getImm();
110       else
111         Imm = Inst.getOperand(2).getImm();
112       Target = Addr + Imm;
113       return true;
114     }
115 
116     if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
117       Target = Addr + Inst.getOperand(0).getImm();
118       return true;
119     }
120 
121     if (Inst.getOpcode() == RISCV::JAL) {
122       Target = Addr + Inst.getOperand(1).getImm();
123       return true;
124     }
125 
126     return false;
127   }
128 };
129 
130 } // end anonymous namespace
131 
132 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
133   return new RISCVMCInstrAnalysis(Info);
134 }
135 
136 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
137   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
138     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
139     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
140     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
141     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
142     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
143     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
144     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
145     TargetRegistry::RegisterObjectTargetStreamer(
146         *T, createRISCVObjectTargetStreamer);
147     TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
148 
149     // Register the asm target streamer.
150     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
151   }
152 }
153