1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVELFStreamer.h"
15 #include "RISCVInstPrinter.h"
16 #include "RISCVMCAsmInfo.h"
17 #include "RISCVTargetStreamer.h"
18 #include "TargetInfo/RISCVTargetInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
28 
29 #define GET_INSTRINFO_MC_DESC
30 #include "RISCVGenInstrInfo.inc"
31 
32 #define GET_REGINFO_MC_DESC
33 #include "RISCVGenRegisterInfo.inc"
34 
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "RISCVGenSubtargetInfo.inc"
37 
38 using namespace llvm;
39 
40 static MCInstrInfo *createRISCVMCInstrInfo() {
41   MCInstrInfo *X = new MCInstrInfo();
42   InitRISCVMCInstrInfo(X);
43   return X;
44 }
45 
46 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
47   MCRegisterInfo *X = new MCRegisterInfo();
48   InitRISCVMCRegisterInfo(X, RISCV::X1);
49   return X;
50 }
51 
52 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
53                                        const Triple &TT) {
54   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
55 
56   Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
57   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
58   MAI->addInitialFrameState(Inst);
59 
60   return MAI;
61 }
62 
63 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
64                                                    StringRef CPU, StringRef FS) {
65   std::string CPUName = CPU;
66   if (CPUName.empty())
67     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
68   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
69 }
70 
71 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
72                                                unsigned SyntaxVariant,
73                                                const MCAsmInfo &MAI,
74                                                const MCInstrInfo &MII,
75                                                const MCRegisterInfo &MRI) {
76   return new RISCVInstPrinter(MAI, MII, MRI);
77 }
78 
79 static MCTargetStreamer *
80 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
81   const Triple &TT = STI.getTargetTriple();
82   if (TT.isOSBinFormatELF())
83     return new RISCVTargetELFStreamer(S, STI);
84   return nullptr;
85 }
86 
87 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
88                                                       formatted_raw_ostream &OS,
89                                                       MCInstPrinter *InstPrint,
90                                                       bool isVerboseAsm) {
91   return new RISCVTargetAsmStreamer(S, OS);
92 }
93 
94 extern "C" void LLVMInitializeRISCVTargetMC() {
95   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
96     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
97     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
98     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
99     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
100     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
101     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
102     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
103     TargetRegistry::RegisterObjectTargetStreamer(
104         *T, createRISCVObjectTargetStreamer);
105 
106     // Register the asm target streamer.
107     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
108   }
109 }
110