1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVInstPrinter.h"
17 #include "RISCVMCAsmInfo.h"
18 #include "RISCVMCObjectFileInfo.h"
19 #include "RISCVTargetStreamer.h"
20 #include "TargetInfo/RISCVTargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/MC/MCAsmBackend.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCCodeEmitter.h"
25 #include "llvm/MC/MCInstrAnalysis.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCObjectFileInfo.h"
28 #include "llvm/MC/MCObjectWriter.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/MC/TargetRegistry.h"
33 #include "llvm/Support/ErrorHandling.h"
34 
35 #define GET_INSTRINFO_MC_DESC
36 #include "RISCVGenInstrInfo.inc"
37 
38 #define GET_REGINFO_MC_DESC
39 #include "RISCVGenRegisterInfo.inc"
40 
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "RISCVGenSubtargetInfo.inc"
43 
44 using namespace llvm;
45 
46 static MCInstrInfo *createRISCVMCInstrInfo() {
47   MCInstrInfo *X = new MCInstrInfo();
48   InitRISCVMCInstrInfo(X);
49   return X;
50 }
51 
52 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
53   MCRegisterInfo *X = new MCRegisterInfo();
54   InitRISCVMCRegisterInfo(X, RISCV::X1);
55   return X;
56 }
57 
58 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
59                                        const Triple &TT,
60                                        const MCTargetOptions &Options) {
61   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
62 
63   MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
64   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
65   MAI->addInitialFrameState(Inst);
66 
67   return MAI;
68 }
69 
70 static MCObjectFileInfo *
71 createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
72                             bool LargeCodeModel = false) {
73   MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo();
74   MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
75   return MOFI;
76 }
77 
78 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
79                                                    StringRef CPU, StringRef FS) {
80   if (CPU.empty() || CPU == "generic")
81     CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
82 
83   return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
84 }
85 
86 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
87                                                unsigned SyntaxVariant,
88                                                const MCAsmInfo &MAI,
89                                                const MCInstrInfo &MII,
90                                                const MCRegisterInfo &MRI) {
91   return new RISCVInstPrinter(MAI, MII, MRI);
92 }
93 
94 static MCTargetStreamer *
95 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
96   const Triple &TT = STI.getTargetTriple();
97   if (TT.isOSBinFormatELF())
98     return new RISCVTargetELFStreamer(S, STI);
99   return nullptr;
100 }
101 
102 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
103                                                       formatted_raw_ostream &OS,
104                                                       MCInstPrinter *InstPrint,
105                                                       bool isVerboseAsm) {
106   return new RISCVTargetAsmStreamer(S, OS);
107 }
108 
109 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
110   return new RISCVTargetStreamer(S);
111 }
112 
113 namespace {
114 
115 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
116 public:
117   explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
118       : MCInstrAnalysis(Info) {}
119 
120   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
121                       uint64_t &Target) const override {
122     if (isConditionalBranch(Inst)) {
123       int64_t Imm;
124       if (Size == 2)
125         Imm = Inst.getOperand(1).getImm();
126       else
127         Imm = Inst.getOperand(2).getImm();
128       Target = Addr + Imm;
129       return true;
130     }
131 
132     if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
133       Target = Addr + Inst.getOperand(0).getImm();
134       return true;
135     }
136 
137     if (Inst.getOpcode() == RISCV::JAL) {
138       Target = Addr + Inst.getOperand(1).getImm();
139       return true;
140     }
141 
142     return false;
143   }
144 };
145 
146 } // end anonymous namespace
147 
148 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
149   return new RISCVMCInstrAnalysis(Info);
150 }
151 
152 namespace {
153 MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context,
154                                    std::unique_ptr<MCAsmBackend> &&MAB,
155                                    std::unique_ptr<MCObjectWriter> &&MOW,
156                                    std::unique_ptr<MCCodeEmitter> &&MCE,
157                                    bool RelaxAll) {
158   return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
159                                 std::move(MCE), RelaxAll);
160 }
161 } // end anonymous namespace
162 
163 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
164   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
165     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
166     TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo);
167     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
168     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
169     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
170     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
171     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
172     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
173     TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
174     TargetRegistry::RegisterObjectTargetStreamer(
175         *T, createRISCVObjectTargetStreamer);
176     TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
177 
178     // Register the asm target streamer.
179     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
180     // Register the null target streamer.
181     TargetRegistry::RegisterNullTargetStreamer(*T,
182                                                createRISCVNullTargetStreamer);
183   }
184 }
185