1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// This file provides RISCV-specific target descriptions.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVMCTargetDesc.h"
15 #include "InstPrinter/RISCVInstPrinter.h"
16 #include "RISCVMCAsmInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 
26 #define GET_INSTRINFO_MC_DESC
27 #include "RISCVGenInstrInfo.inc"
28 
29 #define GET_REGINFO_MC_DESC
30 #include "RISCVGenRegisterInfo.inc"
31 
32 #define GET_SUBTARGETINFO_MC_DESC
33 #include "RISCVGenSubtargetInfo.inc"
34 
35 using namespace llvm;
36 
37 static MCInstrInfo *createRISCVMCInstrInfo() {
38   MCInstrInfo *X = new MCInstrInfo();
39   InitRISCVMCInstrInfo(X);
40   return X;
41 }
42 
43 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
44   MCRegisterInfo *X = new MCRegisterInfo();
45   InitRISCVMCRegisterInfo(X, RISCV::X1);
46   return X;
47 }
48 
49 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
50                                        const Triple &TT) {
51   return new RISCVMCAsmInfo(TT);
52 }
53 
54 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
55                                                    StringRef CPU, StringRef FS) {
56   std::string CPUName = CPU;
57   if (CPUName.empty())
58     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
59   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
60 }
61 
62 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
63                                                unsigned SyntaxVariant,
64                                                const MCAsmInfo &MAI,
65                                                const MCInstrInfo &MII,
66                                                const MCRegisterInfo &MRI) {
67   return new RISCVInstPrinter(MAI, MII, MRI);
68 }
69 
70 extern "C" void LLVMInitializeRISCVTargetMC() {
71   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
72     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
73     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
74     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
75     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
76     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
77     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
78     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
79   }
80 }
81