1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This file provides RISCV-specific target descriptions.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVMCTargetDesc.h"
14 #include "InstPrinter/RISCVInstPrinter.h"
15 #include "RISCVELFStreamer.h"
16 #include "RISCVMCAsmInfo.h"
17 #include "RISCVTargetStreamer.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 
27 #define GET_INSTRINFO_MC_DESC
28 #include "RISCVGenInstrInfo.inc"
29 
30 #define GET_REGINFO_MC_DESC
31 #include "RISCVGenRegisterInfo.inc"
32 
33 #define GET_SUBTARGETINFO_MC_DESC
34 #include "RISCVGenSubtargetInfo.inc"
35 
36 using namespace llvm;
37 
38 static MCInstrInfo *createRISCVMCInstrInfo() {
39   MCInstrInfo *X = new MCInstrInfo();
40   InitRISCVMCInstrInfo(X);
41   return X;
42 }
43 
44 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
45   MCRegisterInfo *X = new MCRegisterInfo();
46   InitRISCVMCRegisterInfo(X, RISCV::X1);
47   return X;
48 }
49 
50 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
51                                        const Triple &TT) {
52   return new RISCVMCAsmInfo(TT);
53 }
54 
55 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
56                                                    StringRef CPU, StringRef FS) {
57   std::string CPUName = CPU;
58   if (CPUName.empty())
59     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
60   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
61 }
62 
63 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
64                                                unsigned SyntaxVariant,
65                                                const MCAsmInfo &MAI,
66                                                const MCInstrInfo &MII,
67                                                const MCRegisterInfo &MRI) {
68   return new RISCVInstPrinter(MAI, MII, MRI);
69 }
70 
71 static MCTargetStreamer *
72 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
73   const Triple &TT = STI.getTargetTriple();
74   if (TT.isOSBinFormatELF())
75     return new RISCVTargetELFStreamer(S, STI);
76   return nullptr;
77 }
78 
79 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
80                                                       formatted_raw_ostream &OS,
81                                                       MCInstPrinter *InstPrint,
82                                                       bool isVerboseAsm) {
83   return new RISCVTargetAsmStreamer(S, OS);
84 }
85 
86 extern "C" void LLVMInitializeRISCVTargetMC() {
87   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
88     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
89     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
90     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
91     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
92     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
93     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
94     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
95     TargetRegistry::RegisterObjectTargetStreamer(
96         *T, createRISCVObjectTargetStreamer);
97 
98     // Register the asm target streamer.
99     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
100   }
101 }
102