1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RISCVDisassembler class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/RISCVMCTargetDesc.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
17 #include "llvm/MC/MCFixedLenDisassembler.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/Endian.h"
22 #include "llvm/Support/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "riscv-disassembler"
27 
28 typedef MCDisassembler::DecodeStatus DecodeStatus;
29 
30 namespace {
31 class RISCVDisassembler : public MCDisassembler {
32 
33 public:
34   RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
35       : MCDisassembler(STI, Ctx) {}
36 
37   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
38                               ArrayRef<uint8_t> Bytes, uint64_t Address,
39                               raw_ostream &VStream,
40                               raw_ostream &CStream) const override;
41 };
42 } // end anonymous namespace
43 
44 static MCDisassembler *createRISCVDisassembler(const Target &T,
45                                                const MCSubtargetInfo &STI,
46                                                MCContext &Ctx) {
47   return new RISCVDisassembler(STI, Ctx);
48 }
49 
50 extern "C" void LLVMInitializeRISCVDisassembler() {
51   // Register the disassembler for each target.
52   TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
53                                          createRISCVDisassembler);
54   TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
55                                          createRISCVDisassembler);
56 }
57 
58 static const unsigned GPRDecoderTable[] = {
59   RISCV::X0,  RISCV::X1,  RISCV::X2,  RISCV::X3,
60   RISCV::X4,  RISCV::X5,  RISCV::X6,  RISCV::X7,
61   RISCV::X8,  RISCV::X9,  RISCV::X10, RISCV::X11,
62   RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
63   RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
64   RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
65   RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
66   RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
67 };
68 
69 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
70                                            uint64_t Address,
71                                            const void *Decoder) {
72    if (RegNo > sizeof(GPRDecoderTable))
73      return MCDisassembler::Fail;
74 
75    // We must define our own mapping from RegNo to register identifier.
76    // Accessing index RegNo in the register class will work in the case that
77    // registers were added in ascending order, but not in general.
78    unsigned Reg = GPRDecoderTable[RegNo];
79    Inst.addOperand(MCOperand::createReg(Reg));
80    return MCDisassembler::Success;
81 }
82 
83 template <unsigned N>
84 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
85                                       int64_t Address, const void *Decoder) {
86   assert(isUInt<N>(Imm) && "Invalid immediate");
87   Inst.addOperand(MCOperand::createImm(Imm));
88   return MCDisassembler::Success;
89 }
90 
91 template <unsigned N>
92 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
93                                       int64_t Address, const void *Decoder) {
94   assert(isUInt<N>(Imm) && "Invalid immediate");
95   // Sign-extend the number in the bottom N bits of Imm
96   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
97   return MCDisassembler::Success;
98 }
99 
100 template <unsigned N>
101 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
102                                              int64_t Address,
103                                              const void *Decoder) {
104   assert(isUInt<N>(Imm) && "Invalid immediate");
105   // Sign-extend the number in the bottom N bits of Imm after accounting for
106   // the fact that the N bit immediate is stored in N-1 bits (the LSB is
107   // always zero)
108   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
109   return MCDisassembler::Success;
110 }
111 
112 #include "RISCVGenDisassemblerTables.inc"
113 
114 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
115                                                ArrayRef<uint8_t> Bytes,
116                                                uint64_t Address,
117                                                raw_ostream &OS,
118                                                raw_ostream &CS) const {
119   // TODO: although assuming 4-byte instructions is sufficient for RV32 and
120   // RV64, this will need modification when supporting the compressed
121   // instruction set extension (RVC) which uses 16-bit instructions. Other
122   // instruction set extensions have the option of defining instructions up to
123   // 176 bits wide.
124   Size = 4;
125   if (Bytes.size() < 4) {
126     Size = 0;
127     return MCDisassembler::Fail;
128   }
129 
130   // Get the four bytes of the instruction.
131   uint32_t Inst = support::endian::read32le(Bytes.data());
132 
133   return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
134 }
135