1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetFrameLowering.h" 39 #include "llvm/Target/TargetInstrInfo.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 static cl::opt<bool> 52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 53 cl::desc("Enable use of a base pointer for complex stack frames")); 54 55 static cl::opt<bool> 56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 57 cl::desc("Force the use of a base pointer in every function")); 58 59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 63 Subtarget(ST) { 64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 73 74 // 64-bit 75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 80 } 81 82 /// getPointerRegClass - Return the register class to use to hold pointers. 83 /// This is used for addressing modes. 84 const TargetRegisterClass * 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 86 const { 87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 88 // when it checks for ZERO folding. 89 if (Kind == 1) { 90 if (Subtarget.isPPC64()) 91 return &PPC::G8RC_NOX0RegClass; 92 return &PPC::GPRC_NOR0RegClass; 93 } 94 95 if (Subtarget.isPPC64()) 96 return &PPC::G8RCRegClass; 97 return &PPC::GPRCRegClass; 98 } 99 100 const MCPhysReg* 101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 102 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 103 if (Subtarget.hasVSX()) 104 return CSR_64_AllRegs_VSX_SaveList; 105 if (Subtarget.hasAltivec()) 106 return CSR_64_AllRegs_Altivec_SaveList; 107 return CSR_64_AllRegs_SaveList; 108 } 109 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 112 CSR_Darwin64_Altivec_SaveList : 113 CSR_Darwin64_SaveList) : 114 (Subtarget.hasAltivec() ? 115 CSR_Darwin32_Altivec_SaveList : 116 CSR_Darwin32_SaveList); 117 118 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 119 CSR_SVR464_Altivec_SaveList : 120 CSR_SVR464_SaveList) : 121 (Subtarget.hasAltivec() ? 122 CSR_SVR432_Altivec_SaveList : 123 CSR_SVR432_SaveList); 124 } 125 126 const uint32_t* 127 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 128 if (CC == CallingConv::AnyReg) { 129 if (Subtarget.hasVSX()) 130 return CSR_64_AllRegs_VSX_RegMask; 131 if (Subtarget.hasAltivec()) 132 return CSR_64_AllRegs_Altivec_RegMask; 133 return CSR_64_AllRegs_RegMask; 134 } 135 136 if (Subtarget.isDarwinABI()) 137 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 138 CSR_Darwin64_Altivec_RegMask : 139 CSR_Darwin64_RegMask) : 140 (Subtarget.hasAltivec() ? 141 CSR_Darwin32_Altivec_RegMask : 142 CSR_Darwin32_RegMask); 143 144 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 145 CSR_SVR464_Altivec_RegMask : 146 CSR_SVR464_RegMask) : 147 (Subtarget.hasAltivec() ? 148 CSR_SVR432_Altivec_RegMask : 149 CSR_SVR432_RegMask); 150 } 151 152 const uint32_t* 153 PPCRegisterInfo::getNoPreservedMask() const { 154 return CSR_NoRegs_RegMask; 155 } 156 157 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 158 unsigned PseudoRegs[] = { PPC::ZERO, PPC::ZERO8, PPC::RM }; 159 for (unsigned i = 0, ie = array_lengthof(PseudoRegs); i != ie; ++i) { 160 unsigned Reg = PseudoRegs[i]; 161 Mask[Reg / 32] &= ~(1u << (Reg % 32)); 162 } 163 } 164 165 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 166 BitVector Reserved(getNumRegs()); 167 const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( 168 MF.getSubtarget().getFrameLowering()); 169 170 // The ZERO register is not really a register, but the representation of r0 171 // when used in instructions that treat r0 as the constant 0. 172 Reserved.set(PPC::ZERO); 173 Reserved.set(PPC::ZERO8); 174 175 // The FP register is also not really a register, but is the representation 176 // of the frame pointer register used by ISD::FRAMEADDR. 177 Reserved.set(PPC::FP); 178 Reserved.set(PPC::FP8); 179 180 // The BP register is also not really a register, but is the representation 181 // of the base pointer register used by setjmp. 182 Reserved.set(PPC::BP); 183 Reserved.set(PPC::BP8); 184 185 // The counter registers must be reserved so that counter-based loops can 186 // be correctly formed (and the mtctr instructions are not DCE'd). 187 Reserved.set(PPC::CTR); 188 Reserved.set(PPC::CTR8); 189 190 Reserved.set(PPC::R1); 191 Reserved.set(PPC::LR); 192 Reserved.set(PPC::LR8); 193 Reserved.set(PPC::RM); 194 195 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 196 Reserved.set(PPC::VRSAVE); 197 198 // The SVR4 ABI reserves r2 and r13 199 if (Subtarget.isSVR4ABI()) { 200 Reserved.set(PPC::R2); // System-reserved register 201 Reserved.set(PPC::R13); // Small Data Area pointer register 202 } 203 204 // On PPC64, r13 is the thread pointer. Never allocate this register. 205 if (Subtarget.isPPC64()) { 206 Reserved.set(PPC::R13); 207 208 Reserved.set(PPC::X1); 209 Reserved.set(PPC::X13); 210 211 if (PPCFI->needsFP(MF)) 212 Reserved.set(PPC::X31); 213 214 if (hasBasePointer(MF)) 215 Reserved.set(PPC::X30); 216 217 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 218 if (Subtarget.isSVR4ABI()) { 219 Reserved.set(PPC::X2); 220 } 221 } 222 223 if (PPCFI->needsFP(MF)) 224 Reserved.set(PPC::R31); 225 226 if (hasBasePointer(MF)) { 227 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 228 MF.getTarget().getRelocationModel() == Reloc::PIC_) 229 Reserved.set(PPC::R29); 230 else 231 Reserved.set(PPC::R30); 232 } 233 234 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 235 MF.getTarget().getRelocationModel() == Reloc::PIC_) 236 Reserved.set(PPC::R30); 237 238 // Reserve Altivec registers when Altivec is unavailable. 239 if (!Subtarget.hasAltivec()) 240 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 241 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 242 Reserved.set(*I); 243 244 return Reserved; 245 } 246 247 unsigned 248 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 249 MachineFunction &MF) const { 250 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 251 const unsigned DefaultSafety = 1; 252 253 switch (RC->getID()) { 254 default: 255 return 0; 256 case PPC::G8RC_NOX0RegClassID: 257 case PPC::GPRC_NOR0RegClassID: 258 case PPC::G8RCRegClassID: 259 case PPC::GPRCRegClassID: { 260 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 261 return 32 - FP - DefaultSafety; 262 } 263 case PPC::F8RCRegClassID: 264 case PPC::F4RCRegClassID: 265 case PPC::VRRCRegClassID: 266 case PPC::VFRCRegClassID: 267 case PPC::VSLRCRegClassID: 268 case PPC::VSHRCRegClassID: 269 return 32 - DefaultSafety; 270 case PPC::VSRCRegClassID: 271 case PPC::VSFRCRegClassID: 272 return 64 - DefaultSafety; 273 case PPC::CRRCRegClassID: 274 return 8 - DefaultSafety; 275 } 276 } 277 278 const TargetRegisterClass* 279 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const { 280 if (Subtarget.hasVSX()) { 281 // With VSX, we can inflate various sub-register classes to the full VSX 282 // register set. 283 284 if (RC == &PPC::F8RCRegClass) 285 return &PPC::VSFRCRegClass; 286 else if (RC == &PPC::VRRCRegClass) 287 return &PPC::VSRCRegClass; 288 } 289 290 return TargetRegisterInfo::getLargestLegalSuperClass(RC); 291 } 292 293 //===----------------------------------------------------------------------===// 294 // Stack Frame Processing methods 295 //===----------------------------------------------------------------------===// 296 297 /// lowerDynamicAlloc - Generate the code for allocating an object in the 298 /// current frame. The sequence of code with be in the general form 299 /// 300 /// addi R0, SP, \#frameSize ; get the address of the previous frame 301 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 302 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 303 /// 304 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 305 // Get the instruction. 306 MachineInstr &MI = *II; 307 // Get the instruction's basic block. 308 MachineBasicBlock &MBB = *MI.getParent(); 309 // Get the basic block's function. 310 MachineFunction &MF = *MBB.getParent(); 311 // Get the frame info. 312 MachineFrameInfo *MFI = MF.getFrameInfo(); 313 // Get the instruction info. 314 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 315 // Determine whether 64-bit pointers are used. 316 bool LP64 = Subtarget.isPPC64(); 317 DebugLoc dl = MI.getDebugLoc(); 318 319 // Get the maximum call stack size. 320 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 321 // Get the total frame size. 322 unsigned FrameSize = MFI->getStackSize(); 323 324 // Get stack alignments. 325 unsigned TargetAlign = MF.getTarget() 326 .getSubtargetImpl() 327 ->getFrameLowering() 328 ->getStackAlignment(); 329 unsigned MaxAlign = MFI->getMaxAlignment(); 330 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 331 "Maximum call-frame size not sufficiently aligned"); 332 333 // Determine the previous frame's address. If FrameSize can't be 334 // represented as 16 bits or we need special alignment, then we load the 335 // previous frame's address from 0(SP). Why not do an addis of the hi? 336 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 337 // Constructing the constant and adding would take 3 instructions. 338 // Fortunately, a frame greater than 32K is rare. 339 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 340 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 341 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 342 343 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 344 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 345 .addReg(PPC::R31) 346 .addImm(FrameSize); 347 } else if (LP64) { 348 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 349 .addImm(0) 350 .addReg(PPC::X1); 351 } else { 352 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 353 .addImm(0) 354 .addReg(PPC::R1); 355 } 356 357 bool KillNegSizeReg = MI.getOperand(1).isKill(); 358 unsigned NegSizeReg = MI.getOperand(1).getReg(); 359 360 // Grow the stack and update the stack pointer link, then determine the 361 // address of new allocated space. 362 if (LP64) { 363 if (MaxAlign > TargetAlign) { 364 unsigned UnalNegSizeReg = NegSizeReg; 365 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 366 367 // Unfortunately, there is no andi, only andi., and we can't insert that 368 // here because we might clobber cr0 while it is live. 369 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 370 .addImm(~(MaxAlign-1)); 371 372 unsigned NegSizeReg1 = NegSizeReg; 373 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 374 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 375 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 376 .addReg(NegSizeReg1, RegState::Kill); 377 KillNegSizeReg = true; 378 } 379 380 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 381 .addReg(Reg, RegState::Kill) 382 .addReg(PPC::X1) 383 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 384 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 385 .addReg(PPC::X1) 386 .addImm(maxCallFrameSize); 387 } else { 388 if (MaxAlign > TargetAlign) { 389 unsigned UnalNegSizeReg = NegSizeReg; 390 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 391 392 // Unfortunately, there is no andi, only andi., and we can't insert that 393 // here because we might clobber cr0 while it is live. 394 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 395 .addImm(~(MaxAlign-1)); 396 397 unsigned NegSizeReg1 = NegSizeReg; 398 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 399 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 400 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 401 .addReg(NegSizeReg1, RegState::Kill); 402 KillNegSizeReg = true; 403 } 404 405 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 406 .addReg(Reg, RegState::Kill) 407 .addReg(PPC::R1) 408 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 409 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 410 .addReg(PPC::R1) 411 .addImm(maxCallFrameSize); 412 } 413 414 // Discard the DYNALLOC instruction. 415 MBB.erase(II); 416 } 417 418 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 419 /// reserving a whole register (R0), we scrounge for one here. This generates 420 /// code like this: 421 /// 422 /// mfcr rA ; Move the conditional register into GPR rA. 423 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 424 /// stw rA, FI ; Store rA to the frame. 425 /// 426 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 427 unsigned FrameIndex) const { 428 // Get the instruction. 429 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 430 // Get the instruction's basic block. 431 MachineBasicBlock &MBB = *MI.getParent(); 432 MachineFunction &MF = *MBB.getParent(); 433 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 434 DebugLoc dl = MI.getDebugLoc(); 435 436 bool LP64 = Subtarget.isPPC64(); 437 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 438 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 439 440 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 441 unsigned SrcReg = MI.getOperand(0).getReg(); 442 443 // We need to store the CR in the low 4-bits of the saved value. First, issue 444 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 445 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 446 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 447 448 // If the saved register wasn't CR0, shift the bits left so that they are in 449 // CR0's slot. 450 if (SrcReg != PPC::CR0) { 451 unsigned Reg1 = Reg; 452 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 453 454 // rlwinm rA, rA, ShiftBits, 0, 31. 455 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 456 .addReg(Reg1, RegState::Kill) 457 .addImm(getEncodingValue(SrcReg) * 4) 458 .addImm(0) 459 .addImm(31); 460 } 461 462 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 463 .addReg(Reg, RegState::Kill), 464 FrameIndex); 465 466 // Discard the pseudo instruction. 467 MBB.erase(II); 468 } 469 470 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 471 unsigned FrameIndex) const { 472 // Get the instruction. 473 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 474 // Get the instruction's basic block. 475 MachineBasicBlock &MBB = *MI.getParent(); 476 MachineFunction &MF = *MBB.getParent(); 477 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 478 DebugLoc dl = MI.getDebugLoc(); 479 480 bool LP64 = Subtarget.isPPC64(); 481 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 482 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 483 484 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 485 unsigned DestReg = MI.getOperand(0).getReg(); 486 assert(MI.definesRegister(DestReg) && 487 "RESTORE_CR does not define its destination"); 488 489 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 490 Reg), FrameIndex); 491 492 // If the reloaded register isn't CR0, shift the bits right so that they are 493 // in the right CR's slot. 494 if (DestReg != PPC::CR0) { 495 unsigned Reg1 = Reg; 496 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 497 498 unsigned ShiftBits = getEncodingValue(DestReg)*4; 499 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 500 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 501 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 502 .addImm(31); 503 } 504 505 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 506 .addReg(Reg, RegState::Kill); 507 508 // Discard the pseudo instruction. 509 MBB.erase(II); 510 } 511 512 static unsigned getCRFromCRBit(unsigned SrcReg) { 513 unsigned Reg = 0; 514 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 515 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 516 Reg = PPC::CR0; 517 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 518 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 519 Reg = PPC::CR1; 520 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 521 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 522 Reg = PPC::CR2; 523 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 524 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 525 Reg = PPC::CR3; 526 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 527 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 528 Reg = PPC::CR4; 529 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 530 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 531 Reg = PPC::CR5; 532 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 533 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 534 Reg = PPC::CR6; 535 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 536 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 537 Reg = PPC::CR7; 538 539 assert(Reg != 0 && "Invalid CR bit register"); 540 return Reg; 541 } 542 543 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 544 unsigned FrameIndex) const { 545 // Get the instruction. 546 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 547 // Get the instruction's basic block. 548 MachineBasicBlock &MBB = *MI.getParent(); 549 MachineFunction &MF = *MBB.getParent(); 550 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 551 DebugLoc dl = MI.getDebugLoc(); 552 553 bool LP64 = Subtarget.isPPC64(); 554 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 555 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 556 557 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 558 unsigned SrcReg = MI.getOperand(0).getReg(); 559 560 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 561 getCRFromCRBit(SrcReg)) 562 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 563 564 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 565 .addReg(getCRFromCRBit(SrcReg)); 566 567 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 568 // store is the first one. Mask all but that bit. 569 unsigned Reg1 = Reg; 570 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 571 572 // rlwinm rA, rA, ShiftBits, 0, 0. 573 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 574 .addReg(Reg1, RegState::Kill) 575 .addImm(getEncodingValue(SrcReg)) 576 .addImm(0).addImm(0); 577 578 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 579 .addReg(Reg, RegState::Kill), 580 FrameIndex); 581 582 // Discard the pseudo instruction. 583 MBB.erase(II); 584 } 585 586 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 587 unsigned FrameIndex) const { 588 // Get the instruction. 589 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 590 // Get the instruction's basic block. 591 MachineBasicBlock &MBB = *MI.getParent(); 592 MachineFunction &MF = *MBB.getParent(); 593 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 594 DebugLoc dl = MI.getDebugLoc(); 595 596 bool LP64 = Subtarget.isPPC64(); 597 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 598 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 599 600 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 601 unsigned DestReg = MI.getOperand(0).getReg(); 602 assert(MI.definesRegister(DestReg) && 603 "RESTORE_CRBIT does not define its destination"); 604 605 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 606 Reg), FrameIndex); 607 608 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 609 610 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 611 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 612 .addReg(getCRFromCRBit(DestReg)); 613 614 unsigned ShiftBits = getEncodingValue(DestReg); 615 // rlwimi r11, r10, 32-ShiftBits, ..., ... 616 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 617 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 618 .addImm(ShiftBits ? 32-ShiftBits : 0) 619 .addImm(ShiftBits).addImm(ShiftBits); 620 621 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 622 getCRFromCRBit(DestReg)) 623 .addReg(RegO, RegState::Kill) 624 // Make sure we have a use dependency all the way through this 625 // sequence of instructions. We can't have the other bits in the CR 626 // modified in between the mfocrf and the mtocrf. 627 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 628 629 // Discard the pseudo instruction. 630 MBB.erase(II); 631 } 632 633 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 634 unsigned FrameIndex) const { 635 // Get the instruction. 636 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 637 // Get the instruction's basic block. 638 MachineBasicBlock &MBB = *MI.getParent(); 639 MachineFunction &MF = *MBB.getParent(); 640 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 641 DebugLoc dl = MI.getDebugLoc(); 642 643 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 644 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 645 unsigned SrcReg = MI.getOperand(0).getReg(); 646 647 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 648 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 649 650 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 651 .addReg(Reg, RegState::Kill), 652 FrameIndex); 653 654 // Discard the pseudo instruction. 655 MBB.erase(II); 656 } 657 658 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 659 unsigned FrameIndex) const { 660 // Get the instruction. 661 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 662 // Get the instruction's basic block. 663 MachineBasicBlock &MBB = *MI.getParent(); 664 MachineFunction &MF = *MBB.getParent(); 665 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 666 DebugLoc dl = MI.getDebugLoc(); 667 668 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 669 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 670 unsigned DestReg = MI.getOperand(0).getReg(); 671 assert(MI.definesRegister(DestReg) && 672 "RESTORE_VRSAVE does not define its destination"); 673 674 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 675 Reg), FrameIndex); 676 677 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 678 .addReg(Reg, RegState::Kill); 679 680 // Discard the pseudo instruction. 681 MBB.erase(II); 682 } 683 684 bool 685 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 686 unsigned Reg, int &FrameIdx) const { 687 688 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 689 // ABI, return true to prevent allocating an additional frame slot. 690 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 691 // is arbitrary and will be subsequently ignored. For 32-bit, we have 692 // previously created the stack slot if needed, so return its FrameIdx. 693 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 694 if (Subtarget.isPPC64()) 695 FrameIdx = 0; 696 else { 697 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 698 FrameIdx = FI->getCRSpillFrameIndex(); 699 } 700 return true; 701 } 702 return false; 703 } 704 705 // Figure out if the offset in the instruction must be a multiple of 4. 706 // This is true for instructions like "STD". 707 static bool usesIXAddr(const MachineInstr &MI) { 708 unsigned OpC = MI.getOpcode(); 709 710 switch (OpC) { 711 default: 712 return false; 713 case PPC::LWA: 714 case PPC::LWA_32: 715 case PPC::LD: 716 case PPC::STD: 717 return true; 718 } 719 } 720 721 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 722 static unsigned getOffsetONFromFION(const MachineInstr &MI, 723 unsigned FIOperandNum) { 724 // Take into account whether it's an add or mem instruction 725 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 726 if (MI.isInlineAsm()) 727 OffsetOperandNo = FIOperandNum - 1; 728 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 729 MI.getOpcode() == TargetOpcode::PATCHPOINT) 730 OffsetOperandNo = FIOperandNum + 1; 731 732 return OffsetOperandNo; 733 } 734 735 void 736 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 737 int SPAdj, unsigned FIOperandNum, 738 RegScavenger *RS) const { 739 assert(SPAdj == 0 && "Unexpected"); 740 741 // Get the instruction. 742 MachineInstr &MI = *II; 743 // Get the instruction's basic block. 744 MachineBasicBlock &MBB = *MI.getParent(); 745 // Get the basic block's function. 746 MachineFunction &MF = *MBB.getParent(); 747 // Get the instruction info. 748 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 749 // Get the frame info. 750 MachineFrameInfo *MFI = MF.getFrameInfo(); 751 DebugLoc dl = MI.getDebugLoc(); 752 753 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 754 755 // Get the frame index. 756 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 757 758 // Get the frame pointer save index. Users of this index are primarily 759 // DYNALLOC instructions. 760 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 761 int FPSI = FI->getFramePointerSaveIndex(); 762 // Get the instruction opcode. 763 unsigned OpC = MI.getOpcode(); 764 765 // Special case for dynamic alloca. 766 if (FPSI && FrameIndex == FPSI && 767 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 768 lowerDynamicAlloc(II); 769 return; 770 } 771 772 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 773 if (OpC == PPC::SPILL_CR) { 774 lowerCRSpilling(II, FrameIndex); 775 return; 776 } else if (OpC == PPC::RESTORE_CR) { 777 lowerCRRestore(II, FrameIndex); 778 return; 779 } else if (OpC == PPC::SPILL_CRBIT) { 780 lowerCRBitSpilling(II, FrameIndex); 781 return; 782 } else if (OpC == PPC::RESTORE_CRBIT) { 783 lowerCRBitRestore(II, FrameIndex); 784 return; 785 } else if (OpC == PPC::SPILL_VRSAVE) { 786 lowerVRSAVESpilling(II, FrameIndex); 787 return; 788 } else if (OpC == PPC::RESTORE_VRSAVE) { 789 lowerVRSAVERestore(II, FrameIndex); 790 return; 791 } 792 793 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 794 MI.getOperand(FIOperandNum).ChangeToRegister( 795 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 796 797 // Figure out if the offset in the instruction is shifted right two bits. 798 bool isIXAddr = usesIXAddr(MI); 799 800 // If the instruction is not present in ImmToIdxMap, then it has no immediate 801 // form (and must be r+r). 802 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 803 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 804 805 // Now add the frame object offset to the offset from r1. 806 int Offset = MFI->getObjectOffset(FrameIndex); 807 Offset += MI.getOperand(OffsetOperandNo).getImm(); 808 809 // If we're not using a Frame Pointer that has been set to the value of the 810 // SP before having the stack size subtracted from it, then add the stack size 811 // to Offset to get the correct offset. 812 // Naked functions have stack size 0, although getStackSize may not reflect that 813 // because we didn't call all the pieces that compute it for naked functions. 814 if (!MF.getFunction()->getAttributes(). 815 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) { 816 if (!(hasBasePointer(MF) && FrameIndex < 0)) 817 Offset += MFI->getStackSize(); 818 } 819 820 // If we can, encode the offset directly into the instruction. If this is a 821 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 822 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 823 // clear can be encoded. This is extremely uncommon, because normally you 824 // only "std" to a stack slot that is at least 4-byte aligned, but it can 825 // happen in invalid code. 826 assert(OpC != PPC::DBG_VALUE && 827 "This should be handled in a target-independent way"); 828 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 829 OpC == TargetOpcode::STACKMAP || 830 OpC == TargetOpcode::PATCHPOINT)) { 831 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 832 return; 833 } 834 835 // The offset doesn't fit into a single register, scavenge one to build the 836 // offset in. 837 838 bool is64Bit = Subtarget.isPPC64(); 839 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 840 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 841 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 842 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 843 SReg = MF.getRegInfo().createVirtualRegister(RC); 844 845 // Insert a set of rA with the full offset value before the ld, st, or add 846 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 847 .addImm(Offset >> 16); 848 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 849 .addReg(SRegHi, RegState::Kill) 850 .addImm(Offset); 851 852 // Convert into indexed form of the instruction: 853 // 854 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 855 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 856 unsigned OperandBase; 857 858 if (noImmForm) 859 OperandBase = 1; 860 else if (OpC != TargetOpcode::INLINEASM) { 861 assert(ImmToIdxMap.count(OpC) && 862 "No indexed form of load or store available!"); 863 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 864 MI.setDesc(TII.get(NewOpcode)); 865 OperandBase = 1; 866 } else { 867 OperandBase = OffsetOperandNo; 868 } 869 870 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 871 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 872 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 873 } 874 875 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 876 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 877 878 if (!Subtarget.isPPC64()) 879 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 880 else 881 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 882 } 883 884 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 885 if (!hasBasePointer(MF)) 886 return getFrameRegister(MF); 887 888 if (Subtarget.isPPC64()) 889 return PPC::X30; 890 891 if (Subtarget.isSVR4ABI() && 892 MF.getTarget().getRelocationModel() == Reloc::PIC_) 893 return PPC::R29; 894 895 return PPC::R30; 896 } 897 898 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 899 if (!EnableBasePointer) 900 return false; 901 if (AlwaysBasePointer) 902 return true; 903 904 // If we need to realign the stack, then the stack pointer can no longer 905 // serve as an offset into the caller's stack space. As a result, we need a 906 // base pointer. 907 return needsStackRealignment(MF); 908 } 909 910 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 911 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 912 return false; 913 914 return true; 915 } 916 917 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 918 const MachineFrameInfo *MFI = MF.getFrameInfo(); 919 const Function *F = MF.getFunction(); 920 unsigned StackAlign = MF.getTarget() 921 .getSubtargetImpl() 922 ->getFrameLowering() 923 ->getStackAlignment(); 924 bool requiresRealignment = 925 ((MFI->getMaxAlignment() > StackAlign) || 926 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 927 Attribute::StackAlignment)); 928 929 return requiresRealignment && canRealignStack(MF); 930 } 931 932 /// Returns true if the instruction's frame index 933 /// reference would be better served by a base register other than FP 934 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 935 /// references it should create new base registers for. 936 bool PPCRegisterInfo:: 937 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 938 assert(Offset < 0 && "Local offset must be negative"); 939 940 // It's the load/store FI references that cause issues, as it can be difficult 941 // to materialize the offset if it won't fit in the literal field. Estimate 942 // based on the size of the local frame and some conservative assumptions 943 // about the rest of the stack frame (note, this is pre-regalloc, so 944 // we don't know everything for certain yet) whether this offset is likely 945 // to be out of range of the immediate. Return true if so. 946 947 // We only generate virtual base registers for loads and stores that have 948 // an r+i form. Return false for everything else. 949 unsigned OpC = MI->getOpcode(); 950 if (!ImmToIdxMap.count(OpC)) 951 return false; 952 953 // Don't generate a new virtual base register just to add zero to it. 954 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 955 MI->getOperand(2).getImm() == 0) 956 return false; 957 958 MachineBasicBlock &MBB = *MI->getParent(); 959 MachineFunction &MF = *MBB.getParent(); 960 961 const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( 962 MF.getSubtarget().getFrameLowering()); 963 unsigned StackEst = 964 PPCFI->determineFrameLayout(MF, false, true); 965 966 // If we likely don't need a stack frame, then we probably don't need a 967 // virtual base register either. 968 if (!StackEst) 969 return false; 970 971 // Estimate an offset from the stack pointer. 972 // The incoming offset is relating to the SP at the start of the function, 973 // but when we access the local it'll be relative to the SP after local 974 // allocation, so adjust our SP-relative offset by that allocation size. 975 Offset += StackEst; 976 977 // The frame pointer will point to the end of the stack, so estimate the 978 // offset as the difference between the object offset and the FP location. 979 return !isFrameOffsetLegal(MI, Offset); 980 } 981 982 /// Insert defining instruction(s) for BaseReg to 983 /// be a pointer to FrameIdx at the beginning of the basic block. 984 void PPCRegisterInfo:: 985 materializeFrameBaseRegister(MachineBasicBlock *MBB, 986 unsigned BaseReg, int FrameIdx, 987 int64_t Offset) const { 988 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 989 990 MachineBasicBlock::iterator Ins = MBB->begin(); 991 DebugLoc DL; // Defaults to "unknown" 992 if (Ins != MBB->end()) 993 DL = Ins->getDebugLoc(); 994 995 const MachineFunction &MF = *MBB->getParent(); 996 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 997 const MCInstrDesc &MCID = TII.get(ADDriOpc); 998 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 999 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1000 1001 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1002 .addFrameIndex(FrameIdx).addImm(Offset); 1003 } 1004 1005 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 1006 int64_t Offset) const { 1007 unsigned FIOperandNum = 0; 1008 while (!MI.getOperand(FIOperandNum).isFI()) { 1009 ++FIOperandNum; 1010 assert(FIOperandNum < MI.getNumOperands() && 1011 "Instr doesn't have FrameIndex operand!"); 1012 } 1013 1014 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1015 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1016 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1017 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1018 1019 MachineBasicBlock &MBB = *MI.getParent(); 1020 MachineFunction &MF = *MBB.getParent(); 1021 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 1022 const MCInstrDesc &MCID = MI.getDesc(); 1023 MachineRegisterInfo &MRI = MF.getRegInfo(); 1024 MRI.constrainRegClass(BaseReg, 1025 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1026 } 1027 1028 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1029 int64_t Offset) const { 1030 unsigned FIOperandNum = 0; 1031 while (!MI->getOperand(FIOperandNum).isFI()) { 1032 ++FIOperandNum; 1033 assert(FIOperandNum < MI->getNumOperands() && 1034 "Instr doesn't have FrameIndex operand!"); 1035 } 1036 1037 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1038 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1039 1040 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1041 MI->getOpcode() == TargetOpcode::STACKMAP || 1042 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1043 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1044 } 1045 1046