1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/Type.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/Target/TargetFrameLowering.h" 40 #include "llvm/Target/TargetInstrInfo.h" 41 #include "llvm/Target/TargetMachine.h" 42 #include "llvm/Target/TargetOptions.h" 43 #include <cstdlib> 44 45 #define GET_REGINFO_TARGET_DESC 46 #include "PPCGenRegisterInfo.inc" 47 48 using namespace llvm; 49 50 static cl::opt<bool> 51 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 52 cl::desc("Enable use of a base pointer for complex stack frames")); 53 54 static cl::opt<bool> 55 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 56 cl::desc("Force the use of a base pointer in every function")); 57 58 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 59 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 60 ST.isPPC64() ? 0 : 1, 61 ST.isPPC64() ? 0 : 1), 62 Subtarget(ST) { 63 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 64 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 65 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 66 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 67 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 68 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 69 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 70 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 71 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 72 73 // 64-bit 74 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 75 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 76 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 77 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 78 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 79 } 80 81 /// getPointerRegClass - Return the register class to use to hold pointers. 82 /// This is used for addressing modes. 83 const TargetRegisterClass * 84 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 85 const { 86 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 87 // when it checks for ZERO folding. 88 if (Kind == 1) { 89 if (Subtarget.isPPC64()) 90 return &PPC::G8RC_NOX0RegClass; 91 return &PPC::GPRC_NOR0RegClass; 92 } 93 94 if (Subtarget.isPPC64()) 95 return &PPC::G8RCRegClass; 96 return &PPC::GPRCRegClass; 97 } 98 99 const uint16_t* 100 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 101 if (Subtarget.isDarwinABI()) 102 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 103 CSR_Darwin64_Altivec_SaveList : 104 CSR_Darwin64_SaveList) : 105 (Subtarget.hasAltivec() ? 106 CSR_Darwin32_Altivec_SaveList : 107 CSR_Darwin32_SaveList); 108 109 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 110 CSR_SVR464_Altivec_SaveList : 111 CSR_SVR464_SaveList) : 112 (Subtarget.hasAltivec() ? 113 CSR_SVR432_Altivec_SaveList : 114 CSR_SVR432_SaveList); 115 } 116 117 const uint32_t* 118 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 119 if (Subtarget.isDarwinABI()) 120 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 121 CSR_Darwin64_Altivec_RegMask : 122 CSR_Darwin64_RegMask) : 123 (Subtarget.hasAltivec() ? 124 CSR_Darwin32_Altivec_RegMask : 125 CSR_Darwin32_RegMask); 126 127 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 128 CSR_SVR464_Altivec_RegMask : 129 CSR_SVR464_RegMask) : 130 (Subtarget.hasAltivec() ? 131 CSR_SVR432_Altivec_RegMask : 132 CSR_SVR432_RegMask); 133 } 134 135 const uint32_t* 136 PPCRegisterInfo::getNoPreservedMask() const { 137 return CSR_NoRegs_RegMask; 138 } 139 140 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 141 BitVector Reserved(getNumRegs()); 142 const PPCFrameLowering *PPCFI = 143 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 144 145 // The ZERO register is not really a register, but the representation of r0 146 // when used in instructions that treat r0 as the constant 0. 147 Reserved.set(PPC::ZERO); 148 Reserved.set(PPC::ZERO8); 149 150 // The FP register is also not really a register, but is the representation 151 // of the frame pointer register used by ISD::FRAMEADDR. 152 Reserved.set(PPC::FP); 153 Reserved.set(PPC::FP8); 154 155 // The BP register is also not really a register, but is the representation 156 // of the base pointer register used by setjmp. 157 Reserved.set(PPC::BP); 158 Reserved.set(PPC::BP8); 159 160 // The counter registers must be reserved so that counter-based loops can 161 // be correctly formed (and the mtctr instructions are not DCE'd). 162 Reserved.set(PPC::CTR); 163 Reserved.set(PPC::CTR8); 164 165 Reserved.set(PPC::R1); 166 Reserved.set(PPC::LR); 167 Reserved.set(PPC::LR8); 168 Reserved.set(PPC::RM); 169 170 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 171 Reserved.set(PPC::VRSAVE); 172 173 // The SVR4 ABI reserves r2 and r13 174 if (Subtarget.isSVR4ABI()) { 175 Reserved.set(PPC::R2); // System-reserved register 176 Reserved.set(PPC::R13); // Small Data Area pointer register 177 } 178 179 // On PPC64, r13 is the thread pointer. Never allocate this register. 180 if (Subtarget.isPPC64()) { 181 Reserved.set(PPC::R13); 182 183 Reserved.set(PPC::X1); 184 Reserved.set(PPC::X13); 185 186 if (PPCFI->needsFP(MF)) 187 Reserved.set(PPC::X31); 188 189 if (hasBasePointer(MF)) 190 Reserved.set(PPC::X30); 191 192 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 193 if (Subtarget.isSVR4ABI()) { 194 Reserved.set(PPC::X2); 195 } 196 } 197 198 if (PPCFI->needsFP(MF)) 199 Reserved.set(PPC::R31); 200 201 if (hasBasePointer(MF)) 202 Reserved.set(PPC::R30); 203 204 // Reserve Altivec registers when Altivec is unavailable. 205 if (!Subtarget.hasAltivec()) 206 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 207 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 208 Reserved.set(*I); 209 210 return Reserved; 211 } 212 213 unsigned 214 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 215 MachineFunction &MF) const { 216 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 217 const unsigned DefaultSafety = 1; 218 219 switch (RC->getID()) { 220 default: 221 return 0; 222 case PPC::G8RC_NOX0RegClassID: 223 case PPC::GPRC_NOR0RegClassID: 224 case PPC::G8RCRegClassID: 225 case PPC::GPRCRegClassID: { 226 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 227 return 32 - FP - DefaultSafety; 228 } 229 case PPC::F8RCRegClassID: 230 case PPC::F4RCRegClassID: 231 case PPC::VRRCRegClassID: 232 case PPC::VSLRCRegClassID: 233 case PPC::VSHRCRegClassID: 234 return 32 - DefaultSafety; 235 case PPC::VSRCRegClassID: 236 return 64 - DefaultSafety; 237 case PPC::CRRCRegClassID: 238 return 8 - DefaultSafety; 239 } 240 } 241 242 //===----------------------------------------------------------------------===// 243 // Stack Frame Processing methods 244 //===----------------------------------------------------------------------===// 245 246 /// lowerDynamicAlloc - Generate the code for allocating an object in the 247 /// current frame. The sequence of code with be in the general form 248 /// 249 /// addi R0, SP, \#frameSize ; get the address of the previous frame 250 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 251 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 252 /// 253 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 254 // Get the instruction. 255 MachineInstr &MI = *II; 256 // Get the instruction's basic block. 257 MachineBasicBlock &MBB = *MI.getParent(); 258 // Get the basic block's function. 259 MachineFunction &MF = *MBB.getParent(); 260 // Get the frame info. 261 MachineFrameInfo *MFI = MF.getFrameInfo(); 262 // Get the instruction info. 263 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 264 // Determine whether 64-bit pointers are used. 265 bool LP64 = Subtarget.isPPC64(); 266 DebugLoc dl = MI.getDebugLoc(); 267 268 // Get the maximum call stack size. 269 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 270 // Get the total frame size. 271 unsigned FrameSize = MFI->getStackSize(); 272 273 // Get stack alignments. 274 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 275 unsigned MaxAlign = MFI->getMaxAlignment(); 276 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 277 "Maximum call-frame size not sufficiently aligned"); 278 279 // Determine the previous frame's address. If FrameSize can't be 280 // represented as 16 bits or we need special alignment, then we load the 281 // previous frame's address from 0(SP). Why not do an addis of the hi? 282 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 283 // Constructing the constant and adding would take 3 instructions. 284 // Fortunately, a frame greater than 32K is rare. 285 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 286 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 287 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 288 289 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 290 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 291 .addReg(PPC::R31) 292 .addImm(FrameSize); 293 } else if (LP64) { 294 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 295 .addImm(0) 296 .addReg(PPC::X1); 297 } else { 298 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 299 .addImm(0) 300 .addReg(PPC::R1); 301 } 302 303 bool KillNegSizeReg = MI.getOperand(1).isKill(); 304 unsigned NegSizeReg = MI.getOperand(1).getReg(); 305 306 // Grow the stack and update the stack pointer link, then determine the 307 // address of new allocated space. 308 if (LP64) { 309 if (MaxAlign > TargetAlign) { 310 unsigned UnalNegSizeReg = NegSizeReg; 311 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 312 313 // Unfortunately, there is no andi, only andi., and we can't insert that 314 // here because we might clobber cr0 while it is live. 315 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 316 .addImm(~(MaxAlign-1)); 317 318 unsigned NegSizeReg1 = NegSizeReg; 319 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 320 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 321 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 322 .addReg(NegSizeReg1, RegState::Kill); 323 KillNegSizeReg = true; 324 } 325 326 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 327 .addReg(Reg, RegState::Kill) 328 .addReg(PPC::X1) 329 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 330 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 331 .addReg(PPC::X1) 332 .addImm(maxCallFrameSize); 333 } else { 334 if (MaxAlign > TargetAlign) { 335 unsigned UnalNegSizeReg = NegSizeReg; 336 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 337 338 // Unfortunately, there is no andi, only andi., and we can't insert that 339 // here because we might clobber cr0 while it is live. 340 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 341 .addImm(~(MaxAlign-1)); 342 343 unsigned NegSizeReg1 = NegSizeReg; 344 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 345 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 346 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 347 .addReg(NegSizeReg1, RegState::Kill); 348 KillNegSizeReg = true; 349 } 350 351 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 352 .addReg(Reg, RegState::Kill) 353 .addReg(PPC::R1) 354 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 355 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 356 .addReg(PPC::R1) 357 .addImm(maxCallFrameSize); 358 } 359 360 // Discard the DYNALLOC instruction. 361 MBB.erase(II); 362 } 363 364 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 365 /// reserving a whole register (R0), we scrounge for one here. This generates 366 /// code like this: 367 /// 368 /// mfcr rA ; Move the conditional register into GPR rA. 369 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 370 /// stw rA, FI ; Store rA to the frame. 371 /// 372 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 373 unsigned FrameIndex) const { 374 // Get the instruction. 375 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 376 // Get the instruction's basic block. 377 MachineBasicBlock &MBB = *MI.getParent(); 378 MachineFunction &MF = *MBB.getParent(); 379 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 380 DebugLoc dl = MI.getDebugLoc(); 381 382 bool LP64 = Subtarget.isPPC64(); 383 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 384 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 385 386 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 387 unsigned SrcReg = MI.getOperand(0).getReg(); 388 389 // We need to store the CR in the low 4-bits of the saved value. First, issue 390 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 391 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 392 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 393 394 // If the saved register wasn't CR0, shift the bits left so that they are in 395 // CR0's slot. 396 if (SrcReg != PPC::CR0) { 397 unsigned Reg1 = Reg; 398 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 399 400 // rlwinm rA, rA, ShiftBits, 0, 31. 401 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 402 .addReg(Reg1, RegState::Kill) 403 .addImm(getEncodingValue(SrcReg) * 4) 404 .addImm(0) 405 .addImm(31); 406 } 407 408 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 409 .addReg(Reg, RegState::Kill), 410 FrameIndex); 411 412 // Discard the pseudo instruction. 413 MBB.erase(II); 414 } 415 416 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 417 unsigned FrameIndex) const { 418 // Get the instruction. 419 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 420 // Get the instruction's basic block. 421 MachineBasicBlock &MBB = *MI.getParent(); 422 MachineFunction &MF = *MBB.getParent(); 423 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 424 DebugLoc dl = MI.getDebugLoc(); 425 426 bool LP64 = Subtarget.isPPC64(); 427 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 428 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 429 430 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 431 unsigned DestReg = MI.getOperand(0).getReg(); 432 assert(MI.definesRegister(DestReg) && 433 "RESTORE_CR does not define its destination"); 434 435 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 436 Reg), FrameIndex); 437 438 // If the reloaded register isn't CR0, shift the bits right so that they are 439 // in the right CR's slot. 440 if (DestReg != PPC::CR0) { 441 unsigned Reg1 = Reg; 442 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 443 444 unsigned ShiftBits = getEncodingValue(DestReg)*4; 445 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 446 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 447 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 448 .addImm(31); 449 } 450 451 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 452 .addReg(Reg, RegState::Kill); 453 454 // Discard the pseudo instruction. 455 MBB.erase(II); 456 } 457 458 static unsigned getCRFromCRBit(unsigned SrcReg) { 459 unsigned Reg = 0; 460 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 461 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 462 Reg = PPC::CR0; 463 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 464 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 465 Reg = PPC::CR1; 466 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 467 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 468 Reg = PPC::CR2; 469 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 470 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 471 Reg = PPC::CR3; 472 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 473 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 474 Reg = PPC::CR4; 475 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 476 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 477 Reg = PPC::CR5; 478 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 479 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 480 Reg = PPC::CR6; 481 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 482 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 483 Reg = PPC::CR7; 484 485 assert(Reg != 0 && "Invalid CR bit register"); 486 return Reg; 487 } 488 489 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 490 unsigned FrameIndex) const { 491 // Get the instruction. 492 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 493 // Get the instruction's basic block. 494 MachineBasicBlock &MBB = *MI.getParent(); 495 MachineFunction &MF = *MBB.getParent(); 496 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 497 DebugLoc dl = MI.getDebugLoc(); 498 499 bool LP64 = Subtarget.isPPC64(); 500 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 501 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 502 503 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 504 unsigned SrcReg = MI.getOperand(0).getReg(); 505 506 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 507 getCRFromCRBit(SrcReg)) 508 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 509 510 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 511 .addReg(getCRFromCRBit(SrcReg)); 512 513 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 514 // store is the first one. Mask all but that bit. 515 unsigned Reg1 = Reg; 516 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 517 518 // rlwinm rA, rA, ShiftBits, 0, 0. 519 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 520 .addReg(Reg1, RegState::Kill) 521 .addImm(getEncodingValue(SrcReg)) 522 .addImm(0).addImm(0); 523 524 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 525 .addReg(Reg, RegState::Kill), 526 FrameIndex); 527 528 // Discard the pseudo instruction. 529 MBB.erase(II); 530 } 531 532 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 533 unsigned FrameIndex) const { 534 // Get the instruction. 535 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 536 // Get the instruction's basic block. 537 MachineBasicBlock &MBB = *MI.getParent(); 538 MachineFunction &MF = *MBB.getParent(); 539 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 540 DebugLoc dl = MI.getDebugLoc(); 541 542 bool LP64 = Subtarget.isPPC64(); 543 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 544 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 545 546 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 547 unsigned DestReg = MI.getOperand(0).getReg(); 548 assert(MI.definesRegister(DestReg) && 549 "RESTORE_CRBIT does not define its destination"); 550 551 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 552 Reg), FrameIndex); 553 554 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 555 556 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 557 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 558 .addReg(getCRFromCRBit(DestReg)); 559 560 unsigned ShiftBits = getEncodingValue(DestReg); 561 // rlwimi r11, r10, 32-ShiftBits, ..., ... 562 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 563 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 564 .addImm(ShiftBits ? 32-ShiftBits : 0) 565 .addImm(ShiftBits).addImm(ShiftBits); 566 567 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 568 getCRFromCRBit(DestReg)) 569 .addReg(RegO, RegState::Kill) 570 // Make sure we have a use dependency all the way through this 571 // sequence of instructions. We can't have the other bits in the CR 572 // modified in between the mfocrf and the mtocrf. 573 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 574 575 // Discard the pseudo instruction. 576 MBB.erase(II); 577 } 578 579 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 580 unsigned FrameIndex) const { 581 // Get the instruction. 582 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 583 // Get the instruction's basic block. 584 MachineBasicBlock &MBB = *MI.getParent(); 585 MachineFunction &MF = *MBB.getParent(); 586 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 587 DebugLoc dl = MI.getDebugLoc(); 588 589 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 590 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 591 unsigned SrcReg = MI.getOperand(0).getReg(); 592 593 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 594 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 595 596 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 597 .addReg(Reg, RegState::Kill), 598 FrameIndex); 599 600 // Discard the pseudo instruction. 601 MBB.erase(II); 602 } 603 604 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 605 unsigned FrameIndex) const { 606 // Get the instruction. 607 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 608 // Get the instruction's basic block. 609 MachineBasicBlock &MBB = *MI.getParent(); 610 MachineFunction &MF = *MBB.getParent(); 611 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 612 DebugLoc dl = MI.getDebugLoc(); 613 614 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 615 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 616 unsigned DestReg = MI.getOperand(0).getReg(); 617 assert(MI.definesRegister(DestReg) && 618 "RESTORE_VRSAVE does not define its destination"); 619 620 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 621 Reg), FrameIndex); 622 623 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 624 .addReg(Reg, RegState::Kill); 625 626 // Discard the pseudo instruction. 627 MBB.erase(II); 628 } 629 630 bool 631 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 632 unsigned Reg, int &FrameIdx) const { 633 634 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 635 // ABI, return true to prevent allocating an additional frame slot. 636 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 637 // is arbitrary and will be subsequently ignored. For 32-bit, we have 638 // previously created the stack slot if needed, so return its FrameIdx. 639 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 640 if (Subtarget.isPPC64()) 641 FrameIdx = 0; 642 else { 643 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 644 FrameIdx = FI->getCRSpillFrameIndex(); 645 } 646 return true; 647 } 648 return false; 649 } 650 651 // Figure out if the offset in the instruction must be a multiple of 4. 652 // This is true for instructions like "STD". 653 static bool usesIXAddr(const MachineInstr &MI) { 654 unsigned OpC = MI.getOpcode(); 655 656 switch (OpC) { 657 default: 658 return false; 659 case PPC::LWA: 660 case PPC::LWA_32: 661 case PPC::LD: 662 case PPC::STD: 663 return true; 664 } 665 } 666 667 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 668 static unsigned getOffsetONFromFION(const MachineInstr &MI, 669 unsigned FIOperandNum) { 670 // Take into account whether it's an add or mem instruction 671 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 672 if (MI.isInlineAsm()) 673 OffsetOperandNo = FIOperandNum-1; 674 675 return OffsetOperandNo; 676 } 677 678 void 679 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 680 int SPAdj, unsigned FIOperandNum, 681 RegScavenger *RS) const { 682 assert(SPAdj == 0 && "Unexpected"); 683 684 // Get the instruction. 685 MachineInstr &MI = *II; 686 // Get the instruction's basic block. 687 MachineBasicBlock &MBB = *MI.getParent(); 688 // Get the basic block's function. 689 MachineFunction &MF = *MBB.getParent(); 690 // Get the instruction info. 691 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 692 // Get the frame info. 693 MachineFrameInfo *MFI = MF.getFrameInfo(); 694 DebugLoc dl = MI.getDebugLoc(); 695 696 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 697 698 // Get the frame index. 699 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 700 701 // Get the frame pointer save index. Users of this index are primarily 702 // DYNALLOC instructions. 703 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 704 int FPSI = FI->getFramePointerSaveIndex(); 705 // Get the instruction opcode. 706 unsigned OpC = MI.getOpcode(); 707 708 // Special case for dynamic alloca. 709 if (FPSI && FrameIndex == FPSI && 710 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 711 lowerDynamicAlloc(II); 712 return; 713 } 714 715 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 716 if (OpC == PPC::SPILL_CR) { 717 lowerCRSpilling(II, FrameIndex); 718 return; 719 } else if (OpC == PPC::RESTORE_CR) { 720 lowerCRRestore(II, FrameIndex); 721 return; 722 } else if (OpC == PPC::SPILL_CRBIT) { 723 lowerCRBitSpilling(II, FrameIndex); 724 return; 725 } else if (OpC == PPC::RESTORE_CRBIT) { 726 lowerCRBitRestore(II, FrameIndex); 727 return; 728 } else if (OpC == PPC::SPILL_VRSAVE) { 729 lowerVRSAVESpilling(II, FrameIndex); 730 return; 731 } else if (OpC == PPC::RESTORE_VRSAVE) { 732 lowerVRSAVERestore(II, FrameIndex); 733 return; 734 } 735 736 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 737 MI.getOperand(FIOperandNum).ChangeToRegister( 738 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 739 740 // Figure out if the offset in the instruction is shifted right two bits. 741 bool isIXAddr = usesIXAddr(MI); 742 743 // If the instruction is not present in ImmToIdxMap, then it has no immediate 744 // form (and must be r+r). 745 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC); 746 747 // Now add the frame object offset to the offset from r1. 748 int Offset = MFI->getObjectOffset(FrameIndex); 749 Offset += MI.getOperand(OffsetOperandNo).getImm(); 750 751 // If we're not using a Frame Pointer that has been set to the value of the 752 // SP before having the stack size subtracted from it, then add the stack size 753 // to Offset to get the correct offset. 754 // Naked functions have stack size 0, although getStackSize may not reflect that 755 // because we didn't call all the pieces that compute it for naked functions. 756 if (!MF.getFunction()->getAttributes(). 757 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) { 758 if (!(hasBasePointer(MF) && FrameIndex < 0)) 759 Offset += MFI->getStackSize(); 760 } 761 762 // If we can, encode the offset directly into the instruction. If this is a 763 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 764 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 765 // clear can be encoded. This is extremely uncommon, because normally you 766 // only "std" to a stack slot that is at least 4-byte aligned, but it can 767 // happen in invalid code. 768 assert(OpC != PPC::DBG_VALUE && 769 "This should be handle in a target independent way"); 770 if (!noImmForm && isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 771 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 772 return; 773 } 774 775 // The offset doesn't fit into a single register, scavenge one to build the 776 // offset in. 777 778 bool is64Bit = Subtarget.isPPC64(); 779 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 780 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 781 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 782 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 783 SReg = MF.getRegInfo().createVirtualRegister(RC); 784 785 // Insert a set of rA with the full offset value before the ld, st, or add 786 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 787 .addImm(Offset >> 16); 788 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 789 .addReg(SRegHi, RegState::Kill) 790 .addImm(Offset); 791 792 // Convert into indexed form of the instruction: 793 // 794 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 795 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 796 unsigned OperandBase; 797 798 if (noImmForm) 799 OperandBase = 1; 800 else if (OpC != TargetOpcode::INLINEASM) { 801 assert(ImmToIdxMap.count(OpC) && 802 "No indexed form of load or store available!"); 803 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 804 MI.setDesc(TII.get(NewOpcode)); 805 OperandBase = 1; 806 } else { 807 OperandBase = OffsetOperandNo; 808 } 809 810 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 811 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 812 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 813 } 814 815 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 816 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 817 818 if (!Subtarget.isPPC64()) 819 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 820 else 821 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 822 } 823 824 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 825 if (!hasBasePointer(MF)) 826 return getFrameRegister(MF); 827 828 return Subtarget.isPPC64() ? PPC::X30 : PPC::R30; 829 } 830 831 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 832 if (!EnableBasePointer) 833 return false; 834 if (AlwaysBasePointer) 835 return true; 836 837 // If we need to realign the stack, then the stack pointer can no longer 838 // serve as an offset into the caller's stack space. As a result, we need a 839 // base pointer. 840 return needsStackRealignment(MF); 841 } 842 843 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 844 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 845 return false; 846 847 return true; 848 } 849 850 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 851 const MachineFrameInfo *MFI = MF.getFrameInfo(); 852 const Function *F = MF.getFunction(); 853 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 854 bool requiresRealignment = 855 ((MFI->getMaxAlignment() > StackAlign) || 856 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 857 Attribute::StackAlignment)); 858 859 return requiresRealignment && canRealignStack(MF); 860 } 861 862 /// Returns true if the instruction's frame index 863 /// reference would be better served by a base register other than FP 864 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 865 /// references it should create new base registers for. 866 bool PPCRegisterInfo:: 867 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 868 assert(Offset < 0 && "Local offset must be negative"); 869 870 unsigned FIOperandNum = 0; 871 while (!MI->getOperand(FIOperandNum).isFI()) { 872 ++FIOperandNum; 873 assert(FIOperandNum < MI->getNumOperands() && 874 "Instr doesn't have FrameIndex operand!"); 875 } 876 877 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 878 Offset += MI->getOperand(OffsetOperandNo).getImm(); 879 880 // It's the load/store FI references that cause issues, as it can be difficult 881 // to materialize the offset if it won't fit in the literal field. Estimate 882 // based on the size of the local frame and some conservative assumptions 883 // about the rest of the stack frame (note, this is pre-regalloc, so 884 // we don't know everything for certain yet) whether this offset is likely 885 // to be out of range of the immediate. Return true if so. 886 887 // We only generate virtual base registers for loads and stores that have 888 // an r+i form. Return false for everything else. 889 unsigned OpC = MI->getOpcode(); 890 if (!ImmToIdxMap.count(OpC)) 891 return false; 892 893 // Don't generate a new virtual base register just to add zero to it. 894 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 895 MI->getOperand(2).getImm() == 0) 896 return false; 897 898 MachineBasicBlock &MBB = *MI->getParent(); 899 MachineFunction &MF = *MBB.getParent(); 900 901 const PPCFrameLowering *PPCFI = 902 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 903 unsigned StackEst = 904 PPCFI->determineFrameLayout(MF, false, true); 905 906 // If we likely don't need a stack frame, then we probably don't need a 907 // virtual base register either. 908 if (!StackEst) 909 return false; 910 911 // Estimate an offset from the stack pointer. 912 // The incoming offset is relating to the SP at the start of the function, 913 // but when we access the local it'll be relative to the SP after local 914 // allocation, so adjust our SP-relative offset by that allocation size. 915 Offset += StackEst; 916 917 // The frame pointer will point to the end of the stack, so estimate the 918 // offset as the difference between the object offset and the FP location. 919 return !isFrameOffsetLegal(MI, Offset); 920 } 921 922 /// Insert defining instruction(s) for BaseReg to 923 /// be a pointer to FrameIdx at the beginning of the basic block. 924 void PPCRegisterInfo:: 925 materializeFrameBaseRegister(MachineBasicBlock *MBB, 926 unsigned BaseReg, int FrameIdx, 927 int64_t Offset) const { 928 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 929 930 MachineBasicBlock::iterator Ins = MBB->begin(); 931 DebugLoc DL; // Defaults to "unknown" 932 if (Ins != MBB->end()) 933 DL = Ins->getDebugLoc(); 934 935 const MachineFunction &MF = *MBB->getParent(); 936 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 937 const MCInstrDesc &MCID = TII.get(ADDriOpc); 938 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 939 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 940 941 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 942 .addFrameIndex(FrameIdx).addImm(Offset); 943 } 944 945 void 946 PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 947 unsigned BaseReg, int64_t Offset) const { 948 MachineInstr &MI = *I; 949 950 unsigned FIOperandNum = 0; 951 while (!MI.getOperand(FIOperandNum).isFI()) { 952 ++FIOperandNum; 953 assert(FIOperandNum < MI.getNumOperands() && 954 "Instr doesn't have FrameIndex operand!"); 955 } 956 957 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 958 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 959 Offset += MI.getOperand(OffsetOperandNo).getImm(); 960 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 961 } 962 963 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 964 int64_t Offset) const { 965 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 966 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 967 } 968 969