1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPCRegisterInfo.h"
16 #include "PPC.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RegisterScavenging.h"
31 #include "llvm/CodeGen/TargetFrameLowering.h"
32 #include "llvm/CodeGen/TargetInstrInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include <cstdlib>
45 
46 using namespace llvm;
47 
48 #define DEBUG_TYPE "reginfo"
49 
50 #define GET_REGINFO_TARGET_DESC
51 #include "PPCGenRegisterInfo.inc"
52 
53 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
54 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
55 
56 static cl::opt<bool>
57 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
58          cl::desc("Enable use of a base pointer for complex stack frames"));
59 
60 static cl::opt<bool>
61 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
62          cl::desc("Force the use of a base pointer in every function"));
63 
64 static cl::opt<bool>
65 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
66          cl::desc("Enable spills from gpr to vsr rather than stack"));
67 
68 static cl::opt<bool>
69 StackPtrConst("ppc-stack-ptr-caller-preserved",
70                 cl::desc("Consider R1 caller preserved so stack saves of "
71                          "caller preserved registers can be LICM candidates"),
72                 cl::init(true), cl::Hidden);
73 
74 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
75   : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
76                        TM.isPPC64() ? 0 : 1,
77                        TM.isPPC64() ? 0 : 1),
78     TM(TM) {
79   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
80   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
81   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
82   ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
83   ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
84   ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
85   ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
86   ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
87   ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
88 
89   // 64-bit
90   ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
91   ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
92   ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
93   ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
94   ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
95 
96   // VSX
97   ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
98   ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
99   ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
100   ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
101   ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
102   ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
103   ImmToIdxMap[PPC::LXV] = PPC::LXVX;
104   ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
105   ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
106   ImmToIdxMap[PPC::STXV] = PPC::STXVX;
107   ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
108   ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
109 
110   // SPE
111   ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
112   ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
113   ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
114   ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
115 }
116 
117 /// getPointerRegClass - Return the register class to use to hold pointers.
118 /// This is used for addressing modes.
119 const TargetRegisterClass *
120 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
121                                                                        const {
122   // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
123   // when it checks for ZERO folding.
124   if (Kind == 1) {
125     if (TM.isPPC64())
126       return &PPC::G8RC_NOX0RegClass;
127     return &PPC::GPRC_NOR0RegClass;
128   }
129 
130   if (TM.isPPC64())
131     return &PPC::G8RCRegClass;
132   return &PPC::GPRCRegClass;
133 }
134 
135 const MCPhysReg*
136 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
137   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
138   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
139     if (Subtarget.hasVSX())
140       return CSR_64_AllRegs_VSX_SaveList;
141     if (Subtarget.hasAltivec())
142       return CSR_64_AllRegs_Altivec_SaveList;
143     return CSR_64_AllRegs_SaveList;
144   }
145 
146   if (Subtarget.isDarwinABI())
147     return TM.isPPC64()
148                ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
149                                          : CSR_Darwin64_SaveList)
150                : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
151                                          : CSR_Darwin32_SaveList);
152 
153   if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
154     return CSR_SRV464_TLS_PE_SaveList;
155 
156   if (Subtarget.hasSPE())
157     return CSR_SVR432_SPE_SaveList;
158 
159   // On PPC64, we might need to save r2 (but only if it is not reserved).
160   bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
161 
162   if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
163     return TM.isPPC64()
164                ? (Subtarget.hasAltivec()
165                       ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
166                                 : CSR_SVR64_ColdCC_Altivec_SaveList)
167                       : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
168                                 : CSR_SVR64_ColdCC_SaveList))
169                : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList
170                                          : CSR_SVR32_ColdCC_SaveList);
171   }
172 
173   return TM.isPPC64()
174              ? (Subtarget.hasAltivec()
175                     ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
176                               : CSR_SVR464_Altivec_SaveList)
177                     : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
178              : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
179                                        : CSR_SVR432_SaveList);
180 }
181 
182 const MCPhysReg *
183 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
184   assert(MF && "Invalid MachineFunction pointer.");
185   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
186   if (Subtarget.isDarwinABI())
187     return nullptr;
188   if (!TM.isPPC64())
189     return nullptr;
190   if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS)
191     return nullptr;
192   if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
193     return nullptr;
194 
195   // On PPC64, we might need to save r2 (but only if it is not reserved).
196   bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
197   if (Subtarget.hasAltivec())
198     return SaveR2
199       ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
200       : CSR_SVR464_Altivec_ViaCopy_SaveList;
201   else
202     return SaveR2
203       ? CSR_SVR464_R2_ViaCopy_SaveList
204       : CSR_SVR464_ViaCopy_SaveList;
205 }
206 
207 const uint32_t *
208 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
209                                       CallingConv::ID CC) const {
210   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
211   if (CC == CallingConv::AnyReg) {
212     if (Subtarget.hasVSX())
213       return CSR_64_AllRegs_VSX_RegMask;
214     if (Subtarget.hasAltivec())
215       return CSR_64_AllRegs_Altivec_RegMask;
216     return CSR_64_AllRegs_RegMask;
217   }
218 
219   if (Subtarget.isDarwinABI())
220     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
221                                                   : CSR_Darwin64_RegMask)
222                         : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
223                                                   : CSR_Darwin32_RegMask);
224 
225   if (CC == CallingConv::Cold) {
226     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
227                                                   : CSR_SVR64_ColdCC_RegMask)
228                         : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
229                                                   : CSR_SVR32_ColdCC_RegMask);
230   }
231 
232   return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
233                                                 : CSR_SVR464_RegMask)
234                       : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
235                                                 : CSR_SVR432_RegMask);
236 }
237 
238 const uint32_t*
239 PPCRegisterInfo::getNoPreservedMask() const {
240   return CSR_NoRegs_RegMask;
241 }
242 
243 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
244   for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
245     Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
246 }
247 
248 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
249   BitVector Reserved(getNumRegs());
250   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
251   const PPCFrameLowering *TFI = getFrameLowering(MF);
252 
253   // The ZERO register is not really a register, but the representation of r0
254   // when used in instructions that treat r0 as the constant 0.
255   markSuperRegs(Reserved, PPC::ZERO);
256 
257   // The FP register is also not really a register, but is the representation
258   // of the frame pointer register used by ISD::FRAMEADDR.
259   markSuperRegs(Reserved, PPC::FP);
260 
261   // The BP register is also not really a register, but is the representation
262   // of the base pointer register used by setjmp.
263   markSuperRegs(Reserved, PPC::BP);
264 
265   // The counter registers must be reserved so that counter-based loops can
266   // be correctly formed (and the mtctr instructions are not DCE'd).
267   markSuperRegs(Reserved, PPC::CTR);
268   markSuperRegs(Reserved, PPC::CTR8);
269 
270   markSuperRegs(Reserved, PPC::R1);
271   markSuperRegs(Reserved, PPC::LR);
272   markSuperRegs(Reserved, PPC::LR8);
273   markSuperRegs(Reserved, PPC::RM);
274 
275   if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
276     markSuperRegs(Reserved, PPC::VRSAVE);
277 
278   // The SVR4 ABI reserves r2 and r13
279   if (Subtarget.isSVR4ABI()) {
280     // We only reserve r2 if we need to use the TOC pointer. If we have no
281     // explicit uses of the TOC pointer (meaning we're a leaf function with
282     // no constant-pool loads, etc.) and we have no potential uses inside an
283     // inline asm block, then we can treat r2 has an ordinary callee-saved
284     // register.
285     const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
286     if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
287       markSuperRegs(Reserved, PPC::R2);  // System-reserved register
288     markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
289   }
290 
291   // On PPC64, r13 is the thread pointer. Never allocate this register.
292   if (TM.isPPC64())
293     markSuperRegs(Reserved, PPC::R13);
294 
295   if (TFI->needsFP(MF))
296     markSuperRegs(Reserved, PPC::R31);
297 
298   bool IsPositionIndependent = TM.isPositionIndependent();
299   if (hasBasePointer(MF)) {
300     if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
301       markSuperRegs(Reserved, PPC::R29);
302     else
303       markSuperRegs(Reserved, PPC::R30);
304   }
305 
306   if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
307     markSuperRegs(Reserved, PPC::R30);
308 
309   // Reserve Altivec registers when Altivec is unavailable.
310   if (!Subtarget.hasAltivec())
311     for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
312          IE = PPC::VRRCRegClass.end(); I != IE; ++I)
313       markSuperRegs(Reserved, *I);
314 
315   assert(checkAllSuperRegsMarked(Reserved));
316   return Reserved;
317 }
318 
319 bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg,
320                                                const MachineFunction &MF) const {
321   assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
322   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
323   const MachineFrameInfo &MFI = MF.getFrameInfo();
324   if (!TM.isPPC64())
325     return false;
326 
327   if (!Subtarget.isSVR4ABI())
328     return false;
329   if (PhysReg == PPC::X2)
330     // X2 is guaranteed to be preserved within a function if it is reserved.
331     // The reason it's reserved is that it's the TOC pointer (and the function
332     // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
333     // with no TOC access), we can't claim that it is preserved.
334     return (getReservedRegs(MF).test(PPC::X2));
335   if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
336       && !MFI.hasOpaqueSPAdjustment())
337     // The value of the stack pointer does not change within a function after
338     // the prologue and before the epilogue if there are no dynamic allocations
339     // and no inline asm which clobbers X1.
340     return true;
341   return false;
342 }
343 
344 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
345                                               MachineFunction &MF) const {
346   const PPCFrameLowering *TFI = getFrameLowering(MF);
347   const unsigned DefaultSafety = 1;
348 
349   switch (RC->getID()) {
350   default:
351     return 0;
352   case PPC::G8RC_NOX0RegClassID:
353   case PPC::GPRC_NOR0RegClassID:
354   case PPC::SPERCRegClassID:
355   case PPC::SPE4RCRegClassID:
356   case PPC::G8RCRegClassID:
357   case PPC::GPRCRegClassID: {
358     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
359     return 32 - FP - DefaultSafety;
360   }
361   case PPC::F8RCRegClassID:
362   case PPC::F4RCRegClassID:
363   case PPC::QFRCRegClassID:
364   case PPC::QSRCRegClassID:
365   case PPC::QBRCRegClassID:
366   case PPC::VRRCRegClassID:
367   case PPC::VFRCRegClassID:
368   case PPC::VSLRCRegClassID:
369     return 32 - DefaultSafety;
370   case PPC::VSRCRegClassID:
371   case PPC::VSFRCRegClassID:
372   case PPC::VSSRCRegClassID:
373     return 64 - DefaultSafety;
374   case PPC::CRRCRegClassID:
375     return 8 - DefaultSafety;
376   }
377 }
378 
379 const TargetRegisterClass *
380 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
381                                            const MachineFunction &MF) const {
382   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
383   if (Subtarget.hasVSX()) {
384     // With VSX, we can inflate various sub-register classes to the full VSX
385     // register set.
386 
387     // For Power9 we allow the user to enable GPR to vector spills.
388     // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
389     // support to spill GPRC.
390     if (TM.isELFv2ABI()) {
391       if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
392           RC == &PPC::G8RCRegClass) {
393         InflateGP8RC++;
394         return &PPC::SPILLTOVSRRCRegClass;
395       }
396       if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
397         InflateGPRC++;
398     }
399     if (RC == &PPC::F8RCRegClass)
400       return &PPC::VSFRCRegClass;
401     else if (RC == &PPC::VRRCRegClass)
402       return &PPC::VSRCRegClass;
403     else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
404       return &PPC::VSSRCRegClass;
405   }
406 
407   return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
408 }
409 
410 //===----------------------------------------------------------------------===//
411 // Stack Frame Processing methods
412 //===----------------------------------------------------------------------===//
413 
414 /// lowerDynamicAlloc - Generate the code for allocating an object in the
415 /// current frame.  The sequence of code will be in the general form
416 ///
417 ///   addi   R0, SP, \#frameSize ; get the address of the previous frame
418 ///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
419 ///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
420 ///
421 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
422   // Get the instruction.
423   MachineInstr &MI = *II;
424   // Get the instruction's basic block.
425   MachineBasicBlock &MBB = *MI.getParent();
426   // Get the basic block's function.
427   MachineFunction &MF = *MBB.getParent();
428   // Get the frame info.
429   MachineFrameInfo &MFI = MF.getFrameInfo();
430   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
431   // Get the instruction info.
432   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
433   // Determine whether 64-bit pointers are used.
434   bool LP64 = TM.isPPC64();
435   DebugLoc dl = MI.getDebugLoc();
436 
437   // Get the maximum call stack size.
438   unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
439   // Get the total frame size.
440   unsigned FrameSize = MFI.getStackSize();
441 
442   // Get stack alignments.
443   const PPCFrameLowering *TFI = getFrameLowering(MF);
444   unsigned TargetAlign = TFI->getStackAlignment();
445   unsigned MaxAlign = MFI.getMaxAlignment();
446   assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
447          "Maximum call-frame size not sufficiently aligned");
448 
449   // Determine the previous frame's address.  If FrameSize can't be
450   // represented as 16 bits or we need special alignment, then we load the
451   // previous frame's address from 0(SP).  Why not do an addis of the hi?
452   // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
453   // Constructing the constant and adding would take 3 instructions.
454   // Fortunately, a frame greater than 32K is rare.
455   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
456   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
457   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
458 
459   if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
460     if (LP64)
461       BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
462         .addReg(PPC::X31)
463         .addImm(FrameSize);
464     else
465       BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
466         .addReg(PPC::R31)
467         .addImm(FrameSize);
468   } else if (LP64) {
469     BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
470       .addImm(0)
471       .addReg(PPC::X1);
472   } else {
473     BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
474       .addImm(0)
475       .addReg(PPC::R1);
476   }
477 
478   bool KillNegSizeReg = MI.getOperand(1).isKill();
479   unsigned NegSizeReg = MI.getOperand(1).getReg();
480 
481   // Grow the stack and update the stack pointer link, then determine the
482   // address of new allocated space.
483   if (LP64) {
484     if (MaxAlign > TargetAlign) {
485       unsigned UnalNegSizeReg = NegSizeReg;
486       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
487 
488       // Unfortunately, there is no andi, only andi., and we can't insert that
489       // here because we might clobber cr0 while it is live.
490       BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
491         .addImm(~(MaxAlign-1));
492 
493       unsigned NegSizeReg1 = NegSizeReg;
494       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
495       BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
496         .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
497         .addReg(NegSizeReg1, RegState::Kill);
498       KillNegSizeReg = true;
499     }
500 
501     BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
502       .addReg(Reg, RegState::Kill)
503       .addReg(PPC::X1)
504       .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
505     BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
506       .addReg(PPC::X1)
507       .addImm(maxCallFrameSize);
508   } else {
509     if (MaxAlign > TargetAlign) {
510       unsigned UnalNegSizeReg = NegSizeReg;
511       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
512 
513       // Unfortunately, there is no andi, only andi., and we can't insert that
514       // here because we might clobber cr0 while it is live.
515       BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
516         .addImm(~(MaxAlign-1));
517 
518       unsigned NegSizeReg1 = NegSizeReg;
519       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
520       BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
521         .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
522         .addReg(NegSizeReg1, RegState::Kill);
523       KillNegSizeReg = true;
524     }
525 
526     BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
527       .addReg(Reg, RegState::Kill)
528       .addReg(PPC::R1)
529       .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
530     BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
531       .addReg(PPC::R1)
532       .addImm(maxCallFrameSize);
533   }
534 
535   // Discard the DYNALLOC instruction.
536   MBB.erase(II);
537 }
538 
539 void PPCRegisterInfo::lowerDynamicAreaOffset(
540     MachineBasicBlock::iterator II) const {
541   // Get the instruction.
542   MachineInstr &MI = *II;
543   // Get the instruction's basic block.
544   MachineBasicBlock &MBB = *MI.getParent();
545   // Get the basic block's function.
546   MachineFunction &MF = *MBB.getParent();
547   // Get the frame info.
548   MachineFrameInfo &MFI = MF.getFrameInfo();
549   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
550   // Get the instruction info.
551   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
552 
553   unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
554   bool is64Bit = TM.isPPC64();
555   DebugLoc dl = MI.getDebugLoc();
556   BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
557           MI.getOperand(0).getReg())
558       .addImm(maxCallFrameSize);
559   MBB.erase(II);
560 }
561 
562 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
563 /// reserving a whole register (R0), we scrounge for one here. This generates
564 /// code like this:
565 ///
566 ///   mfcr rA                  ; Move the conditional register into GPR rA.
567 ///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
568 ///   stw rA, FI               ; Store rA to the frame.
569 ///
570 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
571                                       unsigned FrameIndex) const {
572   // Get the instruction.
573   MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
574   // Get the instruction's basic block.
575   MachineBasicBlock &MBB = *MI.getParent();
576   MachineFunction &MF = *MBB.getParent();
577   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
578   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
579   DebugLoc dl = MI.getDebugLoc();
580 
581   bool LP64 = TM.isPPC64();
582   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
583   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
584 
585   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
586   unsigned SrcReg = MI.getOperand(0).getReg();
587 
588   // We need to store the CR in the low 4-bits of the saved value. First, issue
589   // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
590   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
591       .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
592 
593   // If the saved register wasn't CR0, shift the bits left so that they are in
594   // CR0's slot.
595   if (SrcReg != PPC::CR0) {
596     unsigned Reg1 = Reg;
597     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
598 
599     // rlwinm rA, rA, ShiftBits, 0, 31.
600     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
601       .addReg(Reg1, RegState::Kill)
602       .addImm(getEncodingValue(SrcReg) * 4)
603       .addImm(0)
604       .addImm(31);
605   }
606 
607   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
608                     .addReg(Reg, RegState::Kill),
609                     FrameIndex);
610 
611   // Discard the pseudo instruction.
612   MBB.erase(II);
613 }
614 
615 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
616                                       unsigned FrameIndex) const {
617   // Get the instruction.
618   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
619   // Get the instruction's basic block.
620   MachineBasicBlock &MBB = *MI.getParent();
621   MachineFunction &MF = *MBB.getParent();
622   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
623   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
624   DebugLoc dl = MI.getDebugLoc();
625 
626   bool LP64 = TM.isPPC64();
627   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
628   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
629 
630   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
631   unsigned DestReg = MI.getOperand(0).getReg();
632   assert(MI.definesRegister(DestReg) &&
633     "RESTORE_CR does not define its destination");
634 
635   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
636                               Reg), FrameIndex);
637 
638   // If the reloaded register isn't CR0, shift the bits right so that they are
639   // in the right CR's slot.
640   if (DestReg != PPC::CR0) {
641     unsigned Reg1 = Reg;
642     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
643 
644     unsigned ShiftBits = getEncodingValue(DestReg)*4;
645     // rlwinm r11, r11, 32-ShiftBits, 0, 31.
646     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
647              .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
648              .addImm(31);
649   }
650 
651   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
652              .addReg(Reg, RegState::Kill);
653 
654   // Discard the pseudo instruction.
655   MBB.erase(II);
656 }
657 
658 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
659                                          unsigned FrameIndex) const {
660   // Get the instruction.
661   MachineInstr &MI = *II;       // ; SPILL_CRBIT <SrcReg>, <offset>
662   // Get the instruction's basic block.
663   MachineBasicBlock &MBB = *MI.getParent();
664   MachineFunction &MF = *MBB.getParent();
665   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
666   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
667   DebugLoc dl = MI.getDebugLoc();
668 
669   bool LP64 = TM.isPPC64();
670   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
671   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
672 
673   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
674   unsigned SrcReg = MI.getOperand(0).getReg();
675 
676   // We need to move the CR field that contains the CR bit we are spilling.
677   // The super register may not be explicitly defined (i.e. it can be defined
678   // by a CR-logical that only defines the subreg) so we state that the CR
679   // field is undef. Also, in order to preserve the kill flag on the CR bit,
680   // we add it as an implicit use.
681   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
682       .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
683       .addReg(SrcReg,
684               RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
685 
686   // If the saved register wasn't CR0LT, shift the bits left so that the bit to
687   // store is the first one. Mask all but that bit.
688   unsigned Reg1 = Reg;
689   Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
690 
691   // rlwinm rA, rA, ShiftBits, 0, 0.
692   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
693     .addReg(Reg1, RegState::Kill)
694     .addImm(getEncodingValue(SrcReg))
695     .addImm(0).addImm(0);
696 
697   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
698                     .addReg(Reg, RegState::Kill),
699                     FrameIndex);
700 
701   // Discard the pseudo instruction.
702   MBB.erase(II);
703 }
704 
705 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
706                                       unsigned FrameIndex) const {
707   // Get the instruction.
708   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CRBIT <offset>
709   // Get the instruction's basic block.
710   MachineBasicBlock &MBB = *MI.getParent();
711   MachineFunction &MF = *MBB.getParent();
712   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
713   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
714   DebugLoc dl = MI.getDebugLoc();
715 
716   bool LP64 = TM.isPPC64();
717   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
718   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
719 
720   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
721   unsigned DestReg = MI.getOperand(0).getReg();
722   assert(MI.definesRegister(DestReg) &&
723     "RESTORE_CRBIT does not define its destination");
724 
725   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
726                               Reg), FrameIndex);
727 
728   BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
729 
730   unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
731   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
732           .addReg(getCRFromCRBit(DestReg));
733 
734   unsigned ShiftBits = getEncodingValue(DestReg);
735   // rlwimi r11, r10, 32-ShiftBits, ..., ...
736   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
737       .addReg(RegO, RegState::Kill)
738       .addReg(Reg, RegState::Kill)
739       .addImm(ShiftBits ? 32 - ShiftBits : 0)
740       .addImm(ShiftBits)
741       .addImm(ShiftBits);
742 
743   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
744           getCRFromCRBit(DestReg))
745       .addReg(RegO, RegState::Kill)
746       // Make sure we have a use dependency all the way through this
747       // sequence of instructions. We can't have the other bits in the CR
748       // modified in between the mfocrf and the mtocrf.
749       .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
750 
751   // Discard the pseudo instruction.
752   MBB.erase(II);
753 }
754 
755 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
756                                           unsigned FrameIndex) const {
757   // Get the instruction.
758   MachineInstr &MI = *II;       // ; SPILL_VRSAVE <SrcReg>, <offset>
759   // Get the instruction's basic block.
760   MachineBasicBlock &MBB = *MI.getParent();
761   MachineFunction &MF = *MBB.getParent();
762   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
763   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
764   DebugLoc dl = MI.getDebugLoc();
765 
766   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
767   unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
768   unsigned SrcReg = MI.getOperand(0).getReg();
769 
770   BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
771       .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
772 
773   addFrameReference(
774       BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
775       FrameIndex);
776 
777   // Discard the pseudo instruction.
778   MBB.erase(II);
779 }
780 
781 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
782                                          unsigned FrameIndex) const {
783   // Get the instruction.
784   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_VRSAVE <offset>
785   // Get the instruction's basic block.
786   MachineBasicBlock &MBB = *MI.getParent();
787   MachineFunction &MF = *MBB.getParent();
788   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
789   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
790   DebugLoc dl = MI.getDebugLoc();
791 
792   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
793   unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
794   unsigned DestReg = MI.getOperand(0).getReg();
795   assert(MI.definesRegister(DestReg) &&
796     "RESTORE_VRSAVE does not define its destination");
797 
798   addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
799                               Reg), FrameIndex);
800 
801   BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
802              .addReg(Reg, RegState::Kill);
803 
804   // Discard the pseudo instruction.
805   MBB.erase(II);
806 }
807 
808 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
809                                            unsigned Reg, int &FrameIdx) const {
810   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
811   // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
812   // ABI, return true to prevent allocating an additional frame slot.
813   // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
814   // is arbitrary and will be subsequently ignored.  For 32-bit, we have
815   // previously created the stack slot if needed, so return its FrameIdx.
816   if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
817     if (TM.isPPC64())
818       FrameIdx = 0;
819     else {
820       const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
821       FrameIdx = FI->getCRSpillFrameIndex();
822     }
823     return true;
824   }
825   return false;
826 }
827 
828 // If the offset must be a multiple of some value, return what that value is.
829 static unsigned offsetMinAlign(const MachineInstr &MI) {
830   unsigned OpC = MI.getOpcode();
831 
832   switch (OpC) {
833   default:
834     return 1;
835   case PPC::LWA:
836   case PPC::LWA_32:
837   case PPC::LD:
838   case PPC::LDU:
839   case PPC::STD:
840   case PPC::STDU:
841   case PPC::DFLOADf32:
842   case PPC::DFLOADf64:
843   case PPC::DFSTOREf32:
844   case PPC::DFSTOREf64:
845   case PPC::LXSD:
846   case PPC::LXSSP:
847   case PPC::STXSD:
848   case PPC::STXSSP:
849     return 4;
850   case PPC::LXV:
851   case PPC::STXV:
852     return 16;
853   }
854 }
855 
856 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
857 static unsigned getOffsetONFromFION(const MachineInstr &MI,
858                                     unsigned FIOperandNum) {
859   // Take into account whether it's an add or mem instruction
860   unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
861   if (MI.isInlineAsm())
862     OffsetOperandNo = FIOperandNum - 1;
863   else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
864            MI.getOpcode() == TargetOpcode::PATCHPOINT)
865     OffsetOperandNo = FIOperandNum + 1;
866 
867   return OffsetOperandNo;
868 }
869 
870 void
871 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
872                                      int SPAdj, unsigned FIOperandNum,
873                                      RegScavenger *RS) const {
874   assert(SPAdj == 0 && "Unexpected");
875 
876   // Get the instruction.
877   MachineInstr &MI = *II;
878   // Get the instruction's basic block.
879   MachineBasicBlock &MBB = *MI.getParent();
880   // Get the basic block's function.
881   MachineFunction &MF = *MBB.getParent();
882   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
883   // Get the instruction info.
884   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
885   // Get the frame info.
886   MachineFrameInfo &MFI = MF.getFrameInfo();
887   DebugLoc dl = MI.getDebugLoc();
888 
889   unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
890 
891   // Get the frame index.
892   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
893 
894   // Get the frame pointer save index.  Users of this index are primarily
895   // DYNALLOC instructions.
896   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
897   int FPSI = FI->getFramePointerSaveIndex();
898   // Get the instruction opcode.
899   unsigned OpC = MI.getOpcode();
900 
901   if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
902     lowerDynamicAreaOffset(II);
903     return;
904   }
905 
906   // Special case for dynamic alloca.
907   if (FPSI && FrameIndex == FPSI &&
908       (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
909     lowerDynamicAlloc(II);
910     return;
911   }
912 
913   // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
914   if (OpC == PPC::SPILL_CR) {
915     lowerCRSpilling(II, FrameIndex);
916     return;
917   } else if (OpC == PPC::RESTORE_CR) {
918     lowerCRRestore(II, FrameIndex);
919     return;
920   } else if (OpC == PPC::SPILL_CRBIT) {
921     lowerCRBitSpilling(II, FrameIndex);
922     return;
923   } else if (OpC == PPC::RESTORE_CRBIT) {
924     lowerCRBitRestore(II, FrameIndex);
925     return;
926   } else if (OpC == PPC::SPILL_VRSAVE) {
927     lowerVRSAVESpilling(II, FrameIndex);
928     return;
929   } else if (OpC == PPC::RESTORE_VRSAVE) {
930     lowerVRSAVERestore(II, FrameIndex);
931     return;
932   }
933 
934   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
935   MI.getOperand(FIOperandNum).ChangeToRegister(
936     FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
937 
938   // If the instruction is not present in ImmToIdxMap, then it has no immediate
939   // form (and must be r+r).
940   bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
941                    OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
942 
943   // Now add the frame object offset to the offset from r1.
944   int Offset = MFI.getObjectOffset(FrameIndex);
945   Offset += MI.getOperand(OffsetOperandNo).getImm();
946 
947   // If we're not using a Frame Pointer that has been set to the value of the
948   // SP before having the stack size subtracted from it, then add the stack size
949   // to Offset to get the correct offset.
950   // Naked functions have stack size 0, although getStackSize may not reflect
951   // that because we didn't call all the pieces that compute it for naked
952   // functions.
953   if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
954     if (!(hasBasePointer(MF) && FrameIndex < 0))
955       Offset += MFI.getStackSize();
956   }
957 
958   // If we can, encode the offset directly into the instruction.  If this is a
959   // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
960   // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
961   // clear can be encoded.  This is extremely uncommon, because normally you
962   // only "std" to a stack slot that is at least 4-byte aligned, but it can
963   // happen in invalid code.
964   assert(OpC != PPC::DBG_VALUE &&
965          "This should be handled in a target-independent way");
966   if (!noImmForm && ((isInt<16>(Offset) &&
967                       ((Offset % offsetMinAlign(MI)) == 0)) ||
968                      OpC == TargetOpcode::STACKMAP ||
969                      OpC == TargetOpcode::PATCHPOINT)) {
970     MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
971     return;
972   }
973 
974   // The offset doesn't fit into a single register, scavenge one to build the
975   // offset in.
976 
977   bool is64Bit = TM.isPPC64();
978   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
979   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
980   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
981   unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
982            SReg = MF.getRegInfo().createVirtualRegister(RC);
983 
984   // Insert a set of rA with the full offset value before the ld, st, or add
985   if (isInt<16>(Offset))
986     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
987       .addImm(Offset);
988   else {
989     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
990       .addImm(Offset >> 16);
991     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
992       .addReg(SRegHi, RegState::Kill)
993       .addImm(Offset);
994   }
995 
996   // Convert into indexed form of the instruction:
997   //
998   //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
999   //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1000   unsigned OperandBase;
1001 
1002   if (noImmForm)
1003     OperandBase = 1;
1004   else if (OpC != TargetOpcode::INLINEASM) {
1005     assert(ImmToIdxMap.count(OpC) &&
1006            "No indexed form of load or store available!");
1007     unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1008     MI.setDesc(TII.get(NewOpcode));
1009     OperandBase = 1;
1010   } else {
1011     OperandBase = OffsetOperandNo;
1012   }
1013 
1014   unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
1015   MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1016   MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1017 }
1018 
1019 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1020   const PPCFrameLowering *TFI = getFrameLowering(MF);
1021 
1022   if (!TM.isPPC64())
1023     return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1024   else
1025     return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1026 }
1027 
1028 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1029   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1030   if (!hasBasePointer(MF))
1031     return getFrameRegister(MF);
1032 
1033   if (TM.isPPC64())
1034     return PPC::X30;
1035 
1036   if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1037     return PPC::R29;
1038 
1039   return PPC::R30;
1040 }
1041 
1042 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1043   if (!EnableBasePointer)
1044     return false;
1045   if (AlwaysBasePointer)
1046     return true;
1047 
1048   // If we need to realign the stack, then the stack pointer can no longer
1049   // serve as an offset into the caller's stack space. As a result, we need a
1050   // base pointer.
1051   return needsStackRealignment(MF);
1052 }
1053 
1054 /// Returns true if the instruction's frame index
1055 /// reference would be better served by a base register other than FP
1056 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1057 /// references it should create new base registers for.
1058 bool PPCRegisterInfo::
1059 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1060   assert(Offset < 0 && "Local offset must be negative");
1061 
1062   // It's the load/store FI references that cause issues, as it can be difficult
1063   // to materialize the offset if it won't fit in the literal field. Estimate
1064   // based on the size of the local frame and some conservative assumptions
1065   // about the rest of the stack frame (note, this is pre-regalloc, so
1066   // we don't know everything for certain yet) whether this offset is likely
1067   // to be out of range of the immediate. Return true if so.
1068 
1069   // We only generate virtual base registers for loads and stores that have
1070   // an r+i form. Return false for everything else.
1071   unsigned OpC = MI->getOpcode();
1072   if (!ImmToIdxMap.count(OpC))
1073     return false;
1074 
1075   // Don't generate a new virtual base register just to add zero to it.
1076   if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1077       MI->getOperand(2).getImm() == 0)
1078     return false;
1079 
1080   MachineBasicBlock &MBB = *MI->getParent();
1081   MachineFunction &MF = *MBB.getParent();
1082   const PPCFrameLowering *TFI = getFrameLowering(MF);
1083   unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
1084 
1085   // If we likely don't need a stack frame, then we probably don't need a
1086   // virtual base register either.
1087   if (!StackEst)
1088     return false;
1089 
1090   // Estimate an offset from the stack pointer.
1091   // The incoming offset is relating to the SP at the start of the function,
1092   // but when we access the local it'll be relative to the SP after local
1093   // allocation, so adjust our SP-relative offset by that allocation size.
1094   Offset += StackEst;
1095 
1096   // The frame pointer will point to the end of the stack, so estimate the
1097   // offset as the difference between the object offset and the FP location.
1098   return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1099 }
1100 
1101 /// Insert defining instruction(s) for BaseReg to
1102 /// be a pointer to FrameIdx at the beginning of the basic block.
1103 void PPCRegisterInfo::
1104 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1105                              unsigned BaseReg, int FrameIdx,
1106                              int64_t Offset) const {
1107   unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1108 
1109   MachineBasicBlock::iterator Ins = MBB->begin();
1110   DebugLoc DL;                  // Defaults to "unknown"
1111   if (Ins != MBB->end())
1112     DL = Ins->getDebugLoc();
1113 
1114   const MachineFunction &MF = *MBB->getParent();
1115   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1116   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1117   const MCInstrDesc &MCID = TII.get(ADDriOpc);
1118   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1119   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1120 
1121   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1122     .addFrameIndex(FrameIdx).addImm(Offset);
1123 }
1124 
1125 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1126                                         int64_t Offset) const {
1127   unsigned FIOperandNum = 0;
1128   while (!MI.getOperand(FIOperandNum).isFI()) {
1129     ++FIOperandNum;
1130     assert(FIOperandNum < MI.getNumOperands() &&
1131            "Instr doesn't have FrameIndex operand!");
1132   }
1133 
1134   MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1135   unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1136   Offset += MI.getOperand(OffsetOperandNo).getImm();
1137   MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1138 
1139   MachineBasicBlock &MBB = *MI.getParent();
1140   MachineFunction &MF = *MBB.getParent();
1141   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1142   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1143   const MCInstrDesc &MCID = MI.getDesc();
1144   MachineRegisterInfo &MRI = MF.getRegInfo();
1145   MRI.constrainRegClass(BaseReg,
1146                         TII.getRegClass(MCID, FIOperandNum, this, MF));
1147 }
1148 
1149 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1150                                          unsigned BaseReg,
1151                                          int64_t Offset) const {
1152   unsigned FIOperandNum = 0;
1153   while (!MI->getOperand(FIOperandNum).isFI()) {
1154     ++FIOperandNum;
1155     assert(FIOperandNum < MI->getNumOperands() &&
1156            "Instr doesn't have FrameIndex operand!");
1157   }
1158 
1159   unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1160   Offset += MI->getOperand(OffsetOperandNo).getImm();
1161 
1162   return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1163          MI->getOpcode() == TargetOpcode::STACKMAP ||
1164          MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1165          (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1166 }
1167