1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===---------------------------------------------------------------------===//
9 //
10 // This pass performs peephole optimizations to clean up ugly code
11 // sequences at the MachineInstruction layer.  It runs at the end of
12 // the SSA phases, following VSX swap removal.  A pass of dead code
13 // elimination follows this one for quick clean-up of any dead
14 // instructions introduced here.  Although we could do this as callbacks
15 // from the generic peephole pass, this would have a couple of bad
16 // effects:  it might remove optimization opportunities for VSX swap
17 // removal, and it would miss cleanups made possible following VSX
18 // swap removal.
19 //
20 //===---------------------------------------------------------------------===//
21 
22 #include "PPCInstrInfo.h"
23 #include "PPC.h"
24 #include "PPCInstrBuilder.h"
25 #include "PPCTargetMachine.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Support/Debug.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ppc-mi-peepholes"
34 
35 namespace llvm {
36   void initializePPCMIPeepholePass(PassRegistry&);
37 }
38 
39 namespace {
40 
41 struct PPCMIPeephole : public MachineFunctionPass {
42 
43   static char ID;
44   const PPCInstrInfo *TII;
45   MachineFunction *MF;
46   MachineRegisterInfo *MRI;
47 
48   PPCMIPeephole() : MachineFunctionPass(ID) {
49     initializePPCMIPeepholePass(*PassRegistry::getPassRegistry());
50   }
51 
52 private:
53   // Initialize class variables.
54   void initialize(MachineFunction &MFParm);
55 
56   // Perform peepholes.
57   bool simplifyCode(void);
58 
59   // Find the "true" register represented by SrcReg (following chains
60   // of copies and subreg_to_reg operations).
61   unsigned lookThruCopyLike(unsigned SrcReg);
62 
63 public:
64   // Main entry point for this pass.
65   bool runOnMachineFunction(MachineFunction &MF) override {
66     if (skipFunction(*MF.getFunction()))
67       return false;
68     initialize(MF);
69     return simplifyCode();
70   }
71 };
72 
73 // Initialize class variables.
74 void PPCMIPeephole::initialize(MachineFunction &MFParm) {
75   MF = &MFParm;
76   MRI = &MF->getRegInfo();
77   TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
78   DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
79   DEBUG(MF->dump());
80 }
81 
82 // Perform peephole optimizations.
83 bool PPCMIPeephole::simplifyCode(void) {
84   bool Simplified = false;
85   MachineInstr* ToErase = nullptr;
86 
87   for (MachineBasicBlock &MBB : *MF) {
88     for (MachineInstr &MI : MBB) {
89 
90       // If the previous instruction was marked for elimination,
91       // remove it now.
92       if (ToErase) {
93         ToErase->eraseFromParent();
94         ToErase = nullptr;
95       }
96 
97       // Ignore debug instructions.
98       if (MI.isDebugValue())
99         continue;
100 
101       // Per-opcode peepholes.
102       switch (MI.getOpcode()) {
103 
104       default:
105         break;
106 
107       case PPC::XXPERMDI: {
108         // Perform simplifications of 2x64 vector swaps and splats.
109         // A swap is identified by an immediate value of 2, and a splat
110         // is identified by an immediate value of 0 or 3.
111         int Immed = MI.getOperand(3).getImm();
112 
113         if (Immed != 1) {
114 
115           // For each of these simplifications, we need the two source
116           // regs to match.  Unfortunately, MachineCSE ignores COPY and
117           // SUBREG_TO_REG, so for example we can see
118           //   XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
119           // We have to look through chains of COPY and SUBREG_TO_REG
120           // to find the real source values for comparison.
121           unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg());
122           unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg());
123 
124           if (TrueReg1 == TrueReg2
125               && TargetRegisterInfo::isVirtualRegister(TrueReg1)) {
126             MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
127 
128             // If this is a splat or a swap fed by another splat, we
129             // can replace it with a copy.
130             if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
131               unsigned FeedImmed = DefMI->getOperand(3).getImm();
132               unsigned FeedReg1
133                 = lookThruCopyLike(DefMI->getOperand(1).getReg());
134               unsigned FeedReg2
135                 = lookThruCopyLike(DefMI->getOperand(2).getReg());
136 
137               if ((FeedImmed == 0 || FeedImmed == 3) && FeedReg1 == FeedReg2) {
138                 DEBUG(dbgs()
139                       << "Optimizing splat/swap or splat/splat "
140                       "to splat/copy: ");
141                 DEBUG(MI.dump());
142                 BuildMI(MBB, &MI, MI.getDebugLoc(),
143                         TII->get(PPC::COPY), MI.getOperand(0).getReg())
144                   .addOperand(MI.getOperand(1));
145                 ToErase = &MI;
146                 Simplified = true;
147               }
148 
149               // If this is a splat fed by a swap, we can simplify modify
150               // the splat to splat the other value from the swap's input
151               // parameter.
152               else if ((Immed == 0 || Immed == 3)
153                        && FeedImmed == 2 && FeedReg1 == FeedReg2) {
154                 DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
155                 DEBUG(MI.dump());
156                 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
157                 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
158                 MI.getOperand(3).setImm(3 - Immed);
159                 Simplified = true;
160               }
161 
162               // If this is a swap fed by a swap, we can replace it
163               // with a copy from the first swap's input.
164               else if (Immed == 2 && FeedImmed == 2 && FeedReg1 == FeedReg2) {
165                 DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
166                 DEBUG(MI.dump());
167                 BuildMI(MBB, &MI, MI.getDebugLoc(),
168                         TII->get(PPC::COPY), MI.getOperand(0).getReg())
169                   .addOperand(DefMI->getOperand(1));
170                 ToErase = &MI;
171                 Simplified = true;
172               }
173             } else if ((Immed == 0 || Immed == 3) &&
174                        DefMI && DefMI->getOpcode() == PPC::XXPERMDIs) {
175               // Splat fed by another splat - switch the output of the first
176               // and remove the second.
177               DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
178               ToErase = &MI;
179               Simplified = true;
180               DEBUG(dbgs() << "Removing redundant splat: ");
181               DEBUG(MI.dump());
182             }
183           }
184         }
185         break;
186       }
187       case PPC::VSPLTB:
188       case PPC::VSPLTH:
189       case PPC::XXSPLTW: {
190         unsigned MyOpcode = MI.getOpcode();
191         unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
192         unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg());
193         MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
194         if (!DefMI)
195           break;
196         unsigned DefOpcode = DefMI->getOpcode();
197         bool SameOpcode = (MyOpcode == DefOpcode) ||
198           (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
199           (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
200           (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs);
201         // Splat fed by another splat - switch the output of the first
202         // and remove the second.
203         if (SameOpcode) {
204           DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
205           ToErase = &MI;
206           Simplified = true;
207           DEBUG(dbgs() << "Removing redundant splat: ");
208           DEBUG(MI.dump());
209         }
210         // Splat fed by a shift. Usually when we align value to splat into
211         // vector element zero.
212         if (DefOpcode == PPC::XXSLDWI) {
213           unsigned ShiftRes = DefMI->getOperand(0).getReg();
214           unsigned ShiftOp1 = DefMI->getOperand(1).getReg();
215           unsigned ShiftOp2 = DefMI->getOperand(2).getReg();
216           unsigned ShiftImm = DefMI->getOperand(3).getImm();
217           unsigned SplatImm = MI.getOperand(2).getImm();
218           if (ShiftOp1 == ShiftOp2) {
219             unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
220             if (MRI->hasOneNonDBGUse(ShiftRes)) {
221               DEBUG(dbgs() << "Removing redundant shift: ");
222               DEBUG(DefMI->dump());
223               ToErase = DefMI;
224             }
225             Simplified = true;
226             DEBUG(dbgs() << "Changing splat immediate from " << SplatImm <<
227                   " to " << NewElem << " in instruction: ");
228             DEBUG(MI.dump());
229             MI.getOperand(1).setReg(ShiftOp1);
230             MI.getOperand(2).setImm(NewElem);
231           }
232         }
233         break;
234       }
235       }
236     }
237 
238     // If the last instruction was marked for elimination,
239     // remove it now.
240     if (ToErase) {
241       ToErase->eraseFromParent();
242       ToErase = nullptr;
243     }
244   }
245 
246   return Simplified;
247 }
248 
249 // This is used to find the "true" source register for an
250 // XXPERMDI instruction, since MachineCSE does not handle the
251 // "copy-like" operations (Copy and SubregToReg).  Returns
252 // the original SrcReg unless it is the target of a copy-like
253 // operation, in which case we chain backwards through all
254 // such operations to the ultimate source register.  If a
255 // physical register is encountered, we stop the search.
256 unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
257 
258   while (true) {
259 
260     MachineInstr *MI = MRI->getVRegDef(SrcReg);
261     if (!MI->isCopyLike())
262       return SrcReg;
263 
264     unsigned CopySrcReg;
265     if (MI->isCopy())
266       CopySrcReg = MI->getOperand(1).getReg();
267     else {
268       assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
269       CopySrcReg = MI->getOperand(2).getReg();
270     }
271 
272     if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg))
273       return CopySrcReg;
274 
275     SrcReg = CopySrcReg;
276   }
277 }
278 
279 } // end default namespace
280 
281 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
282                       "PowerPC MI Peephole Optimization", false, false)
283 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
284                     "PowerPC MI Peephole Optimization", false, false)
285 
286 char PPCMIPeephole::ID = 0;
287 FunctionPass*
288 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
289 
290