1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===---------------------------------------------------------------------===// 8 // 9 // This pass performs peephole optimizations to clean up ugly code 10 // sequences at the MachineInstruction layer. It runs at the end of 11 // the SSA phases, following VSX swap removal. A pass of dead code 12 // elimination follows this one for quick clean-up of any dead 13 // instructions introduced here. Although we could do this as callbacks 14 // from the generic peephole pass, this would have a couple of bad 15 // effects: it might remove optimization opportunities for VSX swap 16 // removal, and it would miss cleanups made possible following VSX 17 // swap removal. 18 // 19 //===---------------------------------------------------------------------===// 20 21 #include "MCTargetDesc/PPCMCTargetDesc.h" 22 #include "MCTargetDesc/PPCPredicates.h" 23 #include "PPC.h" 24 #include "PPCInstrBuilder.h" 25 #include "PPCInstrInfo.h" 26 #include "PPCMachineFunctionInfo.h" 27 #include "PPCTargetMachine.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 30 #include "llvm/CodeGen/MachineDominators.h" 31 #include "llvm/CodeGen/MachineFunctionPass.h" 32 #include "llvm/CodeGen/MachineInstrBuilder.h" 33 #include "llvm/CodeGen/MachinePostDominators.h" 34 #include "llvm/CodeGen/MachineRegisterInfo.h" 35 #include "llvm/InitializePasses.h" 36 #include "llvm/Support/Debug.h" 37 38 using namespace llvm; 39 40 #define DEBUG_TYPE "ppc-mi-peepholes" 41 42 STATISTIC(RemoveTOCSave, "Number of TOC saves removed"); 43 STATISTIC(MultiTOCSaves, 44 "Number of functions with multiple TOC saves that must be kept"); 45 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue"); 46 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions"); 47 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions"); 48 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI"); 49 STATISTIC(NumConvertedToImmediateForm, 50 "Number of instructions converted to their immediate form"); 51 STATISTIC(NumFunctionsEnteredInMIPeephole, 52 "Number of functions entered in PPC MI Peepholes"); 53 STATISTIC(NumFixedPointIterations, 54 "Number of fixed-point iterations converting reg-reg instructions " 55 "to reg-imm ones"); 56 STATISTIC(NumRotatesCollapsed, 57 "Number of pairs of rotate left, clear left/right collapsed"); 58 STATISTIC(NumEXTSWAndSLDICombined, 59 "Number of pairs of EXTSW and SLDI combined as EXTSWSLI"); 60 61 static cl::opt<bool> 62 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), 63 cl::desc("Iterate to a fixed point when attempting to " 64 "convert reg-reg instructions to reg-imm")); 65 66 static cl::opt<bool> 67 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), 68 cl::desc("Convert eligible reg+reg instructions to reg+imm")); 69 70 static cl::opt<bool> 71 EnableSExtElimination("ppc-eliminate-signext", 72 cl::desc("enable elimination of sign-extensions"), 73 cl::init(false), cl::Hidden); 74 75 static cl::opt<bool> 76 EnableZExtElimination("ppc-eliminate-zeroext", 77 cl::desc("enable elimination of zero-extensions"), 78 cl::init(false), cl::Hidden); 79 80 namespace { 81 82 struct PPCMIPeephole : public MachineFunctionPass { 83 84 static char ID; 85 const PPCInstrInfo *TII; 86 MachineFunction *MF; 87 MachineRegisterInfo *MRI; 88 89 PPCMIPeephole() : MachineFunctionPass(ID) { 90 initializePPCMIPeepholePass(*PassRegistry::getPassRegistry()); 91 } 92 93 private: 94 MachineDominatorTree *MDT; 95 MachinePostDominatorTree *MPDT; 96 MachineBlockFrequencyInfo *MBFI; 97 uint64_t EntryFreq; 98 99 // Initialize class variables. 100 void initialize(MachineFunction &MFParm); 101 102 // Perform peepholes. 103 bool simplifyCode(void); 104 105 // Perform peepholes. 106 bool eliminateRedundantCompare(void); 107 bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves); 108 bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase); 109 bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI); 110 void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves, 111 MachineInstr *MI); 112 113 public: 114 115 void getAnalysisUsage(AnalysisUsage &AU) const override { 116 AU.addRequired<MachineDominatorTree>(); 117 AU.addRequired<MachinePostDominatorTree>(); 118 AU.addRequired<MachineBlockFrequencyInfo>(); 119 AU.addPreserved<MachineDominatorTree>(); 120 AU.addPreserved<MachinePostDominatorTree>(); 121 AU.addPreserved<MachineBlockFrequencyInfo>(); 122 MachineFunctionPass::getAnalysisUsage(AU); 123 } 124 125 // Main entry point for this pass. 126 bool runOnMachineFunction(MachineFunction &MF) override { 127 if (skipFunction(MF.getFunction())) 128 return false; 129 initialize(MF); 130 return simplifyCode(); 131 } 132 }; 133 134 // Initialize class variables. 135 void PPCMIPeephole::initialize(MachineFunction &MFParm) { 136 MF = &MFParm; 137 MRI = &MF->getRegInfo(); 138 MDT = &getAnalysis<MachineDominatorTree>(); 139 MPDT = &getAnalysis<MachinePostDominatorTree>(); 140 MBFI = &getAnalysis<MachineBlockFrequencyInfo>(); 141 EntryFreq = MBFI->getEntryFreq(); 142 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 143 LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 144 LLVM_DEBUG(MF->dump()); 145 } 146 147 static MachineInstr *getVRegDefOrNull(MachineOperand *Op, 148 MachineRegisterInfo *MRI) { 149 assert(Op && "Invalid Operand!"); 150 if (!Op->isReg()) 151 return nullptr; 152 153 Register Reg = Op->getReg(); 154 if (!Register::isVirtualRegister(Reg)) 155 return nullptr; 156 157 return MRI->getVRegDef(Reg); 158 } 159 160 // This function returns number of known zero bits in output of MI 161 // starting from the most significant bit. 162 static unsigned 163 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) { 164 unsigned Opcode = MI->getOpcode(); 165 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || 166 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) 167 return MI->getOperand(3).getImm(); 168 169 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && 170 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) 171 return MI->getOperand(3).getImm(); 172 173 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || 174 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || 175 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && 176 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) 177 return 32 + MI->getOperand(3).getImm(); 178 179 if (Opcode == PPC::ANDI_rec) { 180 uint16_t Imm = MI->getOperand(2).getImm(); 181 return 48 + countLeadingZeros(Imm); 182 } 183 184 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || 185 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || 186 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) 187 // The result ranges from 0 to 32. 188 return 58; 189 190 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec || 191 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec) 192 // The result ranges from 0 to 64. 193 return 57; 194 195 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || 196 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || 197 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || 198 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) 199 return 48; 200 201 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || 202 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || 203 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || 204 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) 205 return 56; 206 207 if (TII->isZeroExtended(*MI)) 208 return 32; 209 210 return 0; 211 } 212 213 // This function maintains a map for the pairs <TOC Save Instr, Keep> 214 // Each time a new TOC save is encountered, it checks if any of the existing 215 // ones are dominated by the new one. If so, it marks the existing one as 216 // redundant by setting it's entry in the map as false. It then adds the new 217 // instruction to the map with either true or false depending on if any 218 // existing instructions dominated the new one. 219 void PPCMIPeephole::UpdateTOCSaves( 220 std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) { 221 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here"); 222 assert(MF->getSubtarget<PPCSubtarget>().isELFv2ABI() && 223 "TOC-save removal only supported on ELFv2"); 224 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 225 226 MachineBasicBlock *Entry = &MF->front(); 227 uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency(); 228 229 // If the block in which the TOC save resides is in a block that 230 // post-dominates Entry, or a block that is hotter than entry (keep in mind 231 // that early MachineLICM has already run so the TOC save won't be hoisted) 232 // we can just do the save in the prologue. 233 if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry)) 234 FI->setMustSaveTOC(true); 235 236 // If we are saving the TOC in the prologue, all the TOC saves can be removed 237 // from the code. 238 if (FI->mustSaveTOC()) { 239 for (auto &TOCSave : TOCSaves) 240 TOCSave.second = false; 241 // Add new instruction to map. 242 TOCSaves[MI] = false; 243 return; 244 } 245 246 bool Keep = true; 247 for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) { 248 MachineInstr *CurrInst = It->first; 249 // If new instruction dominates an existing one, mark existing one as 250 // redundant. 251 if (It->second && MDT->dominates(MI, CurrInst)) 252 It->second = false; 253 // Check if the new instruction is redundant. 254 if (MDT->dominates(CurrInst, MI)) { 255 Keep = false; 256 break; 257 } 258 } 259 // Add new instruction to map. 260 TOCSaves[MI] = Keep; 261 } 262 263 // Perform peephole optimizations. 264 bool PPCMIPeephole::simplifyCode(void) { 265 bool Simplified = false; 266 MachineInstr* ToErase = nullptr; 267 std::map<MachineInstr *, bool> TOCSaves; 268 const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); 269 NumFunctionsEnteredInMIPeephole++; 270 if (ConvertRegReg) { 271 // Fixed-point conversion of reg/reg instructions fed by load-immediate 272 // into reg/imm instructions. FIXME: This is expensive, control it with 273 // an option. 274 bool SomethingChanged = false; 275 do { 276 NumFixedPointIterations++; 277 SomethingChanged = false; 278 for (MachineBasicBlock &MBB : *MF) { 279 for (MachineInstr &MI : MBB) { 280 if (MI.isDebugInstr()) 281 continue; 282 283 if (TII->convertToImmediateForm(MI)) { 284 // We don't erase anything in case the def has other uses. Let DCE 285 // remove it if it can be removed. 286 LLVM_DEBUG(dbgs() << "Converted instruction to imm form: "); 287 LLVM_DEBUG(MI.dump()); 288 NumConvertedToImmediateForm++; 289 SomethingChanged = true; 290 Simplified = true; 291 continue; 292 } 293 } 294 } 295 } while (SomethingChanged && FixedPointRegToImm); 296 } 297 298 for (MachineBasicBlock &MBB : *MF) { 299 for (MachineInstr &MI : MBB) { 300 301 // If the previous instruction was marked for elimination, 302 // remove it now. 303 if (ToErase) { 304 ToErase->eraseFromParent(); 305 ToErase = nullptr; 306 } 307 308 // Ignore debug instructions. 309 if (MI.isDebugInstr()) 310 continue; 311 312 // Per-opcode peepholes. 313 switch (MI.getOpcode()) { 314 315 default: 316 break; 317 318 case PPC::STD: { 319 MachineFrameInfo &MFI = MF->getFrameInfo(); 320 if (MFI.hasVarSizedObjects() || 321 !MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) 322 break; 323 // When encountering a TOC save instruction, call UpdateTOCSaves 324 // to add it to the TOCSaves map and mark any existing TOC saves 325 // it dominates as redundant. 326 if (TII->isTOCSaveMI(MI)) 327 UpdateTOCSaves(TOCSaves, &MI); 328 break; 329 } 330 case PPC::XXPERMDI: { 331 // Perform simplifications of 2x64 vector swaps and splats. 332 // A swap is identified by an immediate value of 2, and a splat 333 // is identified by an immediate value of 0 or 3. 334 int Immed = MI.getOperand(3).getImm(); 335 336 if (Immed == 1) 337 break; 338 339 // For each of these simplifications, we need the two source 340 // regs to match. Unfortunately, MachineCSE ignores COPY and 341 // SUBREG_TO_REG, so for example we can see 342 // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed. 343 // We have to look through chains of COPY and SUBREG_TO_REG 344 // to find the real source values for comparison. 345 unsigned TrueReg1 = 346 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 347 unsigned TrueReg2 = 348 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); 349 350 if (!(TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1))) 351 break; 352 353 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 354 355 if (!DefMI) 356 break; 357 358 unsigned DefOpc = DefMI->getOpcode(); 359 360 // If this is a splat fed by a splatting load, the splat is 361 // redundant. Replace with a copy. This doesn't happen directly due 362 // to code in PPCDAGToDAGISel.cpp, but it can happen when converting 363 // a load of a double to a vector of 64-bit integers. 364 auto isConversionOfLoadAndSplat = [=]() -> bool { 365 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) 366 return false; 367 unsigned FeedReg1 = 368 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 369 if (Register::isVirtualRegister(FeedReg1)) { 370 MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1); 371 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) 372 return true; 373 } 374 return false; 375 }; 376 if ((Immed == 0 || Immed == 3) && 377 (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) { 378 LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat " 379 "to load-and-splat/copy: "); 380 LLVM_DEBUG(MI.dump()); 381 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 382 MI.getOperand(0).getReg()) 383 .add(MI.getOperand(1)); 384 ToErase = &MI; 385 Simplified = true; 386 } 387 388 // If this is a splat or a swap fed by another splat, we 389 // can replace it with a copy. 390 if (DefOpc == PPC::XXPERMDI) { 391 unsigned DefReg1 = DefMI->getOperand(1).getReg(); 392 unsigned DefReg2 = DefMI->getOperand(2).getReg(); 393 unsigned DefImmed = DefMI->getOperand(3).getImm(); 394 395 // If the two inputs are not the same register, check to see if 396 // they originate from the same virtual register after only 397 // copy-like instructions. 398 if (DefReg1 != DefReg2) { 399 unsigned FeedReg1 = TRI->lookThruCopyLike(DefReg1, MRI); 400 unsigned FeedReg2 = TRI->lookThruCopyLike(DefReg2, MRI); 401 402 if (!(FeedReg1 == FeedReg2 && 403 Register::isVirtualRegister(FeedReg1))) 404 break; 405 } 406 407 if (DefImmed == 0 || DefImmed == 3) { 408 LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat " 409 "to splat/copy: "); 410 LLVM_DEBUG(MI.dump()); 411 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 412 MI.getOperand(0).getReg()) 413 .add(MI.getOperand(1)); 414 ToErase = &MI; 415 Simplified = true; 416 } 417 418 // If this is a splat fed by a swap, we can simplify modify 419 // the splat to splat the other value from the swap's input 420 // parameter. 421 else if ((Immed == 0 || Immed == 3) && DefImmed == 2) { 422 LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: "); 423 LLVM_DEBUG(MI.dump()); 424 MI.getOperand(1).setReg(DefReg1); 425 MI.getOperand(2).setReg(DefReg2); 426 MI.getOperand(3).setImm(3 - Immed); 427 Simplified = true; 428 } 429 430 // If this is a swap fed by a swap, we can replace it 431 // with a copy from the first swap's input. 432 else if (Immed == 2 && DefImmed == 2) { 433 LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: "); 434 LLVM_DEBUG(MI.dump()); 435 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 436 MI.getOperand(0).getReg()) 437 .add(DefMI->getOperand(1)); 438 ToErase = &MI; 439 Simplified = true; 440 } 441 } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs && 442 (DefMI->getOperand(2).getImm() == 0 || 443 DefMI->getOperand(2).getImm() == 3)) { 444 // Splat fed by another splat - switch the output of the first 445 // and remove the second. 446 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 447 ToErase = &MI; 448 Simplified = true; 449 LLVM_DEBUG(dbgs() << "Removing redundant splat: "); 450 LLVM_DEBUG(MI.dump()); 451 } 452 break; 453 } 454 case PPC::VSPLTB: 455 case PPC::VSPLTH: 456 case PPC::XXSPLTW: { 457 unsigned MyOpcode = MI.getOpcode(); 458 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; 459 unsigned TrueReg = 460 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI); 461 if (!Register::isVirtualRegister(TrueReg)) 462 break; 463 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 464 if (!DefMI) 465 break; 466 unsigned DefOpcode = DefMI->getOpcode(); 467 auto isConvertOfSplat = [=]() -> bool { 468 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) 469 return false; 470 Register ConvReg = DefMI->getOperand(1).getReg(); 471 if (!Register::isVirtualRegister(ConvReg)) 472 return false; 473 MachineInstr *Splt = MRI->getVRegDef(ConvReg); 474 return Splt && (Splt->getOpcode() == PPC::LXVWSX || 475 Splt->getOpcode() == PPC::XXSPLTW); 476 }; 477 bool AlreadySplat = (MyOpcode == DefOpcode) || 478 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || 479 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || 480 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || 481 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || 482 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| 483 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); 484 // If the instruction[s] that feed this splat have already splat 485 // the value, this splat is redundant. 486 if (AlreadySplat) { 487 LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: "); 488 LLVM_DEBUG(MI.dump()); 489 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 490 MI.getOperand(0).getReg()) 491 .add(MI.getOperand(OpNo)); 492 ToErase = &MI; 493 Simplified = true; 494 } 495 // Splat fed by a shift. Usually when we align value to splat into 496 // vector element zero. 497 if (DefOpcode == PPC::XXSLDWI) { 498 Register ShiftRes = DefMI->getOperand(0).getReg(); 499 Register ShiftOp1 = DefMI->getOperand(1).getReg(); 500 Register ShiftOp2 = DefMI->getOperand(2).getReg(); 501 unsigned ShiftImm = DefMI->getOperand(3).getImm(); 502 unsigned SplatImm = MI.getOperand(2).getImm(); 503 if (ShiftOp1 == ShiftOp2) { 504 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; 505 if (MRI->hasOneNonDBGUse(ShiftRes)) { 506 LLVM_DEBUG(dbgs() << "Removing redundant shift: "); 507 LLVM_DEBUG(DefMI->dump()); 508 ToErase = DefMI; 509 } 510 Simplified = true; 511 LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm 512 << " to " << NewElem << " in instruction: "); 513 LLVM_DEBUG(MI.dump()); 514 MI.getOperand(1).setReg(ShiftOp1); 515 MI.getOperand(2).setImm(NewElem); 516 } 517 } 518 break; 519 } 520 case PPC::XVCVDPSP: { 521 // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant. 522 unsigned TrueReg = 523 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 524 if (!Register::isVirtualRegister(TrueReg)) 525 break; 526 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); 527 528 // This can occur when building a vector of single precision or integer 529 // values. 530 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 531 unsigned DefsReg1 = 532 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); 533 unsigned DefsReg2 = 534 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI); 535 if (!Register::isVirtualRegister(DefsReg1) || 536 !Register::isVirtualRegister(DefsReg2)) 537 break; 538 MachineInstr *P1 = MRI->getVRegDef(DefsReg1); 539 MachineInstr *P2 = MRI->getVRegDef(DefsReg2); 540 541 if (!P1 || !P2) 542 break; 543 544 // Remove the passed FRSP/XSRSP instruction if it only feeds this MI 545 // and set any uses of that FRSP/XSRSP (in this MI) to the source of 546 // the FRSP/XSRSP. 547 auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) { 548 unsigned Opc = RoundInstr->getOpcode(); 549 if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) && 550 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) { 551 Simplified = true; 552 Register ConvReg1 = RoundInstr->getOperand(1).getReg(); 553 Register FRSPDefines = RoundInstr->getOperand(0).getReg(); 554 MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines)); 555 for (int i = 0, e = Use.getNumOperands(); i < e; ++i) 556 if (Use.getOperand(i).isReg() && 557 Use.getOperand(i).getReg() == FRSPDefines) 558 Use.getOperand(i).setReg(ConvReg1); 559 LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n"); 560 LLVM_DEBUG(RoundInstr->dump()); 561 LLVM_DEBUG(dbgs() << "As it feeds instruction:\n"); 562 LLVM_DEBUG(MI.dump()); 563 LLVM_DEBUG(dbgs() << "Through instruction:\n"); 564 LLVM_DEBUG(DefMI->dump()); 565 RoundInstr->eraseFromParent(); 566 } 567 }; 568 569 // If the input to XVCVDPSP is a vector that was built (even 570 // partially) out of FRSP's, the FRSP(s) can safely be removed 571 // since this instruction performs the same operation. 572 if (P1 != P2) { 573 removeFRSPIfPossible(P1); 574 removeFRSPIfPossible(P2); 575 break; 576 } 577 removeFRSPIfPossible(P1); 578 } 579 break; 580 } 581 case PPC::EXTSH: 582 case PPC::EXTSH8: 583 case PPC::EXTSH8_32_64: { 584 if (!EnableSExtElimination) break; 585 Register NarrowReg = MI.getOperand(1).getReg(); 586 if (!Register::isVirtualRegister(NarrowReg)) 587 break; 588 589 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 590 // If we've used a zero-extending load that we will sign-extend, 591 // just do a sign-extending load. 592 if (SrcMI->getOpcode() == PPC::LHZ || 593 SrcMI->getOpcode() == PPC::LHZX) { 594 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 595 break; 596 auto is64Bit = [] (unsigned Opcode) { 597 return Opcode == PPC::EXTSH8; 598 }; 599 auto isXForm = [] (unsigned Opcode) { 600 return Opcode == PPC::LHZX; 601 }; 602 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 603 if (is64Bit) 604 if (isXForm) return PPC::LHAX8; 605 else return PPC::LHA8; 606 else 607 if (isXForm) return PPC::LHAX; 608 else return PPC::LHA; 609 }; 610 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 611 isXForm(SrcMI->getOpcode())); 612 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 613 LLVM_DEBUG(SrcMI->dump()); 614 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 615 LLVM_DEBUG(MI.dump()); 616 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 617 SrcMI->setDesc(TII->get(Opc)); 618 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 619 ToErase = &MI; 620 Simplified = true; 621 NumEliminatedSExt++; 622 } 623 break; 624 } 625 case PPC::EXTSW: 626 case PPC::EXTSW_32: 627 case PPC::EXTSW_32_64: { 628 if (!EnableSExtElimination) break; 629 Register NarrowReg = MI.getOperand(1).getReg(); 630 if (!Register::isVirtualRegister(NarrowReg)) 631 break; 632 633 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); 634 // If we've used a zero-extending load that we will sign-extend, 635 // just do a sign-extending load. 636 if (SrcMI->getOpcode() == PPC::LWZ || 637 SrcMI->getOpcode() == PPC::LWZX) { 638 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) 639 break; 640 auto is64Bit = [] (unsigned Opcode) { 641 return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64; 642 }; 643 auto isXForm = [] (unsigned Opcode) { 644 return Opcode == PPC::LWZX; 645 }; 646 auto getSextLoadOp = [] (bool is64Bit, bool isXForm) { 647 if (is64Bit) 648 if (isXForm) return PPC::LWAX; 649 else return PPC::LWA; 650 else 651 if (isXForm) return PPC::LWAX_32; 652 else return PPC::LWA_32; 653 }; 654 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 655 isXForm(SrcMI->getOpcode())); 656 LLVM_DEBUG(dbgs() << "Zero-extending load\n"); 657 LLVM_DEBUG(SrcMI->dump()); 658 LLVM_DEBUG(dbgs() << "and sign-extension\n"); 659 LLVM_DEBUG(MI.dump()); 660 LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n"); 661 SrcMI->setDesc(TII->get(Opc)); 662 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 663 ToErase = &MI; 664 Simplified = true; 665 NumEliminatedSExt++; 666 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && 667 TII->isSignExtended(*SrcMI)) { 668 // We can eliminate EXTSW if the input is known to be already 669 // sign-extended. 670 LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n"); 671 Register TmpReg = 672 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); 673 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 674 TmpReg); 675 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 676 MI.getOperand(0).getReg()) 677 .addReg(TmpReg) 678 .addReg(NarrowReg) 679 .addImm(PPC::sub_32); 680 ToErase = &MI; 681 Simplified = true; 682 NumEliminatedSExt++; 683 } 684 break; 685 } 686 case PPC::RLDICL: { 687 // We can eliminate RLDICL (e.g. for zero-extension) 688 // if all bits to clear are already zero in the input. 689 // This code assume following code sequence for zero-extension. 690 // %6 = COPY %5:sub_32; (optional) 691 // %8 = IMPLICIT_DEF; 692 // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32; 693 if (!EnableZExtElimination) break; 694 695 if (MI.getOperand(2).getImm() != 0) 696 break; 697 698 Register SrcReg = MI.getOperand(1).getReg(); 699 if (!Register::isVirtualRegister(SrcReg)) 700 break; 701 702 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 703 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && 704 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) 705 break; 706 707 MachineInstr *ImpDefMI, *SubRegMI; 708 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 709 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg()); 710 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; 711 712 SrcMI = SubRegMI; 713 if (SubRegMI->getOpcode() == PPC::COPY) { 714 Register CopyReg = SubRegMI->getOperand(1).getReg(); 715 if (Register::isVirtualRegister(CopyReg)) 716 SrcMI = MRI->getVRegDef(CopyReg); 717 } 718 719 unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII); 720 if (MI.getOperand(3).getImm() <= KnownZeroCount) { 721 LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n"); 722 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 723 MI.getOperand(0).getReg()) 724 .addReg(SrcReg); 725 ToErase = &MI; 726 Simplified = true; 727 NumEliminatedZExt++; 728 } 729 break; 730 } 731 732 // TODO: Any instruction that has an immediate form fed only by a PHI 733 // whose operands are all load immediate can be folded away. We currently 734 // do this for ADD instructions, but should expand it to arithmetic and 735 // binary instructions with immediate forms in the future. 736 case PPC::ADD4: 737 case PPC::ADD8: { 738 auto isSingleUsePHI = [&](MachineOperand *PhiOp) { 739 assert(PhiOp && "Invalid Operand!"); 740 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 741 742 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && 743 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg()); 744 }; 745 746 auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp, 747 MachineOperand *PhiOp) { 748 assert(PhiOp && "Invalid Operand!"); 749 assert(DominatorOp && "Invalid Operand!"); 750 MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI); 751 MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI); 752 753 // Note: the vregs only show up at odd indices position of PHI Node, 754 // the even indices position save the BB info. 755 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 756 MachineInstr *LiMI = 757 getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 758 if (!LiMI || 759 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) 760 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) || 761 !MDT->dominates(DefDomMI, LiMI)) 762 return false; 763 } 764 765 return true; 766 }; 767 768 MachineOperand Op1 = MI.getOperand(1); 769 MachineOperand Op2 = MI.getOperand(2); 770 if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2)) 771 std::swap(Op1, Op2); 772 else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1)) 773 break; // We don't have an ADD fed by LI's that can be transformed 774 775 // Now we know that Op1 is the PHI node and Op2 is the dominator 776 Register DominatorReg = Op2.getReg(); 777 778 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 779 ? &PPC::G8RC_and_G8RC_NOX0RegClass 780 : &PPC::GPRC_and_GPRC_NOR0RegClass; 781 MRI->setRegClass(DominatorReg, TRC); 782 783 // replace LIs with ADDIs 784 MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI); 785 for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) { 786 MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI); 787 LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: "); 788 LLVM_DEBUG(LiMI->dump()); 789 790 // There could be repeated registers in the PHI, e.g: %1 = 791 // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've 792 // already replaced the def instruction, skip. 793 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) 794 continue; 795 796 assert((LiMI->getOpcode() == PPC::LI || 797 LiMI->getOpcode() == PPC::LI8) && 798 "Invalid Opcode!"); 799 auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI 800 LiMI->RemoveOperand(1); // remove the imm of LI 801 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI 802 : PPC::ADDI8)); 803 MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI) 804 .addReg(DominatorReg) 805 .addImm(LiImm); // restore the imm of LI 806 LLVM_DEBUG(LiMI->dump()); 807 } 808 809 // Replace ADD with COPY 810 LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: "); 811 LLVM_DEBUG(MI.dump()); 812 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 813 MI.getOperand(0).getReg()) 814 .add(Op1); 815 ToErase = &MI; 816 Simplified = true; 817 NumOptADDLIs++; 818 break; 819 } 820 case PPC::RLDICR: { 821 Simplified |= emitRLDICWhenLoweringJumpTables(MI) || 822 combineSEXTAndSHL(MI, ToErase); 823 break; 824 } 825 case PPC::RLWINM: 826 case PPC::RLWINM_rec: 827 case PPC::RLWINM8: 828 case PPC::RLWINM8_rec: { 829 unsigned FoldingReg = MI.getOperand(1).getReg(); 830 if (!Register::isVirtualRegister(FoldingReg)) 831 break; 832 833 MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg); 834 if (SrcMI->getOpcode() != PPC::RLWINM && 835 SrcMI->getOpcode() != PPC::RLWINM_rec && 836 SrcMI->getOpcode() != PPC::RLWINM8 && 837 SrcMI->getOpcode() != PPC::RLWINM8_rec) 838 break; 839 assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() && 840 MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() && 841 SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) && 842 "Invalid PPC::RLWINM Instruction!"); 843 uint64_t SHSrc = SrcMI->getOperand(2).getImm(); 844 uint64_t SHMI = MI.getOperand(2).getImm(); 845 uint64_t MBSrc = SrcMI->getOperand(3).getImm(); 846 uint64_t MBMI = MI.getOperand(3).getImm(); 847 uint64_t MESrc = SrcMI->getOperand(4).getImm(); 848 uint64_t MEMI = MI.getOperand(4).getImm(); 849 850 assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) && 851 "Invalid PPC::RLWINM Instruction!"); 852 853 // If MBMI is bigger than MEMI, we always can not get run of ones. 854 // RotatedSrcMask non-wrap: 855 // 0........31|32........63 856 // RotatedSrcMask: B---E B---E 857 // MaskMI: -----------|--E B------ 858 // Result: ----- --- (Bad candidate) 859 // 860 // RotatedSrcMask wrap: 861 // 0........31|32........63 862 // RotatedSrcMask: --E B----|--E B---- 863 // MaskMI: -----------|--E B------ 864 // Result: --- -----|--- ----- (Bad candidate) 865 // 866 // One special case is RotatedSrcMask is a full set mask. 867 // RotatedSrcMask full: 868 // 0........31|32........63 869 // RotatedSrcMask: ------EB---|-------EB--- 870 // MaskMI: -----------|--E B------ 871 // Result: -----------|--- ------- (Good candidate) 872 873 // Mark special case. 874 bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31); 875 876 // For other MBMI > MEMI cases, just return. 877 if ((MBMI > MEMI) && !SrcMaskFull) 878 break; 879 880 // Handle MBMI <= MEMI cases. 881 APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI); 882 // In MI, we only need low 32 bits of SrcMI, just consider about low 32 883 // bit of SrcMI mask. Note that in APInt, lowerest bit is at index 0, 884 // while in PowerPC ISA, lowerest bit is at index 63. 885 APInt MaskSrc = 886 APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc); 887 // Current APInt::getBitsSetWithWrap sets all bits to 0 if loBit is 888 // equal to highBit. 889 // If MBSrc - MESrc == 1, we expect a full set mask instead of Null. 890 if (SrcMaskFull && (MBSrc - MESrc == 1)) 891 MaskSrc.setAllBits(); 892 893 APInt RotatedSrcMask = MaskSrc.rotl(SHMI); 894 APInt FinalMask = RotatedSrcMask & MaskMI; 895 uint32_t NewMB, NewME; 896 897 // If final mask is 0, MI result should be 0 too. 898 if (FinalMask.isNullValue()) { 899 bool Is64Bit = (MI.getOpcode() == PPC::RLWINM8 || 900 MI.getOpcode() == PPC::RLWINM8_rec); 901 902 Simplified = true; 903 904 LLVM_DEBUG(dbgs() << "Replace Instr: "); 905 LLVM_DEBUG(MI.dump()); 906 907 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { 908 // Replace MI with "LI 0" 909 MI.RemoveOperand(4); 910 MI.RemoveOperand(3); 911 MI.RemoveOperand(2); 912 MI.getOperand(1).ChangeToImmediate(0); 913 MI.setDesc(TII->get(Is64Bit ? PPC::LI8 : PPC::LI)); 914 } else { 915 // Replace MI with "ANDI_rec reg, 0" 916 MI.RemoveOperand(4); 917 MI.RemoveOperand(3); 918 MI.getOperand(2).setImm(0); 919 MI.setDesc(TII->get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); 920 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 921 if (SrcMI->getOperand(1).isKill()) { 922 MI.getOperand(1).setIsKill(true); 923 SrcMI->getOperand(1).setIsKill(false); 924 } else 925 // About to replace MI.getOperand(1), clear its kill flag. 926 MI.getOperand(1).setIsKill(false); 927 } 928 929 LLVM_DEBUG(dbgs() << "With: "); 930 LLVM_DEBUG(MI.dump()); 931 } else if ((isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, 932 NewME) && NewMB <= NewME)|| SrcMaskFull) { 933 // Here we only handle MBMI <= MEMI case, so NewMB must be no bigger 934 // than NewME. Otherwise we get a 64 bit value after folding, but MI 935 // return a 32 bit value. 936 937 Simplified = true; 938 LLVM_DEBUG(dbgs() << "Converting Instr: "); 939 LLVM_DEBUG(MI.dump()); 940 941 uint16_t NewSH = (SHSrc + SHMI) % 32; 942 MI.getOperand(2).setImm(NewSH); 943 // If SrcMI mask is full, no need to update MBMI and MEMI. 944 if (!SrcMaskFull) { 945 MI.getOperand(3).setImm(NewMB); 946 MI.getOperand(4).setImm(NewME); 947 } 948 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 949 if (SrcMI->getOperand(1).isKill()) { 950 MI.getOperand(1).setIsKill(true); 951 SrcMI->getOperand(1).setIsKill(false); 952 } else 953 // About to replace MI.getOperand(1), clear its kill flag. 954 MI.getOperand(1).setIsKill(false); 955 956 LLVM_DEBUG(dbgs() << "To: "); 957 LLVM_DEBUG(MI.dump()); 958 } 959 if (Simplified) { 960 // If FoldingReg has no non-debug use and it has no implicit def (it 961 // is not RLWINMO or RLWINM8o), it's safe to delete its def SrcMI. 962 // Otherwise keep it. 963 ++NumRotatesCollapsed; 964 if (MRI->use_nodbg_empty(FoldingReg) && !SrcMI->hasImplicitDef()) { 965 ToErase = SrcMI; 966 LLVM_DEBUG(dbgs() << "Delete dead instruction: "); 967 LLVM_DEBUG(SrcMI->dump()); 968 } 969 } 970 break; 971 } 972 } 973 } 974 975 // If the last instruction was marked for elimination, 976 // remove it now. 977 if (ToErase) { 978 ToErase->eraseFromParent(); 979 ToErase = nullptr; 980 } 981 } 982 983 // Eliminate all the TOC save instructions which are redundant. 984 Simplified |= eliminateRedundantTOCSaves(TOCSaves); 985 PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); 986 if (FI->mustSaveTOC()) 987 NumTOCSavesInPrologue++; 988 989 // We try to eliminate redundant compare instruction. 990 Simplified |= eliminateRedundantCompare(); 991 992 return Simplified; 993 } 994 995 // helper functions for eliminateRedundantCompare 996 static bool isEqOrNe(MachineInstr *BI) { 997 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 998 unsigned PredCond = PPC::getPredicateCondition(Pred); 999 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); 1000 } 1001 1002 static bool isSupportedCmpOp(unsigned opCode) { 1003 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 1004 opCode == PPC::CMPLW || opCode == PPC::CMPW || 1005 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || 1006 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); 1007 } 1008 1009 static bool is64bitCmpOp(unsigned opCode) { 1010 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || 1011 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); 1012 } 1013 1014 static bool isSignedCmpOp(unsigned opCode) { 1015 return (opCode == PPC::CMPD || opCode == PPC::CMPW || 1016 opCode == PPC::CMPDI || opCode == PPC::CMPWI); 1017 } 1018 1019 static unsigned getSignedCmpOpCode(unsigned opCode) { 1020 if (opCode == PPC::CMPLD) return PPC::CMPD; 1021 if (opCode == PPC::CMPLW) return PPC::CMPW; 1022 if (opCode == PPC::CMPLDI) return PPC::CMPDI; 1023 if (opCode == PPC::CMPLWI) return PPC::CMPWI; 1024 return opCode; 1025 } 1026 1027 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or 1028 // (LT x) to (LE x-1) 1029 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) { 1030 uint64_t Imm = CMPI->getOperand(2).getImm(); 1031 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1032 if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000)) 1033 return 0; 1034 1035 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1036 unsigned PredCond = PPC::getPredicateCondition(Pred); 1037 unsigned PredHint = PPC::getPredicateHint(Pred); 1038 if (PredCond == PPC::PRED_GE) 1039 return PPC::getPredicate(PPC::PRED_GT, PredHint); 1040 if (PredCond == PPC::PRED_LT) 1041 return PPC::getPredicate(PPC::PRED_LE, PredHint); 1042 1043 return 0; 1044 } 1045 1046 // We can increment immediate x in (GT x) by changing it to (GE x+1) or 1047 // (LE x) to (LT x+1) 1048 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) { 1049 uint64_t Imm = CMPI->getOperand(2).getImm(); 1050 bool SignedCmp = isSignedCmpOp(CMPI->getOpcode()); 1051 if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF)) 1052 return 0; 1053 1054 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); 1055 unsigned PredCond = PPC::getPredicateCondition(Pred); 1056 unsigned PredHint = PPC::getPredicateHint(Pred); 1057 if (PredCond == PPC::PRED_GT) 1058 return PPC::getPredicate(PPC::PRED_GE, PredHint); 1059 if (PredCond == PPC::PRED_LE) 1060 return PPC::getPredicate(PPC::PRED_LT, PredHint); 1061 1062 return 0; 1063 } 1064 1065 // This takes a Phi node and returns a register value for the specified BB. 1066 static unsigned getIncomingRegForBlock(MachineInstr *Phi, 1067 MachineBasicBlock *MBB) { 1068 for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) { 1069 MachineOperand &MO = Phi->getOperand(I); 1070 if (MO.getMBB() == MBB) 1071 return Phi->getOperand(I-1).getReg(); 1072 } 1073 llvm_unreachable("invalid src basic block for this Phi node\n"); 1074 return 0; 1075 } 1076 1077 // This function tracks the source of the register through register copy. 1078 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2 1079 // assuming that the control comes from BB1 into BB2. 1080 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1, 1081 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) { 1082 unsigned SrcReg = Reg; 1083 while (1) { 1084 unsigned NextReg = SrcReg; 1085 MachineInstr *Inst = MRI->getVRegDef(SrcReg); 1086 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { 1087 NextReg = getIncomingRegForBlock(Inst, BB1); 1088 // We track through PHI only once to avoid infinite loop. 1089 BB1 = nullptr; 1090 } 1091 else if (Inst->isFullCopy()) 1092 NextReg = Inst->getOperand(1).getReg(); 1093 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg)) 1094 break; 1095 SrcReg = NextReg; 1096 } 1097 return SrcReg; 1098 } 1099 1100 static bool eligibleForCompareElimination(MachineBasicBlock &MBB, 1101 MachineBasicBlock *&PredMBB, 1102 MachineBasicBlock *&MBBtoMoveCmp, 1103 MachineRegisterInfo *MRI) { 1104 1105 auto isEligibleBB = [&](MachineBasicBlock &BB) { 1106 auto BII = BB.getFirstInstrTerminator(); 1107 // We optimize BBs ending with a conditional branch. 1108 // We check only for BCC here, not BCCLR, because BCCLR 1109 // will be formed only later in the pipeline. 1110 if (BB.succ_size() == 2 && 1111 BII != BB.instr_end() && 1112 (*BII).getOpcode() == PPC::BCC && 1113 (*BII).getOperand(1).isReg()) { 1114 // We optimize only if the condition code is used only by one BCC. 1115 Register CndReg = (*BII).getOperand(1).getReg(); 1116 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg)) 1117 return false; 1118 1119 MachineInstr *CMPI = MRI->getVRegDef(CndReg); 1120 // We assume compare and branch are in the same BB for ease of analysis. 1121 if (CMPI->getParent() != &BB) 1122 return false; 1123 1124 // We skip this BB if a physical register is used in comparison. 1125 for (MachineOperand &MO : CMPI->operands()) 1126 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg())) 1127 return false; 1128 1129 return true; 1130 } 1131 return false; 1132 }; 1133 1134 // If this BB has more than one successor, we can create a new BB and 1135 // move the compare instruction in the new BB. 1136 // So far, we do not move compare instruction to a BB having multiple 1137 // successors to avoid potentially increasing code size. 1138 auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) { 1139 return BB.succ_size() == 1; 1140 }; 1141 1142 if (!isEligibleBB(MBB)) 1143 return false; 1144 1145 unsigned NumPredBBs = MBB.pred_size(); 1146 if (NumPredBBs == 1) { 1147 MachineBasicBlock *TmpMBB = *MBB.pred_begin(); 1148 if (isEligibleBB(*TmpMBB)) { 1149 PredMBB = TmpMBB; 1150 MBBtoMoveCmp = nullptr; 1151 return true; 1152 } 1153 } 1154 else if (NumPredBBs == 2) { 1155 // We check for partially redundant case. 1156 // So far, we support cases with only two predecessors 1157 // to avoid increasing the number of instructions. 1158 MachineBasicBlock::pred_iterator PI = MBB.pred_begin(); 1159 MachineBasicBlock *Pred1MBB = *PI; 1160 MachineBasicBlock *Pred2MBB = *(PI+1); 1161 1162 if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) { 1163 // We assume Pred1MBB is the BB containing the compare to be merged and 1164 // Pred2MBB is the BB to which we will append a compare instruction. 1165 // Hence we can proceed as is. 1166 } 1167 else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) { 1168 // We need to swap Pred1MBB and Pred2MBB to canonicalize. 1169 std::swap(Pred1MBB, Pred2MBB); 1170 } 1171 else return false; 1172 1173 // Here, Pred2MBB is the BB to which we need to append a compare inst. 1174 // We cannot move the compare instruction if operands are not available 1175 // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI). 1176 MachineInstr *BI = &*MBB.getFirstInstrTerminator(); 1177 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg()); 1178 for (int I = 1; I <= 2; I++) 1179 if (CMPI->getOperand(I).isReg()) { 1180 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg()); 1181 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) 1182 return false; 1183 } 1184 1185 PredMBB = Pred1MBB; 1186 MBBtoMoveCmp = Pred2MBB; 1187 return true; 1188 } 1189 1190 return false; 1191 } 1192 1193 // This function will iterate over the input map containing a pair of TOC save 1194 // instruction and a flag. The flag will be set to false if the TOC save is 1195 // proven redundant. This function will erase from the basic block all the TOC 1196 // saves marked as redundant. 1197 bool PPCMIPeephole::eliminateRedundantTOCSaves( 1198 std::map<MachineInstr *, bool> &TOCSaves) { 1199 bool Simplified = false; 1200 int NumKept = 0; 1201 for (auto TOCSave : TOCSaves) { 1202 if (!TOCSave.second) { 1203 TOCSave.first->eraseFromParent(); 1204 RemoveTOCSave++; 1205 Simplified = true; 1206 } else { 1207 NumKept++; 1208 } 1209 } 1210 1211 if (NumKept > 1) 1212 MultiTOCSaves++; 1213 1214 return Simplified; 1215 } 1216 1217 // If multiple conditional branches are executed based on the (essentially) 1218 // same comparison, we merge compare instructions into one and make multiple 1219 // conditional branches on this comparison. 1220 // For example, 1221 // if (a == 0) { ... } 1222 // else if (a < 0) { ... } 1223 // can be executed by one compare and two conditional branches instead of 1224 // two pairs of a compare and a conditional branch. 1225 // 1226 // This method merges two compare instructions in two MBBs and modifies the 1227 // compare and conditional branch instructions if needed. 1228 // For the above example, the input for this pass looks like: 1229 // cmplwi r3, 0 1230 // beq 0, .LBB0_3 1231 // cmpwi r3, -1 1232 // bgt 0, .LBB0_4 1233 // So, before merging two compares, we need to modify these instructions as 1234 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq 1235 // beq 0, .LBB0_3 1236 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0 1237 // bge 0, .LBB0_4 1238 1239 bool PPCMIPeephole::eliminateRedundantCompare(void) { 1240 bool Simplified = false; 1241 1242 for (MachineBasicBlock &MBB2 : *MF) { 1243 MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr; 1244 1245 // For fully redundant case, we select two basic blocks MBB1 and MBB2 1246 // as an optimization target if 1247 // - both MBBs end with a conditional branch, 1248 // - MBB1 is the only predecessor of MBB2, and 1249 // - compare does not take a physical register as a operand in both MBBs. 1250 // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr. 1251 // 1252 // As partially redundant case, we additionally handle if MBB2 has one 1253 // additional predecessor, which has only one successor (MBB2). 1254 // In this case, we move the compare instruction originally in MBB2 into 1255 // MBBtoMoveCmp. This partially redundant case is typically appear by 1256 // compiling a while loop; here, MBBtoMoveCmp is the loop preheader. 1257 // 1258 // Overview of CFG of related basic blocks 1259 // Fully redundant case Partially redundant case 1260 // -------- ---------------- -------- 1261 // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ) 1262 // -------- ---------------- -------- 1263 // | \ (w/ 1 succ) \ | \ 1264 // | \ \ | \ 1265 // | \ | 1266 // -------- -------- 1267 // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred 1268 // -------- and 2 succ) -------- and 2 succ) 1269 // | \ | \ 1270 // | \ | \ 1271 // 1272 if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI)) 1273 continue; 1274 1275 MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator(); 1276 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg()); 1277 1278 MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator(); 1279 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg()); 1280 bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr); 1281 1282 // We cannot optimize an unsupported compare opcode or 1283 // a mix of 32-bit and 64-bit comaprisons 1284 if (!isSupportedCmpOp(CMPI1->getOpcode()) || 1285 !isSupportedCmpOp(CMPI2->getOpcode()) || 1286 is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode())) 1287 continue; 1288 1289 unsigned NewOpCode = 0; 1290 unsigned NewPredicate1 = 0, NewPredicate2 = 0; 1291 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0; 1292 bool SwapOperands = false; 1293 1294 if (CMPI1->getOpcode() != CMPI2->getOpcode()) { 1295 // Typically, unsigned comparison is used for equality check, but 1296 // we replace it with a signed comparison if the comparison 1297 // to be merged is a signed comparison. 1298 // In other cases of opcode mismatch, we cannot optimize this. 1299 1300 // We cannot change opcode when comparing against an immediate 1301 // if the most significant bit of the immediate is one 1302 // due to the difference in sign extension. 1303 auto CmpAgainstImmWithSignBit = [](MachineInstr *I) { 1304 if (!I->getOperand(2).isImm()) 1305 return false; 1306 int16_t Imm = (int16_t)I->getOperand(2).getImm(); 1307 return Imm < 0; 1308 }; 1309 1310 if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) && 1311 CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode())) 1312 NewOpCode = CMPI1->getOpcode(); 1313 else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) && 1314 getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode()) 1315 NewOpCode = CMPI2->getOpcode(); 1316 else continue; 1317 } 1318 1319 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { 1320 // In case of comparisons between two registers, these two registers 1321 // must be same to merge two comparisons. 1322 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1323 nullptr, nullptr, MRI); 1324 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(), 1325 nullptr, nullptr, MRI); 1326 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1327 MBB1, &MBB2, MRI); 1328 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(), 1329 MBB1, &MBB2, MRI); 1330 1331 if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) { 1332 // Same pair of registers in the same order; ready to merge as is. 1333 } 1334 else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) { 1335 // Same pair of registers in different order. 1336 // We reverse the predicate to merge compare instructions. 1337 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); 1338 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); 1339 // In case of partial redundancy, we need to swap operands 1340 // in another compare instruction. 1341 SwapOperands = true; 1342 } 1343 else continue; 1344 } 1345 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { 1346 // In case of comparisons between a register and an immediate, 1347 // the operand register must be same for two compare instructions. 1348 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), 1349 nullptr, nullptr, MRI); 1350 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(), 1351 MBB1, &MBB2, MRI); 1352 if (Cmp1Operand1 != Cmp2Operand1) 1353 continue; 1354 1355 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm(); 1356 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm(); 1357 1358 // If immediate are not same, we try to adjust by changing predicate; 1359 // e.g. GT imm means GE (imm+1). 1360 if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) { 1361 int Diff = Imm1 - Imm2; 1362 if (Diff < -2 || Diff > 2) 1363 continue; 1364 1365 unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1); 1366 unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1); 1367 unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2); 1368 unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2); 1369 if (Diff == 2) { 1370 if (PredToInc2 && PredToDec1) { 1371 NewPredicate2 = PredToInc2; 1372 NewPredicate1 = PredToDec1; 1373 NewImm2++; 1374 NewImm1--; 1375 } 1376 } 1377 else if (Diff == 1) { 1378 if (PredToInc2) { 1379 NewImm2++; 1380 NewPredicate2 = PredToInc2; 1381 } 1382 else if (PredToDec1) { 1383 NewImm1--; 1384 NewPredicate1 = PredToDec1; 1385 } 1386 } 1387 else if (Diff == -1) { 1388 if (PredToDec2) { 1389 NewImm2--; 1390 NewPredicate2 = PredToDec2; 1391 } 1392 else if (PredToInc1) { 1393 NewImm1++; 1394 NewPredicate1 = PredToInc1; 1395 } 1396 } 1397 else if (Diff == -2) { 1398 if (PredToDec2 && PredToInc1) { 1399 NewPredicate2 = PredToDec2; 1400 NewPredicate1 = PredToInc1; 1401 NewImm2--; 1402 NewImm1++; 1403 } 1404 } 1405 } 1406 1407 // We cannot merge two compares if the immediates are not same. 1408 if (NewImm2 != NewImm1) 1409 continue; 1410 } 1411 1412 LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n"); 1413 LLVM_DEBUG(CMPI1->dump()); 1414 LLVM_DEBUG(BI1->dump()); 1415 LLVM_DEBUG(CMPI2->dump()); 1416 LLVM_DEBUG(BI2->dump()); 1417 1418 // We adjust opcode, predicates and immediate as we determined above. 1419 if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) { 1420 CMPI1->setDesc(TII->get(NewOpCode)); 1421 } 1422 if (NewPredicate1) { 1423 BI1->getOperand(0).setImm(NewPredicate1); 1424 } 1425 if (NewPredicate2) { 1426 BI2->getOperand(0).setImm(NewPredicate2); 1427 } 1428 if (NewImm1 != Imm1) { 1429 CMPI1->getOperand(2).setImm(NewImm1); 1430 } 1431 1432 if (IsPartiallyRedundant) { 1433 // We touch up the compare instruction in MBB2 and move it to 1434 // a previous BB to handle partially redundant case. 1435 if (SwapOperands) { 1436 Register Op1 = CMPI2->getOperand(1).getReg(); 1437 Register Op2 = CMPI2->getOperand(2).getReg(); 1438 CMPI2->getOperand(1).setReg(Op2); 1439 CMPI2->getOperand(2).setReg(Op1); 1440 } 1441 if (NewImm2 != Imm2) 1442 CMPI2->getOperand(2).setImm(NewImm2); 1443 1444 for (int I = 1; I <= 2; I++) { 1445 if (CMPI2->getOperand(I).isReg()) { 1446 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg()); 1447 if (Inst->getParent() != &MBB2) 1448 continue; 1449 1450 assert(Inst->getOpcode() == PPC::PHI && 1451 "We cannot support if an operand comes from this BB."); 1452 unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp); 1453 CMPI2->getOperand(I).setReg(SrcReg); 1454 } 1455 } 1456 auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator()); 1457 MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2)); 1458 1459 DebugLoc DL = CMPI2->getDebugLoc(); 1460 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); 1461 BuildMI(MBB2, MBB2.begin(), DL, 1462 TII->get(PPC::PHI), NewVReg) 1463 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1) 1464 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp); 1465 BI2->getOperand(1).setReg(NewVReg); 1466 } 1467 else { 1468 // We finally eliminate compare instruction in MBB2. 1469 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); 1470 CMPI2->eraseFromParent(); 1471 } 1472 BI2->getOperand(1).setIsKill(true); 1473 BI1->getOperand(1).setIsKill(false); 1474 1475 LLVM_DEBUG(dbgs() << "into a compare and two branches:\n"); 1476 LLVM_DEBUG(CMPI1->dump()); 1477 LLVM_DEBUG(BI1->dump()); 1478 LLVM_DEBUG(BI2->dump()); 1479 if (IsPartiallyRedundant) { 1480 LLVM_DEBUG(dbgs() << "The following compare is moved into " 1481 << printMBBReference(*MBBtoMoveCmp) 1482 << " to handle partial redundancy.\n"); 1483 LLVM_DEBUG(CMPI2->dump()); 1484 } 1485 1486 Simplified = true; 1487 } 1488 1489 return Simplified; 1490 } 1491 1492 // We miss the opportunity to emit an RLDIC when lowering jump tables 1493 // since ISEL sees only a single basic block. When selecting, the clear 1494 // and shift left will be in different blocks. 1495 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) { 1496 if (MI.getOpcode() != PPC::RLDICR) 1497 return false; 1498 1499 Register SrcReg = MI.getOperand(1).getReg(); 1500 if (!Register::isVirtualRegister(SrcReg)) 1501 return false; 1502 1503 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1504 if (SrcMI->getOpcode() != PPC::RLDICL) 1505 return false; 1506 1507 MachineOperand MOpSHSrc = SrcMI->getOperand(2); 1508 MachineOperand MOpMBSrc = SrcMI->getOperand(3); 1509 MachineOperand MOpSHMI = MI.getOperand(2); 1510 MachineOperand MOpMEMI = MI.getOperand(3); 1511 if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() && 1512 MOpMEMI.isImm())) 1513 return false; 1514 1515 uint64_t SHSrc = MOpSHSrc.getImm(); 1516 uint64_t MBSrc = MOpMBSrc.getImm(); 1517 uint64_t SHMI = MOpSHMI.getImm(); 1518 uint64_t MEMI = MOpMEMI.getImm(); 1519 uint64_t NewSH = SHSrc + SHMI; 1520 uint64_t NewMB = MBSrc - SHMI; 1521 if (NewMB > 63 || NewSH > 63) 1522 return false; 1523 1524 // The bits cleared with RLDICL are [0, MBSrc). 1525 // The bits cleared with RLDICR are (MEMI, 63]. 1526 // After the sequence, the bits cleared are: 1527 // [0, MBSrc-SHMI) and (MEMI, 63). 1528 // 1529 // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63]. 1530 if ((63 - NewSH) != MEMI) 1531 return false; 1532 1533 LLVM_DEBUG(dbgs() << "Converting pair: "); 1534 LLVM_DEBUG(SrcMI->dump()); 1535 LLVM_DEBUG(MI.dump()); 1536 1537 MI.setDesc(TII->get(PPC::RLDIC)); 1538 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); 1539 MI.getOperand(2).setImm(NewSH); 1540 MI.getOperand(3).setImm(NewMB); 1541 1542 LLVM_DEBUG(dbgs() << "To: "); 1543 LLVM_DEBUG(MI.dump()); 1544 NumRotatesCollapsed++; 1545 return true; 1546 } 1547 1548 // For case in LLVM IR 1549 // entry: 1550 // %iconv = sext i32 %index to i64 1551 // br i1 undef label %true, label %false 1552 // true: 1553 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv 1554 // ... 1555 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in 1556 // different BBs when conducting instruction selection. We can do a peephole 1557 // optimization to combine these two instructions into extswsli after 1558 // instruction selection. 1559 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI, 1560 MachineInstr *&ToErase) { 1561 if (MI.getOpcode() != PPC::RLDICR) 1562 return false; 1563 1564 if (!MF->getSubtarget<PPCSubtarget>().isISA3_0()) 1565 return false; 1566 1567 assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands"); 1568 1569 MachineOperand MOpSHMI = MI.getOperand(2); 1570 MachineOperand MOpMEMI = MI.getOperand(3); 1571 if (!(MOpSHMI.isImm() && MOpMEMI.isImm())) 1572 return false; 1573 1574 uint64_t SHMI = MOpSHMI.getImm(); 1575 uint64_t MEMI = MOpMEMI.getImm(); 1576 if (SHMI + MEMI != 63) 1577 return false; 1578 1579 Register SrcReg = MI.getOperand(1).getReg(); 1580 if (!Register::isVirtualRegister(SrcReg)) 1581 return false; 1582 1583 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 1584 if (SrcMI->getOpcode() != PPC::EXTSW && 1585 SrcMI->getOpcode() != PPC::EXTSW_32_64) 1586 return false; 1587 1588 // If the register defined by extsw has more than one use, combination is not 1589 // needed. 1590 if (!MRI->hasOneNonDBGUse(SrcReg)) 1591 return false; 1592 1593 assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands"); 1594 assert(SrcMI->getOperand(1).isReg() && 1595 "EXTSW's second operand should be a register"); 1596 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) 1597 return false; 1598 1599 LLVM_DEBUG(dbgs() << "Combining pair: "); 1600 LLVM_DEBUG(SrcMI->dump()); 1601 LLVM_DEBUG(MI.dump()); 1602 1603 MachineInstr *NewInstr = 1604 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), 1605 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) 1606 : TII->get(PPC::EXTSWSLI_32_64), 1607 MI.getOperand(0).getReg()) 1608 .add(SrcMI->getOperand(1)) 1609 .add(MOpSHMI); 1610 (void)NewInstr; 1611 1612 LLVM_DEBUG(dbgs() << "TO: "); 1613 LLVM_DEBUG(NewInstr->dump()); 1614 ++NumEXTSWAndSLDICombined; 1615 ToErase = &MI; 1616 // SrcMI, which is extsw, is of no use now, erase it. 1617 SrcMI->eraseFromParent(); 1618 return true; 1619 } 1620 1621 } // end default namespace 1622 1623 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, 1624 "PowerPC MI Peephole Optimization", false, false) 1625 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) 1626 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 1627 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) 1628 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE, 1629 "PowerPC MI Peephole Optimization", false, false) 1630 1631 char PPCMIPeephole::ID = 0; 1632 FunctionPass* 1633 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); } 1634 1635