1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34              cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44                         cl::init(false),
45                         cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51   const char *RegName = getRegisterName(RegNo);
52   if (RegName[0] == 'q' /* QPX */) {
53     // The system toolchain on the BG/Q does not understand QPX register names
54     // in .cfi_* directives, so print the name of the floating-point
55     // subregister instead.
56     std::string RN(RegName);
57 
58     RN[0] = 'f';
59     OS << RN;
60 
61     return;
62   }
63 
64   OS << RegName;
65 }
66 
67 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
68                                StringRef Annot, const MCSubtargetInfo &STI,
69                                raw_ostream &O) {
70   // Customize printing of the addis instruction on AIX. When an operand is a
71   // symbol reference, the instruction syntax is changed to look like a load
72   // operation, i.e:
73   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
74   if (TT.isOSAIX() &&
75       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
76       MI->getOperand(2).isExpr()) {
77     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
78            "The first and the second operand of an addis instruction"
79            " should be registers.");
80 
81     assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
82            "The third operand of an addis instruction should be a symbol "
83            "reference expression if it is an expression at all.");
84 
85     O << "\taddis ";
86     printOperand(MI, 0, O);
87     O << ", ";
88     printOperand(MI, 2, O);
89     O << "(";
90     printOperand(MI, 1, O);
91     O << ")";
92     return;
93   }
94 
95   // Check for slwi/srwi mnemonics.
96   if (MI->getOpcode() == PPC::RLWINM) {
97     unsigned char SH = MI->getOperand(2).getImm();
98     unsigned char MB = MI->getOperand(3).getImm();
99     unsigned char ME = MI->getOperand(4).getImm();
100     bool useSubstituteMnemonic = false;
101     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
102       O << "\tslwi "; useSubstituteMnemonic = true;
103     }
104     if (SH <= 31 && MB == (32-SH) && ME == 31) {
105       O << "\tsrwi "; useSubstituteMnemonic = true;
106       SH = 32-SH;
107     }
108     if (useSubstituteMnemonic) {
109       printOperand(MI, 0, O);
110       O << ", ";
111       printOperand(MI, 1, O);
112       O << ", " << (unsigned int)SH;
113 
114       printAnnotation(O, Annot);
115       return;
116     }
117   }
118 
119   if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
120       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
121     O << "\tmr ";
122     printOperand(MI, 0, O);
123     O << ", ";
124     printOperand(MI, 1, O);
125     printAnnotation(O, Annot);
126     return;
127   }
128 
129   if (MI->getOpcode() == PPC::RLDICR ||
130       MI->getOpcode() == PPC::RLDICR_32) {
131     unsigned char SH = MI->getOperand(2).getImm();
132     unsigned char ME = MI->getOperand(3).getImm();
133     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
134     if (63-SH == ME) {
135       O << "\tsldi ";
136       printOperand(MI, 0, O);
137       O << ", ";
138       printOperand(MI, 1, O);
139       O << ", " << (unsigned int)SH;
140       printAnnotation(O, Annot);
141       return;
142     }
143   }
144 
145   // dcbt[st] is printed manually here because:
146   //  1. The assembly syntax is different between embedded and server targets
147   //  2. We must print the short mnemonics for TH == 0 because the
148   //     embedded/server syntax default will not be stable across assemblers
149   //  The syntax for dcbt is:
150   //    dcbt ra, rb, th [server]
151   //    dcbt th, ra, rb [embedded]
152   //  where th can be omitted when it is 0. dcbtst is the same.
153   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
154     unsigned char TH = MI->getOperand(0).getImm();
155     O << "\tdcbt";
156     if (MI->getOpcode() == PPC::DCBTST)
157       O << "st";
158     if (TH == 16)
159       O << "t";
160     O << " ";
161 
162     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
163     if (IsBookE && TH != 0 && TH != 16)
164       O << (unsigned int) TH << ", ";
165 
166     printOperand(MI, 1, O);
167     O << ", ";
168     printOperand(MI, 2, O);
169 
170     if (!IsBookE && TH != 0 && TH != 16)
171       O << ", " << (unsigned int) TH;
172 
173     printAnnotation(O, Annot);
174     return;
175   }
176 
177   if (MI->getOpcode() == PPC::DCBF) {
178     unsigned char L = MI->getOperand(0).getImm();
179     if (!L || L == 1 || L == 3) {
180       O << "\tdcbf";
181       if (L == 1 || L == 3)
182         O << "l";
183       if (L == 3)
184         O << "p";
185       O << " ";
186 
187       printOperand(MI, 1, O);
188       O << ", ";
189       printOperand(MI, 2, O);
190 
191       printAnnotation(O, Annot);
192       return;
193     }
194   }
195 
196   if (!printAliasInstr(MI, O))
197     printInstruction(MI, Address, O);
198   printAnnotation(O, Annot);
199 }
200 
201 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
202                                            raw_ostream &O,
203                                            const char *Modifier) {
204   unsigned Code = MI->getOperand(OpNo).getImm();
205 
206   if (StringRef(Modifier) == "cc") {
207     switch ((PPC::Predicate)Code) {
208     case PPC::PRED_LT_MINUS:
209     case PPC::PRED_LT_PLUS:
210     case PPC::PRED_LT:
211       O << "lt";
212       return;
213     case PPC::PRED_LE_MINUS:
214     case PPC::PRED_LE_PLUS:
215     case PPC::PRED_LE:
216       O << "le";
217       return;
218     case PPC::PRED_EQ_MINUS:
219     case PPC::PRED_EQ_PLUS:
220     case PPC::PRED_EQ:
221       O << "eq";
222       return;
223     case PPC::PRED_GE_MINUS:
224     case PPC::PRED_GE_PLUS:
225     case PPC::PRED_GE:
226       O << "ge";
227       return;
228     case PPC::PRED_GT_MINUS:
229     case PPC::PRED_GT_PLUS:
230     case PPC::PRED_GT:
231       O << "gt";
232       return;
233     case PPC::PRED_NE_MINUS:
234     case PPC::PRED_NE_PLUS:
235     case PPC::PRED_NE:
236       O << "ne";
237       return;
238     case PPC::PRED_UN_MINUS:
239     case PPC::PRED_UN_PLUS:
240     case PPC::PRED_UN:
241       O << "un";
242       return;
243     case PPC::PRED_NU_MINUS:
244     case PPC::PRED_NU_PLUS:
245     case PPC::PRED_NU:
246       O << "nu";
247       return;
248     case PPC::PRED_BIT_SET:
249     case PPC::PRED_BIT_UNSET:
250       llvm_unreachable("Invalid use of bit predicate code");
251     }
252     llvm_unreachable("Invalid predicate code");
253   }
254 
255   if (StringRef(Modifier) == "pm") {
256     switch ((PPC::Predicate)Code) {
257     case PPC::PRED_LT:
258     case PPC::PRED_LE:
259     case PPC::PRED_EQ:
260     case PPC::PRED_GE:
261     case PPC::PRED_GT:
262     case PPC::PRED_NE:
263     case PPC::PRED_UN:
264     case PPC::PRED_NU:
265       return;
266     case PPC::PRED_LT_MINUS:
267     case PPC::PRED_LE_MINUS:
268     case PPC::PRED_EQ_MINUS:
269     case PPC::PRED_GE_MINUS:
270     case PPC::PRED_GT_MINUS:
271     case PPC::PRED_NE_MINUS:
272     case PPC::PRED_UN_MINUS:
273     case PPC::PRED_NU_MINUS:
274       O << "-";
275       return;
276     case PPC::PRED_LT_PLUS:
277     case PPC::PRED_LE_PLUS:
278     case PPC::PRED_EQ_PLUS:
279     case PPC::PRED_GE_PLUS:
280     case PPC::PRED_GT_PLUS:
281     case PPC::PRED_NE_PLUS:
282     case PPC::PRED_UN_PLUS:
283     case PPC::PRED_NU_PLUS:
284       O << "+";
285       return;
286     case PPC::PRED_BIT_SET:
287     case PPC::PRED_BIT_UNSET:
288       llvm_unreachable("Invalid use of bit predicate code");
289     }
290     llvm_unreachable("Invalid predicate code");
291   }
292 
293   assert(StringRef(Modifier) == "reg" &&
294          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
295   printOperand(MI, OpNo+1, O);
296 }
297 
298 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
299                                        raw_ostream &O) {
300   unsigned Code = MI->getOperand(OpNo).getImm();
301   if (Code == 2)
302     O << "-";
303   else if (Code == 3)
304     O << "+";
305 }
306 
307 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
308                                        raw_ostream &O) {
309   unsigned int Value = MI->getOperand(OpNo).getImm();
310   assert(Value <= 1 && "Invalid u1imm argument!");
311   O << (unsigned int)Value;
312 }
313 
314 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
315                                        raw_ostream &O) {
316   unsigned int Value = MI->getOperand(OpNo).getImm();
317   assert(Value <= 3 && "Invalid u2imm argument!");
318   O << (unsigned int)Value;
319 }
320 
321 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
322                                        raw_ostream &O) {
323   unsigned int Value = MI->getOperand(OpNo).getImm();
324   assert(Value <= 8 && "Invalid u3imm argument!");
325   O << (unsigned int)Value;
326 }
327 
328 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
329                                        raw_ostream &O) {
330   unsigned int Value = MI->getOperand(OpNo).getImm();
331   assert(Value <= 15 && "Invalid u4imm argument!");
332   O << (unsigned int)Value;
333 }
334 
335 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
336                                        raw_ostream &O) {
337   int Value = MI->getOperand(OpNo).getImm();
338   Value = SignExtend32<5>(Value);
339   O << (int)Value;
340 }
341 
342 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
343                                          raw_ostream &O) {
344   unsigned int Value = MI->getOperand(OpNo).getImm();
345   assert(Value == 0 && "Operand must be zero");
346   O << (unsigned int)Value;
347 }
348 
349 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
350                                        raw_ostream &O) {
351   unsigned int Value = MI->getOperand(OpNo).getImm();
352   assert(Value <= 31 && "Invalid u5imm argument!");
353   O << (unsigned int)Value;
354 }
355 
356 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
357                                        raw_ostream &O) {
358   unsigned int Value = MI->getOperand(OpNo).getImm();
359   assert(Value <= 63 && "Invalid u6imm argument!");
360   O << (unsigned int)Value;
361 }
362 
363 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
364                                        raw_ostream &O) {
365   unsigned int Value = MI->getOperand(OpNo).getImm();
366   assert(Value <= 127 && "Invalid u7imm argument!");
367   O << (unsigned int)Value;
368 }
369 
370 // Operands of BUILD_VECTOR are signed and we use this to print operands
371 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
372 // print as unsigned.
373 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
374                                        raw_ostream &O) {
375   unsigned char Value = MI->getOperand(OpNo).getImm();
376   O << (unsigned int)Value;
377 }
378 
379 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
380                                         raw_ostream &O) {
381   unsigned short Value = MI->getOperand(OpNo).getImm();
382   assert(Value <= 1023 && "Invalid u10imm argument!");
383   O << (unsigned short)Value;
384 }
385 
386 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
387                                         raw_ostream &O) {
388   unsigned short Value = MI->getOperand(OpNo).getImm();
389   assert(Value <= 4095 && "Invalid u12imm argument!");
390   O << (unsigned short)Value;
391 }
392 
393 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
394                                         raw_ostream &O) {
395   if (MI->getOperand(OpNo).isImm())
396     O << (short)MI->getOperand(OpNo).getImm();
397   else
398     printOperand(MI, OpNo, O);
399 }
400 
401 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
402                                         raw_ostream &O) {
403   long long Value = MI->getOperand(OpNo).getImm();
404   assert(isInt<34>(Value) && "Invalid s34imm argument!");
405   O << (long long)Value;
406 }
407 
408 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
409                                         raw_ostream &O) {
410   if (MI->getOperand(OpNo).isImm())
411     O << (unsigned short)MI->getOperand(OpNo).getImm();
412   else
413     printOperand(MI, OpNo, O);
414 }
415 
416 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
417                                         raw_ostream &O) {
418   if (!MI->getOperand(OpNo).isImm())
419     return printOperand(MI, OpNo, O);
420 
421   // Branches can take an immediate operand.  This is used by the branch
422   // selection pass to print .+8, an eight byte displacement from the PC.
423   O << ".";
424   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
425   if (Imm >= 0)
426     O << "+";
427   O << Imm;
428 }
429 
430 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
431                                            raw_ostream &O) {
432   if (!MI->getOperand(OpNo).isImm())
433     return printOperand(MI, OpNo, O);
434 
435   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
436 }
437 
438 
439 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
440                                  raw_ostream &O) {
441   unsigned CCReg = MI->getOperand(OpNo).getReg();
442   unsigned RegNo;
443   switch (CCReg) {
444   default: llvm_unreachable("Unknown CR register");
445   case PPC::CR0: RegNo = 0; break;
446   case PPC::CR1: RegNo = 1; break;
447   case PPC::CR2: RegNo = 2; break;
448   case PPC::CR3: RegNo = 3; break;
449   case PPC::CR4: RegNo = 4; break;
450   case PPC::CR5: RegNo = 5; break;
451   case PPC::CR6: RegNo = 6; break;
452   case PPC::CR7: RegNo = 7; break;
453   }
454   O << (0x80 >> RegNo);
455 }
456 
457 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
458                                     raw_ostream &O) {
459   printS16ImmOperand(MI, OpNo, O);
460   O << '(';
461   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
462     O << "0";
463   else
464     printOperand(MI, OpNo+1, O);
465   O << ')';
466 }
467 
468 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
469                                     raw_ostream &O) {
470   // When used as the base register, r0 reads constant zero rather than
471   // the value contained in the register.  For this reason, the darwin
472   // assembler requires that we print r0 as 0 (no r) when used as the base.
473   if (MI->getOperand(OpNo).getReg() == PPC::R0)
474     O << "0";
475   else
476     printOperand(MI, OpNo, O);
477   O << ", ";
478   printOperand(MI, OpNo+1, O);
479 }
480 
481 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
482                                   raw_ostream &O) {
483   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
484   // come at the _end_ of the expression.
485   const MCOperand &Op = MI->getOperand(OpNo);
486   const MCSymbolRefExpr *RefExp = nullptr;
487   const MCConstantExpr *ConstExp = nullptr;
488   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
489     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
490     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
491   } else
492     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
493 
494   O << RefExp->getSymbol().getName();
495   O << '(';
496   printOperand(MI, OpNo+1, O);
497   O << ')';
498   if (RefExp->getKind() != MCSymbolRefExpr::VK_None)
499     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
500   if (ConstExp != nullptr)
501     O << '+' << ConstExp->getValue();
502 }
503 
504 /// showRegistersWithPercentPrefix - Check if this register name should be
505 /// printed with a percentage symbol as prefix.
506 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
507   if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
508     return false;
509 
510   switch (RegName[0]) {
511   default:
512     return false;
513   case 'r':
514   case 'f':
515   case 'q':
516   case 'v':
517   case 'c':
518     return true;
519   }
520 }
521 
522 /// getVerboseConditionalRegName - This method expands the condition register
523 /// when requested explicitly or targetting Darwin.
524 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
525                                                        unsigned RegEncoding)
526                                                        const {
527   if (!TT.isOSDarwin() && !FullRegNames)
528     return nullptr;
529   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
530     return nullptr;
531   const char *CRBits[] = {
532     "lt", "gt", "eq", "un",
533     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
534     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
535     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
536     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
537     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
538     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
539     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
540   };
541   return CRBits[RegEncoding];
542 }
543 
544 // showRegistersWithPrefix - This method determines whether registers
545 // should be number-only or include the prefix.
546 bool PPCInstPrinter::showRegistersWithPrefix() const {
547   if (TT.getOS() == Triple::AIX)
548     return false;
549   return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
550 }
551 
552 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
553                                   raw_ostream &O) {
554   const MCOperand &Op = MI->getOperand(OpNo);
555   if (Op.isReg()) {
556     unsigned Reg = Op.getReg();
557     if (!ShowVSRNumsAsVR)
558       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
559                                               Reg, OpNo);
560 
561     const char *RegName;
562     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
563     if (RegName == nullptr)
564      RegName = getRegisterName(Reg);
565     if (showRegistersWithPercentPrefix(RegName))
566       O << "%";
567     if (!showRegistersWithPrefix())
568       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
569 
570     O << RegName;
571     return;
572   }
573 
574   if (Op.isImm()) {
575     O << Op.getImm();
576     return;
577   }
578 
579   assert(Op.isExpr() && "unknown operand kind in printOperand");
580   Op.getExpr()->print(O, &MAI);
581 }
582 
583