1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "asm-printer"
29 
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34              cl::desc("Use full register names when printing assembly"));
35 
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39              cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40 
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44                         cl::init(false),
45                         cl::desc("Prints full register names with percent"));
46 
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49 
50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51   const char *RegName = getRegisterName(RegNo);
52   OS << RegName;
53 }
54 
55 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
56                                StringRef Annot, const MCSubtargetInfo &STI,
57                                raw_ostream &O) {
58   // Customize printing of the addis instruction on AIX. When an operand is a
59   // symbol reference, the instruction syntax is changed to look like a load
60   // operation, i.e:
61   //     Transform:  addis $rD, $rA, $src --> addis $rD, $src($rA).
62   if (TT.isOSAIX() &&
63       (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
64       MI->getOperand(2).isExpr()) {
65     assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
66            "The first and the second operand of an addis instruction"
67            " should be registers.");
68 
69     assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
70            "The third operand of an addis instruction should be a symbol "
71            "reference expression if it is an expression at all.");
72 
73     O << "\taddis ";
74     printOperand(MI, 0, O);
75     O << ", ";
76     printOperand(MI, 2, O);
77     O << "(";
78     printOperand(MI, 1, O);
79     O << ")";
80     return;
81   }
82 
83   // Check if the last operand is an expression with the variant kind
84   // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
85   // relocation and the .reloc directive needs to be added.
86   unsigned LastOp = MI->getNumOperands() - 1;
87   if (MI->getNumOperands() > 1) {
88     const MCOperand &Operand = MI->getOperand(LastOp);
89     if (Operand.isExpr()) {
90       const MCExpr *Expr = Operand.getExpr();
91       const MCSymbolRefExpr *SymExpr =
92           static_cast<const MCSymbolRefExpr *>(Expr);
93 
94       if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
95         const MCSymbol &Symbol = SymExpr->getSymbol();
96         if (MI->getOpcode() == PPC::PLDpc) {
97           printInstruction(MI, Address, O);
98           O << "\n";
99           Symbol.print(O, &MAI);
100           O << ":";
101           return;
102         } else {
103           O << "\t.reloc ";
104           Symbol.print(O, &MAI);
105           O << "-8,R_PPC64_PCREL_OPT,.-(";
106           Symbol.print(O, &MAI);
107           O << "-8)\n";
108         }
109       }
110     }
111   }
112 
113   // Check for slwi/srwi mnemonics.
114   if (MI->getOpcode() == PPC::RLWINM) {
115     unsigned char SH = MI->getOperand(2).getImm();
116     unsigned char MB = MI->getOperand(3).getImm();
117     unsigned char ME = MI->getOperand(4).getImm();
118     bool useSubstituteMnemonic = false;
119     if (SH <= 31 && MB == 0 && ME == (31-SH)) {
120       O << "\tslwi "; useSubstituteMnemonic = true;
121     }
122     if (SH <= 31 && MB == (32-SH) && ME == 31) {
123       O << "\tsrwi "; useSubstituteMnemonic = true;
124       SH = 32-SH;
125     }
126     if (useSubstituteMnemonic) {
127       printOperand(MI, 0, O);
128       O << ", ";
129       printOperand(MI, 1, O);
130       O << ", " << (unsigned int)SH;
131 
132       printAnnotation(O, Annot);
133       return;
134     }
135   }
136 
137   if (MI->getOpcode() == PPC::RLDICR ||
138       MI->getOpcode() == PPC::RLDICR_32) {
139     unsigned char SH = MI->getOperand(2).getImm();
140     unsigned char ME = MI->getOperand(3).getImm();
141     // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
142     if (63-SH == ME) {
143       O << "\tsldi ";
144       printOperand(MI, 0, O);
145       O << ", ";
146       printOperand(MI, 1, O);
147       O << ", " << (unsigned int)SH;
148       printAnnotation(O, Annot);
149       return;
150     }
151   }
152 
153   // dcbt[st] is printed manually here because:
154   //  1. The assembly syntax is different between embedded and server targets
155   //  2. We must print the short mnemonics for TH == 0 because the
156   //     embedded/server syntax default will not be stable across assemblers
157   //  The syntax for dcbt is:
158   //    dcbt ra, rb, th [server]
159   //    dcbt th, ra, rb [embedded]
160   //  where th can be omitted when it is 0. dcbtst is the same.
161   if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
162     unsigned char TH = MI->getOperand(0).getImm();
163     O << "\tdcbt";
164     if (MI->getOpcode() == PPC::DCBTST)
165       O << "st";
166     if (TH == 16)
167       O << "t";
168     O << " ";
169 
170     bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
171     if (IsBookE && TH != 0 && TH != 16)
172       O << (unsigned int) TH << ", ";
173 
174     printOperand(MI, 1, O);
175     O << ", ";
176     printOperand(MI, 2, O);
177 
178     if (!IsBookE && TH != 0 && TH != 16)
179       O << ", " << (unsigned int) TH;
180 
181     printAnnotation(O, Annot);
182     return;
183   }
184 
185   if (MI->getOpcode() == PPC::DCBF) {
186     unsigned char L = MI->getOperand(0).getImm();
187     if (!L || L == 1 || L == 3) {
188       O << "\tdcbf";
189       if (L == 1 || L == 3)
190         O << "l";
191       if (L == 3)
192         O << "p";
193       O << " ";
194 
195       printOperand(MI, 1, O);
196       O << ", ";
197       printOperand(MI, 2, O);
198 
199       printAnnotation(O, Annot);
200       return;
201     }
202   }
203 
204   if (!printAliasInstr(MI, Address, O))
205     printInstruction(MI, Address, O);
206   printAnnotation(O, Annot);
207 }
208 
209 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
210                                            raw_ostream &O,
211                                            const char *Modifier) {
212   unsigned Code = MI->getOperand(OpNo).getImm();
213 
214   if (StringRef(Modifier) == "cc") {
215     switch ((PPC::Predicate)Code) {
216     case PPC::PRED_LT_MINUS:
217     case PPC::PRED_LT_PLUS:
218     case PPC::PRED_LT:
219       O << "lt";
220       return;
221     case PPC::PRED_LE_MINUS:
222     case PPC::PRED_LE_PLUS:
223     case PPC::PRED_LE:
224       O << "le";
225       return;
226     case PPC::PRED_EQ_MINUS:
227     case PPC::PRED_EQ_PLUS:
228     case PPC::PRED_EQ:
229       O << "eq";
230       return;
231     case PPC::PRED_GE_MINUS:
232     case PPC::PRED_GE_PLUS:
233     case PPC::PRED_GE:
234       O << "ge";
235       return;
236     case PPC::PRED_GT_MINUS:
237     case PPC::PRED_GT_PLUS:
238     case PPC::PRED_GT:
239       O << "gt";
240       return;
241     case PPC::PRED_NE_MINUS:
242     case PPC::PRED_NE_PLUS:
243     case PPC::PRED_NE:
244       O << "ne";
245       return;
246     case PPC::PRED_UN_MINUS:
247     case PPC::PRED_UN_PLUS:
248     case PPC::PRED_UN:
249       O << "un";
250       return;
251     case PPC::PRED_NU_MINUS:
252     case PPC::PRED_NU_PLUS:
253     case PPC::PRED_NU:
254       O << "nu";
255       return;
256     case PPC::PRED_BIT_SET:
257     case PPC::PRED_BIT_UNSET:
258       llvm_unreachable("Invalid use of bit predicate code");
259     }
260     llvm_unreachable("Invalid predicate code");
261   }
262 
263   if (StringRef(Modifier) == "pm") {
264     switch ((PPC::Predicate)Code) {
265     case PPC::PRED_LT:
266     case PPC::PRED_LE:
267     case PPC::PRED_EQ:
268     case PPC::PRED_GE:
269     case PPC::PRED_GT:
270     case PPC::PRED_NE:
271     case PPC::PRED_UN:
272     case PPC::PRED_NU:
273       return;
274     case PPC::PRED_LT_MINUS:
275     case PPC::PRED_LE_MINUS:
276     case PPC::PRED_EQ_MINUS:
277     case PPC::PRED_GE_MINUS:
278     case PPC::PRED_GT_MINUS:
279     case PPC::PRED_NE_MINUS:
280     case PPC::PRED_UN_MINUS:
281     case PPC::PRED_NU_MINUS:
282       O << "-";
283       return;
284     case PPC::PRED_LT_PLUS:
285     case PPC::PRED_LE_PLUS:
286     case PPC::PRED_EQ_PLUS:
287     case PPC::PRED_GE_PLUS:
288     case PPC::PRED_GT_PLUS:
289     case PPC::PRED_NE_PLUS:
290     case PPC::PRED_UN_PLUS:
291     case PPC::PRED_NU_PLUS:
292       O << "+";
293       return;
294     case PPC::PRED_BIT_SET:
295     case PPC::PRED_BIT_UNSET:
296       llvm_unreachable("Invalid use of bit predicate code");
297     }
298     llvm_unreachable("Invalid predicate code");
299   }
300 
301   assert(StringRef(Modifier) == "reg" &&
302          "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
303   printOperand(MI, OpNo+1, O);
304 }
305 
306 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
307                                        raw_ostream &O) {
308   unsigned Code = MI->getOperand(OpNo).getImm();
309   if (Code == 2)
310     O << "-";
311   else if (Code == 3)
312     O << "+";
313 }
314 
315 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
316                                        raw_ostream &O) {
317   unsigned int Value = MI->getOperand(OpNo).getImm();
318   assert(Value <= 1 && "Invalid u1imm argument!");
319   O << (unsigned int)Value;
320 }
321 
322 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
323                                        raw_ostream &O) {
324   unsigned int Value = MI->getOperand(OpNo).getImm();
325   assert(Value <= 3 && "Invalid u2imm argument!");
326   O << (unsigned int)Value;
327 }
328 
329 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
330                                        raw_ostream &O) {
331   unsigned int Value = MI->getOperand(OpNo).getImm();
332   assert(Value <= 8 && "Invalid u3imm argument!");
333   O << (unsigned int)Value;
334 }
335 
336 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
337                                        raw_ostream &O) {
338   unsigned int Value = MI->getOperand(OpNo).getImm();
339   assert(Value <= 15 && "Invalid u4imm argument!");
340   O << (unsigned int)Value;
341 }
342 
343 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
344                                        raw_ostream &O) {
345   int Value = MI->getOperand(OpNo).getImm();
346   Value = SignExtend32<5>(Value);
347   O << (int)Value;
348 }
349 
350 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
351                                          raw_ostream &O) {
352   unsigned int Value = MI->getOperand(OpNo).getImm();
353   assert(Value == 0 && "Operand must be zero");
354   O << (unsigned int)Value;
355 }
356 
357 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
358                                        raw_ostream &O) {
359   unsigned int Value = MI->getOperand(OpNo).getImm();
360   assert(Value <= 31 && "Invalid u5imm argument!");
361   O << (unsigned int)Value;
362 }
363 
364 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
365                                        raw_ostream &O) {
366   unsigned int Value = MI->getOperand(OpNo).getImm();
367   assert(Value <= 63 && "Invalid u6imm argument!");
368   O << (unsigned int)Value;
369 }
370 
371 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
372                                        raw_ostream &O) {
373   unsigned int Value = MI->getOperand(OpNo).getImm();
374   assert(Value <= 127 && "Invalid u7imm argument!");
375   O << (unsigned int)Value;
376 }
377 
378 // Operands of BUILD_VECTOR are signed and we use this to print operands
379 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
380 // print as unsigned.
381 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
382                                        raw_ostream &O) {
383   unsigned char Value = MI->getOperand(OpNo).getImm();
384   O << (unsigned int)Value;
385 }
386 
387 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
388                                         raw_ostream &O) {
389   unsigned short Value = MI->getOperand(OpNo).getImm();
390   assert(Value <= 1023 && "Invalid u10imm argument!");
391   O << (unsigned short)Value;
392 }
393 
394 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
395                                         raw_ostream &O) {
396   unsigned short Value = MI->getOperand(OpNo).getImm();
397   assert(Value <= 4095 && "Invalid u12imm argument!");
398   O << (unsigned short)Value;
399 }
400 
401 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
402                                         raw_ostream &O) {
403   if (MI->getOperand(OpNo).isImm())
404     O << (short)MI->getOperand(OpNo).getImm();
405   else
406     printOperand(MI, OpNo, O);
407 }
408 
409 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
410                                         raw_ostream &O) {
411   if (MI->getOperand(OpNo).isImm()) {
412     long long Value = MI->getOperand(OpNo).getImm();
413     assert(isInt<34>(Value) && "Invalid s34imm argument!");
414     O << (long long)Value;
415   }
416   else
417     printOperand(MI, OpNo, O);
418 }
419 
420 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
421                                         raw_ostream &O) {
422   if (MI->getOperand(OpNo).isImm())
423     O << (unsigned short)MI->getOperand(OpNo).getImm();
424   else
425     printOperand(MI, OpNo, O);
426 }
427 
428 void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
429                                         unsigned OpNo, raw_ostream &O) {
430   if (!MI->getOperand(OpNo).isImm())
431     return printOperand(MI, OpNo, O);
432   int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
433   if (PrintBranchImmAsAddress) {
434     uint64_t Target = Address + Imm;
435     if (!TT.isPPC64())
436       Target &= 0xffffffff;
437     O << formatHex(Target);
438   } else {
439     // Branches can take an immediate operand. This is used by the branch
440     // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
441     // to express an eight byte displacement from the program counter.
442     if (!TT.isOSAIX())
443       O << ".";
444     else
445       O << "$";
446 
447     if (Imm >= 0)
448       O << "+";
449     O << Imm;
450   }
451 }
452 
453 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
454                                            raw_ostream &O) {
455   if (!MI->getOperand(OpNo).isImm())
456     return printOperand(MI, OpNo, O);
457 
458   O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
459 }
460 
461 
462 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
463                                  raw_ostream &O) {
464   unsigned CCReg = MI->getOperand(OpNo).getReg();
465   unsigned RegNo;
466   switch (CCReg) {
467   default: llvm_unreachable("Unknown CR register");
468   case PPC::CR0: RegNo = 0; break;
469   case PPC::CR1: RegNo = 1; break;
470   case PPC::CR2: RegNo = 2; break;
471   case PPC::CR3: RegNo = 3; break;
472   case PPC::CR4: RegNo = 4; break;
473   case PPC::CR5: RegNo = 5; break;
474   case PPC::CR6: RegNo = 6; break;
475   case PPC::CR7: RegNo = 7; break;
476   }
477   O << (0x80 >> RegNo);
478 }
479 
480 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
481                                     raw_ostream &O) {
482   printS16ImmOperand(MI, OpNo, O);
483   O << '(';
484   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
485     O << "0";
486   else
487     printOperand(MI, OpNo+1, O);
488   O << ')';
489 }
490 
491 void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
492                                            raw_ostream &O) {
493   printS34ImmOperand(MI, OpNo, O);
494   O << '(';
495   printImmZeroOperand(MI, OpNo + 1, O);
496   O << ')';
497 }
498 
499 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
500                                         raw_ostream &O) {
501   printS34ImmOperand(MI, OpNo, O);
502   O << '(';
503   printOperand(MI, OpNo + 1, O);
504   O << ')';
505 }
506 
507 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
508                                     raw_ostream &O) {
509   // When used as the base register, r0 reads constant zero rather than
510   // the value contained in the register.  For this reason, the darwin
511   // assembler requires that we print r0 as 0 (no r) when used as the base.
512   if (MI->getOperand(OpNo).getReg() == PPC::R0)
513     O << "0";
514   else
515     printOperand(MI, OpNo, O);
516   O << ", ";
517   printOperand(MI, OpNo+1, O);
518 }
519 
520 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
521                                   raw_ostream &O) {
522   // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
523   // come at the _end_ of the expression.
524   const MCOperand &Op = MI->getOperand(OpNo);
525   const MCSymbolRefExpr *RefExp = nullptr;
526   const MCConstantExpr *ConstExp = nullptr;
527   if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
528     RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
529     ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
530   } else
531     RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
532 
533   O << RefExp->getSymbol().getName();
534   // The variant kind VK_PPC_NOTOC needs to be handled as a special case
535   // because we do not want the assembly to print out the @notoc at the
536   // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
537   // like __tls_get_addr@notoc(x@tlsgd).
538   if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
539     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
540   O << '(';
541   printOperand(MI, OpNo+1, O);
542   O << ')';
543   if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
544       RefExp->getKind() != MCSymbolRefExpr::VK_PPC_NOTOC)
545     O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
546   if (ConstExp != nullptr)
547     O << '+' << ConstExp->getValue();
548 }
549 
550 /// showRegistersWithPercentPrefix - Check if this register name should be
551 /// printed with a percentage symbol as prefix.
552 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
553   if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
554     return false;
555 
556   switch (RegName[0]) {
557   default:
558     return false;
559   case 'r':
560   case 'f':
561   case 'q':
562   case 'v':
563   case 'c':
564     return true;
565   }
566 }
567 
568 /// getVerboseConditionalRegName - This method expands the condition register
569 /// when requested explicitly or targetting Darwin.
570 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
571                                                        unsigned RegEncoding)
572                                                        const {
573   if (!TT.isOSDarwin() && !FullRegNames)
574     return nullptr;
575   if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
576     return nullptr;
577   const char *CRBits[] = {
578     "lt", "gt", "eq", "un",
579     "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
580     "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
581     "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
582     "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
583     "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
584     "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
585     "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
586   };
587   return CRBits[RegEncoding];
588 }
589 
590 // showRegistersWithPrefix - This method determines whether registers
591 // should be number-only or include the prefix.
592 bool PPCInstPrinter::showRegistersWithPrefix() const {
593   if (TT.getOS() == Triple::AIX)
594     return false;
595   return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
596 }
597 
598 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
599                                   raw_ostream &O) {
600   const MCOperand &Op = MI->getOperand(OpNo);
601   if (Op.isReg()) {
602     unsigned Reg = Op.getReg();
603     if (!ShowVSRNumsAsVR)
604       Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
605                                               Reg, OpNo);
606 
607     const char *RegName;
608     RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
609     if (RegName == nullptr)
610      RegName = getRegisterName(Reg);
611     if (showRegistersWithPercentPrefix(RegName))
612       O << "%";
613     if (!showRegistersWithPrefix())
614       RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
615 
616     O << RegName;
617     return;
618   }
619 
620   if (Op.isImm()) {
621     O << Op.getImm();
622     return;
623   }
624 
625   assert(Op.isExpr() && "unknown operand kind in printOperand");
626   Op.getExpr()->print(O, &MAI);
627 }
628 
629