1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsABIInfo.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCExpr.h"
19 #include "MipsMCTargetDesc.h"
20 #include "MipsTargetObjectFile.h"
21 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 static cl::opt<bool> RoundSectionSizes(
34     "mips-round-section-sizes", cl::init(false),
35     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
36 } // end anonymous namespace
37 
38 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
39     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
40   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
41 }
42 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
43 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
44 void MipsTargetStreamer::setUsesMicroMips() {}
45 void MipsTargetStreamer::emitDirectiveSetMips16() {}
46 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
47 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
48 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
49 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetMt() {}
54 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
55 void MipsTargetStreamer::emitDirectiveSetCRC() {}
56 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
57 void MipsTargetStreamer::emitDirectiveSetVirt() {}
58 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
59 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
60 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
61   forbidModuleDirective();
62 }
63 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
64 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
65 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
66 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
67 void MipsTargetStreamer::emitDirectiveNaN2008() {}
68 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
69 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
70 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
71 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
72 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
73                                    unsigned ReturnReg) {}
74 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
75 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
76 }
77 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
78   forbidModuleDirective();
79 }
80 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
95 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
96 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
97 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
98 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
99   forbidModuleDirective();
100 }
101 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
102   forbidModuleDirective();
103 }
104 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
105 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
106 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
107 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
108 bool MipsTargetStreamer::emitDirectiveCpRestore(
109     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
110     const MCSubtargetInfo *STI) {
111   forbidModuleDirective();
112   return true;
113 }
114 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
115                                               const MCSymbol &Sym, bool IsReg) {
116 }
117 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
118                                                bool SaveLocationIsRegister) {}
119 
120 void MipsTargetStreamer::emitDirectiveModuleFP() {}
121 
122 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
123   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
124     report_fatal_error("+nooddspreg is only valid for O32");
125 }
126 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
127 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
128 void MipsTargetStreamer::emitDirectiveModuleMT() {}
129 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
130 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
131 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
132 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
133 void MipsTargetStreamer::emitDirectiveSetFp(
134     MipsABIFlagsSection::FpABIKind Value) {
135   forbidModuleDirective();
136 }
137 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
138 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
139   forbidModuleDirective();
140 }
141 
142 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
143                                const MCSubtargetInfo *STI) {
144   MCInst TmpInst;
145   TmpInst.setOpcode(Opcode);
146   TmpInst.addOperand(MCOperand::createReg(Reg0));
147   TmpInst.setLoc(IDLoc);
148   getStreamer().EmitInstruction(TmpInst, *STI);
149 }
150 
151 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
152                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
153   MCInst TmpInst;
154   TmpInst.setOpcode(Opcode);
155   TmpInst.addOperand(MCOperand::createReg(Reg0));
156   TmpInst.addOperand(Op1);
157   TmpInst.setLoc(IDLoc);
158   getStreamer().EmitInstruction(TmpInst, *STI);
159 }
160 
161 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
162                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
163   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
164 }
165 
166 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
167                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
168   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
169 }
170 
171 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
172                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
173   MCInst TmpInst;
174   TmpInst.setOpcode(Opcode);
175   TmpInst.addOperand(MCOperand::createImm(Imm1));
176   TmpInst.addOperand(MCOperand::createImm(Imm2));
177   TmpInst.setLoc(IDLoc);
178   getStreamer().EmitInstruction(TmpInst, *STI);
179 }
180 
181 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
182                                  MCOperand Op2, SMLoc IDLoc,
183                                  const MCSubtargetInfo *STI) {
184   MCInst TmpInst;
185   TmpInst.setOpcode(Opcode);
186   TmpInst.addOperand(MCOperand::createReg(Reg0));
187   TmpInst.addOperand(MCOperand::createReg(Reg1));
188   TmpInst.addOperand(Op2);
189   TmpInst.setLoc(IDLoc);
190   getStreamer().EmitInstruction(TmpInst, *STI);
191 }
192 
193 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
194                                  unsigned Reg2, SMLoc IDLoc,
195                                  const MCSubtargetInfo *STI) {
196   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
197 }
198 
199 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
200                                  int16_t Imm, SMLoc IDLoc,
201                                  const MCSubtargetInfo *STI) {
202   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
203 }
204 
205 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
206                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
207                                    int16_t Imm2, SMLoc IDLoc,
208                                    const MCSubtargetInfo *STI) {
209   MCInst TmpInst;
210   TmpInst.setOpcode(Opcode);
211   TmpInst.addOperand(MCOperand::createReg(Reg0));
212   TmpInst.addOperand(MCOperand::createReg(Reg1));
213   TmpInst.addOperand(MCOperand::createImm(Imm0));
214   TmpInst.addOperand(MCOperand::createImm(Imm1));
215   TmpInst.addOperand(MCOperand::createImm(Imm2));
216   TmpInst.setLoc(IDLoc);
217   getStreamer().EmitInstruction(TmpInst, *STI);
218 }
219 
220 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
221                                   unsigned TrgReg, bool Is64Bit,
222                                   const MCSubtargetInfo *STI) {
223   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
224           STI);
225 }
226 
227 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
228                                   int16_t ShiftAmount, SMLoc IDLoc,
229                                   const MCSubtargetInfo *STI) {
230   if (ShiftAmount >= 32) {
231     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
232     return;
233   }
234 
235   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
236 }
237 
238 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
239                                             const MCSubtargetInfo *STI) {
240   if (hasShortDelaySlot)
241     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
242   else
243     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
244 }
245 
246 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
247   emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
248 }
249 
250 /// Emit the $gp restore operation for .cprestore.
251 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
252                                        const MCSubtargetInfo *STI) {
253   emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
254                         STI);
255 }
256 
257 /// Emit a store instruction with an immediate offset.
258 void MipsTargetStreamer::emitStoreWithImmOffset(
259     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
260     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
261     const MCSubtargetInfo *STI) {
262   if (isInt<16>(Offset)) {
263     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
264     return;
265   }
266 
267   // sw $8, offset($8) => lui $at, %hi(offset)
268   //                      add $at, $at, $8
269   //                      sw $8, %lo(offset)($at)
270 
271   unsigned ATReg = GetATReg();
272   if (!ATReg)
273     return;
274 
275   unsigned LoOffset = Offset & 0x0000ffff;
276   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
277 
278   // If msb of LoOffset is 1(negative number) we must increment HiOffset
279   // to account for the sign-extension of the low part.
280   if (LoOffset & 0x8000)
281     HiOffset++;
282 
283   // Generate the base address in ATReg.
284   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
285   if (BaseReg != Mips::ZERO)
286     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
287   // Emit the store with the adjusted base and offset.
288   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
289 }
290 
291 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
292 /// out of range for a simm16 will be expanded to appropriate instructions.
293 void MipsTargetStreamer::emitStoreWithSymOffset(
294     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
295     MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
296     const MCSubtargetInfo *STI) {
297   // sw $8, sym => lui $at, %hi(sym)
298   //               sw $8, %lo(sym)($at)
299 
300   // Generate the base address in ATReg.
301   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
302   if (BaseReg != Mips::ZERO)
303     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
304   // Emit the store with the adjusted base and offset.
305   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
306 }
307 
308 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
309 /// permitted to be the same register iff DstReg is distinct from BaseReg and
310 /// DstReg is a GPR. It is the callers responsibility to identify such cases
311 /// and pass the appropriate register in TmpReg.
312 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
313                                                unsigned BaseReg, int64_t Offset,
314                                                unsigned TmpReg, SMLoc IDLoc,
315                                                const MCSubtargetInfo *STI) {
316   if (isInt<16>(Offset)) {
317     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
318     return;
319   }
320 
321   // 1) lw $8, offset($9) => lui $8, %hi(offset)
322   //                         add $8, $8, $9
323   //                         lw $8, %lo(offset)($9)
324   // 2) lw $8, offset($8) => lui $at, %hi(offset)
325   //                         add $at, $at, $8
326   //                         lw $8, %lo(offset)($at)
327 
328   unsigned LoOffset = Offset & 0x0000ffff;
329   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
330 
331   // If msb of LoOffset is 1(negative number) we must increment HiOffset
332   // to account for the sign-extension of the low part.
333   if (LoOffset & 0x8000)
334     HiOffset++;
335 
336   // Generate the base address in TmpReg.
337   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
338   if (BaseReg != Mips::ZERO)
339     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
340   // Emit the load with the adjusted base and offset.
341   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
342 }
343 
344 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
345 /// out of range for a simm16 will be expanded to appropriate instructions.
346 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
347 /// GPR. It is the callers responsibility to identify such cases and pass the
348 /// appropriate register in TmpReg.
349 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
350                                                unsigned BaseReg,
351                                                MCOperand &HiOperand,
352                                                MCOperand &LoOperand,
353                                                unsigned TmpReg, SMLoc IDLoc,
354                                                const MCSubtargetInfo *STI) {
355   // 1) lw $8, sym        => lui $8, %hi(sym)
356   //                         lw $8, %lo(sym)($8)
357   // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
358   //                         ldc1 $f0, %lo(sym)($at)
359 
360   // Generate the base address in TmpReg.
361   emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
362   if (BaseReg != Mips::ZERO)
363     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
364   // Emit the load with the adjusted base and offset.
365   emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
366 }
367 
368 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
369                                              formatted_raw_ostream &OS)
370     : MipsTargetStreamer(S), OS(OS) {}
371 
372 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
373   OS << "\t.set\tmicromips\n";
374   forbidModuleDirective();
375 }
376 
377 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
378   OS << "\t.set\tnomicromips\n";
379   forbidModuleDirective();
380 }
381 
382 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
383   OS << "\t.set\tmips16\n";
384   forbidModuleDirective();
385 }
386 
387 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
388   OS << "\t.set\tnomips16\n";
389   MipsTargetStreamer::emitDirectiveSetNoMips16();
390 }
391 
392 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
393   OS << "\t.set\treorder\n";
394   MipsTargetStreamer::emitDirectiveSetReorder();
395 }
396 
397 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
398   OS << "\t.set\tnoreorder\n";
399   forbidModuleDirective();
400 }
401 
402 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
403   OS << "\t.set\tmacro\n";
404   MipsTargetStreamer::emitDirectiveSetMacro();
405 }
406 
407 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
408   OS << "\t.set\tnomacro\n";
409   MipsTargetStreamer::emitDirectiveSetNoMacro();
410 }
411 
412 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
413   OS << "\t.set\tmsa\n";
414   MipsTargetStreamer::emitDirectiveSetMsa();
415 }
416 
417 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
418   OS << "\t.set\tnomsa\n";
419   MipsTargetStreamer::emitDirectiveSetNoMsa();
420 }
421 
422 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
423   OS << "\t.set\tmt\n";
424   MipsTargetStreamer::emitDirectiveSetMt();
425 }
426 
427 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
428   OS << "\t.set\tnomt\n";
429   MipsTargetStreamer::emitDirectiveSetNoMt();
430 }
431 
432 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
433   OS << "\t.set\tcrc\n";
434   MipsTargetStreamer::emitDirectiveSetCRC();
435 }
436 
437 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
438   OS << "\t.set\tnocrc\n";
439   MipsTargetStreamer::emitDirectiveSetNoCRC();
440 }
441 
442 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
443   OS << "\t.set\tvirt\n";
444   MipsTargetStreamer::emitDirectiveSetVirt();
445 }
446 
447 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
448   OS << "\t.set\tnovirt\n";
449   MipsTargetStreamer::emitDirectiveSetNoVirt();
450 }
451 
452 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
453   OS << "\t.set\tat\n";
454   MipsTargetStreamer::emitDirectiveSetAt();
455 }
456 
457 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
458   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
459   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
460 }
461 
462 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
463   OS << "\t.set\tnoat\n";
464   MipsTargetStreamer::emitDirectiveSetNoAt();
465 }
466 
467 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
468   OS << "\t.end\t" << Name << '\n';
469 }
470 
471 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
472   OS << "\t.ent\t" << Symbol.getName() << '\n';
473 }
474 
475 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
476 
477 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
478 
479 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
480   OS << "\t.nan\tlegacy\n";
481 }
482 
483 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
484   OS << "\t.option\tpic0\n";
485 }
486 
487 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
488   OS << "\t.option\tpic2\n";
489 }
490 
491 void MipsTargetAsmStreamer::emitDirectiveInsn() {
492   MipsTargetStreamer::emitDirectiveInsn();
493   OS << "\t.insn\n";
494 }
495 
496 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
497                                       unsigned ReturnReg) {
498   OS << "\t.frame\t$"
499      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
500      << StackSize << ",$"
501      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
502 }
503 
504 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
505   OS << "\t.set arch=" << Arch << "\n";
506   MipsTargetStreamer::emitDirectiveSetArch(Arch);
507 }
508 
509 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
510   OS << "\t.set\tmips0\n";
511   MipsTargetStreamer::emitDirectiveSetMips0();
512 }
513 
514 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
515   OS << "\t.set\tmips1\n";
516   MipsTargetStreamer::emitDirectiveSetMips1();
517 }
518 
519 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
520   OS << "\t.set\tmips2\n";
521   MipsTargetStreamer::emitDirectiveSetMips2();
522 }
523 
524 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
525   OS << "\t.set\tmips3\n";
526   MipsTargetStreamer::emitDirectiveSetMips3();
527 }
528 
529 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
530   OS << "\t.set\tmips4\n";
531   MipsTargetStreamer::emitDirectiveSetMips4();
532 }
533 
534 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
535   OS << "\t.set\tmips5\n";
536   MipsTargetStreamer::emitDirectiveSetMips5();
537 }
538 
539 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
540   OS << "\t.set\tmips32\n";
541   MipsTargetStreamer::emitDirectiveSetMips32();
542 }
543 
544 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
545   OS << "\t.set\tmips32r2\n";
546   MipsTargetStreamer::emitDirectiveSetMips32R2();
547 }
548 
549 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
550   OS << "\t.set\tmips32r3\n";
551   MipsTargetStreamer::emitDirectiveSetMips32R3();
552 }
553 
554 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
555   OS << "\t.set\tmips32r5\n";
556   MipsTargetStreamer::emitDirectiveSetMips32R5();
557 }
558 
559 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
560   OS << "\t.set\tmips32r6\n";
561   MipsTargetStreamer::emitDirectiveSetMips32R6();
562 }
563 
564 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
565   OS << "\t.set\tmips64\n";
566   MipsTargetStreamer::emitDirectiveSetMips64();
567 }
568 
569 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
570   OS << "\t.set\tmips64r2\n";
571   MipsTargetStreamer::emitDirectiveSetMips64R2();
572 }
573 
574 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
575   OS << "\t.set\tmips64r3\n";
576   MipsTargetStreamer::emitDirectiveSetMips64R3();
577 }
578 
579 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
580   OS << "\t.set\tmips64r5\n";
581   MipsTargetStreamer::emitDirectiveSetMips64R5();
582 }
583 
584 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
585   OS << "\t.set\tmips64r6\n";
586   MipsTargetStreamer::emitDirectiveSetMips64R6();
587 }
588 
589 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
590   OS << "\t.set\tdsp\n";
591   MipsTargetStreamer::emitDirectiveSetDsp();
592 }
593 
594 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
595   OS << "\t.set\tdspr2\n";
596   MipsTargetStreamer::emitDirectiveSetDspr2();
597 }
598 
599 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
600   OS << "\t.set\tnodsp\n";
601   MipsTargetStreamer::emitDirectiveSetNoDsp();
602 }
603 
604 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
605   OS << "\t.set\tpop\n";
606   MipsTargetStreamer::emitDirectiveSetPop();
607 }
608 
609 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
610  OS << "\t.set\tpush\n";
611  MipsTargetStreamer::emitDirectiveSetPush();
612 }
613 
614 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
615   OS << "\t.set\tsoftfloat\n";
616   MipsTargetStreamer::emitDirectiveSetSoftFloat();
617 }
618 
619 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
620   OS << "\t.set\thardfloat\n";
621   MipsTargetStreamer::emitDirectiveSetHardFloat();
622 }
623 
624 // Print a 32 bit hex number with all numbers.
625 static void printHex32(unsigned Value, raw_ostream &OS) {
626   OS << "0x";
627   for (int i = 7; i >= 0; i--)
628     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
629 }
630 
631 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
632                                      int CPUTopSavedRegOff) {
633   OS << "\t.mask \t";
634   printHex32(CPUBitmask, OS);
635   OS << ',' << CPUTopSavedRegOff << '\n';
636 }
637 
638 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
639                                       int FPUTopSavedRegOff) {
640   OS << "\t.fmask\t";
641   printHex32(FPUBitmask, OS);
642   OS << "," << FPUTopSavedRegOff << '\n';
643 }
644 
645 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
646   OS << "\t.cpload\t$"
647      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
648   forbidModuleDirective();
649 }
650 
651 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
652     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
653     const MCSubtargetInfo *STI) {
654   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
655   OS << "\t.cprestore\t" << Offset << "\n";
656   return true;
657 }
658 
659 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
660                                                  int RegOrOffset,
661                                                  const MCSymbol &Sym,
662                                                  bool IsReg) {
663   OS << "\t.cpsetup\t$"
664      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
665 
666   if (IsReg)
667     OS << "$"
668        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
669   else
670     OS << RegOrOffset;
671 
672   OS << ", ";
673 
674   OS << Sym.getName();
675   forbidModuleDirective();
676 }
677 
678 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
679                                                   bool SaveLocationIsRegister) {
680   OS << "\t.cpreturn";
681   forbidModuleDirective();
682 }
683 
684 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
685   OS << "\t.module\tfp=";
686   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
687 }
688 
689 void MipsTargetAsmStreamer::emitDirectiveSetFp(
690     MipsABIFlagsSection::FpABIKind Value) {
691   MipsTargetStreamer::emitDirectiveSetFp(Value);
692 
693   OS << "\t.set\tfp=";
694   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
695 }
696 
697 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
698   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
699 
700   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
701 }
702 
703 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
704   MipsTargetStreamer::emitDirectiveSetOddSPReg();
705   OS << "\t.set\toddspreg\n";
706 }
707 
708 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
709   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
710   OS << "\t.set\tnooddspreg\n";
711 }
712 
713 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
714   OS << "\t.module\tsoftfloat\n";
715 }
716 
717 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
718   OS << "\t.module\thardfloat\n";
719 }
720 
721 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
722   OS << "\t.module\tmt\n";
723 }
724 
725 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
726   OS << "\t.module\tcrc\n";
727 }
728 
729 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
730   OS << "\t.module\tnocrc\n";
731 }
732 
733 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
734   OS << "\t.module\tvirt\n";
735 }
736 
737 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
738   OS << "\t.module\tnovirt\n";
739 }
740 
741 // This part is for ELF object output.
742 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
743                                              const MCSubtargetInfo &STI)
744     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
745   MCAssembler &MCA = getStreamer().getAssembler();
746 
747   // It's possible that MCObjectFileInfo isn't fully initialized at this point
748   // due to an initialization order problem where LLVMTargetMachine creates the
749   // target streamer before TargetLoweringObjectFile calls
750   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
751   // covers all cases so this statement covers most cases and direct object
752   // emission must call setPic() once MCObjectFileInfo has been initialized. The
753   // cases we don't handle here are covered by MipsAsmPrinter.
754   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
755 
756   const FeatureBitset &Features = STI.getFeatureBits();
757 
758   // Set the header flags that we can in the constructor.
759   // FIXME: This is a fairly terrible hack. We set the rest
760   // of these in the destructor. The problem here is two-fold:
761   //
762   // a: Some of the eflags can be set/reset by directives.
763   // b: There aren't any usage paths that initialize the ABI
764   //    pointer until after we initialize either an assembler
765   //    or the target machine.
766   // We can fix this by making the target streamer construct
767   // the ABI, but this is fraught with wide ranging dependency
768   // issues as well.
769   unsigned EFlags = MCA.getELFHeaderEFlags();
770 
771   // FIXME: Fix a dependency issue by instantiating the ABI object to some
772   // default based off the triple. The triple doesn't describe the target
773   // fully, but any external user of the API that uses the MCTargetStreamer
774   // would otherwise crash on assertion failure.
775 
776   ABI = MipsABIInfo(
777       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
778               STI.getTargetTriple().getArch() == Triple::ArchType::mips
779           ? MipsABIInfo::O32()
780           : MipsABIInfo::N64());
781 
782   // Architecture
783   if (Features[Mips::FeatureMips64r6])
784     EFlags |= ELF::EF_MIPS_ARCH_64R6;
785   else if (Features[Mips::FeatureMips64r2] ||
786            Features[Mips::FeatureMips64r3] ||
787            Features[Mips::FeatureMips64r5])
788     EFlags |= ELF::EF_MIPS_ARCH_64R2;
789   else if (Features[Mips::FeatureMips64])
790     EFlags |= ELF::EF_MIPS_ARCH_64;
791   else if (Features[Mips::FeatureMips5])
792     EFlags |= ELF::EF_MIPS_ARCH_5;
793   else if (Features[Mips::FeatureMips4])
794     EFlags |= ELF::EF_MIPS_ARCH_4;
795   else if (Features[Mips::FeatureMips3])
796     EFlags |= ELF::EF_MIPS_ARCH_3;
797   else if (Features[Mips::FeatureMips32r6])
798     EFlags |= ELF::EF_MIPS_ARCH_32R6;
799   else if (Features[Mips::FeatureMips32r2] ||
800            Features[Mips::FeatureMips32r3] ||
801            Features[Mips::FeatureMips32r5])
802     EFlags |= ELF::EF_MIPS_ARCH_32R2;
803   else if (Features[Mips::FeatureMips32])
804     EFlags |= ELF::EF_MIPS_ARCH_32;
805   else if (Features[Mips::FeatureMips2])
806     EFlags |= ELF::EF_MIPS_ARCH_2;
807   else
808     EFlags |= ELF::EF_MIPS_ARCH_1;
809 
810   // Machine
811   if (Features[Mips::FeatureCnMips])
812     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
813 
814   // Other options.
815   if (Features[Mips::FeatureNaN2008])
816     EFlags |= ELF::EF_MIPS_NAN2008;
817 
818   MCA.setELFHeaderEFlags(EFlags);
819 }
820 
821 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
822   auto *Symbol = cast<MCSymbolELF>(S);
823   getStreamer().getAssembler().registerSymbol(*Symbol);
824   uint8_t Type = Symbol->getType();
825   if (Type != ELF::STT_FUNC)
826     return;
827 
828   if (isMicroMipsEnabled())
829     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
830 }
831 
832 void MipsTargetELFStreamer::finish() {
833   MCAssembler &MCA = getStreamer().getAssembler();
834   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
835 
836   // .bss, .text and .data are always at least 16-byte aligned.
837   MCSection &TextSection = *OFI.getTextSection();
838   MCA.registerSection(TextSection);
839   MCSection &DataSection = *OFI.getDataSection();
840   MCA.registerSection(DataSection);
841   MCSection &BSSSection = *OFI.getBSSSection();
842   MCA.registerSection(BSSSection);
843 
844   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
845   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
846   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
847 
848   if (RoundSectionSizes) {
849     // Make sections sizes a multiple of the alignment. This is useful for
850     // verifying the output of IAS against the output of other assemblers but
851     // it's not necessary to produce a correct object and increases section
852     // size.
853     MCStreamer &OS = getStreamer();
854     for (MCSection &S : MCA) {
855       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
856 
857       unsigned Alignment = Section.getAlignment();
858       if (Alignment) {
859         OS.SwitchSection(&Section);
860         if (Section.UseCodeAlign())
861           OS.EmitCodeAlignment(Alignment, Alignment);
862         else
863           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
864       }
865     }
866   }
867 
868   const FeatureBitset &Features = STI.getFeatureBits();
869 
870   // Update e_header flags. See the FIXME and comment above in
871   // the constructor for a full rundown on this.
872   unsigned EFlags = MCA.getELFHeaderEFlags();
873 
874   // ABI
875   // N64 does not require any ABI bits.
876   if (getABI().IsO32())
877     EFlags |= ELF::EF_MIPS_ABI_O32;
878   else if (getABI().IsN32())
879     EFlags |= ELF::EF_MIPS_ABI2;
880 
881   if (Features[Mips::FeatureGP64Bit]) {
882     if (getABI().IsO32())
883       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
884   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
885     EFlags |= ELF::EF_MIPS_32BITMODE;
886 
887   // -mplt is not implemented but we should act as if it was
888   // given.
889   if (!Features[Mips::FeatureNoABICalls])
890     EFlags |= ELF::EF_MIPS_CPIC;
891 
892   if (Pic)
893     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
894 
895   MCA.setELFHeaderEFlags(EFlags);
896 
897   // Emit all the option records.
898   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
899   // .reginfo.
900   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
901   MEF.EmitMipsOptionRecords();
902 
903   emitMipsAbiFlags();
904 }
905 
906 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
907   auto *Symbol = cast<MCSymbolELF>(S);
908   // If on rhs is micromips symbol then mark Symbol as microMips.
909   if (Value->getKind() != MCExpr::SymbolRef)
910     return;
911   const auto &RhsSym = cast<MCSymbolELF>(
912       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
913 
914   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
915     return;
916 
917   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
918 }
919 
920 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
921   return static_cast<MCELFStreamer &>(Streamer);
922 }
923 
924 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
925   MicroMipsEnabled = true;
926   forbidModuleDirective();
927 }
928 
929 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
930   MicroMipsEnabled = false;
931   forbidModuleDirective();
932 }
933 
934 void MipsTargetELFStreamer::setUsesMicroMips() {
935   MCAssembler &MCA = getStreamer().getAssembler();
936   unsigned Flags = MCA.getELFHeaderEFlags();
937   Flags |= ELF::EF_MIPS_MICROMIPS;
938   MCA.setELFHeaderEFlags(Flags);
939 }
940 
941 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
942   MCAssembler &MCA = getStreamer().getAssembler();
943   unsigned Flags = MCA.getELFHeaderEFlags();
944   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
945   MCA.setELFHeaderEFlags(Flags);
946   forbidModuleDirective();
947 }
948 
949 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
950   MCAssembler &MCA = getStreamer().getAssembler();
951   unsigned Flags = MCA.getELFHeaderEFlags();
952   Flags |= ELF::EF_MIPS_NOREORDER;
953   MCA.setELFHeaderEFlags(Flags);
954   forbidModuleDirective();
955 }
956 
957 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
958   MCAssembler &MCA = getStreamer().getAssembler();
959   MCContext &Context = MCA.getContext();
960   MCStreamer &OS = getStreamer();
961 
962   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
963 
964   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
965   const MCSymbolRefExpr *ExprRef =
966       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
967 
968   MCA.registerSection(*Sec);
969   Sec->setAlignment(4);
970 
971   OS.PushSection();
972 
973   OS.SwitchSection(Sec);
974 
975   OS.EmitValueImpl(ExprRef, 4);
976 
977   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
978   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
979 
980   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
981   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
982 
983   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
984   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
985   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
986 
987   // The .end directive marks the end of a procedure. Invalidate
988   // the information gathered up until this point.
989   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
990 
991   OS.PopSection();
992 
993   // .end also implicitly sets the size.
994   MCSymbol *CurPCSym = Context.createTempSymbol();
995   OS.EmitLabel(CurPCSym);
996   const MCExpr *Size = MCBinaryExpr::createSub(
997       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
998       ExprRef, Context);
999 
1000   // The ELFObjectWriter can determine the absolute size as it has access to
1001   // the layout information of the assembly file, so a size expression rather
1002   // than an absolute value is ok here.
1003   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1004 }
1005 
1006 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1007   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1008 
1009   // .ent also acts like an implicit '.type symbol, STT_FUNC'
1010   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1011 }
1012 
1013 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1014   MCAssembler &MCA = getStreamer().getAssembler();
1015   unsigned Flags = MCA.getELFHeaderEFlags();
1016   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1017   MCA.setELFHeaderEFlags(Flags);
1018 }
1019 
1020 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1021   MCAssembler &MCA = getStreamer().getAssembler();
1022   unsigned Flags = MCA.getELFHeaderEFlags();
1023   Flags |= ELF::EF_MIPS_NAN2008;
1024   MCA.setELFHeaderEFlags(Flags);
1025 }
1026 
1027 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1028   MCAssembler &MCA = getStreamer().getAssembler();
1029   unsigned Flags = MCA.getELFHeaderEFlags();
1030   Flags &= ~ELF::EF_MIPS_NAN2008;
1031   MCA.setELFHeaderEFlags(Flags);
1032 }
1033 
1034 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1035   MCAssembler &MCA = getStreamer().getAssembler();
1036   unsigned Flags = MCA.getELFHeaderEFlags();
1037   // This option overrides other PIC options like -KPIC.
1038   Pic = false;
1039   Flags &= ~ELF::EF_MIPS_PIC;
1040   MCA.setELFHeaderEFlags(Flags);
1041 }
1042 
1043 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1044   MCAssembler &MCA = getStreamer().getAssembler();
1045   unsigned Flags = MCA.getELFHeaderEFlags();
1046   Pic = true;
1047   // NOTE: We are following the GAS behaviour here which means the directive
1048   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1049   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1050   // EF_MIPS_CPIC to be mutually exclusive.
1051   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1052   MCA.setELFHeaderEFlags(Flags);
1053 }
1054 
1055 void MipsTargetELFStreamer::emitDirectiveInsn() {
1056   MipsTargetStreamer::emitDirectiveInsn();
1057   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1058   MEF.createPendingLabelRelocs();
1059 }
1060 
1061 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1062                                       unsigned ReturnReg_) {
1063   MCContext &Context = getStreamer().getAssembler().getContext();
1064   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1065 
1066   FrameInfoSet = true;
1067   FrameReg = RegInfo->getEncodingValue(StackReg);
1068   FrameOffset = StackSize;
1069   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1070 }
1071 
1072 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1073                                      int CPUTopSavedRegOff) {
1074   GPRInfoSet = true;
1075   GPRBitMask = CPUBitmask;
1076   GPROffset = CPUTopSavedRegOff;
1077 }
1078 
1079 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1080                                       int FPUTopSavedRegOff) {
1081   FPRInfoSet = true;
1082   FPRBitMask = FPUBitmask;
1083   FPROffset = FPUTopSavedRegOff;
1084 }
1085 
1086 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1087   // .cpload $reg
1088   // This directive expands to:
1089   // lui   $gp, %hi(_gp_disp)
1090   // addui $gp, $gp, %lo(_gp_disp)
1091   // addu  $gp, $gp, $reg
1092   // when support for position independent code is enabled.
1093   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1094     return;
1095 
1096   // There's a GNU extension controlled by -mno-shared that allows
1097   // locally-binding symbols to be accessed using absolute addresses.
1098   // This is currently not supported. When supported -mno-shared makes
1099   // .cpload expand to:
1100   //   lui     $gp, %hi(__gnu_local_gp)
1101   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1102 
1103   StringRef SymName("_gp_disp");
1104   MCAssembler &MCA = getStreamer().getAssembler();
1105   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1106   MCA.registerSymbol(*GP_Disp);
1107 
1108   MCInst TmpInst;
1109   TmpInst.setOpcode(Mips::LUi);
1110   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1111   const MCExpr *HiSym = MipsMCExpr::create(
1112       MipsMCExpr::MEK_HI,
1113       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1114                               MCA.getContext()),
1115       MCA.getContext());
1116   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1117   getStreamer().EmitInstruction(TmpInst, STI);
1118 
1119   TmpInst.clear();
1120 
1121   TmpInst.setOpcode(Mips::ADDiu);
1122   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1123   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1124   const MCExpr *LoSym = MipsMCExpr::create(
1125       MipsMCExpr::MEK_LO,
1126       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1127                               MCA.getContext()),
1128       MCA.getContext());
1129   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1130   getStreamer().EmitInstruction(TmpInst, STI);
1131 
1132   TmpInst.clear();
1133 
1134   TmpInst.setOpcode(Mips::ADDu);
1135   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1136   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1137   TmpInst.addOperand(MCOperand::createReg(RegNo));
1138   getStreamer().EmitInstruction(TmpInst, STI);
1139 
1140   forbidModuleDirective();
1141 }
1142 
1143 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1144     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1145     const MCSubtargetInfo *STI) {
1146   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1147   // .cprestore offset
1148   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1149   // to:
1150   //    sw $gp, offset($sp)
1151   // and adds a corresponding LW after every JAL.
1152 
1153   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1154   // is used in non-PIC mode.
1155   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1156     return true;
1157 
1158   // Store the $gp on the stack.
1159   emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1160                          STI);
1161   return true;
1162 }
1163 
1164 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1165                                                  int RegOrOffset,
1166                                                  const MCSymbol &Sym,
1167                                                  bool IsReg) {
1168   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1169   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1170     return;
1171 
1172   forbidModuleDirective();
1173 
1174   MCAssembler &MCA = getStreamer().getAssembler();
1175   MCInst Inst;
1176 
1177   // Either store the old $gp in a register or on the stack
1178   if (IsReg) {
1179     // move $save, $gpreg
1180     emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1181   } else {
1182     // sd $gpreg, offset($sp)
1183     emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1184   }
1185 
1186   if (getABI().IsN32()) {
1187     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1188     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1189         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1190         MCA.getContext());
1191     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1192         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1193         MCA.getContext());
1194 
1195     // lui $gp, %hi(__gnu_local_gp)
1196     emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1197 
1198     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1199     emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1200             SMLoc(), &STI);
1201 
1202     return;
1203   }
1204 
1205   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1206       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1207       MCA.getContext());
1208   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1209       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1210       MCA.getContext());
1211 
1212   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1213   emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1214 
1215   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1216   emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1217           SMLoc(), &STI);
1218 
1219   // daddu  $gp, $gp, $funcreg
1220   emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1221 }
1222 
1223 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1224                                                   bool SaveLocationIsRegister) {
1225   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1226   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1227     return;
1228 
1229   MCInst Inst;
1230   // Either restore the old $gp from a register or on the stack
1231   if (SaveLocationIsRegister) {
1232     Inst.setOpcode(Mips::OR);
1233     Inst.addOperand(MCOperand::createReg(Mips::GP));
1234     Inst.addOperand(MCOperand::createReg(SaveLocation));
1235     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1236   } else {
1237     Inst.setOpcode(Mips::LD);
1238     Inst.addOperand(MCOperand::createReg(Mips::GP));
1239     Inst.addOperand(MCOperand::createReg(Mips::SP));
1240     Inst.addOperand(MCOperand::createImm(SaveLocation));
1241   }
1242   getStreamer().EmitInstruction(Inst, STI);
1243 
1244   forbidModuleDirective();
1245 }
1246 
1247 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1248   MCAssembler &MCA = getStreamer().getAssembler();
1249   MCContext &Context = MCA.getContext();
1250   MCStreamer &OS = getStreamer();
1251   MCSectionELF *Sec = Context.getELFSection(
1252       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1253   MCA.registerSection(*Sec);
1254   Sec->setAlignment(8);
1255   OS.SwitchSection(Sec);
1256 
1257   OS << ABIFlagsSection;
1258 }
1259