1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MCTargetDesc/MipsABIInfo.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsInstPrinter.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/Casting.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/FormattedStream.h"
30 
31 using namespace llvm;
32 
33 namespace {
34 static cl::opt<bool> RoundSectionSizes(
35     "mips-round-section-sizes", cl::init(false),
36     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
37 } // end anonymous namespace
38 
39 static bool isMicroMips(const MCSubtargetInfo *STI) {
40   return STI->getFeatureBits()[Mips::FeatureMicroMips];
41 }
42 
43 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
44     : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
45   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
46 }
47 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
48 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
49 void MipsTargetStreamer::setUsesMicroMips() {}
50 void MipsTargetStreamer::emitDirectiveSetMips16() {}
51 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
54 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
55 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
56 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
57 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
58 void MipsTargetStreamer::emitDirectiveSetMt() {}
59 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
60 void MipsTargetStreamer::emitDirectiveSetCRC() {}
61 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
62 void MipsTargetStreamer::emitDirectiveSetVirt() {}
63 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
64 void MipsTargetStreamer::emitDirectiveSetGINV() {}
65 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
66 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
67 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
68   forbidModuleDirective();
69 }
70 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
71 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
72 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
73 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
74 void MipsTargetStreamer::emitDirectiveNaN2008() {}
75 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
76 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
77 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
78 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
80                                    unsigned ReturnReg) {}
81 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
82 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
83 }
84 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
85   forbidModuleDirective();
86 }
87 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
95 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
96 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
97 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
98 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
99 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
100 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
101 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
102 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
103 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
104 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
105 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
106   forbidModuleDirective();
107 }
108 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
109   forbidModuleDirective();
110 }
111 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
112 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
113 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
114 void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); }
115 void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); }
116 void MipsTargetStreamer::emitDirectiveCpAdd(unsigned RegNo) {}
117 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
118 void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
119   // .cplocal $reg
120   // This directive forces to use the alternate register for context pointer.
121   // For example
122   //   .cplocal $4
123   //   jal foo
124   // expands to
125   //   ld    $25, %call16(foo)($4)
126   //   jalr  $25
127 
128   if (!getABI().IsN32() && !getABI().IsN64())
129     return;
130 
131   GPReg = RegNo;
132 
133   forbidModuleDirective();
134 }
135 bool MipsTargetStreamer::emitDirectiveCpRestore(
136     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
137     const MCSubtargetInfo *STI) {
138   forbidModuleDirective();
139   return true;
140 }
141 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
142                                               const MCSymbol &Sym, bool IsReg) {
143 }
144 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
145                                                bool SaveLocationIsRegister) {}
146 
147 void MipsTargetStreamer::emitDirectiveModuleFP() {}
148 
149 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
150   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
151     report_fatal_error("+nooddspreg is only valid for O32");
152 }
153 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
154 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
155 void MipsTargetStreamer::emitDirectiveModuleMT() {}
156 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
157 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
158 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
159 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
160 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
161 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
162 void MipsTargetStreamer::emitDirectiveSetFp(
163     MipsABIFlagsSection::FpABIKind Value) {
164   forbidModuleDirective();
165 }
166 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
167 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
168   forbidModuleDirective();
169 }
170 
171 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
172                                const MCSubtargetInfo *STI) {
173   MCInst TmpInst;
174   TmpInst.setOpcode(Opcode);
175   TmpInst.addOperand(MCOperand::createReg(Reg0));
176   TmpInst.setLoc(IDLoc);
177   getStreamer().emitInstruction(TmpInst, *STI);
178 }
179 
180 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
181                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
182   MCInst TmpInst;
183   TmpInst.setOpcode(Opcode);
184   TmpInst.addOperand(MCOperand::createReg(Reg0));
185   TmpInst.addOperand(Op1);
186   TmpInst.setLoc(IDLoc);
187   getStreamer().emitInstruction(TmpInst, *STI);
188 }
189 
190 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
191                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
192   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
193 }
194 
195 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
196                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
197   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
198 }
199 
200 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
201                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
202   MCInst TmpInst;
203   TmpInst.setOpcode(Opcode);
204   TmpInst.addOperand(MCOperand::createImm(Imm1));
205   TmpInst.addOperand(MCOperand::createImm(Imm2));
206   TmpInst.setLoc(IDLoc);
207   getStreamer().emitInstruction(TmpInst, *STI);
208 }
209 
210 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
211                                  MCOperand Op2, SMLoc IDLoc,
212                                  const MCSubtargetInfo *STI) {
213   MCInst TmpInst;
214   TmpInst.setOpcode(Opcode);
215   TmpInst.addOperand(MCOperand::createReg(Reg0));
216   TmpInst.addOperand(MCOperand::createReg(Reg1));
217   TmpInst.addOperand(Op2);
218   TmpInst.setLoc(IDLoc);
219   getStreamer().emitInstruction(TmpInst, *STI);
220 }
221 
222 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
223                                  unsigned Reg2, SMLoc IDLoc,
224                                  const MCSubtargetInfo *STI) {
225   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
226 }
227 
228 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
229                                   unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
230                                   const MCSubtargetInfo *STI) {
231   MCInst TmpInst;
232   TmpInst.setOpcode(Opcode);
233   TmpInst.addOperand(MCOperand::createReg(Reg0));
234   TmpInst.addOperand(MCOperand::createReg(Reg1));
235   TmpInst.addOperand(MCOperand::createReg(Reg2));
236   TmpInst.addOperand(Op3);
237   TmpInst.setLoc(IDLoc);
238   getStreamer().emitInstruction(TmpInst, *STI);
239 }
240 
241 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
242                                  int16_t Imm, SMLoc IDLoc,
243                                  const MCSubtargetInfo *STI) {
244   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
245 }
246 
247 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
248                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
249                                    int16_t Imm2, SMLoc IDLoc,
250                                    const MCSubtargetInfo *STI) {
251   MCInst TmpInst;
252   TmpInst.setOpcode(Opcode);
253   TmpInst.addOperand(MCOperand::createReg(Reg0));
254   TmpInst.addOperand(MCOperand::createReg(Reg1));
255   TmpInst.addOperand(MCOperand::createImm(Imm0));
256   TmpInst.addOperand(MCOperand::createImm(Imm1));
257   TmpInst.addOperand(MCOperand::createImm(Imm2));
258   TmpInst.setLoc(IDLoc);
259   getStreamer().emitInstruction(TmpInst, *STI);
260 }
261 
262 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
263                                   unsigned TrgReg, bool Is64Bit,
264                                   const MCSubtargetInfo *STI) {
265   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
266           STI);
267 }
268 
269 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
270                                   int16_t ShiftAmount, SMLoc IDLoc,
271                                   const MCSubtargetInfo *STI) {
272   if (ShiftAmount >= 32) {
273     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
274     return;
275   }
276 
277   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
278 }
279 
280 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
281                                             const MCSubtargetInfo *STI) {
282   if (hasShortDelaySlot)
283     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
284   else
285     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
286 }
287 
288 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
289   if (isMicroMips(STI))
290     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
291   else
292     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
293 }
294 
295 /// Emit the $gp restore operation for .cprestore.
296 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
297                                        const MCSubtargetInfo *STI) {
298   emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
299 }
300 
301 /// Emit a store instruction with an immediate offset.
302 void MipsTargetStreamer::emitStoreWithImmOffset(
303     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
304     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
305     const MCSubtargetInfo *STI) {
306   if (isInt<16>(Offset)) {
307     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
308     return;
309   }
310 
311   // sw $8, offset($8) => lui $at, %hi(offset)
312   //                      add $at, $at, $8
313   //                      sw $8, %lo(offset)($at)
314 
315   unsigned ATReg = GetATReg();
316   if (!ATReg)
317     return;
318 
319   unsigned LoOffset = Offset & 0x0000ffff;
320   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
321 
322   // If msb of LoOffset is 1(negative number) we must increment HiOffset
323   // to account for the sign-extension of the low part.
324   if (LoOffset & 0x8000)
325     HiOffset++;
326 
327   // Generate the base address in ATReg.
328   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
329   if (BaseReg != Mips::ZERO)
330     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
331   // Emit the store with the adjusted base and offset.
332   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
333 }
334 
335 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
336 /// permitted to be the same register iff DstReg is distinct from BaseReg and
337 /// DstReg is a GPR. It is the callers responsibility to identify such cases
338 /// and pass the appropriate register in TmpReg.
339 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
340                                                unsigned BaseReg, int64_t Offset,
341                                                unsigned TmpReg, SMLoc IDLoc,
342                                                const MCSubtargetInfo *STI) {
343   if (isInt<16>(Offset)) {
344     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
345     return;
346   }
347 
348   // 1) lw $8, offset($9) => lui $8, %hi(offset)
349   //                         add $8, $8, $9
350   //                         lw $8, %lo(offset)($9)
351   // 2) lw $8, offset($8) => lui $at, %hi(offset)
352   //                         add $at, $at, $8
353   //                         lw $8, %lo(offset)($at)
354 
355   unsigned LoOffset = Offset & 0x0000ffff;
356   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
357 
358   // If msb of LoOffset is 1(negative number) we must increment HiOffset
359   // to account for the sign-extension of the low part.
360   if (LoOffset & 0x8000)
361     HiOffset++;
362 
363   // Generate the base address in TmpReg.
364   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
365   if (BaseReg != Mips::ZERO)
366     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
367   // Emit the load with the adjusted base and offset.
368   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
369 }
370 
371 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
372                                              formatted_raw_ostream &OS)
373     : MipsTargetStreamer(S), OS(OS) {}
374 
375 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
376   OS << "\t.set\tmicromips\n";
377   forbidModuleDirective();
378 }
379 
380 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
381   OS << "\t.set\tnomicromips\n";
382   forbidModuleDirective();
383 }
384 
385 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
386   OS << "\t.set\tmips16\n";
387   forbidModuleDirective();
388 }
389 
390 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
391   OS << "\t.set\tnomips16\n";
392   MipsTargetStreamer::emitDirectiveSetNoMips16();
393 }
394 
395 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
396   OS << "\t.set\treorder\n";
397   MipsTargetStreamer::emitDirectiveSetReorder();
398 }
399 
400 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
401   OS << "\t.set\tnoreorder\n";
402   forbidModuleDirective();
403 }
404 
405 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
406   OS << "\t.set\tmacro\n";
407   MipsTargetStreamer::emitDirectiveSetMacro();
408 }
409 
410 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
411   OS << "\t.set\tnomacro\n";
412   MipsTargetStreamer::emitDirectiveSetNoMacro();
413 }
414 
415 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
416   OS << "\t.set\tmsa\n";
417   MipsTargetStreamer::emitDirectiveSetMsa();
418 }
419 
420 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
421   OS << "\t.set\tnomsa\n";
422   MipsTargetStreamer::emitDirectiveSetNoMsa();
423 }
424 
425 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
426   OS << "\t.set\tmt\n";
427   MipsTargetStreamer::emitDirectiveSetMt();
428 }
429 
430 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
431   OS << "\t.set\tnomt\n";
432   MipsTargetStreamer::emitDirectiveSetNoMt();
433 }
434 
435 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
436   OS << "\t.set\tcrc\n";
437   MipsTargetStreamer::emitDirectiveSetCRC();
438 }
439 
440 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
441   OS << "\t.set\tnocrc\n";
442   MipsTargetStreamer::emitDirectiveSetNoCRC();
443 }
444 
445 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
446   OS << "\t.set\tvirt\n";
447   MipsTargetStreamer::emitDirectiveSetVirt();
448 }
449 
450 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
451   OS << "\t.set\tnovirt\n";
452   MipsTargetStreamer::emitDirectiveSetNoVirt();
453 }
454 
455 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
456   OS << "\t.set\tginv\n";
457   MipsTargetStreamer::emitDirectiveSetGINV();
458 }
459 
460 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
461   OS << "\t.set\tnoginv\n";
462   MipsTargetStreamer::emitDirectiveSetNoGINV();
463 }
464 
465 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
466   OS << "\t.set\tat\n";
467   MipsTargetStreamer::emitDirectiveSetAt();
468 }
469 
470 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
471   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
472   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
473 }
474 
475 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
476   OS << "\t.set\tnoat\n";
477   MipsTargetStreamer::emitDirectiveSetNoAt();
478 }
479 
480 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
481   OS << "\t.end\t" << Name << '\n';
482 }
483 
484 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
485   OS << "\t.ent\t" << Symbol.getName() << '\n';
486 }
487 
488 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
489 
490 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
491 
492 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
493   OS << "\t.nan\tlegacy\n";
494 }
495 
496 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
497   OS << "\t.option\tpic0\n";
498 }
499 
500 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
501   OS << "\t.option\tpic2\n";
502 }
503 
504 void MipsTargetAsmStreamer::emitDirectiveInsn() {
505   MipsTargetStreamer::emitDirectiveInsn();
506   OS << "\t.insn\n";
507 }
508 
509 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
510                                       unsigned ReturnReg) {
511   OS << "\t.frame\t$"
512      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
513      << StackSize << ",$"
514      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
515 }
516 
517 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
518   OS << "\t.set arch=" << Arch << "\n";
519   MipsTargetStreamer::emitDirectiveSetArch(Arch);
520 }
521 
522 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
523   OS << "\t.set\tmips0\n";
524   MipsTargetStreamer::emitDirectiveSetMips0();
525 }
526 
527 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
528   OS << "\t.set\tmips1\n";
529   MipsTargetStreamer::emitDirectiveSetMips1();
530 }
531 
532 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
533   OS << "\t.set\tmips2\n";
534   MipsTargetStreamer::emitDirectiveSetMips2();
535 }
536 
537 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
538   OS << "\t.set\tmips3\n";
539   MipsTargetStreamer::emitDirectiveSetMips3();
540 }
541 
542 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
543   OS << "\t.set\tmips4\n";
544   MipsTargetStreamer::emitDirectiveSetMips4();
545 }
546 
547 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
548   OS << "\t.set\tmips5\n";
549   MipsTargetStreamer::emitDirectiveSetMips5();
550 }
551 
552 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
553   OS << "\t.set\tmips32\n";
554   MipsTargetStreamer::emitDirectiveSetMips32();
555 }
556 
557 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
558   OS << "\t.set\tmips32r2\n";
559   MipsTargetStreamer::emitDirectiveSetMips32R2();
560 }
561 
562 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
563   OS << "\t.set\tmips32r3\n";
564   MipsTargetStreamer::emitDirectiveSetMips32R3();
565 }
566 
567 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
568   OS << "\t.set\tmips32r5\n";
569   MipsTargetStreamer::emitDirectiveSetMips32R5();
570 }
571 
572 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
573   OS << "\t.set\tmips32r6\n";
574   MipsTargetStreamer::emitDirectiveSetMips32R6();
575 }
576 
577 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
578   OS << "\t.set\tmips64\n";
579   MipsTargetStreamer::emitDirectiveSetMips64();
580 }
581 
582 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
583   OS << "\t.set\tmips64r2\n";
584   MipsTargetStreamer::emitDirectiveSetMips64R2();
585 }
586 
587 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
588   OS << "\t.set\tmips64r3\n";
589   MipsTargetStreamer::emitDirectiveSetMips64R3();
590 }
591 
592 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
593   OS << "\t.set\tmips64r5\n";
594   MipsTargetStreamer::emitDirectiveSetMips64R5();
595 }
596 
597 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
598   OS << "\t.set\tmips64r6\n";
599   MipsTargetStreamer::emitDirectiveSetMips64R6();
600 }
601 
602 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
603   OS << "\t.set\tdsp\n";
604   MipsTargetStreamer::emitDirectiveSetDsp();
605 }
606 
607 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
608   OS << "\t.set\tdspr2\n";
609   MipsTargetStreamer::emitDirectiveSetDspr2();
610 }
611 
612 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
613   OS << "\t.set\tnodsp\n";
614   MipsTargetStreamer::emitDirectiveSetNoDsp();
615 }
616 
617 void MipsTargetAsmStreamer::emitDirectiveSetMips3D() {
618   OS << "\t.set\tmips3d\n";
619   MipsTargetStreamer::emitDirectiveSetMips3D();
620 }
621 
622 void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() {
623   OS << "\t.set\tnomips3d\n";
624   MipsTargetStreamer::emitDirectiveSetNoMips3D();
625 }
626 
627 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
628   OS << "\t.set\tpop\n";
629   MipsTargetStreamer::emitDirectiveSetPop();
630 }
631 
632 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
633  OS << "\t.set\tpush\n";
634  MipsTargetStreamer::emitDirectiveSetPush();
635 }
636 
637 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
638   OS << "\t.set\tsoftfloat\n";
639   MipsTargetStreamer::emitDirectiveSetSoftFloat();
640 }
641 
642 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
643   OS << "\t.set\thardfloat\n";
644   MipsTargetStreamer::emitDirectiveSetHardFloat();
645 }
646 
647 // Print a 32 bit hex number with all numbers.
648 static void printHex32(unsigned Value, raw_ostream &OS) {
649   OS << "0x";
650   for (int i = 7; i >= 0; i--)
651     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
652 }
653 
654 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
655                                      int CPUTopSavedRegOff) {
656   OS << "\t.mask \t";
657   printHex32(CPUBitmask, OS);
658   OS << ',' << CPUTopSavedRegOff << '\n';
659 }
660 
661 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
662                                       int FPUTopSavedRegOff) {
663   OS << "\t.fmask\t";
664   printHex32(FPUBitmask, OS);
665   OS << "," << FPUTopSavedRegOff << '\n';
666 }
667 
668 void MipsTargetAsmStreamer::emitDirectiveCpAdd(unsigned RegNo) {
669   OS << "\t.cpadd\t$"
670      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
671   forbidModuleDirective();
672 }
673 
674 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
675   OS << "\t.cpload\t$"
676      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
677   forbidModuleDirective();
678 }
679 
680 void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) {
681   OS << "\t.cplocal\t$"
682      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
683   MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
684 }
685 
686 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
687     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
688     const MCSubtargetInfo *STI) {
689   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
690   OS << "\t.cprestore\t" << Offset << "\n";
691   return true;
692 }
693 
694 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
695                                                  int RegOrOffset,
696                                                  const MCSymbol &Sym,
697                                                  bool IsReg) {
698   OS << "\t.cpsetup\t$"
699      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
700 
701   if (IsReg)
702     OS << "$"
703        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
704   else
705     OS << RegOrOffset;
706 
707   OS << ", ";
708 
709   OS << Sym.getName();
710   forbidModuleDirective();
711 }
712 
713 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
714                                                   bool SaveLocationIsRegister) {
715   OS << "\t.cpreturn";
716   forbidModuleDirective();
717 }
718 
719 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
720   MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
721   if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
722     OS << "\t.module\tsoftfloat\n";
723   else
724     OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
725 }
726 
727 void MipsTargetAsmStreamer::emitDirectiveSetFp(
728     MipsABIFlagsSection::FpABIKind Value) {
729   MipsTargetStreamer::emitDirectiveSetFp(Value);
730 
731   OS << "\t.set\tfp=";
732   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
733 }
734 
735 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
736   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
737 
738   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
739 }
740 
741 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
742   MipsTargetStreamer::emitDirectiveSetOddSPReg();
743   OS << "\t.set\toddspreg\n";
744 }
745 
746 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
747   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
748   OS << "\t.set\tnooddspreg\n";
749 }
750 
751 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
752   OS << "\t.module\tsoftfloat\n";
753 }
754 
755 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
756   OS << "\t.module\thardfloat\n";
757 }
758 
759 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
760   OS << "\t.module\tmt\n";
761 }
762 
763 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
764   OS << "\t.module\tcrc\n";
765 }
766 
767 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
768   OS << "\t.module\tnocrc\n";
769 }
770 
771 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
772   OS << "\t.module\tvirt\n";
773 }
774 
775 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
776   OS << "\t.module\tnovirt\n";
777 }
778 
779 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
780   OS << "\t.module\tginv\n";
781 }
782 
783 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
784   OS << "\t.module\tnoginv\n";
785 }
786 
787 // This part is for ELF object output.
788 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
789                                              const MCSubtargetInfo &STI)
790     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
791   MCAssembler &MCA = getStreamer().getAssembler();
792 
793   // It's possible that MCObjectFileInfo isn't fully initialized at this point
794   // due to an initialization order problem where LLVMTargetMachine creates the
795   // target streamer before TargetLoweringObjectFile calls
796   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
797   // covers all cases so this statement covers most cases and direct object
798   // emission must call setPic() once MCObjectFileInfo has been initialized. The
799   // cases we don't handle here are covered by MipsAsmPrinter.
800   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
801 
802   const FeatureBitset &Features = STI.getFeatureBits();
803 
804   // Set the header flags that we can in the constructor.
805   // FIXME: This is a fairly terrible hack. We set the rest
806   // of these in the destructor. The problem here is two-fold:
807   //
808   // a: Some of the eflags can be set/reset by directives.
809   // b: There aren't any usage paths that initialize the ABI
810   //    pointer until after we initialize either an assembler
811   //    or the target machine.
812   // We can fix this by making the target streamer construct
813   // the ABI, but this is fraught with wide ranging dependency
814   // issues as well.
815   unsigned EFlags = MCA.getELFHeaderEFlags();
816 
817   // FIXME: Fix a dependency issue by instantiating the ABI object to some
818   // default based off the triple. The triple doesn't describe the target
819   // fully, but any external user of the API that uses the MCTargetStreamer
820   // would otherwise crash on assertion failure.
821 
822   ABI = MipsABIInfo(
823       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
824               STI.getTargetTriple().getArch() == Triple::ArchType::mips
825           ? MipsABIInfo::O32()
826           : MipsABIInfo::N64());
827 
828   // Architecture
829   if (Features[Mips::FeatureMips64r6])
830     EFlags |= ELF::EF_MIPS_ARCH_64R6;
831   else if (Features[Mips::FeatureMips64r2] ||
832            Features[Mips::FeatureMips64r3] ||
833            Features[Mips::FeatureMips64r5])
834     EFlags |= ELF::EF_MIPS_ARCH_64R2;
835   else if (Features[Mips::FeatureMips64])
836     EFlags |= ELF::EF_MIPS_ARCH_64;
837   else if (Features[Mips::FeatureMips5])
838     EFlags |= ELF::EF_MIPS_ARCH_5;
839   else if (Features[Mips::FeatureMips4])
840     EFlags |= ELF::EF_MIPS_ARCH_4;
841   else if (Features[Mips::FeatureMips3])
842     EFlags |= ELF::EF_MIPS_ARCH_3;
843   else if (Features[Mips::FeatureMips32r6])
844     EFlags |= ELF::EF_MIPS_ARCH_32R6;
845   else if (Features[Mips::FeatureMips32r2] ||
846            Features[Mips::FeatureMips32r3] ||
847            Features[Mips::FeatureMips32r5])
848     EFlags |= ELF::EF_MIPS_ARCH_32R2;
849   else if (Features[Mips::FeatureMips32])
850     EFlags |= ELF::EF_MIPS_ARCH_32;
851   else if (Features[Mips::FeatureMips2])
852     EFlags |= ELF::EF_MIPS_ARCH_2;
853   else
854     EFlags |= ELF::EF_MIPS_ARCH_1;
855 
856   // Machine
857   if (Features[Mips::FeatureCnMips])
858     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
859 
860   // Other options.
861   if (Features[Mips::FeatureNaN2008])
862     EFlags |= ELF::EF_MIPS_NAN2008;
863 
864   MCA.setELFHeaderEFlags(EFlags);
865 }
866 
867 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
868   auto *Symbol = cast<MCSymbolELF>(S);
869   getStreamer().getAssembler().registerSymbol(*Symbol);
870   uint8_t Type = Symbol->getType();
871   if (Type != ELF::STT_FUNC)
872     return;
873 
874   if (isMicroMipsEnabled())
875     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
876 }
877 
878 void MipsTargetELFStreamer::finish() {
879   MCAssembler &MCA = getStreamer().getAssembler();
880   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
881 
882   // .bss, .text and .data are always at least 16-byte aligned.
883   MCSection &TextSection = *OFI.getTextSection();
884   MCA.registerSection(TextSection);
885   MCSection &DataSection = *OFI.getDataSection();
886   MCA.registerSection(DataSection);
887   MCSection &BSSSection = *OFI.getBSSSection();
888   MCA.registerSection(BSSSection);
889 
890   TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment())));
891   DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment())));
892   BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment())));
893 
894   if (RoundSectionSizes) {
895     // Make sections sizes a multiple of the alignment. This is useful for
896     // verifying the output of IAS against the output of other assemblers but
897     // it's not necessary to produce a correct object and increases section
898     // size.
899     MCStreamer &OS = getStreamer();
900     for (MCSection &S : MCA) {
901       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
902 
903       unsigned Alignment = Section.getAlignment();
904       if (Alignment) {
905         OS.SwitchSection(&Section);
906         if (Section.useCodeAlign())
907           OS.emitCodeAlignment(Alignment, &STI, Alignment);
908         else
909           OS.emitValueToAlignment(Alignment, 0, 1, Alignment);
910       }
911     }
912   }
913 
914   const FeatureBitset &Features = STI.getFeatureBits();
915 
916   // Update e_header flags. See the FIXME and comment above in
917   // the constructor for a full rundown on this.
918   unsigned EFlags = MCA.getELFHeaderEFlags();
919 
920   // ABI
921   // N64 does not require any ABI bits.
922   if (getABI().IsO32())
923     EFlags |= ELF::EF_MIPS_ABI_O32;
924   else if (getABI().IsN32())
925     EFlags |= ELF::EF_MIPS_ABI2;
926 
927   if (Features[Mips::FeatureGP64Bit]) {
928     if (getABI().IsO32())
929       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
930   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
931     EFlags |= ELF::EF_MIPS_32BITMODE;
932 
933   // -mplt is not implemented but we should act as if it was
934   // given.
935   if (!Features[Mips::FeatureNoABICalls])
936     EFlags |= ELF::EF_MIPS_CPIC;
937 
938   if (Pic)
939     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
940 
941   MCA.setELFHeaderEFlags(EFlags);
942 
943   // Emit all the option records.
944   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
945   // .reginfo.
946   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
947   MEF.EmitMipsOptionRecords();
948 
949   emitMipsAbiFlags();
950 }
951 
952 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
953   auto *Symbol = cast<MCSymbolELF>(S);
954   // If on rhs is micromips symbol then mark Symbol as microMips.
955   if (Value->getKind() != MCExpr::SymbolRef)
956     return;
957   const auto &RhsSym = cast<MCSymbolELF>(
958       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
959 
960   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
961     return;
962 
963   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
964 }
965 
966 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
967   return static_cast<MCELFStreamer &>(Streamer);
968 }
969 
970 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
971   MicroMipsEnabled = true;
972   forbidModuleDirective();
973 }
974 
975 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
976   MicroMipsEnabled = false;
977   forbidModuleDirective();
978 }
979 
980 void MipsTargetELFStreamer::setUsesMicroMips() {
981   MCAssembler &MCA = getStreamer().getAssembler();
982   unsigned Flags = MCA.getELFHeaderEFlags();
983   Flags |= ELF::EF_MIPS_MICROMIPS;
984   MCA.setELFHeaderEFlags(Flags);
985 }
986 
987 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
988   MCAssembler &MCA = getStreamer().getAssembler();
989   unsigned Flags = MCA.getELFHeaderEFlags();
990   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
991   MCA.setELFHeaderEFlags(Flags);
992   forbidModuleDirective();
993 }
994 
995 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
996   MCAssembler &MCA = getStreamer().getAssembler();
997   unsigned Flags = MCA.getELFHeaderEFlags();
998   Flags |= ELF::EF_MIPS_NOREORDER;
999   MCA.setELFHeaderEFlags(Flags);
1000   forbidModuleDirective();
1001 }
1002 
1003 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1004   MCAssembler &MCA = getStreamer().getAssembler();
1005   MCContext &Context = MCA.getContext();
1006   MCStreamer &OS = getStreamer();
1007 
1008   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1009 
1010   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1011   const MCSymbolRefExpr *ExprRef =
1012       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
1013 
1014   MCA.registerSection(*Sec);
1015   Sec->setAlignment(Align(4));
1016 
1017   OS.PushSection();
1018 
1019   OS.SwitchSection(Sec);
1020 
1021   OS.emitValueImpl(ExprRef, 4);
1022 
1023   OS.emitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1024   OS.emitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
1025 
1026   OS.emitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1027   OS.emitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
1028 
1029   OS.emitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1030   OS.emitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
1031   OS.emitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
1032 
1033   // The .end directive marks the end of a procedure. Invalidate
1034   // the information gathered up until this point.
1035   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1036 
1037   OS.PopSection();
1038 
1039   // .end also implicitly sets the size.
1040   MCSymbol *CurPCSym = Context.createTempSymbol();
1041   OS.emitLabel(CurPCSym);
1042   const MCExpr *Size = MCBinaryExpr::createSub(
1043       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1044       ExprRef, Context);
1045 
1046   // The ELFObjectWriter can determine the absolute size as it has access to
1047   // the layout information of the assembly file, so a size expression rather
1048   // than an absolute value is ok here.
1049   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1050 }
1051 
1052 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1053   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1054 
1055   // .ent also acts like an implicit '.type symbol, STT_FUNC'
1056   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1057 }
1058 
1059 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1060   MCAssembler &MCA = getStreamer().getAssembler();
1061   unsigned Flags = MCA.getELFHeaderEFlags();
1062   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1063   MCA.setELFHeaderEFlags(Flags);
1064 }
1065 
1066 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1067   MCAssembler &MCA = getStreamer().getAssembler();
1068   unsigned Flags = MCA.getELFHeaderEFlags();
1069   Flags |= ELF::EF_MIPS_NAN2008;
1070   MCA.setELFHeaderEFlags(Flags);
1071 }
1072 
1073 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1074   MCAssembler &MCA = getStreamer().getAssembler();
1075   unsigned Flags = MCA.getELFHeaderEFlags();
1076   Flags &= ~ELF::EF_MIPS_NAN2008;
1077   MCA.setELFHeaderEFlags(Flags);
1078 }
1079 
1080 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1081   MCAssembler &MCA = getStreamer().getAssembler();
1082   unsigned Flags = MCA.getELFHeaderEFlags();
1083   // This option overrides other PIC options like -KPIC.
1084   Pic = false;
1085   Flags &= ~ELF::EF_MIPS_PIC;
1086   MCA.setELFHeaderEFlags(Flags);
1087 }
1088 
1089 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1090   MCAssembler &MCA = getStreamer().getAssembler();
1091   unsigned Flags = MCA.getELFHeaderEFlags();
1092   Pic = true;
1093   // NOTE: We are following the GAS behaviour here which means the directive
1094   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1095   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1096   // EF_MIPS_CPIC to be mutually exclusive.
1097   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1098   MCA.setELFHeaderEFlags(Flags);
1099 }
1100 
1101 void MipsTargetELFStreamer::emitDirectiveInsn() {
1102   MipsTargetStreamer::emitDirectiveInsn();
1103   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1104   MEF.createPendingLabelRelocs();
1105 }
1106 
1107 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1108                                       unsigned ReturnReg_) {
1109   MCContext &Context = getStreamer().getAssembler().getContext();
1110   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1111 
1112   FrameInfoSet = true;
1113   FrameReg = RegInfo->getEncodingValue(StackReg);
1114   FrameOffset = StackSize;
1115   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1116 }
1117 
1118 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1119                                      int CPUTopSavedRegOff) {
1120   GPRInfoSet = true;
1121   GPRBitMask = CPUBitmask;
1122   GPROffset = CPUTopSavedRegOff;
1123 }
1124 
1125 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1126                                       int FPUTopSavedRegOff) {
1127   FPRInfoSet = true;
1128   FPRBitMask = FPUBitmask;
1129   FPROffset = FPUTopSavedRegOff;
1130 }
1131 
1132 void MipsTargetELFStreamer::emitDirectiveCpAdd(unsigned RegNo) {
1133   // .cpadd $reg
1134   // This directive inserts code to add $gp to the argument's register
1135   // when support for position independent code is enabled.
1136   if (!Pic)
1137     return;
1138 
1139   emitAddu(RegNo, RegNo, GPReg, getABI().IsN64(), &STI);
1140   forbidModuleDirective();
1141 }
1142 
1143 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1144   // .cpload $reg
1145   // This directive expands to:
1146   // lui   $gp, %hi(_gp_disp)
1147   // addui $gp, $gp, %lo(_gp_disp)
1148   // addu  $gp, $gp, $reg
1149   // when support for position independent code is enabled.
1150   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1151     return;
1152 
1153   // There's a GNU extension controlled by -mno-shared that allows
1154   // locally-binding symbols to be accessed using absolute addresses.
1155   // This is currently not supported. When supported -mno-shared makes
1156   // .cpload expand to:
1157   //   lui     $gp, %hi(__gnu_local_gp)
1158   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1159 
1160   StringRef SymName("_gp_disp");
1161   MCAssembler &MCA = getStreamer().getAssembler();
1162   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1163   MCA.registerSymbol(*GP_Disp);
1164 
1165   MCInst TmpInst;
1166   TmpInst.setOpcode(Mips::LUi);
1167   TmpInst.addOperand(MCOperand::createReg(GPReg));
1168   const MCExpr *HiSym = MipsMCExpr::create(
1169       MipsMCExpr::MEK_HI,
1170       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1171                               MCA.getContext()),
1172       MCA.getContext());
1173   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1174   getStreamer().emitInstruction(TmpInst, STI);
1175 
1176   TmpInst.clear();
1177 
1178   TmpInst.setOpcode(Mips::ADDiu);
1179   TmpInst.addOperand(MCOperand::createReg(GPReg));
1180   TmpInst.addOperand(MCOperand::createReg(GPReg));
1181   const MCExpr *LoSym = MipsMCExpr::create(
1182       MipsMCExpr::MEK_LO,
1183       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1184                               MCA.getContext()),
1185       MCA.getContext());
1186   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1187   getStreamer().emitInstruction(TmpInst, STI);
1188 
1189   TmpInst.clear();
1190 
1191   TmpInst.setOpcode(Mips::ADDu);
1192   TmpInst.addOperand(MCOperand::createReg(GPReg));
1193   TmpInst.addOperand(MCOperand::createReg(GPReg));
1194   TmpInst.addOperand(MCOperand::createReg(RegNo));
1195   getStreamer().emitInstruction(TmpInst, STI);
1196 
1197   forbidModuleDirective();
1198 }
1199 
1200 void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) {
1201   if (Pic)
1202     MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
1203 }
1204 
1205 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1206     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1207     const MCSubtargetInfo *STI) {
1208   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1209   // .cprestore offset
1210   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1211   // to:
1212   //    sw $gp, offset($sp)
1213   // and adds a corresponding LW after every JAL.
1214 
1215   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1216   // is used in non-PIC mode.
1217   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1218     return true;
1219 
1220   // Store the $gp on the stack.
1221   emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1222                          STI);
1223   return true;
1224 }
1225 
1226 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1227                                                  int RegOrOffset,
1228                                                  const MCSymbol &Sym,
1229                                                  bool IsReg) {
1230   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1231   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1232     return;
1233 
1234   forbidModuleDirective();
1235 
1236   MCAssembler &MCA = getStreamer().getAssembler();
1237   MCInst Inst;
1238 
1239   // Either store the old $gp in a register or on the stack
1240   if (IsReg) {
1241     // move $save, $gpreg
1242     emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1243   } else {
1244     // sd $gpreg, offset($sp)
1245     emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1246   }
1247 
1248   if (getABI().IsN32()) {
1249     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1250     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1251         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1252         MCA.getContext());
1253     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1254         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1255         MCA.getContext());
1256 
1257     // lui $gp, %hi(__gnu_local_gp)
1258     emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1259 
1260     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1261     emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1262             &STI);
1263 
1264     return;
1265   }
1266 
1267   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1268       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1269       MCA.getContext());
1270   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1271       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1272       MCA.getContext());
1273 
1274   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1275   emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1276 
1277   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1278   emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1279           &STI);
1280 
1281   // daddu  $gp, $gp, $funcreg
1282   emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1283 }
1284 
1285 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1286                                                   bool SaveLocationIsRegister) {
1287   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1288   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1289     return;
1290 
1291   MCInst Inst;
1292   // Either restore the old $gp from a register or on the stack
1293   if (SaveLocationIsRegister) {
1294     Inst.setOpcode(Mips::OR);
1295     Inst.addOperand(MCOperand::createReg(GPReg));
1296     Inst.addOperand(MCOperand::createReg(SaveLocation));
1297     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1298   } else {
1299     Inst.setOpcode(Mips::LD);
1300     Inst.addOperand(MCOperand::createReg(GPReg));
1301     Inst.addOperand(MCOperand::createReg(Mips::SP));
1302     Inst.addOperand(MCOperand::createImm(SaveLocation));
1303   }
1304   getStreamer().emitInstruction(Inst, STI);
1305 
1306   forbidModuleDirective();
1307 }
1308 
1309 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1310   MCAssembler &MCA = getStreamer().getAssembler();
1311   MCContext &Context = MCA.getContext();
1312   MCStreamer &OS = getStreamer();
1313   MCSectionELF *Sec = Context.getELFSection(
1314       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24);
1315   MCA.registerSection(*Sec);
1316   Sec->setAlignment(Align(8));
1317   OS.SwitchSection(Sec);
1318 
1319   OS << ABIFlagsSection;
1320 }
1321