1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCTargetDesc.h"
18 #include "MipsTargetObjectFile.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/MC/MCSymbolELF.h"
23 #include "llvm/Support/ELF.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/FormattedStream.h"
26 
27 using namespace llvm;
28 
29 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
30     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
31   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
32 }
33 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
34 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
35 void MipsTargetStreamer::emitDirectiveSetMips16() {}
36 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
37 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
38 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
39 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
40 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
41 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
42 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
43 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
44 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
45   forbidModuleDirective();
46 }
47 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
48 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
49 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
50 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
51 void MipsTargetStreamer::emitDirectiveNaN2008() {}
52 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
53 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
54 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
55 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
56 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
57                                    unsigned ReturnReg) {}
58 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
59 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
60 }
61 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
62   forbidModuleDirective();
63 }
64 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
65 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
66 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
67 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
68 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
69 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
70 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
71 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
72 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
73 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
74 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
75 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
76 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
78 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
80 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
83   forbidModuleDirective();
84 }
85 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
86   forbidModuleDirective();
87 }
88 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
91 void MipsTargetStreamer::emitDirectiveCpRestore(int Offset, unsigned ATReg,
92                                                 SMLoc IDLoc,
93                                                 const MCSubtargetInfo *STI) {
94   forbidModuleDirective();
95 }
96 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
97                                               const MCSymbol &Sym, bool IsReg) {
98 }
99 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
100                                                bool SaveLocationIsRegister) {}
101 
102 void MipsTargetStreamer::emitDirectiveModuleFP() {}
103 
104 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
105   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
106     report_fatal_error("+nooddspreg is only valid for O32");
107 }
108 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
109 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
110 void MipsTargetStreamer::emitDirectiveSetFp(
111     MipsABIFlagsSection::FpABIKind Value) {
112   forbidModuleDirective();
113 }
114 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
115 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
116   forbidModuleDirective();
117 }
118 
119 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
120                                const MCSubtargetInfo *STI) {
121   MCInst TmpInst;
122   TmpInst.setOpcode(Opcode);
123   TmpInst.addOperand(MCOperand::createReg(Reg0));
124   TmpInst.setLoc(IDLoc);
125   getStreamer().EmitInstruction(TmpInst, *STI);
126 }
127 
128 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
129                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
130   MCInst TmpInst;
131   TmpInst.setOpcode(Opcode);
132   TmpInst.addOperand(MCOperand::createReg(Reg0));
133   TmpInst.addOperand(Op1);
134   TmpInst.setLoc(IDLoc);
135   getStreamer().EmitInstruction(TmpInst, *STI);
136 }
137 
138 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
139                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
140   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
141 }
142 
143 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
144                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
145   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
146 }
147 
148 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
149                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
150   MCInst TmpInst;
151   TmpInst.setOpcode(Opcode);
152   TmpInst.addOperand(MCOperand::createImm(Imm1));
153   TmpInst.addOperand(MCOperand::createImm(Imm2));
154   TmpInst.setLoc(IDLoc);
155   getStreamer().EmitInstruction(TmpInst, *STI);
156 }
157 
158 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
159                                  MCOperand Op2, SMLoc IDLoc,
160                                  const MCSubtargetInfo *STI) {
161   MCInst TmpInst;
162   TmpInst.setOpcode(Opcode);
163   TmpInst.addOperand(MCOperand::createReg(Reg0));
164   TmpInst.addOperand(MCOperand::createReg(Reg1));
165   TmpInst.addOperand(Op2);
166   TmpInst.setLoc(IDLoc);
167   getStreamer().EmitInstruction(TmpInst, *STI);
168 }
169 
170 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
171                                  unsigned Reg2, SMLoc IDLoc,
172                                  const MCSubtargetInfo *STI) {
173   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
174 }
175 
176 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
177                                  int16_t Imm, SMLoc IDLoc,
178                                  const MCSubtargetInfo *STI) {
179   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
180 }
181 
182 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
183                                   unsigned TrgReg, bool Is64Bit,
184                                   const MCSubtargetInfo *STI) {
185   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
186           STI);
187 }
188 
189 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
190                                   int16_t ShiftAmount, SMLoc IDLoc,
191                                   const MCSubtargetInfo *STI) {
192   if (ShiftAmount >= 32) {
193     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
194     return;
195   }
196 
197   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
198 }
199 
200 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
201                                             const MCSubtargetInfo *STI) {
202   if (hasShortDelaySlot)
203     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
204   else
205     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
206 }
207 
208 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
209   emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
210 }
211 
212 /// Emit the $gp restore operation for .cprestore.
213 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
214                                        const MCSubtargetInfo *STI) {
215   emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
216                         STI);
217 }
218 
219 /// Emit a store instruction with an immediate offset.
220 void MipsTargetStreamer::emitStoreWithImmOffset(
221     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
222     unsigned ATReg, SMLoc IDLoc, const MCSubtargetInfo *STI) {
223   if (isInt<16>(Offset)) {
224     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
225     return;
226   }
227 
228   // sw $8, offset($8) => lui $at, %hi(offset)
229   //                      add $at, $at, $8
230   //                      sw $8, %lo(offset)($at)
231 
232   unsigned LoOffset = Offset & 0x0000ffff;
233   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
234 
235   // If msb of LoOffset is 1(negative number) we must increment HiOffset
236   // to account for the sign-extension of the low part.
237   if (LoOffset & 0x8000)
238     HiOffset++;
239 
240   // Generate the base address in ATReg.
241   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
242   if (BaseReg != Mips::ZERO)
243     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
244   // Emit the store with the adjusted base and offset.
245   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
246 }
247 
248 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
249 /// out of range for a simm16 will be expanded to appropriate instructions.
250 void MipsTargetStreamer::emitStoreWithSymOffset(
251     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
252     MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
253     const MCSubtargetInfo *STI) {
254   // sw $8, sym => lui $at, %hi(sym)
255   //               sw $8, %lo(sym)($at)
256 
257   // Generate the base address in ATReg.
258   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
259   if (BaseReg != Mips::ZERO)
260     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
261   // Emit the store with the adjusted base and offset.
262   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
263 }
264 
265 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
266 /// permitted to be the same register iff DstReg is distinct from BaseReg and
267 /// DstReg is a GPR. It is the callers responsibility to identify such cases
268 /// and pass the appropriate register in TmpReg.
269 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
270                                                unsigned BaseReg, int64_t Offset,
271                                                unsigned TmpReg, SMLoc IDLoc,
272                                                const MCSubtargetInfo *STI) {
273   if (isInt<16>(Offset)) {
274     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
275     return;
276   }
277 
278   // 1) lw $8, offset($9) => lui $8, %hi(offset)
279   //                         add $8, $8, $9
280   //                         lw $8, %lo(offset)($9)
281   // 2) lw $8, offset($8) => lui $at, %hi(offset)
282   //                         add $at, $at, $8
283   //                         lw $8, %lo(offset)($at)
284 
285   unsigned LoOffset = Offset & 0x0000ffff;
286   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
287 
288   // If msb of LoOffset is 1(negative number) we must increment HiOffset
289   // to account for the sign-extension of the low part.
290   if (LoOffset & 0x8000)
291     HiOffset++;
292 
293   // Generate the base address in TmpReg.
294   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
295   if (BaseReg != Mips::ZERO)
296     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
297   // Emit the load with the adjusted base and offset.
298   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
299 }
300 
301 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
302 /// out of range for a simm16 will be expanded to appropriate instructions.
303 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
304 /// GPR. It is the callers responsibility to identify such cases and pass the
305 /// appropriate register in TmpReg.
306 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
307                                                unsigned BaseReg,
308                                                MCOperand &HiOperand,
309                                                MCOperand &LoOperand,
310                                                unsigned TmpReg, SMLoc IDLoc,
311                                                const MCSubtargetInfo *STI) {
312   // 1) lw $8, sym        => lui $8, %hi(sym)
313   //                         lw $8, %lo(sym)($8)
314   // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
315   //                         ldc1 $f0, %lo(sym)($at)
316 
317   // Generate the base address in TmpReg.
318   emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
319   if (BaseReg != Mips::ZERO)
320     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
321   // Emit the load with the adjusted base and offset.
322   emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
323 }
324 
325 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
326                                              formatted_raw_ostream &OS)
327     : MipsTargetStreamer(S), OS(OS) {}
328 
329 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
330   OS << "\t.set\tmicromips\n";
331   forbidModuleDirective();
332 }
333 
334 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
335   OS << "\t.set\tnomicromips\n";
336   forbidModuleDirective();
337 }
338 
339 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
340   OS << "\t.set\tmips16\n";
341   forbidModuleDirective();
342 }
343 
344 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
345   OS << "\t.set\tnomips16\n";
346   MipsTargetStreamer::emitDirectiveSetNoMips16();
347 }
348 
349 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
350   OS << "\t.set\treorder\n";
351   MipsTargetStreamer::emitDirectiveSetReorder();
352 }
353 
354 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
355   OS << "\t.set\tnoreorder\n";
356   forbidModuleDirective();
357 }
358 
359 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
360   OS << "\t.set\tmacro\n";
361   MipsTargetStreamer::emitDirectiveSetMacro();
362 }
363 
364 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
365   OS << "\t.set\tnomacro\n";
366   MipsTargetStreamer::emitDirectiveSetNoMacro();
367 }
368 
369 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
370   OS << "\t.set\tmsa\n";
371   MipsTargetStreamer::emitDirectiveSetMsa();
372 }
373 
374 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
375   OS << "\t.set\tnomsa\n";
376   MipsTargetStreamer::emitDirectiveSetNoMsa();
377 }
378 
379 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
380   OS << "\t.set\tat\n";
381   MipsTargetStreamer::emitDirectiveSetAt();
382 }
383 
384 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
385   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
386   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
387 }
388 
389 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
390   OS << "\t.set\tnoat\n";
391   MipsTargetStreamer::emitDirectiveSetNoAt();
392 }
393 
394 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
395   OS << "\t.end\t" << Name << '\n';
396 }
397 
398 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
399   OS << "\t.ent\t" << Symbol.getName() << '\n';
400 }
401 
402 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
403 
404 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
405 
406 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
407   OS << "\t.nan\tlegacy\n";
408 }
409 
410 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
411   OS << "\t.option\tpic0\n";
412 }
413 
414 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
415   OS << "\t.option\tpic2\n";
416 }
417 
418 void MipsTargetAsmStreamer::emitDirectiveInsn() {
419   MipsTargetStreamer::emitDirectiveInsn();
420   OS << "\t.insn\n";
421 }
422 
423 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
424                                       unsigned ReturnReg) {
425   OS << "\t.frame\t$"
426      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
427      << StackSize << ",$"
428      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
429 }
430 
431 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
432   OS << "\t.set arch=" << Arch << "\n";
433   MipsTargetStreamer::emitDirectiveSetArch(Arch);
434 }
435 
436 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
437   OS << "\t.set\tmips0\n";
438   MipsTargetStreamer::emitDirectiveSetMips0();
439 }
440 
441 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
442   OS << "\t.set\tmips1\n";
443   MipsTargetStreamer::emitDirectiveSetMips1();
444 }
445 
446 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
447   OS << "\t.set\tmips2\n";
448   MipsTargetStreamer::emitDirectiveSetMips2();
449 }
450 
451 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
452   OS << "\t.set\tmips3\n";
453   MipsTargetStreamer::emitDirectiveSetMips3();
454 }
455 
456 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
457   OS << "\t.set\tmips4\n";
458   MipsTargetStreamer::emitDirectiveSetMips4();
459 }
460 
461 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
462   OS << "\t.set\tmips5\n";
463   MipsTargetStreamer::emitDirectiveSetMips5();
464 }
465 
466 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
467   OS << "\t.set\tmips32\n";
468   MipsTargetStreamer::emitDirectiveSetMips32();
469 }
470 
471 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
472   OS << "\t.set\tmips32r2\n";
473   MipsTargetStreamer::emitDirectiveSetMips32R2();
474 }
475 
476 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
477   OS << "\t.set\tmips32r3\n";
478   MipsTargetStreamer::emitDirectiveSetMips32R3();
479 }
480 
481 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
482   OS << "\t.set\tmips32r5\n";
483   MipsTargetStreamer::emitDirectiveSetMips32R5();
484 }
485 
486 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
487   OS << "\t.set\tmips32r6\n";
488   MipsTargetStreamer::emitDirectiveSetMips32R6();
489 }
490 
491 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
492   OS << "\t.set\tmips64\n";
493   MipsTargetStreamer::emitDirectiveSetMips64();
494 }
495 
496 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
497   OS << "\t.set\tmips64r2\n";
498   MipsTargetStreamer::emitDirectiveSetMips64R2();
499 }
500 
501 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
502   OS << "\t.set\tmips64r3\n";
503   MipsTargetStreamer::emitDirectiveSetMips64R3();
504 }
505 
506 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
507   OS << "\t.set\tmips64r5\n";
508   MipsTargetStreamer::emitDirectiveSetMips64R5();
509 }
510 
511 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
512   OS << "\t.set\tmips64r6\n";
513   MipsTargetStreamer::emitDirectiveSetMips64R6();
514 }
515 
516 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
517   OS << "\t.set\tdsp\n";
518   MipsTargetStreamer::emitDirectiveSetDsp();
519 }
520 
521 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
522   OS << "\t.set\tnodsp\n";
523   MipsTargetStreamer::emitDirectiveSetNoDsp();
524 }
525 
526 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
527   OS << "\t.set\tpop\n";
528   MipsTargetStreamer::emitDirectiveSetPop();
529 }
530 
531 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
532  OS << "\t.set\tpush\n";
533  MipsTargetStreamer::emitDirectiveSetPush();
534 }
535 
536 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
537   OS << "\t.set\tsoftfloat\n";
538   MipsTargetStreamer::emitDirectiveSetSoftFloat();
539 }
540 
541 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
542   OS << "\t.set\thardfloat\n";
543   MipsTargetStreamer::emitDirectiveSetHardFloat();
544 }
545 
546 // Print a 32 bit hex number with all numbers.
547 static void printHex32(unsigned Value, raw_ostream &OS) {
548   OS << "0x";
549   for (int i = 7; i >= 0; i--)
550     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
551 }
552 
553 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
554                                      int CPUTopSavedRegOff) {
555   OS << "\t.mask \t";
556   printHex32(CPUBitmask, OS);
557   OS << ',' << CPUTopSavedRegOff << '\n';
558 }
559 
560 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
561                                       int FPUTopSavedRegOff) {
562   OS << "\t.fmask\t";
563   printHex32(FPUBitmask, OS);
564   OS << "," << FPUTopSavedRegOff << '\n';
565 }
566 
567 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
568   OS << "\t.cpload\t$"
569      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
570   forbidModuleDirective();
571 }
572 
573 void MipsTargetAsmStreamer::emitDirectiveCpRestore(int Offset, unsigned ATReg,
574                                                    SMLoc IDLoc,
575                                                    const MCSubtargetInfo *STI) {
576   MipsTargetStreamer::emitDirectiveCpRestore(Offset, ATReg, IDLoc, STI);
577   OS << "\t.cprestore\t" << Offset << "\n";
578 }
579 
580 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
581                                                  int RegOrOffset,
582                                                  const MCSymbol &Sym,
583                                                  bool IsReg) {
584   OS << "\t.cpsetup\t$"
585      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
586 
587   if (IsReg)
588     OS << "$"
589        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
590   else
591     OS << RegOrOffset;
592 
593   OS << ", ";
594 
595   OS << Sym.getName();
596   forbidModuleDirective();
597 }
598 
599 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
600                                                   bool SaveLocationIsRegister) {
601   OS << "\t.cpreturn";
602   forbidModuleDirective();
603 }
604 
605 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
606   OS << "\t.module\tfp=";
607   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
608 }
609 
610 void MipsTargetAsmStreamer::emitDirectiveSetFp(
611     MipsABIFlagsSection::FpABIKind Value) {
612   MipsTargetStreamer::emitDirectiveSetFp(Value);
613 
614   OS << "\t.set\tfp=";
615   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
616 }
617 
618 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
619   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
620 
621   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
622 }
623 
624 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
625   MipsTargetStreamer::emitDirectiveSetOddSPReg();
626   OS << "\t.set\toddspreg\n";
627 }
628 
629 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
630   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
631   OS << "\t.set\tnooddspreg\n";
632 }
633 
634 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
635   OS << "\t.module\tsoftfloat\n";
636 }
637 
638 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
639   OS << "\t.module\thardfloat\n";
640 }
641 
642 // This part is for ELF object output.
643 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
644                                              const MCSubtargetInfo &STI)
645     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
646   MCAssembler &MCA = getStreamer().getAssembler();
647   Pic = MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
648 
649   const FeatureBitset &Features = STI.getFeatureBits();
650 
651   // Set the header flags that we can in the constructor.
652   // FIXME: This is a fairly terrible hack. We set the rest
653   // of these in the destructor. The problem here is two-fold:
654   //
655   // a: Some of the eflags can be set/reset by directives.
656   // b: There aren't any usage paths that initialize the ABI
657   //    pointer until after we initialize either an assembler
658   //    or the target machine.
659   // We can fix this by making the target streamer construct
660   // the ABI, but this is fraught with wide ranging dependency
661   // issues as well.
662   unsigned EFlags = MCA.getELFHeaderEFlags();
663 
664   // Architecture
665   if (Features[Mips::FeatureMips64r6])
666     EFlags |= ELF::EF_MIPS_ARCH_64R6;
667   else if (Features[Mips::FeatureMips64r2] ||
668            Features[Mips::FeatureMips64r3] ||
669            Features[Mips::FeatureMips64r5])
670     EFlags |= ELF::EF_MIPS_ARCH_64R2;
671   else if (Features[Mips::FeatureMips64])
672     EFlags |= ELF::EF_MIPS_ARCH_64;
673   else if (Features[Mips::FeatureMips5])
674     EFlags |= ELF::EF_MIPS_ARCH_5;
675   else if (Features[Mips::FeatureMips4])
676     EFlags |= ELF::EF_MIPS_ARCH_4;
677   else if (Features[Mips::FeatureMips3])
678     EFlags |= ELF::EF_MIPS_ARCH_3;
679   else if (Features[Mips::FeatureMips32r6])
680     EFlags |= ELF::EF_MIPS_ARCH_32R6;
681   else if (Features[Mips::FeatureMips32r2] ||
682            Features[Mips::FeatureMips32r3] ||
683            Features[Mips::FeatureMips32r5])
684     EFlags |= ELF::EF_MIPS_ARCH_32R2;
685   else if (Features[Mips::FeatureMips32])
686     EFlags |= ELF::EF_MIPS_ARCH_32;
687   else if (Features[Mips::FeatureMips2])
688     EFlags |= ELF::EF_MIPS_ARCH_2;
689   else
690     EFlags |= ELF::EF_MIPS_ARCH_1;
691 
692   // Other options.
693   if (Features[Mips::FeatureNaN2008])
694     EFlags |= ELF::EF_MIPS_NAN2008;
695 
696   // -mabicalls and -mplt are not implemented but we should act as if they were
697   // given.
698   EFlags |= ELF::EF_MIPS_CPIC;
699 
700   MCA.setELFHeaderEFlags(EFlags);
701 }
702 
703 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
704   auto *Symbol = cast<MCSymbolELF>(S);
705   if (!isMicroMipsEnabled())
706     return;
707   getStreamer().getAssembler().registerSymbol(*Symbol);
708   uint8_t Type = Symbol->getType();
709   if (Type != ELF::STT_FUNC)
710     return;
711 
712   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
713 }
714 
715 void MipsTargetELFStreamer::finish() {
716   MCAssembler &MCA = getStreamer().getAssembler();
717   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
718 
719   // .bss, .text and .data are always at least 16-byte aligned.
720   MCSection &TextSection = *OFI.getTextSection();
721   MCA.registerSection(TextSection);
722   MCSection &DataSection = *OFI.getDataSection();
723   MCA.registerSection(DataSection);
724   MCSection &BSSSection = *OFI.getBSSSection();
725   MCA.registerSection(BSSSection);
726 
727   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
728   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
729   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
730 
731   // Make sections sizes a multiple of the alignment.
732   MCStreamer &OS = getStreamer();
733   for (MCSection &S : MCA) {
734     MCSectionELF &Section = static_cast<MCSectionELF &>(S);
735 
736     unsigned Alignment = Section.getAlignment();
737     if (Alignment) {
738       OS.SwitchSection(&Section);
739       if (Section.UseCodeAlign())
740         OS.EmitCodeAlignment(Alignment, Alignment);
741       else
742         OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
743     }
744   }
745 
746   const FeatureBitset &Features = STI.getFeatureBits();
747 
748   // Update e_header flags. See the FIXME and comment above in
749   // the constructor for a full rundown on this.
750   unsigned EFlags = MCA.getELFHeaderEFlags();
751 
752   // ABI
753   // N64 does not require any ABI bits.
754   if (getABI().IsO32())
755     EFlags |= ELF::EF_MIPS_ABI_O32;
756   else if (getABI().IsN32())
757     EFlags |= ELF::EF_MIPS_ABI2;
758 
759   if (Features[Mips::FeatureGP64Bit]) {
760     if (getABI().IsO32())
761       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
762   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
763     EFlags |= ELF::EF_MIPS_32BITMODE;
764 
765   // If we've set the cpic eflag and we're n64, go ahead and set the pic
766   // one as well.
767   if (EFlags & ELF::EF_MIPS_CPIC && getABI().IsN64())
768     EFlags |= ELF::EF_MIPS_PIC;
769 
770   MCA.setELFHeaderEFlags(EFlags);
771 
772   // Emit all the option records.
773   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
774   // .reginfo.
775   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
776   MEF.EmitMipsOptionRecords();
777 
778   emitMipsAbiFlags();
779 }
780 
781 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
782   auto *Symbol = cast<MCSymbolELF>(S);
783   // If on rhs is micromips symbol then mark Symbol as microMips.
784   if (Value->getKind() != MCExpr::SymbolRef)
785     return;
786   const auto &RhsSym = cast<MCSymbolELF>(
787       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
788 
789   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
790     return;
791 
792   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
793 }
794 
795 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
796   return static_cast<MCELFStreamer &>(Streamer);
797 }
798 
799 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
800   MicroMipsEnabled = true;
801 
802   MCAssembler &MCA = getStreamer().getAssembler();
803   unsigned Flags = MCA.getELFHeaderEFlags();
804   Flags |= ELF::EF_MIPS_MICROMIPS;
805   MCA.setELFHeaderEFlags(Flags);
806   forbidModuleDirective();
807 }
808 
809 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
810   MicroMipsEnabled = false;
811   forbidModuleDirective();
812 }
813 
814 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
815   MCAssembler &MCA = getStreamer().getAssembler();
816   unsigned Flags = MCA.getELFHeaderEFlags();
817   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
818   MCA.setELFHeaderEFlags(Flags);
819   forbidModuleDirective();
820 }
821 
822 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
823   MCAssembler &MCA = getStreamer().getAssembler();
824   unsigned Flags = MCA.getELFHeaderEFlags();
825   Flags |= ELF::EF_MIPS_NOREORDER;
826   MCA.setELFHeaderEFlags(Flags);
827   forbidModuleDirective();
828 }
829 
830 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
831   MCAssembler &MCA = getStreamer().getAssembler();
832   MCContext &Context = MCA.getContext();
833   MCStreamer &OS = getStreamer();
834 
835   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
836 
837   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
838   const MCSymbolRefExpr *ExprRef =
839       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
840 
841   MCA.registerSection(*Sec);
842   Sec->setAlignment(4);
843 
844   OS.PushSection();
845 
846   OS.SwitchSection(Sec);
847 
848   OS.EmitValueImpl(ExprRef, 4);
849 
850   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
851   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
852 
853   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
854   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
855 
856   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
857   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
858   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
859 
860   // The .end directive marks the end of a procedure. Invalidate
861   // the information gathered up until this point.
862   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
863 
864   OS.PopSection();
865 
866   // .end also implicitly sets the size.
867   MCSymbol *CurPCSym = Context.createTempSymbol();
868   OS.EmitLabel(CurPCSym);
869   const MCExpr *Size = MCBinaryExpr::createSub(
870       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
871       ExprRef, Context);
872   int64_t AbsSize;
873   if (!Size->evaluateAsAbsolute(AbsSize, MCA))
874     llvm_unreachable("Function size must be evaluatable as absolute");
875   Size = MCConstantExpr::create(AbsSize, Context);
876   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
877 }
878 
879 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
880   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
881 
882   // .ent also acts like an implicit '.type symbol, STT_FUNC'
883   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
884 }
885 
886 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
887   MCAssembler &MCA = getStreamer().getAssembler();
888   unsigned Flags = MCA.getELFHeaderEFlags();
889   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
890   MCA.setELFHeaderEFlags(Flags);
891 }
892 
893 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
894   MCAssembler &MCA = getStreamer().getAssembler();
895   unsigned Flags = MCA.getELFHeaderEFlags();
896   Flags |= ELF::EF_MIPS_NAN2008;
897   MCA.setELFHeaderEFlags(Flags);
898 }
899 
900 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
901   MCAssembler &MCA = getStreamer().getAssembler();
902   unsigned Flags = MCA.getELFHeaderEFlags();
903   Flags &= ~ELF::EF_MIPS_NAN2008;
904   MCA.setELFHeaderEFlags(Flags);
905 }
906 
907 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
908   MCAssembler &MCA = getStreamer().getAssembler();
909   unsigned Flags = MCA.getELFHeaderEFlags();
910   // This option overrides other PIC options like -KPIC.
911   Pic = false;
912   Flags &= ~ELF::EF_MIPS_PIC;
913   MCA.setELFHeaderEFlags(Flags);
914 }
915 
916 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
917   MCAssembler &MCA = getStreamer().getAssembler();
918   unsigned Flags = MCA.getELFHeaderEFlags();
919   Pic = true;
920   // NOTE: We are following the GAS behaviour here which means the directive
921   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
922   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
923   // EF_MIPS_CPIC to be mutually exclusive.
924   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
925   MCA.setELFHeaderEFlags(Flags);
926 }
927 
928 void MipsTargetELFStreamer::emitDirectiveInsn() {
929   MipsTargetStreamer::emitDirectiveInsn();
930   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
931   MEF.createPendingLabelRelocs();
932 }
933 
934 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
935                                       unsigned ReturnReg_) {
936   MCContext &Context = getStreamer().getAssembler().getContext();
937   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
938 
939   FrameInfoSet = true;
940   FrameReg = RegInfo->getEncodingValue(StackReg);
941   FrameOffset = StackSize;
942   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
943 }
944 
945 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
946                                      int CPUTopSavedRegOff) {
947   GPRInfoSet = true;
948   GPRBitMask = CPUBitmask;
949   GPROffset = CPUTopSavedRegOff;
950 }
951 
952 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
953                                       int FPUTopSavedRegOff) {
954   FPRInfoSet = true;
955   FPRBitMask = FPUBitmask;
956   FPROffset = FPUTopSavedRegOff;
957 }
958 
959 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
960   // .cpload $reg
961   // This directive expands to:
962   // lui   $gp, %hi(_gp_disp)
963   // addui $gp, $gp, %lo(_gp_disp)
964   // addu  $gp, $gp, $reg
965   // when support for position independent code is enabled.
966   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
967     return;
968 
969   // There's a GNU extension controlled by -mno-shared that allows
970   // locally-binding symbols to be accessed using absolute addresses.
971   // This is currently not supported. When supported -mno-shared makes
972   // .cpload expand to:
973   //   lui     $gp, %hi(__gnu_local_gp)
974   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
975 
976   StringRef SymName("_gp_disp");
977   MCAssembler &MCA = getStreamer().getAssembler();
978   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
979   MCA.registerSymbol(*GP_Disp);
980 
981   MCInst TmpInst;
982   TmpInst.setOpcode(Mips::LUi);
983   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
984   const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::create(
985       "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
986   TmpInst.addOperand(MCOperand::createExpr(HiSym));
987   getStreamer().EmitInstruction(TmpInst, STI);
988 
989   TmpInst.clear();
990 
991   TmpInst.setOpcode(Mips::ADDiu);
992   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
993   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
994   const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::create(
995       "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
996   TmpInst.addOperand(MCOperand::createExpr(LoSym));
997   getStreamer().EmitInstruction(TmpInst, STI);
998 
999   TmpInst.clear();
1000 
1001   TmpInst.setOpcode(Mips::ADDu);
1002   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1003   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1004   TmpInst.addOperand(MCOperand::createReg(RegNo));
1005   getStreamer().EmitInstruction(TmpInst, STI);
1006 
1007   forbidModuleDirective();
1008 }
1009 
1010 void MipsTargetELFStreamer::emitDirectiveCpRestore(int Offset, unsigned ATReg,
1011                                                    SMLoc IDLoc,
1012                                                    const MCSubtargetInfo *STI) {
1013   MipsTargetStreamer::emitDirectiveCpRestore(Offset, ATReg, IDLoc, STI);
1014   // .cprestore offset
1015   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1016   // to:
1017   //    sw $gp, offset($sp)
1018   // and adds a corresponding LW after every JAL.
1019 
1020   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1021   // is used in non-PIC mode.
1022   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1023     return;
1024 
1025   // Store the $gp on the stack.
1026   emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, ATReg, IDLoc,
1027                          STI);
1028 }
1029 
1030 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1031                                                  int RegOrOffset,
1032                                                  const MCSymbol &Sym,
1033                                                  bool IsReg) {
1034   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1035   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1036     return;
1037 
1038   MCAssembler &MCA = getStreamer().getAssembler();
1039   MCInst Inst;
1040 
1041   // Either store the old $gp in a register or on the stack
1042   if (IsReg) {
1043     // move $save, $gpreg
1044     Inst.setOpcode(Mips::OR64);
1045     Inst.addOperand(MCOperand::createReg(RegOrOffset));
1046     Inst.addOperand(MCOperand::createReg(Mips::GP));
1047     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1048   } else {
1049     // sd $gpreg, offset($sp)
1050     Inst.setOpcode(Mips::SD);
1051     Inst.addOperand(MCOperand::createReg(Mips::GP));
1052     Inst.addOperand(MCOperand::createReg(Mips::SP));
1053     Inst.addOperand(MCOperand::createImm(RegOrOffset));
1054   }
1055   getStreamer().EmitInstruction(Inst, STI);
1056   Inst.clear();
1057 
1058   const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::create(
1059       &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_HI, MCA.getContext());
1060   const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::create(
1061       &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_LO, MCA.getContext());
1062 
1063   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1064   Inst.setOpcode(Mips::LUi);
1065   Inst.addOperand(MCOperand::createReg(Mips::GP));
1066   Inst.addOperand(MCOperand::createExpr(HiExpr));
1067   getStreamer().EmitInstruction(Inst, STI);
1068   Inst.clear();
1069 
1070   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1071   Inst.setOpcode(Mips::ADDiu);
1072   Inst.addOperand(MCOperand::createReg(Mips::GP));
1073   Inst.addOperand(MCOperand::createReg(Mips::GP));
1074   Inst.addOperand(MCOperand::createExpr(LoExpr));
1075   getStreamer().EmitInstruction(Inst, STI);
1076   Inst.clear();
1077 
1078   // daddu  $gp, $gp, $funcreg
1079   Inst.setOpcode(Mips::DADDu);
1080   Inst.addOperand(MCOperand::createReg(Mips::GP));
1081   Inst.addOperand(MCOperand::createReg(Mips::GP));
1082   Inst.addOperand(MCOperand::createReg(RegNo));
1083   getStreamer().EmitInstruction(Inst, STI);
1084 
1085   forbidModuleDirective();
1086 }
1087 
1088 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1089                                                   bool SaveLocationIsRegister) {
1090   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1091   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1092     return;
1093 
1094   MCInst Inst;
1095   // Either restore the old $gp from a register or on the stack
1096   if (SaveLocationIsRegister) {
1097     Inst.setOpcode(Mips::OR);
1098     Inst.addOperand(MCOperand::createReg(Mips::GP));
1099     Inst.addOperand(MCOperand::createReg(SaveLocation));
1100     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1101   } else {
1102     Inst.setOpcode(Mips::LD);
1103     Inst.addOperand(MCOperand::createReg(Mips::GP));
1104     Inst.addOperand(MCOperand::createReg(Mips::SP));
1105     Inst.addOperand(MCOperand::createImm(SaveLocation));
1106   }
1107   getStreamer().EmitInstruction(Inst, STI);
1108 
1109   forbidModuleDirective();
1110 }
1111 
1112 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1113   MCAssembler &MCA = getStreamer().getAssembler();
1114   MCContext &Context = MCA.getContext();
1115   MCStreamer &OS = getStreamer();
1116   MCSectionELF *Sec = Context.getELFSection(
1117       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1118   MCA.registerSection(*Sec);
1119   Sec->setAlignment(8);
1120   OS.SwitchSection(Sec);
1121 
1122   OS << ABIFlagsSection;
1123 }
1124