1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstPrinter/MipsInstPrinter.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsMCTargetDesc.h"
17 #include "MipsTargetObjectFile.h"
18 #include "MipsTargetStreamer.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCSectionELF.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/MC/MCSymbolELF.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ELF.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/FormattedStream.h"
27 
28 using namespace llvm;
29 
30 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
31     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
32   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
33 }
34 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
35 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
36 void MipsTargetStreamer::emitDirectiveSetMips16() {}
37 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
38 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
39 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
40 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
41 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
42 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
43 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
44 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
45 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
46   forbidModuleDirective();
47 }
48 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
49 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
50 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
51 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
52 void MipsTargetStreamer::emitDirectiveNaN2008() {}
53 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
54 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
55 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
56 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
57 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
58                                    unsigned ReturnReg) {}
59 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
60 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
61 }
62 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
63   forbidModuleDirective();
64 }
65 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
66 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
67 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
68 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
69 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
70 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
71 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
72 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
73 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
74 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
75 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
76 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
78 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
80 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
84   forbidModuleDirective();
85 }
86 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
87   forbidModuleDirective();
88 }
89 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
92 void MipsTargetStreamer::emitDirectiveCpRestore(
93     SmallVector<MCInst, 3> &StoreInsts, int Offset) {
94   forbidModuleDirective();
95 }
96 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
97                                               const MCSymbol &Sym, bool IsReg) {
98 }
99 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
100                                                bool SaveLocationIsRegister) {}
101 
102 void MipsTargetStreamer::emitDirectiveModuleFP() {}
103 
104 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
105   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
106     report_fatal_error("+nooddspreg is only valid for O32");
107 }
108 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
109 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
110 void MipsTargetStreamer::emitDirectiveSetFp(
111     MipsABIFlagsSection::FpABIKind Value) {
112   forbidModuleDirective();
113 }
114 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
115 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
116   forbidModuleDirective();
117 }
118 
119 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
120                                              formatted_raw_ostream &OS)
121     : MipsTargetStreamer(S), OS(OS) {}
122 
123 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
124   OS << "\t.set\tmicromips\n";
125   forbidModuleDirective();
126 }
127 
128 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
129   OS << "\t.set\tnomicromips\n";
130   forbidModuleDirective();
131 }
132 
133 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
134   OS << "\t.set\tmips16\n";
135   forbidModuleDirective();
136 }
137 
138 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
139   OS << "\t.set\tnomips16\n";
140   MipsTargetStreamer::emitDirectiveSetNoMips16();
141 }
142 
143 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
144   OS << "\t.set\treorder\n";
145   MipsTargetStreamer::emitDirectiveSetReorder();
146 }
147 
148 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
149   OS << "\t.set\tnoreorder\n";
150   forbidModuleDirective();
151 }
152 
153 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
154   OS << "\t.set\tmacro\n";
155   MipsTargetStreamer::emitDirectiveSetMacro();
156 }
157 
158 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
159   OS << "\t.set\tnomacro\n";
160   MipsTargetStreamer::emitDirectiveSetNoMacro();
161 }
162 
163 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
164   OS << "\t.set\tmsa\n";
165   MipsTargetStreamer::emitDirectiveSetMsa();
166 }
167 
168 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
169   OS << "\t.set\tnomsa\n";
170   MipsTargetStreamer::emitDirectiveSetNoMsa();
171 }
172 
173 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
174   OS << "\t.set\tat\n";
175   MipsTargetStreamer::emitDirectiveSetAt();
176 }
177 
178 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
179   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
180   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
181 }
182 
183 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
184   OS << "\t.set\tnoat\n";
185   MipsTargetStreamer::emitDirectiveSetNoAt();
186 }
187 
188 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
189   OS << "\t.end\t" << Name << '\n';
190 }
191 
192 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
193   OS << "\t.ent\t" << Symbol.getName() << '\n';
194 }
195 
196 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
197 
198 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
199 
200 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
201   OS << "\t.nan\tlegacy\n";
202 }
203 
204 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
205   OS << "\t.option\tpic0\n";
206 }
207 
208 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
209   OS << "\t.option\tpic2\n";
210 }
211 
212 void MipsTargetAsmStreamer::emitDirectiveInsn() {
213   MipsTargetStreamer::emitDirectiveInsn();
214   OS << "\t.insn\n";
215 }
216 
217 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
218                                       unsigned ReturnReg) {
219   OS << "\t.frame\t$"
220      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
221      << StackSize << ",$"
222      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
223 }
224 
225 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
226   OS << "\t.set arch=" << Arch << "\n";
227   MipsTargetStreamer::emitDirectiveSetArch(Arch);
228 }
229 
230 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
231   OS << "\t.set\tmips0\n";
232   MipsTargetStreamer::emitDirectiveSetMips0();
233 }
234 
235 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
236   OS << "\t.set\tmips1\n";
237   MipsTargetStreamer::emitDirectiveSetMips1();
238 }
239 
240 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
241   OS << "\t.set\tmips2\n";
242   MipsTargetStreamer::emitDirectiveSetMips2();
243 }
244 
245 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
246   OS << "\t.set\tmips3\n";
247   MipsTargetStreamer::emitDirectiveSetMips3();
248 }
249 
250 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
251   OS << "\t.set\tmips4\n";
252   MipsTargetStreamer::emitDirectiveSetMips4();
253 }
254 
255 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
256   OS << "\t.set\tmips5\n";
257   MipsTargetStreamer::emitDirectiveSetMips5();
258 }
259 
260 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
261   OS << "\t.set\tmips32\n";
262   MipsTargetStreamer::emitDirectiveSetMips32();
263 }
264 
265 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
266   OS << "\t.set\tmips32r2\n";
267   MipsTargetStreamer::emitDirectiveSetMips32R2();
268 }
269 
270 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
271   OS << "\t.set\tmips32r3\n";
272   MipsTargetStreamer::emitDirectiveSetMips32R3();
273 }
274 
275 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
276   OS << "\t.set\tmips32r5\n";
277   MipsTargetStreamer::emitDirectiveSetMips32R5();
278 }
279 
280 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
281   OS << "\t.set\tmips32r6\n";
282   MipsTargetStreamer::emitDirectiveSetMips32R6();
283 }
284 
285 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
286   OS << "\t.set\tmips64\n";
287   MipsTargetStreamer::emitDirectiveSetMips64();
288 }
289 
290 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
291   OS << "\t.set\tmips64r2\n";
292   MipsTargetStreamer::emitDirectiveSetMips64R2();
293 }
294 
295 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
296   OS << "\t.set\tmips64r3\n";
297   MipsTargetStreamer::emitDirectiveSetMips64R3();
298 }
299 
300 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
301   OS << "\t.set\tmips64r5\n";
302   MipsTargetStreamer::emitDirectiveSetMips64R5();
303 }
304 
305 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
306   OS << "\t.set\tmips64r6\n";
307   MipsTargetStreamer::emitDirectiveSetMips64R6();
308 }
309 
310 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
311   OS << "\t.set\tdsp\n";
312   MipsTargetStreamer::emitDirectiveSetDsp();
313 }
314 
315 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
316   OS << "\t.set\tnodsp\n";
317   MipsTargetStreamer::emitDirectiveSetNoDsp();
318 }
319 
320 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
321   OS << "\t.set\tpop\n";
322   MipsTargetStreamer::emitDirectiveSetPop();
323 }
324 
325 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
326  OS << "\t.set\tpush\n";
327  MipsTargetStreamer::emitDirectiveSetPush();
328 }
329 
330 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
331   OS << "\t.set\tsoftfloat\n";
332   MipsTargetStreamer::emitDirectiveSetSoftFloat();
333 }
334 
335 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
336   OS << "\t.set\thardfloat\n";
337   MipsTargetStreamer::emitDirectiveSetHardFloat();
338 }
339 
340 // Print a 32 bit hex number with all numbers.
341 static void printHex32(unsigned Value, raw_ostream &OS) {
342   OS << "0x";
343   for (int i = 7; i >= 0; i--)
344     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
345 }
346 
347 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
348                                      int CPUTopSavedRegOff) {
349   OS << "\t.mask \t";
350   printHex32(CPUBitmask, OS);
351   OS << ',' << CPUTopSavedRegOff << '\n';
352 }
353 
354 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
355                                       int FPUTopSavedRegOff) {
356   OS << "\t.fmask\t";
357   printHex32(FPUBitmask, OS);
358   OS << "," << FPUTopSavedRegOff << '\n';
359 }
360 
361 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
362   OS << "\t.cpload\t$"
363      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
364   forbidModuleDirective();
365 }
366 
367 void MipsTargetAsmStreamer::emitDirectiveCpRestore(
368     SmallVector<MCInst, 3> &StoreInsts, int Offset) {
369   MipsTargetStreamer::emitDirectiveCpRestore(StoreInsts, Offset);
370   OS << "\t.cprestore\t" << Offset << "\n";
371 }
372 
373 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
374                                                  int RegOrOffset,
375                                                  const MCSymbol &Sym,
376                                                  bool IsReg) {
377   OS << "\t.cpsetup\t$"
378      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
379 
380   if (IsReg)
381     OS << "$"
382        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
383   else
384     OS << RegOrOffset;
385 
386   OS << ", ";
387 
388   OS << Sym.getName();
389   forbidModuleDirective();
390 }
391 
392 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
393                                                   bool SaveLocationIsRegister) {
394   OS << "\t.cpreturn";
395   forbidModuleDirective();
396 }
397 
398 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
399   OS << "\t.module\tfp=";
400   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
401 }
402 
403 void MipsTargetAsmStreamer::emitDirectiveSetFp(
404     MipsABIFlagsSection::FpABIKind Value) {
405   MipsTargetStreamer::emitDirectiveSetFp(Value);
406 
407   OS << "\t.set\tfp=";
408   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
409 }
410 
411 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
412   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
413 
414   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
415 }
416 
417 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
418   MipsTargetStreamer::emitDirectiveSetOddSPReg();
419   OS << "\t.set\toddspreg\n";
420 }
421 
422 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
423   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
424   OS << "\t.set\tnooddspreg\n";
425 }
426 
427 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
428   OS << "\t.module\tsoftfloat\n";
429 }
430 
431 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
432   OS << "\t.module\thardfloat\n";
433 }
434 
435 // This part is for ELF object output.
436 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
437                                              const MCSubtargetInfo &STI)
438     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
439   MCAssembler &MCA = getStreamer().getAssembler();
440   Pic = MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
441 
442   const FeatureBitset &Features = STI.getFeatureBits();
443 
444   // Set the header flags that we can in the constructor.
445   // FIXME: This is a fairly terrible hack. We set the rest
446   // of these in the destructor. The problem here is two-fold:
447   //
448   // a: Some of the eflags can be set/reset by directives.
449   // b: There aren't any usage paths that initialize the ABI
450   //    pointer until after we initialize either an assembler
451   //    or the target machine.
452   // We can fix this by making the target streamer construct
453   // the ABI, but this is fraught with wide ranging dependency
454   // issues as well.
455   unsigned EFlags = MCA.getELFHeaderEFlags();
456 
457   // Architecture
458   if (Features[Mips::FeatureMips64r6])
459     EFlags |= ELF::EF_MIPS_ARCH_64R6;
460   else if (Features[Mips::FeatureMips64r2] ||
461            Features[Mips::FeatureMips64r3] ||
462            Features[Mips::FeatureMips64r5])
463     EFlags |= ELF::EF_MIPS_ARCH_64R2;
464   else if (Features[Mips::FeatureMips64])
465     EFlags |= ELF::EF_MIPS_ARCH_64;
466   else if (Features[Mips::FeatureMips5])
467     EFlags |= ELF::EF_MIPS_ARCH_5;
468   else if (Features[Mips::FeatureMips4])
469     EFlags |= ELF::EF_MIPS_ARCH_4;
470   else if (Features[Mips::FeatureMips3])
471     EFlags |= ELF::EF_MIPS_ARCH_3;
472   else if (Features[Mips::FeatureMips32r6])
473     EFlags |= ELF::EF_MIPS_ARCH_32R6;
474   else if (Features[Mips::FeatureMips32r2] ||
475            Features[Mips::FeatureMips32r3] ||
476            Features[Mips::FeatureMips32r5])
477     EFlags |= ELF::EF_MIPS_ARCH_32R2;
478   else if (Features[Mips::FeatureMips32])
479     EFlags |= ELF::EF_MIPS_ARCH_32;
480   else if (Features[Mips::FeatureMips2])
481     EFlags |= ELF::EF_MIPS_ARCH_2;
482   else
483     EFlags |= ELF::EF_MIPS_ARCH_1;
484 
485   // Other options.
486   if (Features[Mips::FeatureNaN2008])
487     EFlags |= ELF::EF_MIPS_NAN2008;
488 
489   // -mabicalls and -mplt are not implemented but we should act as if they were
490   // given.
491   EFlags |= ELF::EF_MIPS_CPIC;
492 
493   MCA.setELFHeaderEFlags(EFlags);
494 }
495 
496 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
497   auto *Symbol = cast<MCSymbolELF>(S);
498   if (!isMicroMipsEnabled())
499     return;
500   getStreamer().getAssembler().registerSymbol(*Symbol);
501   uint8_t Type = Symbol->getType();
502   if (Type != ELF::STT_FUNC)
503     return;
504 
505   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
506 }
507 
508 void MipsTargetELFStreamer::finish() {
509   MCAssembler &MCA = getStreamer().getAssembler();
510   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
511 
512   // .bss, .text and .data are always at least 16-byte aligned.
513   MCSection &TextSection = *OFI.getTextSection();
514   MCA.registerSection(TextSection);
515   MCSection &DataSection = *OFI.getDataSection();
516   MCA.registerSection(DataSection);
517   MCSection &BSSSection = *OFI.getBSSSection();
518   MCA.registerSection(BSSSection);
519 
520   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
521   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
522   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
523 
524   const FeatureBitset &Features = STI.getFeatureBits();
525 
526   // Update e_header flags. See the FIXME and comment above in
527   // the constructor for a full rundown on this.
528   unsigned EFlags = MCA.getELFHeaderEFlags();
529 
530   // ABI
531   // N64 does not require any ABI bits.
532   if (getABI().IsO32())
533     EFlags |= ELF::EF_MIPS_ABI_O32;
534   else if (getABI().IsN32())
535     EFlags |= ELF::EF_MIPS_ABI2;
536 
537   if (Features[Mips::FeatureGP64Bit]) {
538     if (getABI().IsO32())
539       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
540   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
541     EFlags |= ELF::EF_MIPS_32BITMODE;
542 
543   // If we've set the cpic eflag and we're n64, go ahead and set the pic
544   // one as well.
545   if (EFlags & ELF::EF_MIPS_CPIC && getABI().IsN64())
546     EFlags |= ELF::EF_MIPS_PIC;
547 
548   MCA.setELFHeaderEFlags(EFlags);
549 
550   // Emit all the option records.
551   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
552   // .reginfo.
553   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
554   MEF.EmitMipsOptionRecords();
555 
556   emitMipsAbiFlags();
557 }
558 
559 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
560   auto *Symbol = cast<MCSymbolELF>(S);
561   // If on rhs is micromips symbol then mark Symbol as microMips.
562   if (Value->getKind() != MCExpr::SymbolRef)
563     return;
564   const auto &RhsSym = cast<MCSymbolELF>(
565       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
566 
567   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
568     return;
569 
570   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
571 }
572 
573 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
574   return static_cast<MCELFStreamer &>(Streamer);
575 }
576 
577 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
578   MicroMipsEnabled = true;
579 
580   MCAssembler &MCA = getStreamer().getAssembler();
581   unsigned Flags = MCA.getELFHeaderEFlags();
582   Flags |= ELF::EF_MIPS_MICROMIPS;
583   MCA.setELFHeaderEFlags(Flags);
584   forbidModuleDirective();
585 }
586 
587 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
588   MicroMipsEnabled = false;
589   forbidModuleDirective();
590 }
591 
592 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
593   MCAssembler &MCA = getStreamer().getAssembler();
594   unsigned Flags = MCA.getELFHeaderEFlags();
595   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
596   MCA.setELFHeaderEFlags(Flags);
597   forbidModuleDirective();
598 }
599 
600 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
601   MCAssembler &MCA = getStreamer().getAssembler();
602   unsigned Flags = MCA.getELFHeaderEFlags();
603   Flags |= ELF::EF_MIPS_NOREORDER;
604   MCA.setELFHeaderEFlags(Flags);
605   forbidModuleDirective();
606 }
607 
608 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
609   MCAssembler &MCA = getStreamer().getAssembler();
610   MCContext &Context = MCA.getContext();
611   MCStreamer &OS = getStreamer();
612 
613   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
614 
615   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
616   const MCSymbolRefExpr *ExprRef =
617       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
618 
619   MCA.registerSection(*Sec);
620   Sec->setAlignment(4);
621 
622   OS.PushSection();
623 
624   OS.SwitchSection(Sec);
625 
626   OS.EmitValueImpl(ExprRef, 4);
627 
628   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
629   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
630 
631   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
632   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
633 
634   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
635   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
636   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
637 
638   // The .end directive marks the end of a procedure. Invalidate
639   // the information gathered up until this point.
640   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
641 
642   OS.PopSection();
643 
644   // .end also implicitly sets the size.
645   MCSymbol *CurPCSym = Context.createTempSymbol();
646   OS.EmitLabel(CurPCSym);
647   const MCExpr *Size = MCBinaryExpr::createSub(
648       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
649       ExprRef, Context);
650   int64_t AbsSize;
651   if (!Size->evaluateAsAbsolute(AbsSize, MCA))
652     llvm_unreachable("Function size must be evaluatable as absolute");
653   Size = MCConstantExpr::create(AbsSize, Context);
654   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
655 }
656 
657 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
658   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
659 
660   // .ent also acts like an implicit '.type symbol, STT_FUNC'
661   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
662 }
663 
664 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
665   MCAssembler &MCA = getStreamer().getAssembler();
666   unsigned Flags = MCA.getELFHeaderEFlags();
667   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
668   MCA.setELFHeaderEFlags(Flags);
669 }
670 
671 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
672   MCAssembler &MCA = getStreamer().getAssembler();
673   unsigned Flags = MCA.getELFHeaderEFlags();
674   Flags |= ELF::EF_MIPS_NAN2008;
675   MCA.setELFHeaderEFlags(Flags);
676 }
677 
678 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
679   MCAssembler &MCA = getStreamer().getAssembler();
680   unsigned Flags = MCA.getELFHeaderEFlags();
681   Flags &= ~ELF::EF_MIPS_NAN2008;
682   MCA.setELFHeaderEFlags(Flags);
683 }
684 
685 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
686   MCAssembler &MCA = getStreamer().getAssembler();
687   unsigned Flags = MCA.getELFHeaderEFlags();
688   // This option overrides other PIC options like -KPIC.
689   Pic = false;
690   Flags &= ~ELF::EF_MIPS_PIC;
691   MCA.setELFHeaderEFlags(Flags);
692 }
693 
694 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
695   MCAssembler &MCA = getStreamer().getAssembler();
696   unsigned Flags = MCA.getELFHeaderEFlags();
697   Pic = true;
698   // NOTE: We are following the GAS behaviour here which means the directive
699   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
700   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
701   // EF_MIPS_CPIC to be mutually exclusive.
702   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
703   MCA.setELFHeaderEFlags(Flags);
704 }
705 
706 void MipsTargetELFStreamer::emitDirectiveInsn() {
707   MipsTargetStreamer::emitDirectiveInsn();
708   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
709   MEF.createPendingLabelRelocs();
710 }
711 
712 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
713                                       unsigned ReturnReg_) {
714   MCContext &Context = getStreamer().getAssembler().getContext();
715   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
716 
717   FrameInfoSet = true;
718   FrameReg = RegInfo->getEncodingValue(StackReg);
719   FrameOffset = StackSize;
720   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
721 }
722 
723 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
724                                      int CPUTopSavedRegOff) {
725   GPRInfoSet = true;
726   GPRBitMask = CPUBitmask;
727   GPROffset = CPUTopSavedRegOff;
728 }
729 
730 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
731                                       int FPUTopSavedRegOff) {
732   FPRInfoSet = true;
733   FPRBitMask = FPUBitmask;
734   FPROffset = FPUTopSavedRegOff;
735 }
736 
737 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
738   // .cpload $reg
739   // This directive expands to:
740   // lui   $gp, %hi(_gp_disp)
741   // addui $gp, $gp, %lo(_gp_disp)
742   // addu  $gp, $gp, $reg
743   // when support for position independent code is enabled.
744   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
745     return;
746 
747   // There's a GNU extension controlled by -mno-shared that allows
748   // locally-binding symbols to be accessed using absolute addresses.
749   // This is currently not supported. When supported -mno-shared makes
750   // .cpload expand to:
751   //   lui     $gp, %hi(__gnu_local_gp)
752   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
753 
754   StringRef SymName("_gp_disp");
755   MCAssembler &MCA = getStreamer().getAssembler();
756   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
757   MCA.registerSymbol(*GP_Disp);
758 
759   MCInst TmpInst;
760   TmpInst.setOpcode(Mips::LUi);
761   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
762   const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::create(
763       "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
764   TmpInst.addOperand(MCOperand::createExpr(HiSym));
765   getStreamer().EmitInstruction(TmpInst, STI);
766 
767   TmpInst.clear();
768 
769   TmpInst.setOpcode(Mips::ADDiu);
770   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
771   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
772   const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::create(
773       "_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
774   TmpInst.addOperand(MCOperand::createExpr(LoSym));
775   getStreamer().EmitInstruction(TmpInst, STI);
776 
777   TmpInst.clear();
778 
779   TmpInst.setOpcode(Mips::ADDu);
780   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
781   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
782   TmpInst.addOperand(MCOperand::createReg(RegNo));
783   getStreamer().EmitInstruction(TmpInst, STI);
784 
785   forbidModuleDirective();
786 }
787 
788 void MipsTargetELFStreamer::emitDirectiveCpRestore(
789     SmallVector<MCInst, 3> &StoreInsts, int Offset) {
790   MipsTargetStreamer::emitDirectiveCpRestore(StoreInsts, Offset);
791   // .cprestore offset
792   // When PIC mode is enabled and the O32 ABI is used, this directive expands
793   // to:
794   //    sw $gp, offset($sp)
795   // and adds a corresponding LW after every JAL.
796 
797   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
798   // is used in non-PIC mode.
799   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
800     return;
801 
802   for (const MCInst &Inst : StoreInsts)
803     getStreamer().EmitInstruction(Inst, STI);
804 }
805 
806 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
807                                                  int RegOrOffset,
808                                                  const MCSymbol &Sym,
809                                                  bool IsReg) {
810   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
811   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
812     return;
813 
814   MCAssembler &MCA = getStreamer().getAssembler();
815   MCInst Inst;
816 
817   // Either store the old $gp in a register or on the stack
818   if (IsReg) {
819     // move $save, $gpreg
820     Inst.setOpcode(Mips::OR64);
821     Inst.addOperand(MCOperand::createReg(RegOrOffset));
822     Inst.addOperand(MCOperand::createReg(Mips::GP));
823     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
824   } else {
825     // sd $gpreg, offset($sp)
826     Inst.setOpcode(Mips::SD);
827     Inst.addOperand(MCOperand::createReg(Mips::GP));
828     Inst.addOperand(MCOperand::createReg(Mips::SP));
829     Inst.addOperand(MCOperand::createImm(RegOrOffset));
830   }
831   getStreamer().EmitInstruction(Inst, STI);
832   Inst.clear();
833 
834   const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::create(
835       &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_HI, MCA.getContext());
836   const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::create(
837       &Sym, MCSymbolRefExpr::VK_Mips_GPOFF_LO, MCA.getContext());
838 
839   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
840   Inst.setOpcode(Mips::LUi);
841   Inst.addOperand(MCOperand::createReg(Mips::GP));
842   Inst.addOperand(MCOperand::createExpr(HiExpr));
843   getStreamer().EmitInstruction(Inst, STI);
844   Inst.clear();
845 
846   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
847   Inst.setOpcode(Mips::ADDiu);
848   Inst.addOperand(MCOperand::createReg(Mips::GP));
849   Inst.addOperand(MCOperand::createReg(Mips::GP));
850   Inst.addOperand(MCOperand::createExpr(LoExpr));
851   getStreamer().EmitInstruction(Inst, STI);
852   Inst.clear();
853 
854   // daddu  $gp, $gp, $funcreg
855   Inst.setOpcode(Mips::DADDu);
856   Inst.addOperand(MCOperand::createReg(Mips::GP));
857   Inst.addOperand(MCOperand::createReg(Mips::GP));
858   Inst.addOperand(MCOperand::createReg(RegNo));
859   getStreamer().EmitInstruction(Inst, STI);
860 
861   forbidModuleDirective();
862 }
863 
864 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
865                                                   bool SaveLocationIsRegister) {
866   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
867   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
868     return;
869 
870   MCInst Inst;
871   // Either restore the old $gp from a register or on the stack
872   if (SaveLocationIsRegister) {
873     Inst.setOpcode(Mips::OR);
874     Inst.addOperand(MCOperand::createReg(Mips::GP));
875     Inst.addOperand(MCOperand::createReg(SaveLocation));
876     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
877   } else {
878     Inst.setOpcode(Mips::LD);
879     Inst.addOperand(MCOperand::createReg(Mips::GP));
880     Inst.addOperand(MCOperand::createReg(Mips::SP));
881     Inst.addOperand(MCOperand::createImm(SaveLocation));
882   }
883   getStreamer().EmitInstruction(Inst, STI);
884 
885   forbidModuleDirective();
886 }
887 
888 void MipsTargetELFStreamer::emitMipsAbiFlags() {
889   MCAssembler &MCA = getStreamer().getAssembler();
890   MCContext &Context = MCA.getContext();
891   MCStreamer &OS = getStreamer();
892   MCSectionELF *Sec = Context.getELFSection(
893       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
894   MCA.registerSection(*Sec);
895   Sec->setAlignment(8);
896   OS.SwitchSection(Sec);
897 
898   OS << ABIFlagsSection;
899 }
900