1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Mips specific target streamer methods.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetStreamer.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsABIInfo.h"
17 #include "MipsELFStreamer.h"
18 #include "MipsMCExpr.h"
19 #include "MipsMCTargetDesc.h"
20 #include "MipsTargetObjectFile.h"
21 #include "llvm/BinaryFormat/ELF.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 static cl::opt<bool> RoundSectionSizes(
34     "mips-round-section-sizes", cl::init(false),
35     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
36 } // end anonymous namespace
37 
38 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
39     : MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
40   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
41 }
42 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
43 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
44 void MipsTargetStreamer::setUsesMicroMips() {}
45 void MipsTargetStreamer::emitDirectiveSetMips16() {}
46 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
47 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
48 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
49 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
50 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
51 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
52 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
53 void MipsTargetStreamer::emitDirectiveSetMt() {}
54 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
55 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
56 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
57   forbidModuleDirective();
58 }
59 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
60 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
61 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
62 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
63 void MipsTargetStreamer::emitDirectiveNaN2008() {}
64 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
65 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
66 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
67 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
68 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
69                                    unsigned ReturnReg) {}
70 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
71 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
72 }
73 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
74   forbidModuleDirective();
75 }
76 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
77 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
78 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
79 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
80 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
81 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
82 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
83 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
84 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
85 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
86 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
87 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
88 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
89 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
90 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
91 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
92 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
93 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
94 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
95   forbidModuleDirective();
96 }
97 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
98   forbidModuleDirective();
99 }
100 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
101 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
102 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
103 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
104 bool MipsTargetStreamer::emitDirectiveCpRestore(
105     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
106     const MCSubtargetInfo *STI) {
107   forbidModuleDirective();
108   return true;
109 }
110 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
111                                               const MCSymbol &Sym, bool IsReg) {
112 }
113 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
114                                                bool SaveLocationIsRegister) {}
115 
116 void MipsTargetStreamer::emitDirectiveModuleFP() {}
117 
118 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
119   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
120     report_fatal_error("+nooddspreg is only valid for O32");
121 }
122 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
123 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
124 void MipsTargetStreamer::emitDirectiveModuleMT() {}
125 void MipsTargetStreamer::emitDirectiveSetFp(
126     MipsABIFlagsSection::FpABIKind Value) {
127   forbidModuleDirective();
128 }
129 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
130 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
131   forbidModuleDirective();
132 }
133 
134 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
135                                const MCSubtargetInfo *STI) {
136   MCInst TmpInst;
137   TmpInst.setOpcode(Opcode);
138   TmpInst.addOperand(MCOperand::createReg(Reg0));
139   TmpInst.setLoc(IDLoc);
140   getStreamer().EmitInstruction(TmpInst, *STI);
141 }
142 
143 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
144                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
145   MCInst TmpInst;
146   TmpInst.setOpcode(Opcode);
147   TmpInst.addOperand(MCOperand::createReg(Reg0));
148   TmpInst.addOperand(Op1);
149   TmpInst.setLoc(IDLoc);
150   getStreamer().EmitInstruction(TmpInst, *STI);
151 }
152 
153 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
154                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
155   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
156 }
157 
158 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
159                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
160   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
161 }
162 
163 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
164                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
165   MCInst TmpInst;
166   TmpInst.setOpcode(Opcode);
167   TmpInst.addOperand(MCOperand::createImm(Imm1));
168   TmpInst.addOperand(MCOperand::createImm(Imm2));
169   TmpInst.setLoc(IDLoc);
170   getStreamer().EmitInstruction(TmpInst, *STI);
171 }
172 
173 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
174                                  MCOperand Op2, SMLoc IDLoc,
175                                  const MCSubtargetInfo *STI) {
176   MCInst TmpInst;
177   TmpInst.setOpcode(Opcode);
178   TmpInst.addOperand(MCOperand::createReg(Reg0));
179   TmpInst.addOperand(MCOperand::createReg(Reg1));
180   TmpInst.addOperand(Op2);
181   TmpInst.setLoc(IDLoc);
182   getStreamer().EmitInstruction(TmpInst, *STI);
183 }
184 
185 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
186                                  unsigned Reg2, SMLoc IDLoc,
187                                  const MCSubtargetInfo *STI) {
188   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
189 }
190 
191 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
192                                  int16_t Imm, SMLoc IDLoc,
193                                  const MCSubtargetInfo *STI) {
194   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
195 }
196 
197 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
198                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
199                                    int16_t Imm2, SMLoc IDLoc,
200                                    const MCSubtargetInfo *STI) {
201   MCInst TmpInst;
202   TmpInst.setOpcode(Opcode);
203   TmpInst.addOperand(MCOperand::createReg(Reg0));
204   TmpInst.addOperand(MCOperand::createReg(Reg1));
205   TmpInst.addOperand(MCOperand::createImm(Imm0));
206   TmpInst.addOperand(MCOperand::createImm(Imm1));
207   TmpInst.addOperand(MCOperand::createImm(Imm2));
208   TmpInst.setLoc(IDLoc);
209   getStreamer().EmitInstruction(TmpInst, *STI);
210 }
211 
212 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
213                                   unsigned TrgReg, bool Is64Bit,
214                                   const MCSubtargetInfo *STI) {
215   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
216           STI);
217 }
218 
219 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
220                                   int16_t ShiftAmount, SMLoc IDLoc,
221                                   const MCSubtargetInfo *STI) {
222   if (ShiftAmount >= 32) {
223     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
224     return;
225   }
226 
227   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
228 }
229 
230 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
231                                             const MCSubtargetInfo *STI) {
232   if (hasShortDelaySlot)
233     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
234   else
235     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
236 }
237 
238 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
239   emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
240 }
241 
242 /// Emit the $gp restore operation for .cprestore.
243 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
244                                        const MCSubtargetInfo *STI) {
245   emitLoadWithImmOffset(Mips::LW, Mips::GP, Mips::SP, Offset, Mips::GP, IDLoc,
246                         STI);
247 }
248 
249 /// Emit a store instruction with an immediate offset.
250 void MipsTargetStreamer::emitStoreWithImmOffset(
251     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
252     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
253     const MCSubtargetInfo *STI) {
254   if (isInt<16>(Offset)) {
255     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
256     return;
257   }
258 
259   // sw $8, offset($8) => lui $at, %hi(offset)
260   //                      add $at, $at, $8
261   //                      sw $8, %lo(offset)($at)
262 
263   unsigned ATReg = GetATReg();
264   if (!ATReg)
265     return;
266 
267   unsigned LoOffset = Offset & 0x0000ffff;
268   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
269 
270   // If msb of LoOffset is 1(negative number) we must increment HiOffset
271   // to account for the sign-extension of the low part.
272   if (LoOffset & 0x8000)
273     HiOffset++;
274 
275   // Generate the base address in ATReg.
276   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
277   if (BaseReg != Mips::ZERO)
278     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
279   // Emit the store with the adjusted base and offset.
280   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
281 }
282 
283 /// Emit a store instruction with an symbol offset. Symbols are assumed to be
284 /// out of range for a simm16 will be expanded to appropriate instructions.
285 void MipsTargetStreamer::emitStoreWithSymOffset(
286     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, MCOperand &HiOperand,
287     MCOperand &LoOperand, unsigned ATReg, SMLoc IDLoc,
288     const MCSubtargetInfo *STI) {
289   // sw $8, sym => lui $at, %hi(sym)
290   //               sw $8, %lo(sym)($at)
291 
292   // Generate the base address in ATReg.
293   emitRX(Mips::LUi, ATReg, HiOperand, IDLoc, STI);
294   if (BaseReg != Mips::ZERO)
295     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
296   // Emit the store with the adjusted base and offset.
297   emitRRX(Opcode, SrcReg, ATReg, LoOperand, IDLoc, STI);
298 }
299 
300 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
301 /// permitted to be the same register iff DstReg is distinct from BaseReg and
302 /// DstReg is a GPR. It is the callers responsibility to identify such cases
303 /// and pass the appropriate register in TmpReg.
304 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
305                                                unsigned BaseReg, int64_t Offset,
306                                                unsigned TmpReg, SMLoc IDLoc,
307                                                const MCSubtargetInfo *STI) {
308   if (isInt<16>(Offset)) {
309     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
310     return;
311   }
312 
313   // 1) lw $8, offset($9) => lui $8, %hi(offset)
314   //                         add $8, $8, $9
315   //                         lw $8, %lo(offset)($9)
316   // 2) lw $8, offset($8) => lui $at, %hi(offset)
317   //                         add $at, $at, $8
318   //                         lw $8, %lo(offset)($at)
319 
320   unsigned LoOffset = Offset & 0x0000ffff;
321   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
322 
323   // If msb of LoOffset is 1(negative number) we must increment HiOffset
324   // to account for the sign-extension of the low part.
325   if (LoOffset & 0x8000)
326     HiOffset++;
327 
328   // Generate the base address in TmpReg.
329   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
330   if (BaseReg != Mips::ZERO)
331     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
332   // Emit the load with the adjusted base and offset.
333   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
334 }
335 
336 /// Emit a load instruction with an symbol offset. Symbols are assumed to be
337 /// out of range for a simm16 will be expanded to appropriate instructions.
338 /// DstReg and TmpReg are permitted to be the same register iff DstReg is a
339 /// GPR. It is the callers responsibility to identify such cases and pass the
340 /// appropriate register in TmpReg.
341 void MipsTargetStreamer::emitLoadWithSymOffset(unsigned Opcode, unsigned DstReg,
342                                                unsigned BaseReg,
343                                                MCOperand &HiOperand,
344                                                MCOperand &LoOperand,
345                                                unsigned TmpReg, SMLoc IDLoc,
346                                                const MCSubtargetInfo *STI) {
347   // 1) lw $8, sym        => lui $8, %hi(sym)
348   //                         lw $8, %lo(sym)($8)
349   // 2) ldc1 $f0, sym     => lui $at, %hi(sym)
350   //                         ldc1 $f0, %lo(sym)($at)
351 
352   // Generate the base address in TmpReg.
353   emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
354   if (BaseReg != Mips::ZERO)
355     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
356   // Emit the load with the adjusted base and offset.
357   emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI);
358 }
359 
360 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
361                                              formatted_raw_ostream &OS)
362     : MipsTargetStreamer(S), OS(OS) {}
363 
364 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
365   OS << "\t.set\tmicromips\n";
366   forbidModuleDirective();
367 }
368 
369 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
370   OS << "\t.set\tnomicromips\n";
371   forbidModuleDirective();
372 }
373 
374 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
375   OS << "\t.set\tmips16\n";
376   forbidModuleDirective();
377 }
378 
379 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
380   OS << "\t.set\tnomips16\n";
381   MipsTargetStreamer::emitDirectiveSetNoMips16();
382 }
383 
384 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
385   OS << "\t.set\treorder\n";
386   MipsTargetStreamer::emitDirectiveSetReorder();
387 }
388 
389 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
390   OS << "\t.set\tnoreorder\n";
391   forbidModuleDirective();
392 }
393 
394 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
395   OS << "\t.set\tmacro\n";
396   MipsTargetStreamer::emitDirectiveSetMacro();
397 }
398 
399 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
400   OS << "\t.set\tnomacro\n";
401   MipsTargetStreamer::emitDirectiveSetNoMacro();
402 }
403 
404 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
405   OS << "\t.set\tmsa\n";
406   MipsTargetStreamer::emitDirectiveSetMsa();
407 }
408 
409 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
410   OS << "\t.set\tnomsa\n";
411   MipsTargetStreamer::emitDirectiveSetNoMsa();
412 }
413 
414 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
415   OS << "\t.set\tmt\n";
416   MipsTargetStreamer::emitDirectiveSetMt();
417 }
418 
419 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
420   OS << "\t.set\tnomt\n";
421   MipsTargetStreamer::emitDirectiveSetNoMt();
422 }
423 
424 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
425   OS << "\t.set\tat\n";
426   MipsTargetStreamer::emitDirectiveSetAt();
427 }
428 
429 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
430   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
431   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
432 }
433 
434 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
435   OS << "\t.set\tnoat\n";
436   MipsTargetStreamer::emitDirectiveSetNoAt();
437 }
438 
439 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
440   OS << "\t.end\t" << Name << '\n';
441 }
442 
443 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
444   OS << "\t.ent\t" << Symbol.getName() << '\n';
445 }
446 
447 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
448 
449 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
450 
451 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
452   OS << "\t.nan\tlegacy\n";
453 }
454 
455 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
456   OS << "\t.option\tpic0\n";
457 }
458 
459 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
460   OS << "\t.option\tpic2\n";
461 }
462 
463 void MipsTargetAsmStreamer::emitDirectiveInsn() {
464   MipsTargetStreamer::emitDirectiveInsn();
465   OS << "\t.insn\n";
466 }
467 
468 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
469                                       unsigned ReturnReg) {
470   OS << "\t.frame\t$"
471      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
472      << StackSize << ",$"
473      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
474 }
475 
476 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
477   OS << "\t.set arch=" << Arch << "\n";
478   MipsTargetStreamer::emitDirectiveSetArch(Arch);
479 }
480 
481 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
482   OS << "\t.set\tmips0\n";
483   MipsTargetStreamer::emitDirectiveSetMips0();
484 }
485 
486 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
487   OS << "\t.set\tmips1\n";
488   MipsTargetStreamer::emitDirectiveSetMips1();
489 }
490 
491 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
492   OS << "\t.set\tmips2\n";
493   MipsTargetStreamer::emitDirectiveSetMips2();
494 }
495 
496 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
497   OS << "\t.set\tmips3\n";
498   MipsTargetStreamer::emitDirectiveSetMips3();
499 }
500 
501 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
502   OS << "\t.set\tmips4\n";
503   MipsTargetStreamer::emitDirectiveSetMips4();
504 }
505 
506 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
507   OS << "\t.set\tmips5\n";
508   MipsTargetStreamer::emitDirectiveSetMips5();
509 }
510 
511 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
512   OS << "\t.set\tmips32\n";
513   MipsTargetStreamer::emitDirectiveSetMips32();
514 }
515 
516 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
517   OS << "\t.set\tmips32r2\n";
518   MipsTargetStreamer::emitDirectiveSetMips32R2();
519 }
520 
521 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
522   OS << "\t.set\tmips32r3\n";
523   MipsTargetStreamer::emitDirectiveSetMips32R3();
524 }
525 
526 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
527   OS << "\t.set\tmips32r5\n";
528   MipsTargetStreamer::emitDirectiveSetMips32R5();
529 }
530 
531 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
532   OS << "\t.set\tmips32r6\n";
533   MipsTargetStreamer::emitDirectiveSetMips32R6();
534 }
535 
536 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
537   OS << "\t.set\tmips64\n";
538   MipsTargetStreamer::emitDirectiveSetMips64();
539 }
540 
541 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
542   OS << "\t.set\tmips64r2\n";
543   MipsTargetStreamer::emitDirectiveSetMips64R2();
544 }
545 
546 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
547   OS << "\t.set\tmips64r3\n";
548   MipsTargetStreamer::emitDirectiveSetMips64R3();
549 }
550 
551 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
552   OS << "\t.set\tmips64r5\n";
553   MipsTargetStreamer::emitDirectiveSetMips64R5();
554 }
555 
556 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
557   OS << "\t.set\tmips64r6\n";
558   MipsTargetStreamer::emitDirectiveSetMips64R6();
559 }
560 
561 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
562   OS << "\t.set\tdsp\n";
563   MipsTargetStreamer::emitDirectiveSetDsp();
564 }
565 
566 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
567   OS << "\t.set\tdspr2\n";
568   MipsTargetStreamer::emitDirectiveSetDspr2();
569 }
570 
571 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
572   OS << "\t.set\tnodsp\n";
573   MipsTargetStreamer::emitDirectiveSetNoDsp();
574 }
575 
576 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
577   OS << "\t.set\tpop\n";
578   MipsTargetStreamer::emitDirectiveSetPop();
579 }
580 
581 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
582  OS << "\t.set\tpush\n";
583  MipsTargetStreamer::emitDirectiveSetPush();
584 }
585 
586 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
587   OS << "\t.set\tsoftfloat\n";
588   MipsTargetStreamer::emitDirectiveSetSoftFloat();
589 }
590 
591 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
592   OS << "\t.set\thardfloat\n";
593   MipsTargetStreamer::emitDirectiveSetHardFloat();
594 }
595 
596 // Print a 32 bit hex number with all numbers.
597 static void printHex32(unsigned Value, raw_ostream &OS) {
598   OS << "0x";
599   for (int i = 7; i >= 0; i--)
600     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
601 }
602 
603 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
604                                      int CPUTopSavedRegOff) {
605   OS << "\t.mask \t";
606   printHex32(CPUBitmask, OS);
607   OS << ',' << CPUTopSavedRegOff << '\n';
608 }
609 
610 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
611                                       int FPUTopSavedRegOff) {
612   OS << "\t.fmask\t";
613   printHex32(FPUBitmask, OS);
614   OS << "," << FPUTopSavedRegOff << '\n';
615 }
616 
617 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
618   OS << "\t.cpload\t$"
619      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
620   forbidModuleDirective();
621 }
622 
623 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
624     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
625     const MCSubtargetInfo *STI) {
626   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
627   OS << "\t.cprestore\t" << Offset << "\n";
628   return true;
629 }
630 
631 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
632                                                  int RegOrOffset,
633                                                  const MCSymbol &Sym,
634                                                  bool IsReg) {
635   OS << "\t.cpsetup\t$"
636      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
637 
638   if (IsReg)
639     OS << "$"
640        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
641   else
642     OS << RegOrOffset;
643 
644   OS << ", ";
645 
646   OS << Sym.getName();
647   forbidModuleDirective();
648 }
649 
650 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
651                                                   bool SaveLocationIsRegister) {
652   OS << "\t.cpreturn";
653   forbidModuleDirective();
654 }
655 
656 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
657   OS << "\t.module\tfp=";
658   OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
659 }
660 
661 void MipsTargetAsmStreamer::emitDirectiveSetFp(
662     MipsABIFlagsSection::FpABIKind Value) {
663   MipsTargetStreamer::emitDirectiveSetFp(Value);
664 
665   OS << "\t.set\tfp=";
666   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
667 }
668 
669 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
670   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
671 
672   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
673 }
674 
675 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
676   MipsTargetStreamer::emitDirectiveSetOddSPReg();
677   OS << "\t.set\toddspreg\n";
678 }
679 
680 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
681   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
682   OS << "\t.set\tnooddspreg\n";
683 }
684 
685 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
686   OS << "\t.module\tsoftfloat\n";
687 }
688 
689 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
690   OS << "\t.module\thardfloat\n";
691 }
692 
693 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
694   OS << "\t.module\tmt\n";
695 }
696 
697 // This part is for ELF object output.
698 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
699                                              const MCSubtargetInfo &STI)
700     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
701   MCAssembler &MCA = getStreamer().getAssembler();
702 
703   // It's possible that MCObjectFileInfo isn't fully initialized at this point
704   // due to an initialization order problem where LLVMTargetMachine creates the
705   // target streamer before TargetLoweringObjectFile calls
706   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
707   // covers all cases so this statement covers most cases and direct object
708   // emission must call setPic() once MCObjectFileInfo has been initialized. The
709   // cases we don't handle here are covered by MipsAsmPrinter.
710   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
711 
712   const FeatureBitset &Features = STI.getFeatureBits();
713 
714   // Set the header flags that we can in the constructor.
715   // FIXME: This is a fairly terrible hack. We set the rest
716   // of these in the destructor. The problem here is two-fold:
717   //
718   // a: Some of the eflags can be set/reset by directives.
719   // b: There aren't any usage paths that initialize the ABI
720   //    pointer until after we initialize either an assembler
721   //    or the target machine.
722   // We can fix this by making the target streamer construct
723   // the ABI, but this is fraught with wide ranging dependency
724   // issues as well.
725   unsigned EFlags = MCA.getELFHeaderEFlags();
726 
727   // FIXME: Fix a dependency issue by instantiating the ABI object to some
728   // default based off the triple. The triple doesn't describe the target
729   // fully, but any external user of the API that uses the MCTargetStreamer
730   // would otherwise crash on assertion failure.
731 
732   ABI = MipsABIInfo(
733       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
734               STI.getTargetTriple().getArch() == Triple::ArchType::mips
735           ? MipsABIInfo::O32()
736           : MipsABIInfo::N64());
737 
738   // Architecture
739   if (Features[Mips::FeatureMips64r6])
740     EFlags |= ELF::EF_MIPS_ARCH_64R6;
741   else if (Features[Mips::FeatureMips64r2] ||
742            Features[Mips::FeatureMips64r3] ||
743            Features[Mips::FeatureMips64r5])
744     EFlags |= ELF::EF_MIPS_ARCH_64R2;
745   else if (Features[Mips::FeatureMips64])
746     EFlags |= ELF::EF_MIPS_ARCH_64;
747   else if (Features[Mips::FeatureMips5])
748     EFlags |= ELF::EF_MIPS_ARCH_5;
749   else if (Features[Mips::FeatureMips4])
750     EFlags |= ELF::EF_MIPS_ARCH_4;
751   else if (Features[Mips::FeatureMips3])
752     EFlags |= ELF::EF_MIPS_ARCH_3;
753   else if (Features[Mips::FeatureMips32r6])
754     EFlags |= ELF::EF_MIPS_ARCH_32R6;
755   else if (Features[Mips::FeatureMips32r2] ||
756            Features[Mips::FeatureMips32r3] ||
757            Features[Mips::FeatureMips32r5])
758     EFlags |= ELF::EF_MIPS_ARCH_32R2;
759   else if (Features[Mips::FeatureMips32])
760     EFlags |= ELF::EF_MIPS_ARCH_32;
761   else if (Features[Mips::FeatureMips2])
762     EFlags |= ELF::EF_MIPS_ARCH_2;
763   else
764     EFlags |= ELF::EF_MIPS_ARCH_1;
765 
766   // Machine
767   if (Features[Mips::FeatureCnMips])
768     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
769 
770   // Other options.
771   if (Features[Mips::FeatureNaN2008])
772     EFlags |= ELF::EF_MIPS_NAN2008;
773 
774   MCA.setELFHeaderEFlags(EFlags);
775 }
776 
777 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
778   auto *Symbol = cast<MCSymbolELF>(S);
779   getStreamer().getAssembler().registerSymbol(*Symbol);
780   uint8_t Type = Symbol->getType();
781   if (Type != ELF::STT_FUNC)
782     return;
783 
784   if (isMicroMipsEnabled())
785     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
786 }
787 
788 void MipsTargetELFStreamer::finish() {
789   MCAssembler &MCA = getStreamer().getAssembler();
790   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
791 
792   // .bss, .text and .data are always at least 16-byte aligned.
793   MCSection &TextSection = *OFI.getTextSection();
794   MCA.registerSection(TextSection);
795   MCSection &DataSection = *OFI.getDataSection();
796   MCA.registerSection(DataSection);
797   MCSection &BSSSection = *OFI.getBSSSection();
798   MCA.registerSection(BSSSection);
799 
800   TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
801   DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
802   BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
803 
804   if (RoundSectionSizes) {
805     // Make sections sizes a multiple of the alignment. This is useful for
806     // verifying the output of IAS against the output of other assemblers but
807     // it's not necessary to produce a correct object and increases section
808     // size.
809     MCStreamer &OS = getStreamer();
810     for (MCSection &S : MCA) {
811       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
812 
813       unsigned Alignment = Section.getAlignment();
814       if (Alignment) {
815         OS.SwitchSection(&Section);
816         if (Section.UseCodeAlign())
817           OS.EmitCodeAlignment(Alignment, Alignment);
818         else
819           OS.EmitValueToAlignment(Alignment, 0, 1, Alignment);
820       }
821     }
822   }
823 
824   const FeatureBitset &Features = STI.getFeatureBits();
825 
826   // Update e_header flags. See the FIXME and comment above in
827   // the constructor for a full rundown on this.
828   unsigned EFlags = MCA.getELFHeaderEFlags();
829 
830   // ABI
831   // N64 does not require any ABI bits.
832   if (getABI().IsO32())
833     EFlags |= ELF::EF_MIPS_ABI_O32;
834   else if (getABI().IsN32())
835     EFlags |= ELF::EF_MIPS_ABI2;
836 
837   if (Features[Mips::FeatureGP64Bit]) {
838     if (getABI().IsO32())
839       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
840   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
841     EFlags |= ELF::EF_MIPS_32BITMODE;
842 
843   // -mplt is not implemented but we should act as if it was
844   // given.
845   if (!Features[Mips::FeatureNoABICalls])
846     EFlags |= ELF::EF_MIPS_CPIC;
847 
848   if (Pic)
849     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
850 
851   MCA.setELFHeaderEFlags(EFlags);
852 
853   // Emit all the option records.
854   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
855   // .reginfo.
856   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
857   MEF.EmitMipsOptionRecords();
858 
859   emitMipsAbiFlags();
860 }
861 
862 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
863   auto *Symbol = cast<MCSymbolELF>(S);
864   // If on rhs is micromips symbol then mark Symbol as microMips.
865   if (Value->getKind() != MCExpr::SymbolRef)
866     return;
867   const auto &RhsSym = cast<MCSymbolELF>(
868       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
869 
870   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
871     return;
872 
873   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
874 }
875 
876 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
877   return static_cast<MCELFStreamer &>(Streamer);
878 }
879 
880 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
881   MicroMipsEnabled = true;
882   forbidModuleDirective();
883 }
884 
885 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
886   MicroMipsEnabled = false;
887   forbidModuleDirective();
888 }
889 
890 void MipsTargetELFStreamer::setUsesMicroMips() {
891   MCAssembler &MCA = getStreamer().getAssembler();
892   unsigned Flags = MCA.getELFHeaderEFlags();
893   Flags |= ELF::EF_MIPS_MICROMIPS;
894   MCA.setELFHeaderEFlags(Flags);
895 }
896 
897 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
898   MCAssembler &MCA = getStreamer().getAssembler();
899   unsigned Flags = MCA.getELFHeaderEFlags();
900   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
901   MCA.setELFHeaderEFlags(Flags);
902   forbidModuleDirective();
903 }
904 
905 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
906   MCAssembler &MCA = getStreamer().getAssembler();
907   unsigned Flags = MCA.getELFHeaderEFlags();
908   Flags |= ELF::EF_MIPS_NOREORDER;
909   MCA.setELFHeaderEFlags(Flags);
910   forbidModuleDirective();
911 }
912 
913 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
914   MCAssembler &MCA = getStreamer().getAssembler();
915   MCContext &Context = MCA.getContext();
916   MCStreamer &OS = getStreamer();
917 
918   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
919 
920   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
921   const MCSymbolRefExpr *ExprRef =
922       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
923 
924   MCA.registerSection(*Sec);
925   Sec->setAlignment(4);
926 
927   OS.PushSection();
928 
929   OS.SwitchSection(Sec);
930 
931   OS.EmitValueImpl(ExprRef, 4);
932 
933   OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
934   OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
935 
936   OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
937   OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
938 
939   OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
940   OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
941   OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
942 
943   // The .end directive marks the end of a procedure. Invalidate
944   // the information gathered up until this point.
945   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
946 
947   OS.PopSection();
948 
949   // .end also implicitly sets the size.
950   MCSymbol *CurPCSym = Context.createTempSymbol();
951   OS.EmitLabel(CurPCSym);
952   const MCExpr *Size = MCBinaryExpr::createSub(
953       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
954       ExprRef, Context);
955 
956   // The ELFObjectWriter can determine the absolute size as it has access to
957   // the layout information of the assembly file, so a size expression rather
958   // than an absolute value is ok here.
959   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
960 }
961 
962 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
963   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
964 
965   // .ent also acts like an implicit '.type symbol, STT_FUNC'
966   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
967 }
968 
969 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
970   MCAssembler &MCA = getStreamer().getAssembler();
971   unsigned Flags = MCA.getELFHeaderEFlags();
972   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
973   MCA.setELFHeaderEFlags(Flags);
974 }
975 
976 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
977   MCAssembler &MCA = getStreamer().getAssembler();
978   unsigned Flags = MCA.getELFHeaderEFlags();
979   Flags |= ELF::EF_MIPS_NAN2008;
980   MCA.setELFHeaderEFlags(Flags);
981 }
982 
983 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
984   MCAssembler &MCA = getStreamer().getAssembler();
985   unsigned Flags = MCA.getELFHeaderEFlags();
986   Flags &= ~ELF::EF_MIPS_NAN2008;
987   MCA.setELFHeaderEFlags(Flags);
988 }
989 
990 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
991   MCAssembler &MCA = getStreamer().getAssembler();
992   unsigned Flags = MCA.getELFHeaderEFlags();
993   // This option overrides other PIC options like -KPIC.
994   Pic = false;
995   Flags &= ~ELF::EF_MIPS_PIC;
996   MCA.setELFHeaderEFlags(Flags);
997 }
998 
999 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1000   MCAssembler &MCA = getStreamer().getAssembler();
1001   unsigned Flags = MCA.getELFHeaderEFlags();
1002   Pic = true;
1003   // NOTE: We are following the GAS behaviour here which means the directive
1004   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1005   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1006   // EF_MIPS_CPIC to be mutually exclusive.
1007   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1008   MCA.setELFHeaderEFlags(Flags);
1009 }
1010 
1011 void MipsTargetELFStreamer::emitDirectiveInsn() {
1012   MipsTargetStreamer::emitDirectiveInsn();
1013   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1014   MEF.createPendingLabelRelocs();
1015 }
1016 
1017 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1018                                       unsigned ReturnReg_) {
1019   MCContext &Context = getStreamer().getAssembler().getContext();
1020   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1021 
1022   FrameInfoSet = true;
1023   FrameReg = RegInfo->getEncodingValue(StackReg);
1024   FrameOffset = StackSize;
1025   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1026 }
1027 
1028 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1029                                      int CPUTopSavedRegOff) {
1030   GPRInfoSet = true;
1031   GPRBitMask = CPUBitmask;
1032   GPROffset = CPUTopSavedRegOff;
1033 }
1034 
1035 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1036                                       int FPUTopSavedRegOff) {
1037   FPRInfoSet = true;
1038   FPRBitMask = FPUBitmask;
1039   FPROffset = FPUTopSavedRegOff;
1040 }
1041 
1042 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1043   // .cpload $reg
1044   // This directive expands to:
1045   // lui   $gp, %hi(_gp_disp)
1046   // addui $gp, $gp, %lo(_gp_disp)
1047   // addu  $gp, $gp, $reg
1048   // when support for position independent code is enabled.
1049   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1050     return;
1051 
1052   // There's a GNU extension controlled by -mno-shared that allows
1053   // locally-binding symbols to be accessed using absolute addresses.
1054   // This is currently not supported. When supported -mno-shared makes
1055   // .cpload expand to:
1056   //   lui     $gp, %hi(__gnu_local_gp)
1057   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1058 
1059   StringRef SymName("_gp_disp");
1060   MCAssembler &MCA = getStreamer().getAssembler();
1061   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1062   MCA.registerSymbol(*GP_Disp);
1063 
1064   MCInst TmpInst;
1065   TmpInst.setOpcode(Mips::LUi);
1066   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1067   const MCExpr *HiSym = MipsMCExpr::create(
1068       MipsMCExpr::MEK_HI,
1069       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1070                               MCA.getContext()),
1071       MCA.getContext());
1072   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1073   getStreamer().EmitInstruction(TmpInst, STI);
1074 
1075   TmpInst.clear();
1076 
1077   TmpInst.setOpcode(Mips::ADDiu);
1078   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1079   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1080   const MCExpr *LoSym = MipsMCExpr::create(
1081       MipsMCExpr::MEK_LO,
1082       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1083                               MCA.getContext()),
1084       MCA.getContext());
1085   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1086   getStreamer().EmitInstruction(TmpInst, STI);
1087 
1088   TmpInst.clear();
1089 
1090   TmpInst.setOpcode(Mips::ADDu);
1091   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1092   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
1093   TmpInst.addOperand(MCOperand::createReg(RegNo));
1094   getStreamer().EmitInstruction(TmpInst, STI);
1095 
1096   forbidModuleDirective();
1097 }
1098 
1099 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1100     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1101     const MCSubtargetInfo *STI) {
1102   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1103   // .cprestore offset
1104   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1105   // to:
1106   //    sw $gp, offset($sp)
1107   // and adds a corresponding LW after every JAL.
1108 
1109   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1110   // is used in non-PIC mode.
1111   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1112     return true;
1113 
1114   // Store the $gp on the stack.
1115   emitStoreWithImmOffset(Mips::SW, Mips::GP, Mips::SP, Offset, GetATReg, IDLoc,
1116                          STI);
1117   return true;
1118 }
1119 
1120 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1121                                                  int RegOrOffset,
1122                                                  const MCSymbol &Sym,
1123                                                  bool IsReg) {
1124   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1125   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1126     return;
1127 
1128   forbidModuleDirective();
1129 
1130   MCAssembler &MCA = getStreamer().getAssembler();
1131   MCInst Inst;
1132 
1133   // Either store the old $gp in a register or on the stack
1134   if (IsReg) {
1135     // move $save, $gpreg
1136     emitRRR(Mips::OR64, RegOrOffset, Mips::GP, Mips::ZERO, SMLoc(), &STI);
1137   } else {
1138     // sd $gpreg, offset($sp)
1139     emitRRI(Mips::SD, Mips::GP, Mips::SP, RegOrOffset, SMLoc(), &STI);
1140   }
1141 
1142   if (getABI().IsN32()) {
1143     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1144     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1145         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1146         MCA.getContext());
1147     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1148         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1149         MCA.getContext());
1150 
1151     // lui $gp, %hi(__gnu_local_gp)
1152     emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1153 
1154     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1155     emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1156             SMLoc(), &STI);
1157 
1158     return;
1159   }
1160 
1161   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1162       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1163       MCA.getContext());
1164   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1165       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1166       MCA.getContext());
1167 
1168   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1169   emitRX(Mips::LUi, Mips::GP, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1170 
1171   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1172   emitRRX(Mips::ADDiu, Mips::GP, Mips::GP, MCOperand::createExpr(LoExpr),
1173           SMLoc(), &STI);
1174 
1175   // daddu  $gp, $gp, $funcreg
1176   emitRRR(Mips::DADDu, Mips::GP, Mips::GP, RegNo, SMLoc(), &STI);
1177 }
1178 
1179 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1180                                                   bool SaveLocationIsRegister) {
1181   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1182   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1183     return;
1184 
1185   MCInst Inst;
1186   // Either restore the old $gp from a register or on the stack
1187   if (SaveLocationIsRegister) {
1188     Inst.setOpcode(Mips::OR);
1189     Inst.addOperand(MCOperand::createReg(Mips::GP));
1190     Inst.addOperand(MCOperand::createReg(SaveLocation));
1191     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1192   } else {
1193     Inst.setOpcode(Mips::LD);
1194     Inst.addOperand(MCOperand::createReg(Mips::GP));
1195     Inst.addOperand(MCOperand::createReg(Mips::SP));
1196     Inst.addOperand(MCOperand::createImm(SaveLocation));
1197   }
1198   getStreamer().EmitInstruction(Inst, STI);
1199 
1200   forbidModuleDirective();
1201 }
1202 
1203 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1204   MCAssembler &MCA = getStreamer().getAssembler();
1205   MCContext &Context = MCA.getContext();
1206   MCStreamer &OS = getStreamer();
1207   MCSectionELF *Sec = Context.getELFSection(
1208       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1209   MCA.registerSection(*Sec);
1210   Sec->setAlignment(8);
1211   OS.SwitchSection(Sec);
1212 
1213   OS << ABIFlagsSection;
1214 }
1215