1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MipsMCCodeEmitter.h" 16 #include "MCTargetDesc/MipsFixupKinds.h" 17 #include "MCTargetDesc/MipsMCExpr.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "llvm/ADT/APFloat.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCFixup.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/Support/raw_ostream.h" 29 30 #define DEBUG_TYPE "mccodeemitter" 31 32 #define GET_INSTRMAP_INFO 33 #include "MipsGenInstrInfo.inc" 34 #undef GET_INSTRMAP_INFO 35 36 namespace llvm { 37 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 38 const MCRegisterInfo &MRI, 39 MCContext &Ctx) { 40 return new MipsMCCodeEmitter(MCII, Ctx, false); 41 } 42 43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 44 const MCRegisterInfo &MRI, 45 MCContext &Ctx) { 46 return new MipsMCCodeEmitter(MCII, Ctx, true); 47 } 48 } // End of namespace llvm. 49 50 // If the D<shift> instruction has a shift amount that is greater 51 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction 52 static void LowerLargeShift(MCInst& Inst) { 53 54 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!"); 55 assert(Inst.getOperand(2).isImm()); 56 57 int64_t Shift = Inst.getOperand(2).getImm(); 58 if (Shift <= 31) 59 return; // Do nothing 60 Shift -= 32; 61 62 // saminus32 63 Inst.getOperand(2).setImm(Shift); 64 65 switch (Inst.getOpcode()) { 66 default: 67 // Calling function is not synchronized 68 llvm_unreachable("Unexpected shift instruction"); 69 case Mips::DSLL: 70 Inst.setOpcode(Mips::DSLL32); 71 return; 72 case Mips::DSRL: 73 Inst.setOpcode(Mips::DSRL32); 74 return; 75 case Mips::DSRA: 76 Inst.setOpcode(Mips::DSRA32); 77 return; 78 case Mips::DROTR: 79 Inst.setOpcode(Mips::DROTR32); 80 return; 81 } 82 } 83 84 // Pick a DINS instruction variant based on the pos and size operands 85 static void LowerDins(MCInst& InstIn) { 86 assert(InstIn.getNumOperands() == 5 && 87 "Invalid no. of machine operands for DINS!"); 88 89 assert(InstIn.getOperand(2).isImm()); 90 int64_t pos = InstIn.getOperand(2).getImm(); 91 assert(InstIn.getOperand(3).isImm()); 92 int64_t size = InstIn.getOperand(3).getImm(); 93 94 if (size <= 32) { 95 if (pos < 32) // DINS, do nothing 96 return; 97 // DINSU 98 InstIn.getOperand(2).setImm(pos - 32); 99 InstIn.setOpcode(Mips::DINSU); 100 return; 101 } 102 // DINSM 103 assert(pos < 32 && "DINS cannot have both size and pos > 32"); 104 InstIn.getOperand(3).setImm(size - 32); 105 InstIn.setOpcode(Mips::DINSM); 106 return; 107 } 108 109 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { 110 return STI.getFeatureBits()[Mips::FeatureMicroMips]; 111 } 112 113 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const { 114 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 115 } 116 117 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { 118 OS << (char)C; 119 } 120 121 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, 122 const MCSubtargetInfo &STI, 123 raw_ostream &OS) const { 124 // Output the instruction encoding in little endian byte order. 125 // Little-endian byte ordering: 126 // mips32r2: 4 | 3 | 2 | 1 127 // microMIPS: 2 | 1 | 4 | 3 128 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { 129 EmitInstruction(Val >> 16, 2, STI, OS); 130 EmitInstruction(Val, 2, STI, OS); 131 } else { 132 for (unsigned i = 0; i < Size; ++i) { 133 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 134 EmitByte((Val >> Shift) & 0xff, OS); 135 } 136 } 137 } 138 139 /// encodeInstruction - Emit the instruction. 140 /// Size the instruction with Desc.getSize(). 141 void MipsMCCodeEmitter:: 142 encodeInstruction(const MCInst &MI, raw_ostream &OS, 143 SmallVectorImpl<MCFixup> &Fixups, 144 const MCSubtargetInfo &STI) const 145 { 146 147 // Non-pseudo instructions that get changed for direct object 148 // only based on operand values. 149 // If this list of instructions get much longer we will move 150 // the check to a function call. Until then, this is more efficient. 151 MCInst TmpInst = MI; 152 switch (MI.getOpcode()) { 153 // If shift amount is >= 32 it the inst needs to be lowered further 154 case Mips::DSLL: 155 case Mips::DSRL: 156 case Mips::DSRA: 157 case Mips::DROTR: 158 LowerLargeShift(TmpInst); 159 break; 160 // Double extract instruction is chosen by pos and size operands 161 case Mips::DINS: 162 LowerDins(TmpInst); 163 } 164 165 unsigned long N = Fixups.size(); 166 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 167 168 // Check for unimplemented opcodes. 169 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 170 // so we have to special check for them. 171 unsigned Opcode = TmpInst.getOpcode(); 172 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && 173 (Opcode != Mips::SLL_MM) && !Binary) 174 llvm_unreachable("unimplemented opcode in encodeInstruction()"); 175 176 int NewOpcode = -1; 177 if (isMicroMips(STI)) { 178 if (isMips32r6(STI)) { 179 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); 180 if (NewOpcode == -1) 181 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); 182 } 183 else 184 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); 185 186 // Check whether it is Dsp instruction. 187 if (NewOpcode == -1) 188 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); 189 190 if (NewOpcode != -1) { 191 if (Fixups.size() > N) 192 Fixups.pop_back(); 193 194 Opcode = NewOpcode; 195 TmpInst.setOpcode (NewOpcode); 196 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 197 } 198 } 199 200 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); 201 202 // Get byte count of instruction 203 unsigned Size = Desc.getSize(); 204 if (!Size) 205 llvm_unreachable("Desc.getSize() returns 0"); 206 207 EmitInstruction(Binary, Size, STI, OS); 208 } 209 210 /// getBranchTargetOpValue - Return binary encoding of the branch 211 /// target operand. If the machine operand requires relocation, 212 /// record the relocation and return zero. 213 unsigned MipsMCCodeEmitter:: 214 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 215 SmallVectorImpl<MCFixup> &Fixups, 216 const MCSubtargetInfo &STI) const { 217 218 const MCOperand &MO = MI.getOperand(OpNo); 219 220 // If the destination is an immediate, divide by 4. 221 if (MO.isImm()) return MO.getImm() >> 2; 222 223 assert(MO.isExpr() && 224 "getBranchTargetOpValue expects only expressions or immediates"); 225 226 const MCExpr *FixupExpression = MCBinaryExpr::createAdd( 227 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); 228 Fixups.push_back(MCFixup::create(0, FixupExpression, 229 MCFixupKind(Mips::fixup_Mips_PC16))); 230 return 0; 231 } 232 233 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch 234 /// target operand. If the machine operand requires relocation, 235 /// record the relocation and return zero. 236 unsigned MipsMCCodeEmitter:: 237 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, 238 SmallVectorImpl<MCFixup> &Fixups, 239 const MCSubtargetInfo &STI) const { 240 241 const MCOperand &MO = MI.getOperand(OpNo); 242 243 // If the destination is an immediate, divide by 2. 244 if (MO.isImm()) return MO.getImm() >> 1; 245 246 assert(MO.isExpr() && 247 "getBranchTargetOpValueMM expects only expressions or immediates"); 248 249 const MCExpr *Expr = MO.getExpr(); 250 Fixups.push_back(MCFixup::create(0, Expr, 251 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1))); 252 return 0; 253 } 254 255 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 256 /// 10-bit branch target operand. If the machine operand requires relocation, 257 /// record the relocation and return zero. 258 unsigned MipsMCCodeEmitter:: 259 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, 260 SmallVectorImpl<MCFixup> &Fixups, 261 const MCSubtargetInfo &STI) const { 262 263 const MCOperand &MO = MI.getOperand(OpNo); 264 265 // If the destination is an immediate, divide by 2. 266 if (MO.isImm()) return MO.getImm() >> 1; 267 268 assert(MO.isExpr() && 269 "getBranchTargetOpValuePC10 expects only expressions or immediates"); 270 271 const MCExpr *Expr = MO.getExpr(); 272 Fixups.push_back(MCFixup::create(0, Expr, 273 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1))); 274 return 0; 275 } 276 277 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch 278 /// target operand. If the machine operand requires relocation, 279 /// record the relocation and return zero. 280 unsigned MipsMCCodeEmitter:: 281 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 282 SmallVectorImpl<MCFixup> &Fixups, 283 const MCSubtargetInfo &STI) const { 284 285 const MCOperand &MO = MI.getOperand(OpNo); 286 287 // If the destination is an immediate, divide by 2. 288 if (MO.isImm()) return MO.getImm() >> 1; 289 290 assert(MO.isExpr() && 291 "getBranchTargetOpValueMM expects only expressions or immediates"); 292 293 const MCExpr *Expr = MO.getExpr(); 294 Fixups.push_back(MCFixup::create(0, Expr, 295 MCFixupKind(Mips:: 296 fixup_MICROMIPS_PC16_S1))); 297 return 0; 298 } 299 300 /// getBranchTarget21OpValue - Return binary encoding of the branch 301 /// target operand. If the machine operand requires relocation, 302 /// record the relocation and return zero. 303 unsigned MipsMCCodeEmitter:: 304 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 305 SmallVectorImpl<MCFixup> &Fixups, 306 const MCSubtargetInfo &STI) const { 307 308 const MCOperand &MO = MI.getOperand(OpNo); 309 310 // If the destination is an immediate, divide by 4. 311 if (MO.isImm()) return MO.getImm() >> 2; 312 313 assert(MO.isExpr() && 314 "getBranchTarget21OpValue expects only expressions or immediates"); 315 316 const MCExpr *FixupExpression = MCBinaryExpr::createAdd( 317 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); 318 Fixups.push_back(MCFixup::create(0, FixupExpression, 319 MCFixupKind(Mips::fixup_MIPS_PC21_S2))); 320 return 0; 321 } 322 323 /// getBranchTarget26OpValue - Return binary encoding of the branch 324 /// target operand. If the machine operand requires relocation, 325 /// record the relocation and return zero. 326 unsigned MipsMCCodeEmitter:: 327 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, 328 SmallVectorImpl<MCFixup> &Fixups, 329 const MCSubtargetInfo &STI) const { 330 331 const MCOperand &MO = MI.getOperand(OpNo); 332 333 // If the destination is an immediate, divide by 4. 334 if (MO.isImm()) return MO.getImm() >> 2; 335 336 assert(MO.isExpr() && 337 "getBranchTarget26OpValue expects only expressions or immediates"); 338 339 const MCExpr *FixupExpression = MCBinaryExpr::createAdd( 340 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); 341 Fixups.push_back(MCFixup::create(0, FixupExpression, 342 MCFixupKind(Mips::fixup_MIPS_PC26_S2))); 343 return 0; 344 } 345 346 /// getBranchTarget26OpValueMM - Return binary encoding of the branch 347 /// target operand. If the machine operand requires relocation, 348 /// record the relocation and return zero. 349 unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM( 350 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, 351 const MCSubtargetInfo &STI) const { 352 353 const MCOperand &MO = MI.getOperand(OpNo); 354 355 // If the destination is an immediate, divide by 2. 356 if (MO.isImm()) 357 return MO.getImm() >> 1; 358 359 assert(MO.isExpr() && 360 "getBranchTarget26OpValueMM expects only expressions or immediates"); 361 362 const MCExpr *FixupExpression = MCBinaryExpr::createAdd( 363 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); 364 Fixups.push_back(MCFixup::create(0, FixupExpression, 365 MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1))); 366 return 0; 367 } 368 369 /// getJumpOffset16OpValue - Return binary encoding of the jump 370 /// target operand. If the machine operand requires relocation, 371 /// record the relocation and return zero. 372 unsigned MipsMCCodeEmitter:: 373 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, 374 SmallVectorImpl<MCFixup> &Fixups, 375 const MCSubtargetInfo &STI) const { 376 377 const MCOperand &MO = MI.getOperand(OpNo); 378 379 if (MO.isImm()) return MO.getImm(); 380 381 assert(MO.isExpr() && 382 "getJumpOffset16OpValue expects only expressions or an immediate"); 383 384 // TODO: Push fixup. 385 return 0; 386 } 387 388 /// getJumpTargetOpValue - Return binary encoding of the jump 389 /// target operand. If the machine operand requires relocation, 390 /// record the relocation and return zero. 391 unsigned MipsMCCodeEmitter:: 392 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 393 SmallVectorImpl<MCFixup> &Fixups, 394 const MCSubtargetInfo &STI) const { 395 396 const MCOperand &MO = MI.getOperand(OpNo); 397 // If the destination is an immediate, divide by 4. 398 if (MO.isImm()) return MO.getImm()>>2; 399 400 assert(MO.isExpr() && 401 "getJumpTargetOpValue expects only expressions or an immediate"); 402 403 const MCExpr *Expr = MO.getExpr(); 404 Fixups.push_back(MCFixup::create(0, Expr, 405 MCFixupKind(Mips::fixup_Mips_26))); 406 return 0; 407 } 408 409 unsigned MipsMCCodeEmitter:: 410 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, 411 SmallVectorImpl<MCFixup> &Fixups, 412 const MCSubtargetInfo &STI) const { 413 414 const MCOperand &MO = MI.getOperand(OpNo); 415 // If the destination is an immediate, divide by 2. 416 if (MO.isImm()) return MO.getImm() >> 1; 417 418 assert(MO.isExpr() && 419 "getJumpTargetOpValueMM expects only expressions or an immediate"); 420 421 const MCExpr *Expr = MO.getExpr(); 422 Fixups.push_back(MCFixup::create(0, Expr, 423 MCFixupKind(Mips::fixup_MICROMIPS_26_S1))); 424 return 0; 425 } 426 427 unsigned MipsMCCodeEmitter:: 428 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, 429 SmallVectorImpl<MCFixup> &Fixups, 430 const MCSubtargetInfo &STI) const { 431 432 const MCOperand &MO = MI.getOperand(OpNo); 433 if (MO.isImm()) { 434 // The immediate is encoded as 'immediate << 2'. 435 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); 436 assert((Res & 3) == 0); 437 return Res >> 2; 438 } 439 440 assert(MO.isExpr() && 441 "getUImm5Lsl2Encoding expects only expressions or an immediate"); 442 443 return 0; 444 } 445 446 unsigned MipsMCCodeEmitter:: 447 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, 448 SmallVectorImpl<MCFixup> &Fixups, 449 const MCSubtargetInfo &STI) const { 450 451 const MCOperand &MO = MI.getOperand(OpNo); 452 if (MO.isImm()) { 453 int Value = MO.getImm(); 454 return Value >> 2; 455 } 456 457 return 0; 458 } 459 460 unsigned MipsMCCodeEmitter:: 461 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, 462 SmallVectorImpl<MCFixup> &Fixups, 463 const MCSubtargetInfo &STI) const { 464 465 const MCOperand &MO = MI.getOperand(OpNo); 466 if (MO.isImm()) { 467 unsigned Value = MO.getImm(); 468 return Value >> 2; 469 } 470 471 return 0; 472 } 473 474 unsigned MipsMCCodeEmitter:: 475 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, 476 SmallVectorImpl<MCFixup> &Fixups, 477 const MCSubtargetInfo &STI) const { 478 479 const MCOperand &MO = MI.getOperand(OpNo); 480 if (MO.isImm()) { 481 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff; 482 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff)); 483 } 484 485 return 0; 486 } 487 488 unsigned MipsMCCodeEmitter:: 489 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, 490 const MCSubtargetInfo &STI) const { 491 int64_t Res; 492 493 if (Expr->evaluateAsAbsolute(Res)) 494 return Res; 495 496 MCExpr::ExprKind Kind = Expr->getKind(); 497 if (Kind == MCExpr::Constant) { 498 return cast<MCConstantExpr>(Expr)->getValue(); 499 } 500 501 if (Kind == MCExpr::Binary) { 502 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); 503 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); 504 return Res; 505 } 506 507 if (Kind == MCExpr::Target) { 508 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr); 509 510 Mips::Fixups FixupKind = Mips::Fixups(0); 511 switch (MipsExpr->getKind()) { 512 default: llvm_unreachable("Unsupported fixup kind for target expression!"); 513 case MipsMCExpr::VK_Mips_HIGHEST: 514 FixupKind = Mips::fixup_Mips_HIGHEST; 515 break; 516 case MipsMCExpr::VK_Mips_HIGHER: 517 FixupKind = Mips::fixup_Mips_HIGHER; 518 break; 519 case MipsMCExpr::VK_Mips_HI: 520 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 521 : Mips::fixup_Mips_HI16; 522 break; 523 case MipsMCExpr::VK_Mips_LO: 524 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 525 : Mips::fixup_Mips_LO16; 526 break; 527 } 528 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind))); 529 return 0; 530 } 531 532 if (Kind == MCExpr::SymbolRef) { 533 Mips::Fixups FixupKind = Mips::Fixups(0); 534 535 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { 536 default: llvm_unreachable("Unknown fixup kind!"); 537 break; 538 case MCSymbolRefExpr::VK_None: 539 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64. 540 break; 541 case MCSymbolRefExpr::VK_Mips_GPOFF_HI : 542 FixupKind = Mips::fixup_Mips_GPOFF_HI; 543 break; 544 case MCSymbolRefExpr::VK_Mips_GPOFF_LO : 545 FixupKind = Mips::fixup_Mips_GPOFF_LO; 546 break; 547 case MCSymbolRefExpr::VK_Mips_GOT_PAGE : 548 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE 549 : Mips::fixup_Mips_GOT_PAGE; 550 break; 551 case MCSymbolRefExpr::VK_Mips_GOT_OFST : 552 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST 553 : Mips::fixup_Mips_GOT_OFST; 554 break; 555 case MCSymbolRefExpr::VK_Mips_GOT_DISP : 556 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP 557 : Mips::fixup_Mips_GOT_DISP; 558 break; 559 case MCSymbolRefExpr::VK_Mips_GPREL: 560 FixupKind = Mips::fixup_Mips_GPREL16; 561 break; 562 case MCSymbolRefExpr::VK_Mips_GOT_CALL: 563 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16 564 : Mips::fixup_Mips_CALL16; 565 break; 566 case MCSymbolRefExpr::VK_Mips_GOT16: 567 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 568 : Mips::fixup_Mips_GOT_Global; 569 break; 570 case MCSymbolRefExpr::VK_Mips_GOT: 571 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 572 : Mips::fixup_Mips_GOT_Local; 573 break; 574 case MCSymbolRefExpr::VK_Mips_ABS_HI: 575 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 576 : Mips::fixup_Mips_HI16; 577 break; 578 case MCSymbolRefExpr::VK_Mips_ABS_LO: 579 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 580 : Mips::fixup_Mips_LO16; 581 break; 582 case MCSymbolRefExpr::VK_Mips_TLSGD: 583 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD 584 : Mips::fixup_Mips_TLSGD; 585 break; 586 case MCSymbolRefExpr::VK_Mips_TLSLDM: 587 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM 588 : Mips::fixup_Mips_TLSLDM; 589 break; 590 case MCSymbolRefExpr::VK_Mips_DTPREL_HI: 591 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16 592 : Mips::fixup_Mips_DTPREL_HI; 593 break; 594 case MCSymbolRefExpr::VK_Mips_DTPREL_LO: 595 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16 596 : Mips::fixup_Mips_DTPREL_LO; 597 break; 598 case MCSymbolRefExpr::VK_Mips_GOTTPREL: 599 FixupKind = Mips::fixup_Mips_GOTTPREL; 600 break; 601 case MCSymbolRefExpr::VK_Mips_TPREL_HI: 602 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16 603 : Mips::fixup_Mips_TPREL_HI; 604 break; 605 case MCSymbolRefExpr::VK_Mips_TPREL_LO: 606 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16 607 : Mips::fixup_Mips_TPREL_LO; 608 break; 609 case MCSymbolRefExpr::VK_Mips_HIGHER: 610 FixupKind = Mips::fixup_Mips_HIGHER; 611 break; 612 case MCSymbolRefExpr::VK_Mips_HIGHEST: 613 FixupKind = Mips::fixup_Mips_HIGHEST; 614 break; 615 case MCSymbolRefExpr::VK_Mips_GOT_HI16: 616 FixupKind = Mips::fixup_Mips_GOT_HI16; 617 break; 618 case MCSymbolRefExpr::VK_Mips_GOT_LO16: 619 FixupKind = Mips::fixup_Mips_GOT_LO16; 620 break; 621 case MCSymbolRefExpr::VK_Mips_CALL_HI16: 622 FixupKind = Mips::fixup_Mips_CALL_HI16; 623 break; 624 case MCSymbolRefExpr::VK_Mips_CALL_LO16: 625 FixupKind = Mips::fixup_Mips_CALL_LO16; 626 break; 627 case MCSymbolRefExpr::VK_Mips_PCREL_HI16: 628 FixupKind = Mips::fixup_MIPS_PCHI16; 629 break; 630 case MCSymbolRefExpr::VK_Mips_PCREL_LO16: 631 FixupKind = Mips::fixup_MIPS_PCLO16; 632 break; 633 } // switch 634 635 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); 636 return 0; 637 } 638 return 0; 639 } 640 641 /// getMachineOpValue - Return binary encoding of operand. If the machine 642 /// operand requires relocation, record the relocation and return zero. 643 unsigned MipsMCCodeEmitter:: 644 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 645 SmallVectorImpl<MCFixup> &Fixups, 646 const MCSubtargetInfo &STI) const { 647 if (MO.isReg()) { 648 unsigned Reg = MO.getReg(); 649 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); 650 return RegNo; 651 } else if (MO.isImm()) { 652 return static_cast<unsigned>(MO.getImm()); 653 } else if (MO.isFPImm()) { 654 return static_cast<unsigned>(APFloat(MO.getFPImm()) 655 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 656 } 657 // MO must be an Expr. 658 assert(MO.isExpr()); 659 return getExprOpValue(MO.getExpr(),Fixups, STI); 660 } 661 662 /// Return binary encoding of memory related operand. 663 /// If the offset operand requires relocation, record the relocation. 664 template <unsigned ShiftAmount> 665 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, 666 SmallVectorImpl<MCFixup> &Fixups, 667 const MCSubtargetInfo &STI) const { 668 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. 669 assert(MI.getOperand(OpNo).isReg()); 670 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; 671 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 672 673 // Apply the scale factor if there is one. 674 OffBits >>= ShiftAmount; 675 676 return (OffBits & 0xFFFF) | RegBits; 677 } 678 679 unsigned MipsMCCodeEmitter:: 680 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, 681 SmallVectorImpl<MCFixup> &Fixups, 682 const MCSubtargetInfo &STI) const { 683 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. 684 assert(MI.getOperand(OpNo).isReg()); 685 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 686 Fixups, STI) << 4; 687 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 688 Fixups, STI); 689 690 return (OffBits & 0xF) | RegBits; 691 } 692 693 unsigned MipsMCCodeEmitter:: 694 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, 695 SmallVectorImpl<MCFixup> &Fixups, 696 const MCSubtargetInfo &STI) const { 697 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. 698 assert(MI.getOperand(OpNo).isReg()); 699 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 700 Fixups, STI) << 4; 701 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 702 Fixups, STI) >> 1; 703 704 return (OffBits & 0xF) | RegBits; 705 } 706 707 unsigned MipsMCCodeEmitter:: 708 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, 709 SmallVectorImpl<MCFixup> &Fixups, 710 const MCSubtargetInfo &STI) const { 711 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. 712 assert(MI.getOperand(OpNo).isReg()); 713 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 714 Fixups, STI) << 4; 715 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 716 Fixups, STI) >> 2; 717 718 return (OffBits & 0xF) | RegBits; 719 } 720 721 unsigned MipsMCCodeEmitter:: 722 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, 723 SmallVectorImpl<MCFixup> &Fixups, 724 const MCSubtargetInfo &STI) const { 725 // Register is encoded in bits 9-5, offset is encoded in bits 4-0. 726 assert(MI.getOperand(OpNo).isReg() && 727 (MI.getOperand(OpNo).getReg() == Mips::SP || 728 MI.getOperand(OpNo).getReg() == Mips::SP_64) && 729 "Unexpected base register!"); 730 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 731 Fixups, STI) >> 2; 732 733 return OffBits & 0x1F; 734 } 735 736 unsigned MipsMCCodeEmitter:: 737 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, 738 SmallVectorImpl<MCFixup> &Fixups, 739 const MCSubtargetInfo &STI) const { 740 // Register is encoded in bits 9-7, offset is encoded in bits 6-0. 741 assert(MI.getOperand(OpNo).isReg() && 742 MI.getOperand(OpNo).getReg() == Mips::GP && 743 "Unexpected base register!"); 744 745 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 746 Fixups, STI) >> 2; 747 748 return OffBits & 0x7F; 749 } 750 751 unsigned MipsMCCodeEmitter:: 752 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, 753 SmallVectorImpl<MCFixup> &Fixups, 754 const MCSubtargetInfo &STI) const { 755 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0. 756 assert(MI.getOperand(OpNo).isReg()); 757 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, 758 STI) << 16; 759 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI); 760 761 return (OffBits & 0x1FF) | RegBits; 762 } 763 764 unsigned MipsMCCodeEmitter:: 765 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, 766 SmallVectorImpl<MCFixup> &Fixups, 767 const MCSubtargetInfo &STI) const { 768 // opNum can be invalid if instruction had reglist as operand. 769 // MemOperand is always last operand of instruction (base + offset). 770 switch (MI.getOpcode()) { 771 default: 772 break; 773 case Mips::SWM32_MM: 774 case Mips::LWM32_MM: 775 OpNo = MI.getNumOperands() - 2; 776 break; 777 } 778 779 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. 780 assert(MI.getOperand(OpNo).isReg()); 781 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; 782 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 783 784 return (OffBits & 0x0FFF) | RegBits; 785 } 786 787 unsigned MipsMCCodeEmitter:: 788 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, 789 SmallVectorImpl<MCFixup> &Fixups, 790 const MCSubtargetInfo &STI) const { 791 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. 792 assert(MI.getOperand(OpNo).isReg()); 793 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, 794 STI) << 16; 795 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 796 797 return (OffBits & 0xFFFF) | RegBits; 798 } 799 800 unsigned MipsMCCodeEmitter:: 801 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, 802 SmallVectorImpl<MCFixup> &Fixups, 803 const MCSubtargetInfo &STI) const { 804 // opNum can be invalid if instruction had reglist as operand 805 // MemOperand is always last operand of instruction (base + offset) 806 switch (MI.getOpcode()) { 807 default: 808 break; 809 case Mips::SWM16_MM: 810 case Mips::SWM16_MMR6: 811 case Mips::LWM16_MM: 812 case Mips::LWM16_MMR6: 813 OpNo = MI.getNumOperands() - 2; 814 break; 815 } 816 817 // Offset is encoded in bits 4-0. 818 assert(MI.getOperand(OpNo).isReg()); 819 // Base register is always SP - thus it is not encoded. 820 assert(MI.getOperand(OpNo+1).isImm()); 821 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 822 823 return ((OffBits >> 2) & 0x0F); 824 } 825 826 // FIXME: should be called getMSBEncoding 827 // 828 unsigned 829 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 830 SmallVectorImpl<MCFixup> &Fixups, 831 const MCSubtargetInfo &STI) const { 832 assert(MI.getOperand(OpNo-1).isImm()); 833 assert(MI.getOperand(OpNo).isImm()); 834 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); 835 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 836 837 return Position + Size - 1; 838 } 839 840 template <unsigned Bits, int Offset> 841 unsigned 842 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, 843 SmallVectorImpl<MCFixup> &Fixups, 844 const MCSubtargetInfo &STI) const { 845 assert(MI.getOperand(OpNo).isImm()); 846 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 847 Value -= Offset; 848 return Value; 849 } 850 851 unsigned 852 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, 853 SmallVectorImpl<MCFixup> &Fixups, 854 const MCSubtargetInfo &STI) const { 855 const MCOperand &MO = MI.getOperand(OpNo); 856 if (MO.isImm()) { 857 // The immediate is encoded as 'immediate << 2'. 858 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); 859 assert((Res & 3) == 0); 860 return Res >> 2; 861 } 862 863 assert(MO.isExpr() && 864 "getSimm19Lsl2Encoding expects only expressions or an immediate"); 865 866 const MCExpr *Expr = MO.getExpr(); 867 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2 868 : Mips::fixup_MIPS_PC19_S2; 869 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); 870 return 0; 871 } 872 873 unsigned 874 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, 875 SmallVectorImpl<MCFixup> &Fixups, 876 const MCSubtargetInfo &STI) const { 877 const MCOperand &MO = MI.getOperand(OpNo); 878 if (MO.isImm()) { 879 // The immediate is encoded as 'immediate << 3'. 880 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 881 assert((Res & 7) == 0); 882 return Res >> 3; 883 } 884 885 assert(MO.isExpr() && 886 "getSimm18Lsl2Encoding expects only expressions or an immediate"); 887 888 const MCExpr *Expr = MO.getExpr(); 889 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3 890 : Mips::fixup_MIPS_PC18_S3; 891 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); 892 return 0; 893 } 894 895 unsigned 896 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, 897 SmallVectorImpl<MCFixup> &Fixups, 898 const MCSubtargetInfo &STI) const { 899 assert(MI.getOperand(OpNo).isImm()); 900 const MCOperand &MO = MI.getOperand(OpNo); 901 return MO.getImm() % 8; 902 } 903 904 unsigned 905 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo, 906 SmallVectorImpl<MCFixup> &Fixups, 907 const MCSubtargetInfo &STI) const { 908 assert(MI.getOperand(OpNo).isImm()); 909 const MCOperand &MO = MI.getOperand(OpNo); 910 unsigned Value = MO.getImm(); 911 switch (Value) { 912 case 128: return 0x0; 913 case 1: return 0x1; 914 case 2: return 0x2; 915 case 3: return 0x3; 916 case 4: return 0x4; 917 case 7: return 0x5; 918 case 8: return 0x6; 919 case 15: return 0x7; 920 case 16: return 0x8; 921 case 31: return 0x9; 922 case 32: return 0xa; 923 case 63: return 0xb; 924 case 64: return 0xc; 925 case 255: return 0xd; 926 case 32768: return 0xe; 927 case 65535: return 0xf; 928 } 929 llvm_unreachable("Unexpected value"); 930 } 931 932 unsigned 933 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo, 934 SmallVectorImpl<MCFixup> &Fixups, 935 const MCSubtargetInfo &STI) const { 936 unsigned res = 0; 937 938 // Register list operand is always first operand of instruction and it is 939 // placed before memory operand (register + imm). 940 941 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) { 942 unsigned Reg = MI.getOperand(I).getReg(); 943 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); 944 if (RegNo != 31) 945 res++; 946 else 947 res |= 0x10; 948 } 949 return res; 950 } 951 952 unsigned 953 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, 954 SmallVectorImpl<MCFixup> &Fixups, 955 const MCSubtargetInfo &STI) const { 956 return (MI.getNumOperands() - 4); 957 } 958 959 unsigned 960 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, 961 SmallVectorImpl<MCFixup> &Fixups, 962 const MCSubtargetInfo &STI) const { 963 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 964 } 965 966 unsigned 967 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, 968 SmallVectorImpl<MCFixup> &Fixups, 969 const MCSubtargetInfo &STI) const { 970 unsigned res = 0; 971 972 if (MI.getOperand(0).getReg() == Mips::A1 && 973 MI.getOperand(1).getReg() == Mips::A2) 974 res = 0; 975 else if (MI.getOperand(0).getReg() == Mips::A1 && 976 MI.getOperand(1).getReg() == Mips::A3) 977 res = 1; 978 else if (MI.getOperand(0).getReg() == Mips::A2 && 979 MI.getOperand(1).getReg() == Mips::A3) 980 res = 2; 981 else if (MI.getOperand(0).getReg() == Mips::A0 && 982 MI.getOperand(1).getReg() == Mips::S5) 983 res = 3; 984 else if (MI.getOperand(0).getReg() == Mips::A0 && 985 MI.getOperand(1).getReg() == Mips::S6) 986 res = 4; 987 else if (MI.getOperand(0).getReg() == Mips::A0 && 988 MI.getOperand(1).getReg() == Mips::A1) 989 res = 5; 990 else if (MI.getOperand(0).getReg() == Mips::A0 && 991 MI.getOperand(1).getReg() == Mips::A2) 992 res = 6; 993 else if (MI.getOperand(0).getReg() == Mips::A0 && 994 MI.getOperand(1).getReg() == Mips::A3) 995 res = 7; 996 997 return res; 998 } 999 1000 unsigned 1001 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, 1002 SmallVectorImpl<MCFixup> &Fixups, 1003 const MCSubtargetInfo &STI) const { 1004 const MCOperand &MO = MI.getOperand(OpNo); 1005 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate"); 1006 // The immediate is encoded as 'immediate >> 2'. 1007 unsigned Res = static_cast<unsigned>(MO.getImm()); 1008 assert((Res & 3) == 0); 1009 return Res >> 2; 1010 } 1011 1012 #include "MipsGenMCCodeEmitter.inc" 1013